\chapter{Clock and reset architecture}

\section{Clock generation}
\begin{center}
\begin{tikzpicture}[node distance=8mm and 14mm,font=\footnotesize]
  \node[fnblockD] (osc){16\,MHz\\oscillator};
  \node[fnblockT,right=of osc] (pll){ECP5 \code{EHXPLLL}};
  \node[fnblock,right=of pll] (sys){system clock\\64\,MHz};
  \draw[fnbus] (osc) -- (pll);
  \draw[fnbus] (pll) -- (sys);
\end{tikzpicture}
\end{center}

\code{ecp5\_pll\_sys\_clk.v} instantiates a real \code{EHXPLLL}, with
parameters generated by Project Trellis's own \code{ecppll} utility
(not hand-derived): \code{CLKI\_DIV}=1, \code{CLKFB\_DIV}=4,
\code{CLKOP\_DIV}=9, \code{FEEDBK\_PATH}=\code{CLKOP}, giving a real
VCO frequency of 576\,MHz (within the ECP5's documented 400--800\,MHz
range) and an exact, zero-error 64\,MHz output ($16 \times 4 / 1$,
divided by 9 at the VCO). 64\,MHz was chosen over 80\,MHz specifically
because it is the highest frequency at which \emph{all} measured P\&R
seeds close timing with real margin -- see Chapter~\ref{ch:pinout} for
the full 8-seed table.

Simulation note: \code{EHXPLLL} has no open, licensable behavioral
model (Lattice ships it only inside encrypted simulation libraries).
\code{ecp5\_pll\_sys\_clk.v} therefore provides a declared,
simulation-only bypass under a \code{`SIM} define (\code{clk\_sys}
tied directly to \code{clk\_16mhz}, \code{locked} tied high) -- this is
not, and does not claim to be, a simulation of real PLL lock timing.

\section{Reset architecture}
\begin{center}
\begin{tikzpicture}[node distance=8mm and 14mm,font=\footnotesize]
  \node[fnblockD] (por){External POR\\/ supervisor};
  \node[fnblockT,right=of por] (rs){\code{reset\_sync.v}};
  \node[fnblock,right=of rs] (rst){\code{rst}\\(sync-deassert)};
  \node[fnblock,below=6mm of rs] (lock){PLL \code{locked}};
  \draw[fnbus] (por) -- (rs);
  \draw[fnbus] (rs) -- (rst);
  \draw[fnbus] (lock) -- (rs);
\end{tikzpicture}
\end{center}

\code{reset\_sync.v} is a standard async-assert/sync-deassert bridge:
\code{rst} is asserted \emph{immediately} (combinationally) whenever
either the external POR (\code{ext\_rst\_n}, active-low) is asserted
\emph{or} the PLL has not yet reported lock, and is released only
after two flip-flops of the system clock following both conditions
clearing -- so no downstream synchronous logic (SDRAM controller,
compute datapath, SPI bridge) ever sees an asynchronous release edge.
This is a real, RTL-implemented mechanism, not a placeholder: it is
included, unmodified, in every synthesis and P\&R run reported in this
datasheet.