`timescale 1ns/1ps // ============================================================ // Isolated correctness test for packed_slot.v -- same golden formulas // as EXP-0062's tb_np_packed_layer_reuse.v (independently reproduced, // not shared, per this project's "third oracle" convention), but now // driving packed_slot.v's OWN real sequencing FSM instead of a // testbench procedurally driving each sub-module -- confirms the // promotion from testbench-sequence to real RTL (EXP-0062 -> this) // preserves bit-exact correctness. // // EXP-0079 UPDATE: packed_slot.v now wraps a REAL act_tile_fetch.v // (real DDR3 reads, no stand-in port left) -- this test now preloads // activation data into a real burst-memory backend, matching // act_tile_fetch.v's own real memory layout. // // EXP-0084 UPDATE: real 32-bit DDR3 channel widening -- backend // switched to burst_mem_model32.v (the real AS4C32M16SA x16 SDR model // this test used before is genuinely fixed at 16-bit and can't // represent the new bus width, see that model's own header), and both // preload tasks rewritten for the new BYTES_PER_BURST=4*BURST_LEN // (weights, layer_prefetch_ctrl.v) and 4-tiles-per-burst (activations, // act_tile_fetch.v) real layouts. // ============================================================ module tb; localparam BURST_LEN = 8; localparam SDRAM_ADDR_WIDTH = 25; localparam CLK_FREQ_MHZ = 64; localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ; localparam DATA_WIDTH = 8; localparam P_IN = 8; localparam ACC_WIDTH = 32; localparam ADDR_WIDTH = 26; localparam N_INPUTS = 128; localparam N_TILES = N_INPUTS/P_IN; localparam LAYER_BYTES = N_INPUTS; localparam WORDS_PER_LAYER = LAYER_BYTES/2; localparam L = 3; // layers localparam M = 6; // reuse positions per layer, paired 2 at a time reg clk = 0; always #(CLK_PERIOD_NS/2.0) clk = ~clk; reg rst; integer cyc; always @(posedge clk) if (!rst) cyc <= cyc + 1; // ---- real burst-memory backend ---- wire ctrl_req, ctrl_wr; wire [SDRAM_ADDR_WIDTH-1:0] ctrl_addr; wire [32*BURST_LEN-1:0] ctrl_wdata; wire [4*BURST_LEN-1:0] ctrl_wmask; wire [32*BURST_LEN-1:0] ctrl_rdata; wire ctrl_ready, ctrl_busy; reg wpre_req, wpre_wr; reg [SDRAM_ADDR_WIDTH-1:0] wpre_addr; reg [32*BURST_LEN-1:0] wpre_wdata; reg pre_active; wire slot_ctrl_req, slot_ctrl_wr; wire [SDRAM_ADDR_WIDTH-1:0] slot_ctrl_addr; wire [32*BURST_LEN-1:0] slot_ctrl_wdata; wire [4*BURST_LEN-1:0] slot_ctrl_wmask; assign ctrl_req = pre_active ? wpre_req : slot_ctrl_req; assign ctrl_wr = pre_active ? wpre_wr : slot_ctrl_wr; assign ctrl_addr = pre_active ? wpre_addr : slot_ctrl_addr; assign ctrl_wdata = pre_active ? wpre_wdata : slot_ctrl_wdata; assign ctrl_wmask = pre_active ? {(4*BURST_LEN){1'b0}} : slot_ctrl_wmask; burst_mem_model32 #( .BURST_LEN(BURST_LEN), .ADDR_WIDTH(SDRAM_ADDR_WIDTH) ) u_mem ( .clk(clk), .rst(rst), .req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask), .rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy) ); function automatic signed [7:0] weight_byte(input integer li, input integer t); weight_byte = $signed(8'((li*17 + t*29 + 13) & 8'hFF)); endfunction function automatic signed [7:0] input_byte(input integer li, input integer pos, input integer t); input_byte = $signed(8'((li*11 + pos*41 + t*7 + 3) & 8'hFF)); endfunction task automatic sdram_write_burst(input [SDRAM_ADDR_WIDTH-1:0] word_addr, input [32*BURST_LEN-1:0] data); begin @(posedge clk); while (ctrl_busy) @(posedge clk); wpre_req = 1'b1; wpre_wr = 1'b1; wpre_addr = word_addr; wpre_wdata = data; @(posedge clk); wpre_req = 1'b0; while (!ctrl_ready) @(posedge clk); end endtask // EXP-0084: BYTES_PER_BURST = 4*BURST_LEN (32 bytes/burst, up from // 16) -- 4 consecutive weight bytes pack into each 32-bit word now. task automatic preload_sdram_layers; integer li, bi, wb, tt; reg [32*BURST_LEN-1:0] burst_data; begin for (li = 0; li < L; li = li + 1) begin for (bi = 0; bi < (LAYER_BYTES/(4*BURST_LEN)); bi = bi + 1) begin for (wb = 0; wb < BURST_LEN; wb = wb + 1) begin tt = bi*(4*BURST_LEN) + wb*4; burst_data[wb*32 +: 32] = {weight_byte(li, tt+3), weight_byte(li, tt+2), weight_byte(li, tt+1), weight_byte(li, tt)}; end sdram_write_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), burst_data); end end end endtask // ---- real activation preload (EXP-0084 layout: FOUR consecutive // tiles share one BURST_LEN=8-word (256-bit) burst -- tile parity // 0/1/2/3 -> quarters [63:0]/[127:64]/[191:128]/[255:192], see // act_tile_fetch.v's own header). x_base(li,pos) = ACT_MEM_BASE + // (li*M+pos)*(N_TILES/4*BURST_LEN), well clear of the weight // region. ---- localparam [ADDR_WIDTH-1:0] ACT_MEM_BASE = 26'h10000; function automatic [ADDR_WIDTH-1:0] act_x_base(input integer li, input integer pos); act_x_base = ACT_MEM_BASE + (li*M + pos) * ((N_TILES/4)*BURST_LEN); endfunction task automatic preload_sdram_activations; integer li, pos, tq, qi; reg [32*BURST_LEN-1:0] burst_data; reg [ADDR_WIDTH-1:0] base; begin for (li = 0; li < L; li = li + 1) begin for (pos = 0; pos < M; pos = pos + 1) begin base = act_x_base(li, pos); for (tq = 0; tq < N_TILES/4; tq = tq + 1) begin // tq = burst-quad index burst_data = {(32*BURST_LEN){1'b0}}; for (qi = 0; qi < 4; qi = qi + 1) burst_data[qi*64 +: 64] = {input_byte(li, pos, (4*tq+qi)*P_IN + 7), input_byte(li, pos, (4*tq+qi)*P_IN + 6), input_byte(li, pos, (4*tq+qi)*P_IN + 5), input_byte(li, pos, (4*tq+qi)*P_IN + 4), input_byte(li, pos, (4*tq+qi)*P_IN + 3), input_byte(li, pos, (4*tq+qi)*P_IN + 2), input_byte(li, pos, (4*tq+qi)*P_IN + 1), input_byte(li, pos, (4*tq+qi)*P_IN + 0)}; sdram_write_burst(base[SDRAM_ADDR_WIDTH-1:0] + tq*BURST_LEN, burst_data); end end end end endtask // ---- packed_slot.v (DUT) ---- reg job_start; reg [ADDR_WIDTH-1:0] x_base_a, x_base_b, w_base; reg [15:0] n_tiles_in; reg [ADDR_WIDTH-1:0] result_addr_a, result_addr_b; reg [15:0] node_id_a, node_id_b; wire job_done; wire signed [DATA_WIDTH-1:0] result_data_a, result_data_b; wire [15:0] result_node_id_a, result_node_id_b; wire [ADDR_WIDTH-1:0] result_addr_a_out, result_addr_b_out; packed_slot #( .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH), .LAYER_BYTES(LAYER_BYTES) ) dut ( .clk(clk), .rst(rst), .job_start(job_start), .x_base_a(x_base_a), .x_base_b(x_base_b), .w_base(w_base), .n_tiles(n_tiles_in), .result_addr_a(result_addr_a), .result_addr_b(result_addr_b), .node_id_a(node_id_a), .node_id_b(node_id_b), .job_done(job_done), .result_data_a(result_data_a), .result_data_b(result_data_b), .result_node_id_a(result_node_id_a), .result_node_id_b(result_node_id_b), .result_addr_a_out(result_addr_a_out), .result_addr_b_out(result_addr_b_out), .mem_grant(1'b1), // no arbiter in this single-slot test .ctrl_req(slot_ctrl_req), .ctrl_wr(slot_ctrl_wr), .ctrl_addr(slot_ctrl_addr), .ctrl_wdata(slot_ctrl_wdata), .ctrl_wmask(slot_ctrl_wmask), .ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy) ); integer errors, tests; integer li_i, pp_i; integer acc_a, acc_b, s_a, s_b, k, tt; reg signed [DATA_WIDTH-1:0] expected_a, expected_b; integer wd; // EXP-0088: real read-after-write check that result_writeback.v // (inside the DUT) actually landed the correct value in DDR3 at // result_addr_a/b -- not just that job_done eventually pulsed. // Format matches result_writeback.v's own header exactly: one // 32-bit ctrl-word per lane, {node_id[15:0], 8'h00, // result_data[7:0]}. task automatic verify_writeback( input integer li, input integer pos_a, input integer pos_b, input [ADDR_WIDTH-1:0] raddr_a, input [ADDR_WIDTH-1:0] raddr_b, input signed [DATA_WIDTH-1:0] exp_data_a, input signed [DATA_WIDTH-1:0] exp_data_b, input [15:0] exp_nid_a, input [15:0] exp_nid_b ); reg [31:0] word_a, word_b; reg [SDRAM_ADDR_WIDTH-1:0] burst_addr; reg [2:0] word_in_block; begin pre_active = 1'b1; burst_addr = {raddr_a[SDRAM_ADDR_WIDTH-1:3], 3'b0}; word_in_block = raddr_a[2:0]; @(posedge clk); while (ctrl_busy) @(posedge clk); wpre_req = 1'b1; wpre_wr = 1'b0; wpre_addr = burst_addr; @(posedge clk); wpre_req = 1'b0; while (!ctrl_ready) @(posedge clk); word_a = ctrl_rdata[word_in_block*32 +: 32]; burst_addr = {raddr_b[SDRAM_ADDR_WIDTH-1:3], 3'b0}; word_in_block = raddr_b[2:0]; @(posedge clk); while (ctrl_busy) @(posedge clk); wpre_req = 1'b1; wpre_wr = 1'b0; wpre_addr = burst_addr; @(posedge clk); wpre_req = 1'b0; while (!ctrl_ready) @(posedge clk); word_b = ctrl_rdata[word_in_block*32 +: 32]; pre_active = 1'b0; if (word_a[7:0] !== exp_data_a || word_a[31:16] !== exp_nid_a) begin $display("FAIL li=%0d pos_a=%0d: WRITEBACK readback mismatch lane A: word=%08h (data=%0d nid=%0d) expected data=%0d nid=%0d", li, pos_a, word_a, $signed(word_a[7:0]), word_a[31:16], $signed(exp_data_a), exp_nid_a); errors = errors + 1; end if (word_b[7:0] !== exp_data_b || word_b[31:16] !== exp_nid_b) begin $display("FAIL li=%0d pos_b=%0d: WRITEBACK readback mismatch lane B: word=%08h (data=%0d nid=%0d) expected data=%0d nid=%0d", li, pos_b, word_b, $signed(word_b[7:0]), word_b[31:16], $signed(exp_data_b), exp_nid_b); errors = errors + 1; end end endtask task automatic run_one_pair(input integer li, input integer pos_a, input integer pos_b); begin tests = tests + 1; @(posedge clk); job_start = 1'b1; x_base_a = act_x_base(li, pos_a); x_base_b = act_x_base(li, pos_b); w_base = li*WORDS_PER_LAYER; // WORD address, matching layer_prefetch_ctrl.v's // own convention (EXP-0057/58/62) and this // testbench's own preload_sdram_layers addressing n_tiles_in = N_TILES[15:0]; result_addr_a = 26'h9000 + pos_a; result_addr_b = 26'h9000 + pos_b; node_id_a = li[15:8]*8'(M) + pos_a[15:0]; node_id_b = li[15:8]*8'(M) + pos_b[15:0]; @(posedge clk); job_start = 1'b0; acc_a = 0; acc_b = 0; for (tt = 0; tt < N_INPUTS; tt = tt + 1) begin acc_a = acc_a + (input_byte(li, pos_a, tt) * weight_byte(li, tt)); acc_b = acc_b + (input_byte(li, pos_b, tt) * weight_byte(li, tt)); end s_a = acc_a; s_b = acc_b; if (s_a <= 0) expected_a = 0; else if (s_a > 127) expected_a = 8'sd127; else expected_a = s_a[DATA_WIDTH-1:0]; if (s_b <= 0) expected_b = 0; else if (s_b > 127) expected_b = 8'sd127; else expected_b = s_b[DATA_WIDTH-1:0]; wd = 0; while (!job_done && wd < 2000) begin @(posedge clk); wd = wd + 1; end if (!job_done) begin $display("FAIL li=%0d pos_a=%0d pos_b=%0d: TIMEOUT waiting for job_done", li, pos_a, pos_b); errors = errors + 1; end else if (result_data_a !== expected_a || result_data_b !== expected_b) begin $display("FAIL li=%0d pos_a=%0d pos_b=%0d: got_a=%0d got_b=%0d expected_a=%0d expected_b=%0d", li, pos_a, pos_b, $signed(result_data_a), $signed(result_data_b), $signed(expected_a), $signed(expected_b)); errors = errors + 1; end else if (result_node_id_a !== node_id_a || result_node_id_b !== node_id_b || result_addr_a_out !== result_addr_a || result_addr_b_out !== result_addr_b) begin $display("FAIL li=%0d pos_a=%0d pos_b=%0d: metadata passthrough mismatch (node_a=%0d/%0d node_b=%0d/%0d addr_a=%0d/%0d addr_b=%0d/%0d)", li, pos_a, pos_b, result_node_id_a, node_id_a, result_node_id_b, node_id_b, result_addr_a_out, result_addr_a, result_addr_b_out, result_addr_b); errors = errors + 1; end else begin $display("PASS li=%0d pos_a=%0d pos_b=%0d: a=%0d b=%0d (packed_slot.v real sequencer)", li, pos_a, pos_b, $signed(result_data_a), $signed(result_data_b)); // EXP-0088: real DDR3 read-after-write check -- job_done // now means "written to DDR3", confirm it actually was. verify_writeback(li, pos_a, pos_b, result_addr_a, result_addr_b, expected_a, expected_b, node_id_a, node_id_b); end end endtask initial begin errors = 0; tests = 0; cyc = 0; rst = 1; pre_active = 1'b1; wpre_req = 0; wpre_wr = 0; wpre_addr = 0; wpre_wdata = 0; job_start = 0; x_base_a = 0; x_base_b = 0; w_base = 0; n_tiles_in = 0; result_addr_a = 0; result_addr_b = 0; node_id_a = 0; node_id_b = 0; repeat(5) @(posedge clk); rst = 0; @(posedge clk); while (ctrl_busy) @(posedge clk); $display("=== preload SDRAM with %0d resident-filter weight sets ===", L); preload_sdram_layers; $display("=== preload SDRAM with real activation data (EXP-0079) ==="); preload_sdram_activations; @(posedge clk); pre_active = 1'b0; $display("=== packed_slot.v real sequencer: %0d layers x %0d positions (paired) ===", L, M); for (li_i = 0; li_i < L; li_i = li_i + 1) begin for (pp_i = 0; pp_i < M; pp_i = pp_i + 2) begin run_one_pair(li_i, pp_i, pp_i+1); end end $display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors); if (errors == 0) $display("ALL TESTS PASSED (tb_packed_slot)"); $finish; end endmodule