Info: Logic utilisation before packing: Info: Total LUT4s: 3149/43848 7% Info: logic LUTs: 2367/43848 5% Info: carry LUTs: 782/43848 1% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 2406/43848 5% Info: Packing IOs.. Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y Info: pin 'psram_dq[15]$tr_io' constrained to Bel 'X90/Y41/PIOD'. Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y Info: pin 'psram_dq[14]$tr_io' constrained to Bel 'X90/Y41/PIOC'. Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y Info: pin 'psram_dq[13]$tr_io' constrained to Bel 'X90/Y41/PIOA'. Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y Info: pin 'psram_dq[12]$tr_io' constrained to Bel 'X90/Y41/PIOB'. Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y Info: pin 'psram_dq[11]$tr_io' constrained to Bel 'X90/Y38/PIOD'. Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y Info: pin 'psram_dq[10]$tr_io' constrained to Bel 'X90/Y38/PIOB'. Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y Info: pin 'psram_dq[9]$tr_io' constrained to Bel 'X90/Y32/PIOD'. Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y Info: pin 'psram_dq[8]$tr_io' constrained to Bel 'X90/Y32/PIOB'. Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y Info: pin 'psram_dq[7]$tr_io' constrained to Bel 'X90/Y32/PIOC'. Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y Info: pin 'psram_dq[6]$tr_io' constrained to Bel 'X90/Y32/PIOA'. Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y Info: pin 'psram_dq[5]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y Info: pin 'psram_dq[4]$tr_io' constrained to Bel 'X90/Y29/PIOA'. Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y Info: pin 'psram_dq[3]$tr_io' constrained to Bel 'X90/Y23/PIOC'. Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y Info: pin 'psram_dq[2]$tr_io' constrained to Bel 'X90/Y11/PIOB'. Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y Info: pin 'psram_dq[1]$tr_io' constrained to Bel 'X90/Y11/PIOA'. Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y Info: pin 'psram_dq[0]$tr_io' constrained to Bel 'X90/Y29/PIOD'. Info: pin 'sclk$tr_io' constrained to Bel 'X0/Y11/PIOC'. Info: pin 'rst$tr_io' constrained to Bel 'X0/Y14/PIOB'. Info: pin 'psram_zz_n$tr_io' constrained to Bel 'X90/Y59/PIOB'. Info: pin 'psram_we_n$tr_io' constrained to Bel 'X90/Y44/PIOD'. Info: pin 'psram_ub_n$tr_io' constrained to Bel 'X90/Y59/PIOA'. Info: pin 'psram_oe_n$tr_io' constrained to Bel 'X90/Y44/PIOC'. Info: pin 'psram_lb_n$tr_io' constrained to Bel 'X90/Y53/PIOA'. Info: pin 'psram_ce_n$tr_io' constrained to Bel 'X90/Y44/PIOA'. Info: pin 'psram_a[22]$tr_io' constrained to Bel 'X90/Y59/PIOD'. Info: pin 'psram_a[21]$tr_io' constrained to Bel 'X90/Y29/PIOB'. Info: pin 'psram_a[20]$tr_io' constrained to Bel 'X90/Y26/PIOD'. Info: pin 'psram_a[19]$tr_io' constrained to Bel 'X90/Y26/PIOC'. Info: pin 'psram_a[18]$tr_io' constrained to Bel 'X90/Y26/PIOB'. Info: pin 'psram_a[17]$tr_io' constrained to Bel 'X90/Y26/PIOA'. Info: pin 'psram_a[16]$tr_io' constrained to Bel 'X90/Y23/PIOD'. Info: pin 'psram_a[15]$tr_io' constrained to Bel 'X90/Y23/PIOB'. Info: pin 'psram_a[14]$tr_io' constrained to Bel 'X90/Y23/PIOA'. Info: pin 'psram_a[13]$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'psram_a[12]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'psram_a[11]$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'psram_a[10]$tr_io' constrained to Bel 'X90/Y20/PIOB'. Info: pin 'psram_a[9]$tr_io' constrained to Bel 'X90/Y17/PIOD'. Info: pin 'psram_a[8]$tr_io' constrained to Bel 'X90/Y17/PIOB'. Info: pin 'psram_a[7]$tr_io' constrained to Bel 'X90/Y17/PIOC'. Info: pin 'psram_a[6]$tr_io' constrained to Bel 'X90/Y17/PIOA'. Info: pin 'psram_a[5]$tr_io' constrained to Bel 'X90/Y14/PIOD'. Info: pin 'psram_a[4]$tr_io' constrained to Bel 'X90/Y14/PIOC'. Info: pin 'psram_a[3]$tr_io' constrained to Bel 'X90/Y14/PIOB'. Info: pin 'psram_a[2]$tr_io' constrained to Bel 'X90/Y14/PIOA'. Info: pin 'psram_a[1]$tr_io' constrained to Bel 'X90/Y11/PIOD'. Info: pin 'psram_a[0]$tr_io' constrained to Bel 'X90/Y11/PIOC'. Info: pin 'mosi$tr_io' constrained to Bel 'X0/Y11/PIOD'. Info: pin 'miso$tr_io' constrained to Bel 'X0/Y14/PIOC'. Info: pin 'cs_n$tr_io' constrained to Bel 'X0/Y14/PIOD'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y29/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 531 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0xb44f9876 Info: Device utilisation: Info: TRELLIS_IO: 51/ 245 20% Info: DCCA: 1/ 56 1% Info: DP16KD: 2/ 108 1% Info: MULT18X18D: 4/ 72 5% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 2406/ 43848 5% Info: TRELLIS_COMB: 3323/ 43848 7% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 51 cells based on constraints. Info: Creating initial analytic placement for 3949 cells, random placement wirelen = 289105. Info: at initial placer iter 0, wirelen = 3165 Info: at initial placer iter 1, wirelen = 2074 Info: at initial placer iter 2, wirelen = 2036 Info: at initial placer iter 3, wirelen = 1962 Info: Running main analytical placer, max placement attempts per cell = 4186171. Info: at iteration #1, type ALL: wirelen solved = 1943, spread = 34731, legal = 39344; time = 0.07s Info: at iteration #2, type ALL: wirelen solved = 4630, spread = 26847, legal = 30012; time = 0.05s Info: at iteration #3, type ALL: wirelen solved = 6318, spread = 20818, legal = 23262; time = 0.05s Info: at iteration #4, type ALL: wirelen solved = 7636, spread = 18055, legal = 21757; time = 0.05s Info: at iteration #5, type ALL: wirelen solved = 8380, spread = 18003, legal = 21132; time = 0.04s Info: at iteration #6, type ALL: wirelen solved = 9211, spread = 16061, legal = 20148; time = 0.05s Info: at iteration #7, type ALL: wirelen solved = 9390, spread = 15467, legal = 20281; time = 0.04s Info: at iteration #8, type ALL: wirelen solved = 9701, spread = 17137, legal = 20028; time = 0.04s Info: at iteration #9, type ALL: wirelen solved = 11004, spread = 16326, legal = 19970; time = 0.04s Info: at iteration #10, type ALL: wirelen solved = 11143, spread = 17732, legal = 20591; time = 0.04s Info: at iteration #11, type ALL: wirelen solved = 12249, spread = 17232, legal = 21002; time = 0.04s Info: at iteration #12, type ALL: wirelen solved = 12261, spread = 17941, legal = 20785; time = 0.04s Info: at iteration #13, type ALL: wirelen solved = 12752, spread = 18604, legal = 21539; time = 0.04s Info: at iteration #14, type ALL: wirelen solved = 13508, spread = 17855, legal = 21101; time = 0.04s Info: HeAP Placer Time: 0.88s Info: of which solving equations: 0.56s Info: of which spreading cells: 0.09s Info: of which strict legalisation: 0.11s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 1272, wirelen = 19970 Info: at iteration #5: temp = 0.000000, timing cost = 1343, wirelen = 17573 Info: at iteration #10: temp = 0.000000, timing cost = 1294, wirelen = 16774 Info: at iteration #15: temp = 0.000000, timing cost = 1262, wirelen = 16200 Info: at iteration #20: temp = 0.000000, timing cost = 1241, wirelen = 15946 Info: at iteration #25: temp = 0.000000, timing cost = 1234, wirelen = 15852 Info: at iteration #30: temp = 0.000000, timing cost = 1237, wirelen = 15812 Info: at iteration #33: temp = 0.000000, timing cost = 1233, wirelen = 15791 Info: SA placement time 2.26s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 53.68 MHz (FAIL at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.69 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 7.34 ns Info: Slack histogram: Info: legend: * represents 17 endpoint(s) Info: + represents [1,17) endpoint(s) Info: [ -6129, -5226) |+ Info: [ -5226, -4323) | Info: [ -4323, -3420) |*+ Info: [ -3420, -2517) |**+ Info: [ -2517, -1614) |+ Info: [ -1614, -711) |+ Info: [ -711, 192) | Info: [ 192, 1095) | Info: [ 1095, 1998) | Info: [ 1998, 2901) | Info: [ 2901, 3804) |+ Info: [ 3804, 4707) |*********+ Info: [ 4707, 5610) |***********+ Info: [ 5610, 6513) |***************************+ Info: [ 6513, 7416) |******************************************+ Info: [ 7416, 8319) |*****************************************+ Info: [ 8319, 9222) |*****************************************+ Info: [ 9222, 10125) |************************************************************ Info: [ 10125, 11028) |**********************************************************+ Info: [ 11028, 11931) |*********************************+ Info: Checksum: 0x08000661 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 16026 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 394 605 | 394 605 | 15453| 0.18 0.18| Info: 2000 | 881 1118 | 487 513 | 15022| 0.13 0.31| Info: 3000 | 1163 1836 | 282 718 | 14318| 0.08 0.39| Info: 4000 | 1698 2301 | 535 465 | 13941| 0.14 0.52| Info: 5000 | 2024 2975 | 326 674 | 13398| 0.10 0.62| Info: 6000 | 2366 3633 | 342 658 | 12783| 0.09 0.71| Info: 7000 | 2747 4252 | 381 619 | 12246| 0.12 0.83| Info: 8000 | 3284 4715 | 537 463 | 11883| 0.15 0.98| Info: 9000 | 3755 5244 | 471 529 | 11395| 0.09 1.08| Info: 10000 | 4054 5848 | 299 604 | 10793| 0.09 1.16| Info: 11000 | 4502 6303 | 448 455 | 10269| 0.11 1.27| Info: 12000 | 5100 6659 | 598 356 | 9921| 0.11 1.38| Info: 13000 | 5671 7067 | 571 408 | 9563| 0.10 1.48| Info: 14000 | 6216 7514 | 545 447 | 9157| 0.10 1.58| Info: 15000 | 6762 7968 | 546 454 | 8727| 0.10 1.69| Info: 16000 | 7176 8554 | 414 586 | 8193| 0.13 1.82| Info: 17000 | 7312 9418 | 136 864 | 7384| 0.14 1.96| Info: 18000 | 7467 10263 | 155 845 | 6602| 0.16 2.12| Info: 19000 | 7632 11066 | 165 803 | 5801| 0.16 2.28| Info: 20000 | 7783 11837 | 151 771 | 4974| 0.14 2.41| Info: 21000 | 8032 12514 | 249 677 | 4486| 0.73 3.14| Info: 22000 | 8173 13274 | 141 760 | 3641| 0.12 3.27| Info: 23000 | 8278 14112 | 105 838 | 2761| 0.11 3.38| Info: 24000 | 8401 14916 | 123 804 | 1912| 0.11 3.48| Info: 25000 | 8536 15747 | 135 831 | 1073| 0.15 3.63| Info: 26000 | 8589 16598 | 53 851 | 131| 0.22 3.85| Info: 26159 | 8600 16734 | 11 136 | 0| 0.08 3.93| Info: Routing complete. Info: Router1 time 3.93s Info: Checksum: 0xda4b34ae Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.40 0.40 Source u_graph_engine.u_neuron.group_index_TRELLIS_FF_Q_1.Q Info: routing 1.03 1.43 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_PFUMX_Z_C0_CCU2C_S1_S0[1] (67,15) -> (68,9) Info: Sink u_graph_engine.w_mem[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z.C Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194.36-194.54 Info: /opt/homebrew/bin/../share/yosys/techmap.v:287.21-287.22 Info: logic 0.18 1.61 Source u_graph_engine.w_mem[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z.F Info: routing 0.86 2.47 Net u_graph_engine.w_mem[0]_LUT4_C_Z_PFUMX_BLUT_Z[2] (68,9) -> (68,12) Info: Sink u_graph_engine.u_neuron.u_mac8.x_bus_LUT4_Z_3_D_PFUMX_Z_C0_LUT4_Z.B Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 2.65 Source u_graph_engine.u_neuron.u_mac8.x_bus_LUT4_Z_3_D_PFUMX_Z_C0_LUT4_Z.F Info: routing 0.51 3.16 Net u_graph_engine.u_neuron.u_mac8.x_bus_LUT4_Z_3_D_PFUMX_Z_C0[4] (68,12) -> (68,11) Info: Sink u_graph_engine.u_neuron.u_mac8.x_bus_LUT4_Z_3_D_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.19 3.36 Source u_graph_engine.u_neuron.u_mac8.x_bus_LUT4_Z_3_D_PFUMX_Z_BLUT_LUT4_Z.OFX Info: routing 1.28 4.64 Net u_graph_engine.u_neuron.u_mac8.x_bus_LUT4_Z_3_D[3] (68,11) -> (61,21) Info: Sink u_graph_engine.u_neuron.u_mac8.x_bus_LUT4_Z_3.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 4.82 Source u_graph_engine.u_neuron.u_mac8.x_bus_LUT4_Z_3.F Info: routing 0.93 5.75 Net u_graph_engine.u_neuron.x_group[7] (61,21) -> (61,22) Info: Sink u_graph_engine.u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9.A15 Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:92.43-92.50 Info: logic 3.07 8.82 Source u_graph_engine.u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9.P2 Info: routing 1.59 10.40 Net u_graph_engine.u_neuron.u_mac8.products[0][2] (61,22) -> (66,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB0.B Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13 Info: logic 0.35 10.76 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 10.76 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_FCI_INT (66,13) -> (66,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 10.76 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 10.76 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT (66,13) -> (66,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 10.81 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 10.81 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_FCI_INT (66,13) -> (66,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 10.81 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 10.81 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1_COUT (66,13) -> (67,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 10.87 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 10.87 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_FCI_INT (67,13) -> (67,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.29 11.16 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_S1$CCU2_COMB1.F Info: routing 0.99 12.16 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1 (67,13) -> (70,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.B Info: logic 0.35 12.51 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO Info: routing 0.00 12.51 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (70,13) -> (70,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 12.57 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO Info: routing 0.00 12.57 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (70,13) -> (70,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI Info: logic 0.00 12.57 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO Info: routing 0.00 12.57 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (70,13) -> (70,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 12.62 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO Info: routing 0.00 12.62 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (70,13) -> (70,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI Info: logic 0.00 12.62 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO Info: routing 0.00 12.62 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (70,13) -> (70,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 12.68 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO Info: routing 0.00 12.68 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (70,13) -> (70,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI Info: logic 0.00 12.68 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO Info: routing 0.00 12.68 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (70,13) -> (71,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.33 13.01 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.F Info: routing 0.80 13.81 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[1] (71,13) -> (71,14) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.B Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.35 14.17 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 14.17 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (71,14) -> (71,14) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 14.17 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 14.17 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (71,14) -> (71,14) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:128.24-128.43 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 14.22 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 14.22 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (71,14) -> (71,14) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 14.22 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 14.22 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (71,14) -> (71,14) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:128.24-128.43 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 14.28 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 14.28 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (71,14) -> (71,14) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 14.28 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 14.28 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (71,14) -> (71,14) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:128.24-128.43 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.33 14.61 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.F Info: routing 1.03 15.64 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[2] (71,14) -> (70,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.A Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.35 15.99 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 15.99 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (70,12) -> (71,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165.42-165.58 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 16.05 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 16.05 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (71,12) -> (71,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 16.05 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 16.05 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (71,12) -> (71,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165.42-165.58 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 16.10 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 16.10 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (71,12) -> (71,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 16.10 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 16.10 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (71,12) -> (71,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165.42-165.58 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 16.16 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 16.16 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (71,12) -> (71,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 16.16 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 16.16 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (71,12) -> (71,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165.42-165.58 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 16.22 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 16.22 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (71,12) -> (71,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 16.22 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 16.22 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT_CIN (71,12) -> (72,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165.42-165.58 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 16.27 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_COMB0.FCO Info: routing 0.00 16.27 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_FCI_INT (72,12) -> (72,12) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_COMB1.FCI Info: logic 0.00 16.27 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D_CCU2C_COUT$CCU2_COMB1.FCO Info: routing 0.00 16.27 Net $nextpnr_CCU2C_67$CIN (72,12) -> (72,12) Info: Sink $nextpnr_CCU2C_67$CCU2_COMB0.FCI Info: logic 0.33 16.60 Source $nextpnr_CCU2C_67$CCU2_COMB0.F Info: routing 0.73 17.33 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1_D (72,12) -> (74,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1.D Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:165.42-165.58 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.18 17.51 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z_LUT4_Z_1.F Info: routing 0.51 18.02 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_Z[2] (74,13) -> (75,13) Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1.C Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 18.20 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z_LUT4_Z_1.F Info: routing 0.12 18.32 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_C_1_Z[1] (75,13) -> (75,13) Info: Sink u_graph_engine.u_neuron.y_TRELLIS_FF_Q_1.DI Info: setup 0.00 18.32 Source u_graph_engine.u_neuron.y_TRELLIS_FF_Q_1.DI Info: 7.92 ns logic, 10.40 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source rst$tr_io.O Info: routing 4.69 4.69 Net rst$TRELLIS_IO_IN (0,14) -> (83,26) Info: Sink graph_rst_LUT4_Z.C Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:23.16-23.19 Info: logic 0.18 4.87 Source graph_rst_LUT4_Z.F Info: routing 2.27 7.13 Net graph_rst (83,26) -> (68,7) Info: Sink u_graph_engine.conn_i_TRELLIS_FF_Q_DI_LUT4_D_Z_LUT4_C_D_LUT4_D_2_C_LUT4_C_1.B Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 7.31 Source u_graph_engine.conn_i_TRELLIS_FF_Q_DI_LUT4_D_Z_LUT4_C_D_LUT4_D_2_C_LUT4_C_1.F Info: routing 1.93 9.24 Net u_graph_engine.conn_i_TRELLIS_FF_Q_DI_LUT4_D_Z_LUT4_C_D_LUT4_D_2_C_LUT4_C_1_Z (68,7) -> (66,16) Info: Sink u_graph_engine.w_mem[30]_TRELLIS_FF_Q_2.CE Info: setup 0.00 9.24 Source u_graph_engine.w_mem[30]_TRELLIS_FF_Q_2.CE Info: 0.36 ns logic, 8.88 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source u_spi_slave.miso_TRELLIS_FF_Q.Q Info: routing 4.37 4.76 Net miso$TRELLIS_IO_OUT (79,31) -> (0,14) Info: Sink miso$tr_io.I Info: Defined in: Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:31.17-31.21 Info: 0.40 ns logic, 4.37 ns routing ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 54.58 MHz (FAIL at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.24 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.76 ns Info: Slack histogram: Info: legend: * represents 26 endpoint(s) Info: + represents [1,26) endpoint(s) Info: [ -5821, -4940) |+ Info: [ -4940, -4059) | Info: [ -4059, -3178) |+ Info: [ -3178, -2297) |*+ Info: [ -2297, -1416) |+ Info: [ -1416, -535) |+ Info: [ -535, 346) | Info: [ 346, 1227) | Info: [ 1227, 2108) | Info: [ 2108, 2989) | Info: [ 2989, 3870) |+ Info: [ 3870, 4751) |*+ Info: [ 4751, 5632) |*******+ Info: [ 5632, 6513) |********+ Info: [ 6513, 7394) |************+ Info: [ 7394, 8275) |***************************************+ Info: [ 8275, 9156) |**********************+ Info: [ 9156, 10037) |*****************************+ Info: [ 10037, 10918) |************************************************************ Info: [ 10918, 11799) |*********************************+ 0 warnings, 1 error Info: Program finished normally.