`timescale 1ns/1ps

// ============================================================
// EXP-0084 -- minimal, EXPLICITLY SYNTHETIC 32-bit-wide burst-memory
// test model. NOT a real chip model (unlike sdram_controller.v/
// sdram_model.v, which genuinely represent the real AS4C32M16SA x16
// SDR part this project also uses) -- that real model is inherently
// fixed at 16-bit words (a real hardware fact, not a parameter choice)
// and is shared by 20+ other testbenches across v2 and v3, so it is
// deliberately NOT modified here. This file exists purely so the
// isolated, fast (iverilog) testbenches for modules that now speak
// this project's real 32-bit ctrl bus convention (EXP-0084's DDR3
// widening) have a same-shape, functionally-correct backend to run
// against WITHOUT needing the full real MIG IP + ddr3_model.sv (real
// xsim, much slower) for every isolated glue-logic check -- matching
// this project's own established "verify new glue logic against a
// fast backend first" precedent (tb_act_tile_fetch.v's own header),
// just re-pointed at a backend that actually matches the current real
// bus width. The REAL, trustworthy, board-accurate verification still
// comes from tb_n2_system_ddr3.v against the real ddr3_model.sv, same
// as always -- this model's own fixed latency is a plausible, but NOT
// claimed-real, stand-in.
//
// Small DENSE backing store (2^MEM_ADDR_BITS entries), not a full
// 2^ADDR_WIDTH array -- ADDR_WIDTH=25 would need ~1GB densely
// allocated for no reason; every real test in this project only ever
// touches small, low addresses. MEM_ADDR_BITS=20 (~1M entries, ~32MB
// of simulation memory) comfortably covers any realistic test address
// -- including tb_packed_slot.v's own ACT_MEM_BASE=0x10000 region,
// which a first version of this model sized at 16 bits (65536
// entries) silently WRAPPED to address 0, aliasing weight and
// activation data and producing real, confusing wrong-answer failures
// (found via real simulation, not by inspection -- see EXP-0084's
// log for the full root-cause trace). Staying portable (Icarus's
// associative-array support for a packed-vector key type turned out
// not to work for this purpose -- found via a real elaboration
// error, not assumed).
// ============================================================
module burst_mem_model32 #(
    parameter BURST_LEN     = 8,
    parameter ADDR_WIDTH    = 25,
    parameter MEM_ADDR_BITS = 20,
    parameter LATENCY       = 6   // fixed req->ready cycles, a plausible stand-in, not claimed real
)(
    input  wire clk,
    input  wire rst,

    input  wire                     req,
    input  wire                     wr,
    input  wire [ADDR_WIDTH-1:0]    addr,
    input  wire [32*BURST_LEN-1:0]  wdata,
    input  wire [4*BURST_LEN-1:0]   wmask,
    output reg  [32*BURST_LEN-1:0]  rdata,
    output reg                      ready,
    output wire                     busy
);
    reg [32*BURST_LEN-1:0] mem [0:(1<<MEM_ADDR_BITS)-1];

    localparam S_IDLE = 2'd0, S_BUSY = 2'd1, S_DONE = 2'd2;
    reg [1:0]  state;
    reg [7:0]  cnt;
    reg [ADDR_WIDTH-1:0]   addr_lat;
    reg                    wr_lat;
    reg [32*BURST_LEN-1:0] wdata_lat;
    reg [4*BURST_LEN-1:0]  wmask_lat;
    integer bi;

    assign busy = (state != S_IDLE);

    always @(posedge clk) begin
        if (rst) begin
            state <= S_IDLE;
            ready <= 1'b0;
            cnt   <= 8'd0;
        end else begin
            ready <= 1'b0;
            case (state)
                S_IDLE: begin
                    if (req) begin
                        addr_lat  <= addr;
                        wr_lat    <= wr;
                        wdata_lat <= wdata;
                        wmask_lat <= wmask;
                        cnt       <= LATENCY[7:0];
                        state     <= S_BUSY;
                    end
                end
                S_BUSY: begin
                    if (cnt == 8'd1) state <= S_DONE;
                    else cnt <= cnt - 8'd1;
                end
                S_DONE: begin
                    if (wr_lat) begin
                        // real DQM polarity (matches sdram_controller.v's
                        // own convention): 0=write that byte, 1=masked.
                        for (bi = 0; bi < 4*BURST_LEN; bi = bi + 1)
                            if (!wmask_lat[bi])
                                mem[addr_lat[MEM_ADDR_BITS-1:0]][bi*8 +: 8] <= wdata_lat[bi*8 +: 8];
                    end else begin
                        rdata <= mem[addr_lat[MEM_ADDR_BITS-1:0]];
                    end
                    ready <= 1'b1;
                    state <= S_IDLE;
                end
                default: state <= S_IDLE;
            endcase
        end
    end
endmodule