$date
	Wed Sep  2 14:24:09 2026
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module tb $end
$var wire 8 ! y_e [7:0] $end
$var wire 8 " y_d [7:0] $end
$var wire 8 # y_c [7:0] $end
$var wire 8 $ y_b [7:0] $end
$var wire 8 % y_a [7:0] $end
$var wire 1 & done_e $end
$var wire 1 ' done_d $end
$var wire 1 ( done_c $end
$var wire 1 ) done_b $end
$var wire 1 * done_a $end
$var wire 1 + busy_e $end
$var wire 1 , busy_d $end
$var wire 1 - busy_c $end
$var wire 1 . busy_b $end
$var wire 1 / busy_a $end
$var parameter 32 0 A_ACC_WIDTH $end
$var parameter 32 1 A_DATA_WIDTH $end
$var parameter 32 2 A_N_INPUTS $end
$var parameter 32 3 A_PARALLEL $end
$var parameter 32 4 B_ACC_WIDTH $end
$var parameter 32 5 B_DATA_WIDTH $end
$var parameter 32 6 B_N_INPUTS $end
$var parameter 32 7 B_PARALLEL $end
$var parameter 32 8 C_ACC_WIDTH $end
$var parameter 32 9 C_DATA_WIDTH $end
$var parameter 32 : C_N_INPUTS $end
$var parameter 32 ; C_PARALLEL $end
$var parameter 32 < D_ACC_WIDTH $end
$var parameter 32 = D_DATA_WIDTH $end
$var parameter 32 > D_N_INPUTS $end
$var parameter 32 ? D_PARALLEL $end
$var parameter 32 @ E_ACC_WIDTH $end
$var parameter 32 A E_DATA_WIDTH $end
$var parameter 32 B E_N_INPUTS $end
$var parameter 32 C E_PARALLEL $end
$var reg 8 D bias_a [7:0] $end
$var reg 8 E bias_b [7:0] $end
$var reg 8 F bias_c [7:0] $end
$var reg 8 G bias_d [7:0] $end
$var reg 8 H bias_e [7:0] $end
$var reg 1 I clk $end
$var reg 1 J rst $end
$var reg 1 K start_a $end
$var reg 1 L start_b $end
$var reg 1 M start_c $end
$var reg 1 N start_d $end
$var reg 1 O start_e $end
$var reg 1 P timed_out $end
$var reg 256 Q w_bus_a [255:0] $end
$var reg 240 R w_bus_b [239:0] $end
$var reg 160 S w_bus_c [159:0] $end
$var reg 512 T w_bus_d [511:0] $end
$var reg 32 U w_bus_e [31:0] $end
$var reg 256 V x_bus_a [255:0] $end
$var reg 240 W x_bus_b [239:0] $end
$var reg 160 X x_bus_c [159:0] $end
$var reg 512 Y x_bus_d [511:0] $end
$var reg 32 Z x_bus_e [31:0] $end
$var integer 32 [ count [31:0] $end
$var integer 32 \ errors [31:0] $end
$var integer 32 ] findings [31:0] $end
$var integer 32 ^ max_cycles [31:0] $end
$scope module u_a $end
$var wire 8 _ bias [7:0] $end
$var wire 1 I clk $end
$var wire 1 J rst $end
$var wire 1 K start $end
$var wire 256 ` w_bus [255:0] $end
$var wire 256 a x_bus [255:0] $end
$var wire 64 b x_group [63:0] $end
$var wire 64 c w_group [63:0] $end
$var wire 32 d final_acc [31:0] $end
$var wire 32 e bias_ext [31:0] $end
$var wire 32 f acc_next [31:0] $end
$var parameter 32 g ACC_WIDTH $end
$var parameter 32 h DATA_WIDTH $end
$var parameter 32 i GROUPS $end
$var parameter 32 j GROUP_INDEX_WIDTH $end
$var parameter 32 k N_INPUTS $end
$var parameter 32 l PARALLEL $end
$var reg 32 m acc [31:0] $end
$var reg 1 / busy $end
$var reg 1 * done $end
$var reg 2 n group_index [1:0] $end
$var reg 8 o y [7:0] $end
$scope module u_mac8 $end
$var wire 32 p acc_in [31:0] $end
$var wire 64 q w_bus [63:0] $end
$var wire 64 r x_bus [63:0] $end
$var wire 32 s acc_out [31:0] $end
$var parameter 32 t ACC_WIDTH $end
$var parameter 32 u DATA_WIDTH $end
$var parameter 32 v PARALLEL $end
$var parameter 32 w TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 x i $end
$scope module u_mac $end
$var wire 32 y acc_in [31:0] $end
$var wire 8 z w [7:0] $end
$var wire 8 { x [7:0] $end
$var wire 32 | product_ext [31:0] $end
$var wire 16 } product [15:0] $end
$var wire 32 ~ acc_out [31:0] $end
$var parameter 32 !" ACC_WIDTH $end
$var parameter 32 "" DATA_WIDTH $end
$var parameter 64 #" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 $" i $end
$scope module u_mac $end
$var wire 32 %" acc_in [31:0] $end
$var wire 8 &" w [7:0] $end
$var wire 8 '" x [7:0] $end
$var wire 32 (" product_ext [31:0] $end
$var wire 16 )" product [15:0] $end
$var wire 32 *" acc_out [31:0] $end
$var parameter 32 +" ACC_WIDTH $end
$var parameter 32 ," DATA_WIDTH $end
$var parameter 64 -" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 ." i $end
$scope module u_mac $end
$var wire 32 /" acc_in [31:0] $end
$var wire 8 0" w [7:0] $end
$var wire 8 1" x [7:0] $end
$var wire 32 2" product_ext [31:0] $end
$var wire 16 3" product [15:0] $end
$var wire 32 4" acc_out [31:0] $end
$var parameter 32 5" ACC_WIDTH $end
$var parameter 32 6" DATA_WIDTH $end
$var parameter 64 7" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 8" i $end
$scope module u_mac $end
$var wire 32 9" acc_in [31:0] $end
$var wire 8 :" w [7:0] $end
$var wire 8 ;" x [7:0] $end
$var wire 32 <" product_ext [31:0] $end
$var wire 16 =" product [15:0] $end
$var wire 32 >" acc_out [31:0] $end
$var parameter 32 ?" ACC_WIDTH $end
$var parameter 32 @" DATA_WIDTH $end
$var parameter 64 A" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 B" i $end
$scope module u_mac $end
$var wire 32 C" acc_in [31:0] $end
$var wire 8 D" w [7:0] $end
$var wire 8 E" x [7:0] $end
$var wire 32 F" product_ext [31:0] $end
$var wire 16 G" product [15:0] $end
$var wire 32 H" acc_out [31:0] $end
$var parameter 32 I" ACC_WIDTH $end
$var parameter 32 J" DATA_WIDTH $end
$var parameter 64 K" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 L" i $end
$scope module u_mac $end
$var wire 32 M" acc_in [31:0] $end
$var wire 8 N" w [7:0] $end
$var wire 8 O" x [7:0] $end
$var wire 32 P" product_ext [31:0] $end
$var wire 16 Q" product [15:0] $end
$var wire 32 R" acc_out [31:0] $end
$var parameter 32 S" ACC_WIDTH $end
$var parameter 32 T" DATA_WIDTH $end
$var parameter 64 U" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 V" i $end
$scope module u_mac $end
$var wire 32 W" acc_in [31:0] $end
$var wire 8 X" w [7:0] $end
$var wire 8 Y" x [7:0] $end
$var wire 32 Z" product_ext [31:0] $end
$var wire 16 [" product [15:0] $end
$var wire 32 \" acc_out [31:0] $end
$var parameter 32 ]" ACC_WIDTH $end
$var parameter 32 ^" DATA_WIDTH $end
$var parameter 64 _" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 `" i $end
$scope module u_mac $end
$var wire 32 a" acc_in [31:0] $end
$var wire 8 b" w [7:0] $end
$var wire 8 c" x [7:0] $end
$var wire 32 d" product_ext [31:0] $end
$var wire 16 e" product [15:0] $end
$var wire 32 f" acc_out [31:0] $end
$var parameter 32 g" ACC_WIDTH $end
$var parameter 32 h" DATA_WIDTH $end
$var parameter 64 i" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 j" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 k" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 l" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 m" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 n" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 o" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 p" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 q" i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 r" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 s" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 t" node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 u" node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 v" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 w" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 x" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 y" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 z" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 {" node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_b $end
$var wire 8 |" bias [7:0] $end
$var wire 1 I clk $end
$var wire 1 J rst $end
$var wire 1 L start $end
$var wire 240 }" w_bus [239:0] $end
$var wire 240 ~" x_bus [239:0] $end
$var wire 64 !# x_group [63:0] $end
$var wire 64 "# w_group [63:0] $end
$var wire 32 ## final_acc [31:0] $end
$var wire 32 $# bias_ext [31:0] $end
$var wire 32 %# acc_next [31:0] $end
$var parameter 32 &# ACC_WIDTH $end
$var parameter 32 '# DATA_WIDTH $end
$var parameter 32 (# GROUPS $end
$var parameter 32 )# GROUP_INDEX_WIDTH $end
$var parameter 32 *# N_INPUTS $end
$var parameter 32 +# PARALLEL $end
$var reg 32 ,# acc [31:0] $end
$var reg 1 . busy $end
$var reg 1 ) done $end
$var reg 2 -# group_index [1:0] $end
$var reg 8 .# y [7:0] $end
$scope module u_mac8 $end
$var wire 32 /# acc_in [31:0] $end
$var wire 64 0# w_bus [63:0] $end
$var wire 64 1# x_bus [63:0] $end
$var wire 32 2# acc_out [31:0] $end
$var parameter 32 3# ACC_WIDTH $end
$var parameter 32 4# DATA_WIDTH $end
$var parameter 32 5# PARALLEL $end
$var parameter 32 6# TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 7# i $end
$scope module u_mac $end
$var wire 32 8# acc_in [31:0] $end
$var wire 8 9# w [7:0] $end
$var wire 8 :# x [7:0] $end
$var wire 32 ;# product_ext [31:0] $end
$var wire 16 <# product [15:0] $end
$var wire 32 =# acc_out [31:0] $end
$var parameter 32 ># ACC_WIDTH $end
$var parameter 32 ?# DATA_WIDTH $end
$var parameter 64 @# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 A# i $end
$scope module u_mac $end
$var wire 32 B# acc_in [31:0] $end
$var wire 8 C# w [7:0] $end
$var wire 8 D# x [7:0] $end
$var wire 32 E# product_ext [31:0] $end
$var wire 16 F# product [15:0] $end
$var wire 32 G# acc_out [31:0] $end
$var parameter 32 H# ACC_WIDTH $end
$var parameter 32 I# DATA_WIDTH $end
$var parameter 64 J# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 K# i $end
$scope module u_mac $end
$var wire 32 L# acc_in [31:0] $end
$var wire 8 M# w [7:0] $end
$var wire 8 N# x [7:0] $end
$var wire 32 O# product_ext [31:0] $end
$var wire 16 P# product [15:0] $end
$var wire 32 Q# acc_out [31:0] $end
$var parameter 32 R# ACC_WIDTH $end
$var parameter 32 S# DATA_WIDTH $end
$var parameter 64 T# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 U# i $end
$scope module u_mac $end
$var wire 32 V# acc_in [31:0] $end
$var wire 8 W# w [7:0] $end
$var wire 8 X# x [7:0] $end
$var wire 32 Y# product_ext [31:0] $end
$var wire 16 Z# product [15:0] $end
$var wire 32 [# acc_out [31:0] $end
$var parameter 32 \# ACC_WIDTH $end
$var parameter 32 ]# DATA_WIDTH $end
$var parameter 64 ^# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 _# i $end
$scope module u_mac $end
$var wire 32 `# acc_in [31:0] $end
$var wire 8 a# w [7:0] $end
$var wire 8 b# x [7:0] $end
$var wire 32 c# product_ext [31:0] $end
$var wire 16 d# product [15:0] $end
$var wire 32 e# acc_out [31:0] $end
$var parameter 32 f# ACC_WIDTH $end
$var parameter 32 g# DATA_WIDTH $end
$var parameter 64 h# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 i# i $end
$scope module u_mac $end
$var wire 32 j# acc_in [31:0] $end
$var wire 8 k# w [7:0] $end
$var wire 8 l# x [7:0] $end
$var wire 32 m# product_ext [31:0] $end
$var wire 16 n# product [15:0] $end
$var wire 32 o# acc_out [31:0] $end
$var parameter 32 p# ACC_WIDTH $end
$var parameter 32 q# DATA_WIDTH $end
$var parameter 64 r# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 s# i $end
$scope module u_mac $end
$var wire 32 t# acc_in [31:0] $end
$var wire 8 u# w [7:0] $end
$var wire 8 v# x [7:0] $end
$var wire 32 w# product_ext [31:0] $end
$var wire 16 x# product [15:0] $end
$var wire 32 y# acc_out [31:0] $end
$var parameter 32 z# ACC_WIDTH $end
$var parameter 32 {# DATA_WIDTH $end
$var parameter 64 |# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 }# i $end
$scope module u_mac $end
$var wire 32 ~# acc_in [31:0] $end
$var wire 8 !$ w [7:0] $end
$var wire 8 "$ x [7:0] $end
$var wire 32 #$ product_ext [31:0] $end
$var wire 16 $$ product [15:0] $end
$var wire 32 %$ acc_out [31:0] $end
$var parameter 32 &$ ACC_WIDTH $end
$var parameter 32 '$ DATA_WIDTH $end
$var parameter 64 ($ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 )$ i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 *$ i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 +$ i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 ,$ i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 -$ i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 .$ i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 /$ i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 0$ i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 1$ level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 2$ node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 3$ node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 4$ node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 5$ node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 6$ level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 7$ node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 8$ node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 9$ level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 :$ node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_c $end
$var wire 8 ;$ bias [7:0] $end
$var wire 1 I clk $end
$var wire 1 J rst $end
$var wire 1 M start $end
$var wire 160 <$ w_bus [159:0] $end
$var wire 160 =$ x_bus [159:0] $end
$var wire 128 >$ x_group [127:0] $end
$var wire 128 ?$ w_group [127:0] $end
$var wire 32 @$ final_acc [31:0] $end
$var wire 32 A$ bias_ext [31:0] $end
$var wire 32 B$ acc_next [31:0] $end
$var parameter 32 C$ ACC_WIDTH $end
$var parameter 32 D$ DATA_WIDTH $end
$var parameter 32 E$ GROUPS $end
$var parameter 32 F$ GROUP_INDEX_WIDTH $end
$var parameter 32 G$ N_INPUTS $end
$var parameter 32 H$ PARALLEL $end
$var reg 32 I$ acc [31:0] $end
$var reg 1 - busy $end
$var reg 1 ( done $end
$var reg 1 J$ group_index $end
$var reg 8 K$ y [7:0] $end
$scope module u_mac8 $end
$var wire 32 L$ acc_in [31:0] $end
$var wire 128 M$ w_bus [127:0] $end
$var wire 128 N$ x_bus [127:0] $end
$var wire 32 O$ acc_out [31:0] $end
$var parameter 32 P$ ACC_WIDTH $end
$var parameter 32 Q$ DATA_WIDTH $end
$var parameter 32 R$ PARALLEL $end
$var parameter 32 S$ TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 T$ i $end
$scope module u_mac $end
$var wire 32 U$ acc_in [31:0] $end
$var wire 8 V$ w [7:0] $end
$var wire 8 W$ x [7:0] $end
$var wire 32 X$ product_ext [31:0] $end
$var wire 16 Y$ product [15:0] $end
$var wire 32 Z$ acc_out [31:0] $end
$var parameter 32 [$ ACC_WIDTH $end
$var parameter 32 \$ DATA_WIDTH $end
$var parameter 64 ]$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 ^$ i $end
$scope module u_mac $end
$var wire 32 _$ acc_in [31:0] $end
$var wire 8 `$ w [7:0] $end
$var wire 8 a$ x [7:0] $end
$var wire 32 b$ product_ext [31:0] $end
$var wire 16 c$ product [15:0] $end
$var wire 32 d$ acc_out [31:0] $end
$var parameter 32 e$ ACC_WIDTH $end
$var parameter 32 f$ DATA_WIDTH $end
$var parameter 64 g$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 h$ i $end
$scope module u_mac $end
$var wire 32 i$ acc_in [31:0] $end
$var wire 8 j$ w [7:0] $end
$var wire 8 k$ x [7:0] $end
$var wire 32 l$ product_ext [31:0] $end
$var wire 16 m$ product [15:0] $end
$var wire 32 n$ acc_out [31:0] $end
$var parameter 32 o$ ACC_WIDTH $end
$var parameter 32 p$ DATA_WIDTH $end
$var parameter 64 q$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 r$ i $end
$scope module u_mac $end
$var wire 32 s$ acc_in [31:0] $end
$var wire 8 t$ w [7:0] $end
$var wire 8 u$ x [7:0] $end
$var wire 32 v$ product_ext [31:0] $end
$var wire 16 w$ product [15:0] $end
$var wire 32 x$ acc_out [31:0] $end
$var parameter 32 y$ ACC_WIDTH $end
$var parameter 32 z$ DATA_WIDTH $end
$var parameter 64 {$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 |$ i $end
$scope module u_mac $end
$var wire 32 }$ acc_in [31:0] $end
$var wire 8 ~$ w [7:0] $end
$var wire 8 !% x [7:0] $end
$var wire 32 "% product_ext [31:0] $end
$var wire 16 #% product [15:0] $end
$var wire 32 $% acc_out [31:0] $end
$var parameter 32 %% ACC_WIDTH $end
$var parameter 32 &% DATA_WIDTH $end
$var parameter 64 '% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 (% i $end
$scope module u_mac $end
$var wire 32 )% acc_in [31:0] $end
$var wire 8 *% w [7:0] $end
$var wire 8 +% x [7:0] $end
$var wire 32 ,% product_ext [31:0] $end
$var wire 16 -% product [15:0] $end
$var wire 32 .% acc_out [31:0] $end
$var parameter 32 /% ACC_WIDTH $end
$var parameter 32 0% DATA_WIDTH $end
$var parameter 64 1% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 2% i $end
$scope module u_mac $end
$var wire 32 3% acc_in [31:0] $end
$var wire 8 4% w [7:0] $end
$var wire 8 5% x [7:0] $end
$var wire 32 6% product_ext [31:0] $end
$var wire 16 7% product [15:0] $end
$var wire 32 8% acc_out [31:0] $end
$var parameter 32 9% ACC_WIDTH $end
$var parameter 32 :% DATA_WIDTH $end
$var parameter 64 ;% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 <% i $end
$scope module u_mac $end
$var wire 32 =% acc_in [31:0] $end
$var wire 8 >% w [7:0] $end
$var wire 8 ?% x [7:0] $end
$var wire 32 @% product_ext [31:0] $end
$var wire 16 A% product [15:0] $end
$var wire 32 B% acc_out [31:0] $end
$var parameter 32 C% ACC_WIDTH $end
$var parameter 32 D% DATA_WIDTH $end
$var parameter 64 E% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[8] $end
$var parameter 5 F% i $end
$scope module u_mac $end
$var wire 32 G% acc_in [31:0] $end
$var wire 8 H% w [7:0] $end
$var wire 8 I% x [7:0] $end
$var wire 32 J% product_ext [31:0] $end
$var wire 16 K% product [15:0] $end
$var wire 32 L% acc_out [31:0] $end
$var parameter 32 M% ACC_WIDTH $end
$var parameter 32 N% DATA_WIDTH $end
$var parameter 64 O% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[9] $end
$var parameter 5 P% i $end
$scope module u_mac $end
$var wire 32 Q% acc_in [31:0] $end
$var wire 8 R% w [7:0] $end
$var wire 8 S% x [7:0] $end
$var wire 32 T% product_ext [31:0] $end
$var wire 16 U% product [15:0] $end
$var wire 32 V% acc_out [31:0] $end
$var parameter 32 W% ACC_WIDTH $end
$var parameter 32 X% DATA_WIDTH $end
$var parameter 64 Y% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[10] $end
$var parameter 5 Z% i $end
$scope module u_mac $end
$var wire 32 [% acc_in [31:0] $end
$var wire 8 \% w [7:0] $end
$var wire 8 ]% x [7:0] $end
$var wire 32 ^% product_ext [31:0] $end
$var wire 16 _% product [15:0] $end
$var wire 32 `% acc_out [31:0] $end
$var parameter 32 a% ACC_WIDTH $end
$var parameter 32 b% DATA_WIDTH $end
$var parameter 64 c% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[11] $end
$var parameter 5 d% i $end
$scope module u_mac $end
$var wire 32 e% acc_in [31:0] $end
$var wire 8 f% w [7:0] $end
$var wire 8 g% x [7:0] $end
$var wire 32 h% product_ext [31:0] $end
$var wire 16 i% product [15:0] $end
$var wire 32 j% acc_out [31:0] $end
$var parameter 32 k% ACC_WIDTH $end
$var parameter 32 l% DATA_WIDTH $end
$var parameter 64 m% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[12] $end
$var parameter 5 n% i $end
$scope module u_mac $end
$var wire 32 o% acc_in [31:0] $end
$var wire 8 p% w [7:0] $end
$var wire 8 q% x [7:0] $end
$var wire 32 r% product_ext [31:0] $end
$var wire 16 s% product [15:0] $end
$var wire 32 t% acc_out [31:0] $end
$var parameter 32 u% ACC_WIDTH $end
$var parameter 32 v% DATA_WIDTH $end
$var parameter 64 w% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[13] $end
$var parameter 5 x% i $end
$scope module u_mac $end
$var wire 32 y% acc_in [31:0] $end
$var wire 8 z% w [7:0] $end
$var wire 8 {% x [7:0] $end
$var wire 32 |% product_ext [31:0] $end
$var wire 16 }% product [15:0] $end
$var wire 32 ~% acc_out [31:0] $end
$var parameter 32 !& ACC_WIDTH $end
$var parameter 32 "& DATA_WIDTH $end
$var parameter 64 #& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[14] $end
$var parameter 5 $& i $end
$scope module u_mac $end
$var wire 32 %& acc_in [31:0] $end
$var wire 8 && w [7:0] $end
$var wire 8 '& x [7:0] $end
$var wire 32 (& product_ext [31:0] $end
$var wire 16 )& product [15:0] $end
$var wire 32 *& acc_out [31:0] $end
$var parameter 32 +& ACC_WIDTH $end
$var parameter 32 ,& DATA_WIDTH $end
$var parameter 64 -& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[15] $end
$var parameter 5 .& i $end
$scope module u_mac $end
$var wire 32 /& acc_in [31:0] $end
$var wire 8 0& w [7:0] $end
$var wire 8 1& x [7:0] $end
$var wire 32 2& product_ext [31:0] $end
$var wire 16 3& product [15:0] $end
$var wire 32 4& acc_out [31:0] $end
$var parameter 32 5& ACC_WIDTH $end
$var parameter 32 6& DATA_WIDTH $end
$var parameter 64 7& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 8& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 9& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 :& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 ;& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 <& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 =& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 >& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 ?& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[8] $end
$var parameter 5 @& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[9] $end
$var parameter 5 A& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[10] $end
$var parameter 5 B& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[11] $end
$var parameter 5 C& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[12] $end
$var parameter 5 D& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[13] $end
$var parameter 5 E& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[14] $end
$var parameter 5 F& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[15] $end
$var parameter 5 G& i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 H& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 I& node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 J& node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 K& node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 L& node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 M& node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 N& node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 O& node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 P& node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 Q& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 R& node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 S& node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 T& node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 U& node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 V& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 W& node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 X& node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[3] $end
$var parameter 3 Y& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 Z& node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_d $end
$var wire 8 [& bias [7:0] $end
$var wire 1 I clk $end
$var wire 1 J rst $end
$var wire 1 N start $end
$var wire 512 \& w_bus [511:0] $end
$var wire 512 ]& x_bus [511:0] $end
$var wire 256 ^& x_group [255:0] $end
$var wire 256 _& w_group [255:0] $end
$var wire 32 `& final_acc [31:0] $end
$var wire 32 a& bias_ext [31:0] $end
$var wire 32 b& acc_next [31:0] $end
$var parameter 32 c& ACC_WIDTH $end
$var parameter 32 d& DATA_WIDTH $end
$var parameter 32 e& GROUPS $end
$var parameter 32 f& GROUP_INDEX_WIDTH $end
$var parameter 32 g& N_INPUTS $end
$var parameter 32 h& PARALLEL $end
$var reg 32 i& acc [31:0] $end
$var reg 1 , busy $end
$var reg 1 ' done $end
$var reg 1 j& group_index $end
$var reg 8 k& y [7:0] $end
$scope module u_mac8 $end
$var wire 32 l& acc_in [31:0] $end
$var wire 256 m& w_bus [255:0] $end
$var wire 256 n& x_bus [255:0] $end
$var wire 32 o& acc_out [31:0] $end
$var parameter 32 p& ACC_WIDTH $end
$var parameter 32 q& DATA_WIDTH $end
$var parameter 32 r& PARALLEL $end
$var parameter 32 s& TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 t& i $end
$scope module u_mac $end
$var wire 32 u& acc_in [31:0] $end
$var wire 8 v& w [7:0] $end
$var wire 8 w& x [7:0] $end
$var wire 32 x& product_ext [31:0] $end
$var wire 16 y& product [15:0] $end
$var wire 32 z& acc_out [31:0] $end
$var parameter 32 {& ACC_WIDTH $end
$var parameter 32 |& DATA_WIDTH $end
$var parameter 64 }& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 ~& i $end
$scope module u_mac $end
$var wire 32 !' acc_in [31:0] $end
$var wire 8 "' w [7:0] $end
$var wire 8 #' x [7:0] $end
$var wire 32 $' product_ext [31:0] $end
$var wire 16 %' product [15:0] $end
$var wire 32 &' acc_out [31:0] $end
$var parameter 32 '' ACC_WIDTH $end
$var parameter 32 (' DATA_WIDTH $end
$var parameter 64 )' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 *' i $end
$scope module u_mac $end
$var wire 32 +' acc_in [31:0] $end
$var wire 8 ,' w [7:0] $end
$var wire 8 -' x [7:0] $end
$var wire 32 .' product_ext [31:0] $end
$var wire 16 /' product [15:0] $end
$var wire 32 0' acc_out [31:0] $end
$var parameter 32 1' ACC_WIDTH $end
$var parameter 32 2' DATA_WIDTH $end
$var parameter 64 3' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 4' i $end
$scope module u_mac $end
$var wire 32 5' acc_in [31:0] $end
$var wire 8 6' w [7:0] $end
$var wire 8 7' x [7:0] $end
$var wire 32 8' product_ext [31:0] $end
$var wire 16 9' product [15:0] $end
$var wire 32 :' acc_out [31:0] $end
$var parameter 32 ;' ACC_WIDTH $end
$var parameter 32 <' DATA_WIDTH $end
$var parameter 64 =' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 >' i $end
$scope module u_mac $end
$var wire 32 ?' acc_in [31:0] $end
$var wire 8 @' w [7:0] $end
$var wire 8 A' x [7:0] $end
$var wire 32 B' product_ext [31:0] $end
$var wire 16 C' product [15:0] $end
$var wire 32 D' acc_out [31:0] $end
$var parameter 32 E' ACC_WIDTH $end
$var parameter 32 F' DATA_WIDTH $end
$var parameter 64 G' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 H' i $end
$scope module u_mac $end
$var wire 32 I' acc_in [31:0] $end
$var wire 8 J' w [7:0] $end
$var wire 8 K' x [7:0] $end
$var wire 32 L' product_ext [31:0] $end
$var wire 16 M' product [15:0] $end
$var wire 32 N' acc_out [31:0] $end
$var parameter 32 O' ACC_WIDTH $end
$var parameter 32 P' DATA_WIDTH $end
$var parameter 64 Q' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 R' i $end
$scope module u_mac $end
$var wire 32 S' acc_in [31:0] $end
$var wire 8 T' w [7:0] $end
$var wire 8 U' x [7:0] $end
$var wire 32 V' product_ext [31:0] $end
$var wire 16 W' product [15:0] $end
$var wire 32 X' acc_out [31:0] $end
$var parameter 32 Y' ACC_WIDTH $end
$var parameter 32 Z' DATA_WIDTH $end
$var parameter 64 [' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 \' i $end
$scope module u_mac $end
$var wire 32 ]' acc_in [31:0] $end
$var wire 8 ^' w [7:0] $end
$var wire 8 _' x [7:0] $end
$var wire 32 `' product_ext [31:0] $end
$var wire 16 a' product [15:0] $end
$var wire 32 b' acc_out [31:0] $end
$var parameter 32 c' ACC_WIDTH $end
$var parameter 32 d' DATA_WIDTH $end
$var parameter 64 e' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[8] $end
$var parameter 5 f' i $end
$scope module u_mac $end
$var wire 32 g' acc_in [31:0] $end
$var wire 8 h' w [7:0] $end
$var wire 8 i' x [7:0] $end
$var wire 32 j' product_ext [31:0] $end
$var wire 16 k' product [15:0] $end
$var wire 32 l' acc_out [31:0] $end
$var parameter 32 m' ACC_WIDTH $end
$var parameter 32 n' DATA_WIDTH $end
$var parameter 64 o' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[9] $end
$var parameter 5 p' i $end
$scope module u_mac $end
$var wire 32 q' acc_in [31:0] $end
$var wire 8 r' w [7:0] $end
$var wire 8 s' x [7:0] $end
$var wire 32 t' product_ext [31:0] $end
$var wire 16 u' product [15:0] $end
$var wire 32 v' acc_out [31:0] $end
$var parameter 32 w' ACC_WIDTH $end
$var parameter 32 x' DATA_WIDTH $end
$var parameter 64 y' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[10] $end
$var parameter 5 z' i $end
$scope module u_mac $end
$var wire 32 {' acc_in [31:0] $end
$var wire 8 |' w [7:0] $end
$var wire 8 }' x [7:0] $end
$var wire 32 ~' product_ext [31:0] $end
$var wire 16 !( product [15:0] $end
$var wire 32 "( acc_out [31:0] $end
$var parameter 32 #( ACC_WIDTH $end
$var parameter 32 $( DATA_WIDTH $end
$var parameter 64 %( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[11] $end
$var parameter 5 &( i $end
$scope module u_mac $end
$var wire 32 '( acc_in [31:0] $end
$var wire 8 (( w [7:0] $end
$var wire 8 )( x [7:0] $end
$var wire 32 *( product_ext [31:0] $end
$var wire 16 +( product [15:0] $end
$var wire 32 ,( acc_out [31:0] $end
$var parameter 32 -( ACC_WIDTH $end
$var parameter 32 .( DATA_WIDTH $end
$var parameter 64 /( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[12] $end
$var parameter 5 0( i $end
$scope module u_mac $end
$var wire 32 1( acc_in [31:0] $end
$var wire 8 2( w [7:0] $end
$var wire 8 3( x [7:0] $end
$var wire 32 4( product_ext [31:0] $end
$var wire 16 5( product [15:0] $end
$var wire 32 6( acc_out [31:0] $end
$var parameter 32 7( ACC_WIDTH $end
$var parameter 32 8( DATA_WIDTH $end
$var parameter 64 9( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[13] $end
$var parameter 5 :( i $end
$scope module u_mac $end
$var wire 32 ;( acc_in [31:0] $end
$var wire 8 <( w [7:0] $end
$var wire 8 =( x [7:0] $end
$var wire 32 >( product_ext [31:0] $end
$var wire 16 ?( product [15:0] $end
$var wire 32 @( acc_out [31:0] $end
$var parameter 32 A( ACC_WIDTH $end
$var parameter 32 B( DATA_WIDTH $end
$var parameter 64 C( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[14] $end
$var parameter 5 D( i $end
$scope module u_mac $end
$var wire 32 E( acc_in [31:0] $end
$var wire 8 F( w [7:0] $end
$var wire 8 G( x [7:0] $end
$var wire 32 H( product_ext [31:0] $end
$var wire 16 I( product [15:0] $end
$var wire 32 J( acc_out [31:0] $end
$var parameter 32 K( ACC_WIDTH $end
$var parameter 32 L( DATA_WIDTH $end
$var parameter 64 M( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[15] $end
$var parameter 5 N( i $end
$scope module u_mac $end
$var wire 32 O( acc_in [31:0] $end
$var wire 8 P( w [7:0] $end
$var wire 8 Q( x [7:0] $end
$var wire 32 R( product_ext [31:0] $end
$var wire 16 S( product [15:0] $end
$var wire 32 T( acc_out [31:0] $end
$var parameter 32 U( ACC_WIDTH $end
$var parameter 32 V( DATA_WIDTH $end
$var parameter 64 W( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[16] $end
$var parameter 6 X( i $end
$scope module u_mac $end
$var wire 32 Y( acc_in [31:0] $end
$var wire 8 Z( w [7:0] $end
$var wire 8 [( x [7:0] $end
$var wire 32 \( product_ext [31:0] $end
$var wire 16 ]( product [15:0] $end
$var wire 32 ^( acc_out [31:0] $end
$var parameter 32 _( ACC_WIDTH $end
$var parameter 32 `( DATA_WIDTH $end
$var parameter 64 a( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[17] $end
$var parameter 6 b( i $end
$scope module u_mac $end
$var wire 32 c( acc_in [31:0] $end
$var wire 8 d( w [7:0] $end
$var wire 8 e( x [7:0] $end
$var wire 32 f( product_ext [31:0] $end
$var wire 16 g( product [15:0] $end
$var wire 32 h( acc_out [31:0] $end
$var parameter 32 i( ACC_WIDTH $end
$var parameter 32 j( DATA_WIDTH $end
$var parameter 64 k( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[18] $end
$var parameter 6 l( i $end
$scope module u_mac $end
$var wire 32 m( acc_in [31:0] $end
$var wire 8 n( w [7:0] $end
$var wire 8 o( x [7:0] $end
$var wire 32 p( product_ext [31:0] $end
$var wire 16 q( product [15:0] $end
$var wire 32 r( acc_out [31:0] $end
$var parameter 32 s( ACC_WIDTH $end
$var parameter 32 t( DATA_WIDTH $end
$var parameter 64 u( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[19] $end
$var parameter 6 v( i $end
$scope module u_mac $end
$var wire 32 w( acc_in [31:0] $end
$var wire 8 x( w [7:0] $end
$var wire 8 y( x [7:0] $end
$var wire 32 z( product_ext [31:0] $end
$var wire 16 {( product [15:0] $end
$var wire 32 |( acc_out [31:0] $end
$var parameter 32 }( ACC_WIDTH $end
$var parameter 32 ~( DATA_WIDTH $end
$var parameter 64 !) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[20] $end
$var parameter 6 ") i $end
$scope module u_mac $end
$var wire 32 #) acc_in [31:0] $end
$var wire 8 $) w [7:0] $end
$var wire 8 %) x [7:0] $end
$var wire 32 &) product_ext [31:0] $end
$var wire 16 ') product [15:0] $end
$var wire 32 () acc_out [31:0] $end
$var parameter 32 )) ACC_WIDTH $end
$var parameter 32 *) DATA_WIDTH $end
$var parameter 64 +) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[21] $end
$var parameter 6 ,) i $end
$scope module u_mac $end
$var wire 32 -) acc_in [31:0] $end
$var wire 8 .) w [7:0] $end
$var wire 8 /) x [7:0] $end
$var wire 32 0) product_ext [31:0] $end
$var wire 16 1) product [15:0] $end
$var wire 32 2) acc_out [31:0] $end
$var parameter 32 3) ACC_WIDTH $end
$var parameter 32 4) DATA_WIDTH $end
$var parameter 64 5) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[22] $end
$var parameter 6 6) i $end
$scope module u_mac $end
$var wire 32 7) acc_in [31:0] $end
$var wire 8 8) w [7:0] $end
$var wire 8 9) x [7:0] $end
$var wire 32 :) product_ext [31:0] $end
$var wire 16 ;) product [15:0] $end
$var wire 32 <) acc_out [31:0] $end
$var parameter 32 =) ACC_WIDTH $end
$var parameter 32 >) DATA_WIDTH $end
$var parameter 64 ?) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[23] $end
$var parameter 6 @) i $end
$scope module u_mac $end
$var wire 32 A) acc_in [31:0] $end
$var wire 8 B) w [7:0] $end
$var wire 8 C) x [7:0] $end
$var wire 32 D) product_ext [31:0] $end
$var wire 16 E) product [15:0] $end
$var wire 32 F) acc_out [31:0] $end
$var parameter 32 G) ACC_WIDTH $end
$var parameter 32 H) DATA_WIDTH $end
$var parameter 64 I) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[24] $end
$var parameter 6 J) i $end
$scope module u_mac $end
$var wire 32 K) acc_in [31:0] $end
$var wire 8 L) w [7:0] $end
$var wire 8 M) x [7:0] $end
$var wire 32 N) product_ext [31:0] $end
$var wire 16 O) product [15:0] $end
$var wire 32 P) acc_out [31:0] $end
$var parameter 32 Q) ACC_WIDTH $end
$var parameter 32 R) DATA_WIDTH $end
$var parameter 64 S) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[25] $end
$var parameter 6 T) i $end
$scope module u_mac $end
$var wire 32 U) acc_in [31:0] $end
$var wire 8 V) w [7:0] $end
$var wire 8 W) x [7:0] $end
$var wire 32 X) product_ext [31:0] $end
$var wire 16 Y) product [15:0] $end
$var wire 32 Z) acc_out [31:0] $end
$var parameter 32 [) ACC_WIDTH $end
$var parameter 32 \) DATA_WIDTH $end
$var parameter 64 ]) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[26] $end
$var parameter 6 ^) i $end
$scope module u_mac $end
$var wire 32 _) acc_in [31:0] $end
$var wire 8 `) w [7:0] $end
$var wire 8 a) x [7:0] $end
$var wire 32 b) product_ext [31:0] $end
$var wire 16 c) product [15:0] $end
$var wire 32 d) acc_out [31:0] $end
$var parameter 32 e) ACC_WIDTH $end
$var parameter 32 f) DATA_WIDTH $end
$var parameter 64 g) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[27] $end
$var parameter 6 h) i $end
$scope module u_mac $end
$var wire 32 i) acc_in [31:0] $end
$var wire 8 j) w [7:0] $end
$var wire 8 k) x [7:0] $end
$var wire 32 l) product_ext [31:0] $end
$var wire 16 m) product [15:0] $end
$var wire 32 n) acc_out [31:0] $end
$var parameter 32 o) ACC_WIDTH $end
$var parameter 32 p) DATA_WIDTH $end
$var parameter 64 q) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[28] $end
$var parameter 6 r) i $end
$scope module u_mac $end
$var wire 32 s) acc_in [31:0] $end
$var wire 8 t) w [7:0] $end
$var wire 8 u) x [7:0] $end
$var wire 32 v) product_ext [31:0] $end
$var wire 16 w) product [15:0] $end
$var wire 32 x) acc_out [31:0] $end
$var parameter 32 y) ACC_WIDTH $end
$var parameter 32 z) DATA_WIDTH $end
$var parameter 64 {) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[29] $end
$var parameter 6 |) i $end
$scope module u_mac $end
$var wire 32 }) acc_in [31:0] $end
$var wire 8 ~) w [7:0] $end
$var wire 8 !* x [7:0] $end
$var wire 32 "* product_ext [31:0] $end
$var wire 16 #* product [15:0] $end
$var wire 32 $* acc_out [31:0] $end
$var parameter 32 %* ACC_WIDTH $end
$var parameter 32 &* DATA_WIDTH $end
$var parameter 64 '* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[30] $end
$var parameter 6 (* i $end
$scope module u_mac $end
$var wire 32 )* acc_in [31:0] $end
$var wire 8 ** w [7:0] $end
$var wire 8 +* x [7:0] $end
$var wire 32 ,* product_ext [31:0] $end
$var wire 16 -* product [15:0] $end
$var wire 32 .* acc_out [31:0] $end
$var parameter 32 /* ACC_WIDTH $end
$var parameter 32 0* DATA_WIDTH $end
$var parameter 64 1* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[31] $end
$var parameter 6 2* i $end
$scope module u_mac $end
$var wire 32 3* acc_in [31:0] $end
$var wire 8 4* w [7:0] $end
$var wire 8 5* x [7:0] $end
$var wire 32 6* product_ext [31:0] $end
$var wire 16 7* product [15:0] $end
$var wire 32 8* acc_out [31:0] $end
$var parameter 32 9* ACC_WIDTH $end
$var parameter 32 :* DATA_WIDTH $end
$var parameter 64 ;* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 <* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 =* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 >* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 ?* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 @* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 A* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 B* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 C* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[8] $end
$var parameter 5 D* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[9] $end
$var parameter 5 E* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[10] $end
$var parameter 5 F* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[11] $end
$var parameter 5 G* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[12] $end
$var parameter 5 H* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[13] $end
$var parameter 5 I* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[14] $end
$var parameter 5 J* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[15] $end
$var parameter 5 K* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[16] $end
$var parameter 6 L* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[17] $end
$var parameter 6 M* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[18] $end
$var parameter 6 N* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[19] $end
$var parameter 6 O* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[20] $end
$var parameter 6 P* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[21] $end
$var parameter 6 Q* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[22] $end
$var parameter 6 R* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[23] $end
$var parameter 6 S* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[24] $end
$var parameter 6 T* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[25] $end
$var parameter 6 U* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[26] $end
$var parameter 6 V* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[27] $end
$var parameter 6 W* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[28] $end
$var parameter 6 X* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[29] $end
$var parameter 6 Y* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[30] $end
$var parameter 6 Z* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[31] $end
$var parameter 6 [* i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 \* level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 ]* node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 ^* node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 _* node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 `* node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 a* node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 b* node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 c* node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 d* node $end
$upscope $end
$scope begin GEN_TREE_NODE[8] $end
$var parameter 5 e* node $end
$upscope $end
$scope begin GEN_TREE_NODE[9] $end
$var parameter 5 f* node $end
$upscope $end
$scope begin GEN_TREE_NODE[10] $end
$var parameter 5 g* node $end
$upscope $end
$scope begin GEN_TREE_NODE[11] $end
$var parameter 5 h* node $end
$upscope $end
$scope begin GEN_TREE_NODE[12] $end
$var parameter 5 i* node $end
$upscope $end
$scope begin GEN_TREE_NODE[13] $end
$var parameter 5 j* node $end
$upscope $end
$scope begin GEN_TREE_NODE[14] $end
$var parameter 5 k* node $end
$upscope $end
$scope begin GEN_TREE_NODE[15] $end
$var parameter 5 l* node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 m* level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 n* node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 o* node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 p* node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 q* node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 r* node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 s* node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 t* node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 u* node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 v* level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 w* node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 x* node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 y* node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 z* node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[3] $end
$var parameter 3 {* level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 |* node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 }* node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[4] $end
$var parameter 4 ~* level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 !+ node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_e $end
$var wire 8 "+ bias [7:0] $end
$var wire 1 I clk $end
$var wire 1 J rst $end
$var wire 1 O start $end
$var wire 32 #+ w_bus [31:0] $end
$var wire 32 $+ x_bus [31:0] $end
$var wire 64 %+ x_group [63:0] $end
$var wire 64 &+ w_group [63:0] $end
$var wire 32 '+ final_acc [31:0] $end
$var wire 32 (+ bias_ext [31:0] $end
$var wire 32 )+ acc_next [31:0] $end
$var parameter 32 *+ ACC_WIDTH $end
$var parameter 32 ++ DATA_WIDTH $end
$var parameter 32 ,+ GROUPS $end
$var parameter 32 -+ GROUP_INDEX_WIDTH $end
$var parameter 32 .+ N_INPUTS $end
$var parameter 32 /+ PARALLEL $end
$var reg 32 0+ acc [31:0] $end
$var reg 1 + busy $end
$var reg 1 & done $end
$var reg 1 1+ group_index $end
$var reg 8 2+ y [7:0] $end
$scope module u_mac8 $end
$var wire 32 3+ acc_in [31:0] $end
$var wire 64 4+ w_bus [63:0] $end
$var wire 64 5+ x_bus [63:0] $end
$var wire 32 6+ acc_out [31:0] $end
$var parameter 32 7+ ACC_WIDTH $end
$var parameter 32 8+ DATA_WIDTH $end
$var parameter 32 9+ PARALLEL $end
$var parameter 32 :+ TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 ;+ i $end
$scope module u_mac $end
$var wire 32 <+ acc_in [31:0] $end
$var wire 8 =+ w [7:0] $end
$var wire 8 >+ x [7:0] $end
$var wire 32 ?+ product_ext [31:0] $end
$var wire 16 @+ product [15:0] $end
$var wire 32 A+ acc_out [31:0] $end
$var parameter 32 B+ ACC_WIDTH $end
$var parameter 32 C+ DATA_WIDTH $end
$var parameter 64 D+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 E+ i $end
$scope module u_mac $end
$var wire 32 F+ acc_in [31:0] $end
$var wire 8 G+ w [7:0] $end
$var wire 8 H+ x [7:0] $end
$var wire 32 I+ product_ext [31:0] $end
$var wire 16 J+ product [15:0] $end
$var wire 32 K+ acc_out [31:0] $end
$var parameter 32 L+ ACC_WIDTH $end
$var parameter 32 M+ DATA_WIDTH $end
$var parameter 64 N+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 O+ i $end
$scope module u_mac $end
$var wire 32 P+ acc_in [31:0] $end
$var wire 8 Q+ w [7:0] $end
$var wire 8 R+ x [7:0] $end
$var wire 32 S+ product_ext [31:0] $end
$var wire 16 T+ product [15:0] $end
$var wire 32 U+ acc_out [31:0] $end
$var parameter 32 V+ ACC_WIDTH $end
$var parameter 32 W+ DATA_WIDTH $end
$var parameter 64 X+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 Y+ i $end
$scope module u_mac $end
$var wire 32 Z+ acc_in [31:0] $end
$var wire 8 [+ w [7:0] $end
$var wire 8 \+ x [7:0] $end
$var wire 32 ]+ product_ext [31:0] $end
$var wire 16 ^+ product [15:0] $end
$var wire 32 _+ acc_out [31:0] $end
$var parameter 32 `+ ACC_WIDTH $end
$var parameter 32 a+ DATA_WIDTH $end
$var parameter 64 b+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 c+ i $end
$scope module u_mac $end
$var wire 32 d+ acc_in [31:0] $end
$var wire 8 e+ w [7:0] $end
$var wire 8 f+ x [7:0] $end
$var wire 32 g+ product_ext [31:0] $end
$var wire 16 h+ product [15:0] $end
$var wire 32 i+ acc_out [31:0] $end
$var parameter 32 j+ ACC_WIDTH $end
$var parameter 32 k+ DATA_WIDTH $end
$var parameter 64 l+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 m+ i $end
$scope module u_mac $end
$var wire 32 n+ acc_in [31:0] $end
$var wire 8 o+ w [7:0] $end
$var wire 8 p+ x [7:0] $end
$var wire 32 q+ product_ext [31:0] $end
$var wire 16 r+ product [15:0] $end
$var wire 32 s+ acc_out [31:0] $end
$var parameter 32 t+ ACC_WIDTH $end
$var parameter 32 u+ DATA_WIDTH $end
$var parameter 64 v+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 w+ i $end
$scope module u_mac $end
$var wire 32 x+ acc_in [31:0] $end
$var wire 8 y+ w [7:0] $end
$var wire 8 z+ x [7:0] $end
$var wire 32 {+ product_ext [31:0] $end
$var wire 16 |+ product [15:0] $end
$var wire 32 }+ acc_out [31:0] $end
$var parameter 32 ~+ ACC_WIDTH $end
$var parameter 32 !, DATA_WIDTH $end
$var parameter 64 ", PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 #, i $end
$scope module u_mac $end
$var wire 32 $, acc_in [31:0] $end
$var wire 8 %, w [7:0] $end
$var wire 8 &, x [7:0] $end
$var wire 32 ', product_ext [31:0] $end
$var wire 16 (, product [15:0] $end
$var wire 32 ), acc_out [31:0] $end
$var parameter 32 *, ACC_WIDTH $end
$var parameter 32 +, DATA_WIDTH $end
$var parameter 64 ,, PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 -, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 ., i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 /, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 0, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 1, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 2, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 3, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 4, i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 5, level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 6, node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 7, node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 8, node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 9, node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 :, level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 ;, node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 <, node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 =, level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 >, node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b0 >,
b10 =,
b1 <,
b0 ;,
b1 :,
b11 9,
b10 8,
b1 7,
b0 6,
b0 5,
b111 4,
b110 3,
b101 2,
b100 1,
b11 0,
b10 /,
b1 .,
b0 -,
b10000 ,,
b1000 +,
b100000 *,
b111 #,
b10000 ",
b1000 !,
b100000 ~+
b110 w+
b10000 v+
b1000 u+
b100000 t+
b101 m+
b10000 l+
b1000 k+
b100000 j+
b100 c+
b10000 b+
b1000 a+
b100000 `+
b11 Y+
b10000 X+
b1000 W+
b100000 V+
b10 O+
b10000 N+
b1000 M+
b100000 L+
b1 E+
b10000 D+
b1000 C+
b100000 B+
b0 ;+
b11 :+
b1000 9+
b1000 8+
b100000 7+
b1000 /+
b100 .+
b1 -+
b0 ,+
b1000 ++
b100000 *+
b0 !+
b100 ~*
b1 }*
b0 |*
b11 {*
b11 z*
b10 y*
b1 x*
b0 w*
b10 v*
b111 u*
b110 t*
b101 s*
b100 r*
b11 q*
b10 p*
b1 o*
b0 n*
b1 m*
b1111 l*
b1110 k*
b1101 j*
b1100 i*
b1011 h*
b1010 g*
b1001 f*
b1000 e*
b111 d*
b110 c*
b101 b*
b100 a*
b11 `*
b10 _*
b1 ^*
b0 ]*
b0 \*
b11111 [*
b11110 Z*
b11101 Y*
b11100 X*
b11011 W*
b11010 V*
b11001 U*
b11000 T*
b10111 S*
b10110 R*
b10101 Q*
b10100 P*
b10011 O*
b10010 N*
b10001 M*
b10000 L*
b1111 K*
b1110 J*
b1101 I*
b1100 H*
b1011 G*
b1010 F*
b1001 E*
b1000 D*
b111 C*
b110 B*
b101 A*
b100 @*
b11 ?*
b10 >*
b1 =*
b0 <*
b10000 ;*
b1000 :*
b100000 9*
b11111 2*
b10000 1*
b1000 0*
b100000 /*
b11110 (*
b10000 '*
b1000 &*
b100000 %*
b11101 |)
b10000 {)
b1000 z)
b100000 y)
b11100 r)
b10000 q)
b1000 p)
b100000 o)
b11011 h)
b10000 g)
b1000 f)
b100000 e)
b11010 ^)
b10000 ])
b1000 \)
b100000 [)
b11001 T)
b10000 S)
b1000 R)
b100000 Q)
b11000 J)
b10000 I)
b1000 H)
b100000 G)
b10111 @)
b10000 ?)
b1000 >)
b100000 =)
b10110 6)
b10000 5)
b1000 4)
b100000 3)
b10101 ,)
b10000 +)
b1000 *)
b100000 ))
b10100 ")
b10000 !)
b1000 ~(
b100000 }(
b10011 v(
b10000 u(
b1000 t(
b100000 s(
b10010 l(
b10000 k(
b1000 j(
b100000 i(
b10001 b(
b10000 a(
b1000 `(
b100000 _(
b10000 X(
b10000 W(
b1000 V(
b100000 U(
b1111 N(
b10000 M(
b1000 L(
b100000 K(
b1110 D(
b10000 C(
b1000 B(
b100000 A(
b1101 :(
b10000 9(
b1000 8(
b100000 7(
b1100 0(
b10000 /(
b1000 .(
b100000 -(
b1011 &(
b10000 %(
b1000 $(
b100000 #(
b1010 z'
b10000 y'
b1000 x'
b100000 w'
b1001 p'
b10000 o'
b1000 n'
b100000 m'
b1000 f'
b10000 e'
b1000 d'
b100000 c'
b111 \'
b10000 ['
b1000 Z'
b100000 Y'
b110 R'
b10000 Q'
b1000 P'
b100000 O'
b101 H'
b10000 G'
b1000 F'
b100000 E'
b100 >'
b10000 ='
b1000 <'
b100000 ;'
b11 4'
b10000 3'
b1000 2'
b100000 1'
b10 *'
b10000 )'
b1000 ('
b100000 ''
b1 ~&
b10000 }&
b1000 |&
b100000 {&
b0 t&
b101 s&
b100000 r&
b1000 q&
b100000 p&
b100000 h&
b1000000 g&
b1 f&
b10 e&
b1000 d&
b100000 c&
b0 Z&
b11 Y&
b1 X&
b0 W&
b10 V&
b11 U&
b10 T&
b1 S&
b0 R&
b1 Q&
b111 P&
b110 O&
b101 N&
b100 M&
b11 L&
b10 K&
b1 J&
b0 I&
b0 H&
b1111 G&
b1110 F&
b1101 E&
b1100 D&
b1011 C&
b1010 B&
b1001 A&
b1000 @&
b111 ?&
b110 >&
b101 =&
b100 <&
b11 ;&
b10 :&
b1 9&
b0 8&
b10000 7&
b1000 6&
b100000 5&
b1111 .&
b10000 -&
b1000 ,&
b100000 +&
b1110 $&
b10000 #&
b1000 "&
b100000 !&
b1101 x%
b10000 w%
b1000 v%
b100000 u%
b1100 n%
b10000 m%
b1000 l%
b100000 k%
b1011 d%
b10000 c%
b1000 b%
b100000 a%
b1010 Z%
b10000 Y%
b1000 X%
b100000 W%
b1001 P%
b10000 O%
b1000 N%
b100000 M%
b1000 F%
b10000 E%
b1000 D%
b100000 C%
b111 <%
b10000 ;%
b1000 :%
b100000 9%
b110 2%
b10000 1%
b1000 0%
b100000 /%
b101 (%
b10000 '%
b1000 &%
b100000 %%
b100 |$
b10000 {$
b1000 z$
b100000 y$
b11 r$
b10000 q$
b1000 p$
b100000 o$
b10 h$
b10000 g$
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b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ?$
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