/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Executing script file `synth/ecp5/act_buffer/synth.ys' -- 1. Executing Verilog-2005 frontend: rtl/act_buffer.v Parsing SystemVerilog input from `rtl/act_buffer.v' to AST representation. Generating RTLIL representation for module `\act_buffer'. Successfully finished Verilog frontend. 2. Executing SYNTH_LATTICE pass. 2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 2.3. Executing HIERARCHY pass (managing design hierarchy). 2.3.1. Analyzing design hierarchy.. Top module: \act_buffer 2.3.2. Analyzing design hierarchy.. Top module: \act_buffer Removed 0 unused modules. 2.4. Executing PROC pass (convert processes to netlists). 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$rtl/act_buffer.v:55$2 in module act_buffer. Removed a total of 0 dead cases. 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 4 assignments to connections. 2.4.4. Executing PROC_INIT pass (extract init attributes). 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\act_buffer.$proc$rtl/act_buffer.v:60$9'. Creating decoders for process `\act_buffer.$proc$rtl/act_buffer.v:55$2'. 1/3: $1$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$8 2/3: $1$memwr$\mem$rtl/act_buffer.v:57$1_DATA[7:0]$7 3/3: $1$memwr$\mem$rtl/act_buffer.v:57$1_ADDR[11:0]$6 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\act_buffer.\rd_data' using process `\act_buffer.$proc$rtl/act_buffer.v:60$9'. created $dff cell `$procdff$245' with positive edge clock. Creating register for signal `\act_buffer.$memwr$\mem$rtl/act_buffer.v:57$1_ADDR' using process `\act_buffer.$proc$rtl/act_buffer.v:55$2'. created $dff cell `$procdff$246' with positive edge clock. Creating register for signal `\act_buffer.$memwr$\mem$rtl/act_buffer.v:57$1_DATA' using process `\act_buffer.$proc$rtl/act_buffer.v:55$2'. created $dff cell `$procdff$247' with positive edge clock. Creating register for signal `\act_buffer.$memwr$\mem$rtl/act_buffer.v:57$1_EN' using process `\act_buffer.$proc$rtl/act_buffer.v:55$2'. created $dff cell `$procdff$248' with positive edge clock. 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `act_buffer.$proc$rtl/act_buffer.v:60$9'. Found and cleaned up 1 empty switch in `\act_buffer.$proc$rtl/act_buffer.v:55$2'. Removing empty process `act_buffer.$proc$rtl/act_buffer.v:55$2'. Cleaned up 1 empty switch. 2.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.5. Executing CHECK pass (checking for obvious problems). Checking module act_buffer... Found and reported 0 problems. 2.6. Executing FLATTEN pass (flatten design). 2.7. Executing TRIBUF pass. 2.8. Executing DEMINOUT pass (demote inout ports to input or output). 2.9. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. Removed 3 unused cells and 13 unused wires. 2.11. Executing CHECK pass (checking for obvious problems). Checking module act_buffer... Found and reported 0 problems. 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 6 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \act_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \act_buffer. Consolidated identical input bits for $mux cell $procmux$237: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [0] New connections: $0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [7:1] = { $0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [0] $0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [0] $0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [0] $0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [0] $0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [0] $0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [0] $0$memwr$\mem$rtl/act_buffer.v:57$1_EN[7:0]$5 [0] } Optimizing cells in module \act_buffer. Performed a total of 1 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 6 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \act_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \act_buffer. Performed a total of 0 changes. 2.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 6 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.12.16. Finished fast OPT passes. (There is nothing left to do.) 2.13. Executing FSM pass (extract and optimize FSM). 2.13.1. Executing FSM_DETECT pass (finding FSMs in design). 2.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.14. Executing OPT pass (performing simple optimizations). 2.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 6 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \act_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \act_buffer. Performed a total of 0 changes. 2.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 6 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.14.6. Executing OPT_DFF pass (perform DFF optimizations). 2.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.14.9. Finished fast OPT passes. (There is nothing left to do.) 2.15. Executing WREDUCE pass (reducing word size of cells). 2.16. Executing PEEPOPT pass (run peephole optimizers). 2.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.18. Executing SHARE pass (SAT-based resource sharing). 2.19. Executing TECHMAP pass (map to technology primitives). 2.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.19.2. Continuing TECHMAP pass. No more expansions possible. 2.20. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.22. Executing TECHMAP pass (map to technology primitives). 2.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 2.22.2. Continuing TECHMAP pass. No more expansions possible. 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 2.23.2. Continuing TECHMAP pass. No more expansions possible. 2.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module act_buffer: created 0 $alu and 0 $macc cells. 2.25. Executing OPT pass (performing simple optimizations). 2.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 6 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \act_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \act_buffer. Performed a total of 0 changes. 2.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 6 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.25.6. Executing OPT_DFF pass (perform DFF optimizations). 2.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.25.9. Finished fast OPT passes. (There is nothing left to do.) 2.26. Executing MEMORY pass. 2.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing act_buffer.mem write port 0. 2.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\mem'[0] in module `\act_buffer': merging output FF to cell. Write port 0: non-transparent. 2.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. Removed 1 unused cells and 9 unused wires. 2.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory act_buffer.mem via $__DP16KD_ 2.29. Executing TECHMAP pass (map to technology primitives). 2.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 2.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 2.29.3. Continuing TECHMAP pass. Using template $paramod$c4aea9a221b3d95ca47d9df3d018cdac65e6baac$__DP16KD_ for cells of type $__DP16KD_. No more expansions possible. 2.30. Executing OPT pass (performing simple optimizations). 2.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 10 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.30.3. Executing OPT_DFF pass (perform DFF optimizations). Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$267 ($dffe) from module act_buffer. 2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. Removed 0 unused cells and 51 unused wires. 2.30.5. Rerunning OPT passes. (Removed registers in this run.) 2.30.6. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.30.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 10 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.30.8. Executing OPT_DFF pass (perform DFF optimizations). 2.30.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.30.10. Finished fast OPT passes. 2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.32. Executing OPT pass (performing simple optimizations). 2.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 10 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \act_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \act_buffer. Performed a total of 0 changes. 2.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 10 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.32.6. Executing OPT_DFF pass (perform DFF optimizations). 2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.32.9. Finished fast OPT passes. (There is nothing left to do.) 2.33. Executing TECHMAP pass (map to technology primitives). 2.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 2.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $eq. No more expansions possible. 2.34. Executing OPT pass (performing simple optimizations). 2.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 65 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.34.3. Executing OPT_DFF pass (perform DFF optimizations). 2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. Removed 0 unused cells and 1 unused wires. 2.34.5. Finished fast OPT passes. 2.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. 2.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.37. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\act_buffer'. Computing hashes of 65 cells of `\act_buffer'. Finding duplicate cells in `\act_buffer'. Removed a total of 0 cells. 2.38. Executing TECHMAP pass (map to technology primitives). 2.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.38.2. Continuing TECHMAP pass. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. No more expansions possible. 2.39. Executing OPT_EXPR pass (perform const folding). Optimizing module act_buffer. 2.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.41. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in act_buffer. 2.42. Executing ATTRMVCP pass (move or copy attributes). 2.43. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \act_buffer.. Removed 0 unused cells and 120 unused wires. 2.44. Executing CHECK pass (checking for obvious problems). Checking module act_buffer... Found and reported 0 problems. 2.45. Executing TECHMAP pass (map to technology primitives). 2.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 2.45.2. Continuing TECHMAP pass. No more expansions possible. 2.46. Executing ABC9 pass. 2.46.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.46.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.46.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module act_buffer. Found 0 SCCs. 2.46.4. Executing ABC9_OPS pass (helper functions for ABC9). 2.46.5. Executing TECHMAP pass (map to technology primitives). 2.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.46.5.2. Continuing TECHMAP pass. No more expansions possible. 2.46.6. Executing OPT pass (performing simple optimizations). 2.46.6.1. Executing OPT_EXPR pass (perform const folding). 2.46.6.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 2.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 2.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 2.46.6.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 2.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). 2.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2.46.6.8. Executing OPT_EXPR pass (perform const folding). 2.46.6.9. Finished fast OPT passes. (There is nothing left to do.) 2.46.7. Executing TECHMAP pass (map to technology primitives). 2.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 2.46.7.2. Continuing TECHMAP pass. No more expansions possible. 2.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 2.46.9. Executing ABC9_OPS pass (helper functions for ABC9). 2.46.10. Executing ABC9_OPS pass (helper functions for ABC9). 2.46.11. Executing ABC9_OPS pass (helper functions for ABC9). 2.46.12. Executing AIGMAP pass (map logic to AIG). Module act_buffer: replaced 31 cells with 184 new cells, skipped 34 cells. replaced 3 cell types: 8 $_MUX_ 11 $_OR_ 12 $_XOR_ not replaced 4 cell types: 1 $_AND_ 1 $_NOT_ 30 TRELLIS_FF 2 DP16KD 2.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.46.12.3. Executing XAIGER backend. Extracted 72 AND gates and 260 wires from module `act_buffer' to a netlist network with 72 inputs and 30 outputs. 2.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). 2.46.12.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 72/ 30 and = 72 lev = 7 (0.77) mem = 0.00 MB box = 0 bb = 0 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 72/ 30 and = 99 lev = 6 (0.73) mem = 0.00 MB ch = 9 box = 0 bb = 0 ABC: cst = 0 cls = 9 lit = 9 unused = 153 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 99. Ch = 9. Total mem = 0.03 MB. Peak cut mem = 0.01 MB. ABC: P: Del = 1756.00. Ar = 43.0. Edge = 76. Cut = 391. T = 0.00 sec ABC: P: Del = 1756.00. Ar = 43.0. Edge = 76. Cut = 390. T = 0.00 sec ABC: P: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 505. T = 0.00 sec ABC: F: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 348. T = 0.00 sec ABC: A: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 347. T = 0.00 sec ABC: A: Del = 1756.00. Ar = 37.0. Edge = 76. Cut = 342. T = 0.00 sec ABC: Total time = 0.00 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: Timing manager is given but there is no GIA of boxes. ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. ABC: + &ps -l ABC: /input : i/o = 72/ 30 and = 72 lev = 6 (0.73) mem = 0.00 MB box = 0 bb = 0 ABC: Mapping (K=7) : lut = 20 edge = 76 lev = 3 (0.37) mem = 0.00 MB ABC: LUT = 20 : 2=3 15.0 % 3=8 40.0 % 4=4 20.0 % 5=1 5.0 % 6=3 15.0 % 7=1 5.0 % Ave = 3.80 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.00 sec ABC: + time ABC: elapse: 0.01 seconds, total: 0.01 seconds 2.46.12.6. Executing AIGER frontend. Removed 119 unused cells and 200 unused wires. 2.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 20 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 5 Removing temp directory. 2.46.13. Executing TECHMAP pass (map to technology primitives). 2.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 2.46.13.2. Continuing TECHMAP pass. No more expansions possible. Removed 8 unused cells and 290 unused wires. 2.47. Executing TECHMAP pass (map to technology primitives). 2.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 2.47.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut. Using template $paramod$fe6a5d9c4f188f47ec07e4f5827baa5f3bf54c47$lut for cells of type $lut. Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673$lut for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$96f88ffdf52d3059c17d970c5fe3f19815bfce25$lut for cells of type $lut. Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86$lut for cells of type $lut. Using template $paramod$233b70872b0d11ad6386b65bc4d8864ac02395bb$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$977bf81c91b9e0cdfe901822d1642d278c1b0ecd$lut for cells of type $lut. Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd$lut for cells of type $lut. No more expansions possible. 2.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in act_buffer. Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$1122$lut$aiger1121$100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$83.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$1122$lut$aiger1121$90.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$1122$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 51 unused wires. 2.49. Executing AUTONAME pass. Renamed 149 objects in module act_buffer. 2.50. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `act_buffer'. Setting top module to act_buffer. 2.50.1. Analyzing design hierarchy.. Top module: \act_buffer 2.50.2. Analyzing design hierarchy.. Top module: \act_buffer Removed 0 unused modules. 2.51. Printing statistics. === act_buffer === +----------Local Count, excluding submodules. | 71 wires 229 wire bits 71 public wires 229 public wire bits 6 ports 42 port bits 2 cells 2 DP16KD 84 submodules 6 L6MUX21 37 LUT4 11 PFUMX 30 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 2 act_buffer +----------Count including submodules. | 71 wires 229 wire bits 71 public wires 229 public wire bits 6 ports 42 port bits - memories - memory bits - processes 2 cells 2 DP16KD 84 submodules 6 L6MUX21 37 LUT4 11 PFUMX 30 TRELLIS_FF 2.52. Executing CHECK pass (checking for obvious problems). Checking module act_buffer... Found and reported 0 problems. 2.53. Executing JSON backend. 3. Printing statistics. === act_buffer === +----------Local Count, excluding submodules. | 71 wires 229 wire bits 71 public wires 229 public wire bits 6 ports 42 port bits 86 cells 2 DP16KD 6 L6MUX21 37 LUT4 11 PFUMX 30 TRELLIS_FF End of script. Logfile hash: cbd0193588, time: 0.31s, user: 0.28s, system: 0.01s, MEM: 29.52 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 56% 20x read_verilog (0 sec), 23% 11x techmap (0 sec), ...