/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Parsing `hardware/v2/rtl/dependency_manager.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: hardware/v2/rtl/dependency_manager.v Parsing Verilog input from `hardware/v2/rtl/dependency_manager.v' to AST representation. Storing AST representation for module `$abstract\dependency_manager'. Successfully finished Verilog frontend. -- Running command `synth_ecp5 -json hardware/v2/synthesis/dependency_manager_n16/top.json -top dependency_manager' -- 2. Executing SYNTH_LATTICE pass. 2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 2.3. Executing HIERARCHY pass (managing design hierarchy). 2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\dependency_manager'. Generating RTLIL representation for module `\dependency_manager'. 2.4.1. Analyzing design hierarchy.. Top module: \dependency_manager 2.4.2. Analyzing design hierarchy.. Top module: \dependency_manager Removing unused module `$abstract\dependency_manager'. Removed 1 unused modules. 2.5. Executing PROC pass (convert processes to netlists). 2.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 148 switch rules as full_case in process $proc$hardware/v2/rtl/dependency_manager.v:116$454 in module dependency_manager. Marked 16 switch rules as full_case in process $proc$hardware/v2/rtl/dependency_manager.v:103$421 in module dependency_manager. Removed a total of 0 dead cases. 2.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 279 assignments to connections. 2.5.4. Executing PROC_INIT pass (extract init attributes). 2.5.5. Executing PROC_ARST pass (detect async resets in processes). 2.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. 1/975: $2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_EN[1:0]$2424 2/975: $2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_ADDR[3:0]$2423 3/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$2419 4/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$2414 5/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_DATA[2:0]$2413 6/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$2412 7/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$2404 8/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$2399 9/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_DATA[2:0]$2398 10/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$2397 11/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$2389 12/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$2384 13/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_DATA[2:0]$2383 14/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$2382 15/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$2374 16/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$2369 17/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_DATA[2:0]$2368 18/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$2367 19/975: $19\di[31:0] 20/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$2361 21/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_DATA[2:0]$2360 22/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$2359 23/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$2358 24/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_DATA[2:0]$2357 25/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$2356 26/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$2355 27/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_DATA[2:0]$2354 28/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$2353 29/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$2352 30/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_DATA[2:0]$2351 31/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$2350 32/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$2345 33/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$2340 34/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_DATA[2:0]$2339 35/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$2338 36/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$2330 37/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$2325 38/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_DATA[2:0]$2324 39/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$2323 40/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$2315 41/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$2310 42/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_DATA[2:0]$2309 43/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$2308 44/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$2300 45/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$2295 46/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_DATA[2:0]$2294 47/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$2293 48/975: $18\di[31:0] 49/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$2287 50/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_DATA[2:0]$2286 51/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$2285 52/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$2284 53/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_DATA[2:0]$2283 54/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$2282 55/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$2281 56/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_DATA[2:0]$2280 57/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$2279 58/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$2278 59/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_DATA[2:0]$2277 60/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$2276 61/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$2271 62/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$2266 63/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_DATA[2:0]$2265 64/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$2264 65/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$2256 66/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$2251 67/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_DATA[2:0]$2250 68/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$2249 69/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$2241 70/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$2236 71/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_DATA[2:0]$2235 72/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$2234 73/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$2226 74/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$2221 75/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_DATA[2:0]$2220 76/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$2219 77/975: $17\di[31:0] 78/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$2213 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$1$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$809 937/975: $1$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_EN[1:0]$808 938/975: $1$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_DATA[1:0]$807 939/975: $1$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_ADDR[3:0]$806 940/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN[3:0]$805 941/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_DATA[3:0]$804 942/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_ADDR[31:0]$803 943/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN[3:0]$802 944/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_DATA[3:0]$801 945/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_ADDR[31:0]$800 946/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN[3:0]$799 947/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_DATA[3:0]$798 948/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_ADDR[31:0]$797 949/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN[3:0]$796 950/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_DATA[3:0]$795 951/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_ADDR[31:0]$794 952/975: $1$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$793 953/975: $1$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_DATA[22:0]$792 954/975: $1$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_ADDR[3:0]$791 955/975: $1$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$790 956/975: $1$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_DATA[15:0]$789 957/975: $1$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_ADDR[3:0]$788 958/975: $1$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$787 959/975: $1$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_DATA[22:0]$786 960/975: $1$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_ADDR[3:0]$785 961/975: $1$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$784 962/975: $1$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_DATA[22:0]$783 963/975: $1$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_ADDR[3:0]$782 964/975: $1$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_EN[2:0]$781 965/975: $1$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_ADDR[3:0]$780 966/975: $1$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_EN[2:0]$779 967/975: $1$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_DATA[2:0]$778 968/975: $1$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_ADDR[3:0]$777 969/975: $1\di[31:0] 970/975: $0\ready_result_addr[22:0] 971/975: $0\ready_n_tiles[15:0] 972/975: $0\ready_w_base[22:0] 973/975: $0\ready_x_base[22:0] 974/975: $0\ready_node_id[3:0] 975/975: $0\ready_valid[0:0] Creating decoders for process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$421'. 1/32: $16\any_ready[0:0] 2/32: $16\first_ready_idx[3:0] 3/32: $15\any_ready[0:0] 4/32: $15\first_ready_idx[3:0] 5/32: $14\any_ready[0:0] 6/32: $14\first_ready_idx[3:0] 7/32: $13\any_ready[0:0] 8/32: $13\first_ready_idx[3:0] 9/32: $12\any_ready[0:0] 10/32: $12\first_ready_idx[3:0] 11/32: $11\any_ready[0:0] 12/32: $11\first_ready_idx[3:0] 13/32: $10\any_ready[0:0] 14/32: $10\first_ready_idx[3:0] 15/32: $9\any_ready[0:0] 16/32: $9\first_ready_idx[3:0] 17/32: $8\any_ready[0:0] 18/32: $8\first_ready_idx[3:0] 19/32: $7\any_ready[0:0] 20/32: $7\first_ready_idx[3:0] 21/32: $6\any_ready[0:0] 22/32: $6\first_ready_idx[3:0] 23/32: $5\any_ready[0:0] 24/32: $5\first_ready_idx[3:0] 25/32: $4\any_ready[0:0] 26/32: $4\first_ready_idx[3:0] 27/32: $3\any_ready[0:0] 28/32: $3\first_ready_idx[3:0] 29/32: $2\any_ready[0:0] 30/32: $2\first_ready_idx[3:0] 31/32: $1\any_ready[0:0] 32/32: $1\first_ready_idx[3:0] 2.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\dependency_manager.\first_ready_idx' from process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$421'. No latch inferred for signal `\dependency_manager.\any_ready' from process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$421'. No latch inferred for signal `\dependency_manager.\ri' from process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$421'. 2.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\dependency_manager.\ready_valid' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9913' with positive edge clock. Creating register for signal `\dependency_manager.\ready_node_id' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9914' with positive edge clock. Creating register for signal `\dependency_manager.\ready_x_base' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9915' with positive edge clock. Creating register for signal `\dependency_manager.\ready_w_base' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9916' with positive edge clock. Creating register for signal `\dependency_manager.\ready_n_tiles' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9917' with positive edge clock. Creating register for signal `\dependency_manager.\ready_result_addr' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9918' with positive edge clock. Creating register for signal `\dependency_manager.\ni' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9919' with positive edge clock. Creating register for signal `\dependency_manager.\di' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9920' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$231_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9921' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$232_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9922' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$233_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9923' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$234_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9924' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$235_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9925' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$236_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9926' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$237_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9927' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$238_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9928' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$239_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9929' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$240_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9930' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$241_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9931' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$242_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9932' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$243_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9933' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$244_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9934' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$245_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9935' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$246_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9936' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$247_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9937' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$248_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9938' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$249_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9939' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$250_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9940' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$251_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9941' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$252_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9942' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$253_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9943' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$254_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9944' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$255_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9945' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$256_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9946' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$257_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9947' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$258_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9948' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$259_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9949' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$260_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9950' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$261_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9951' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$262_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9952' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$263_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9953' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$264_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9954' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$265_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9955' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$266_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9956' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$267_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9957' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$268_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9958' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$269_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9959' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$270_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9960' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$271_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9961' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$272_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9962' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$273_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9963' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$274_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9964' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$275_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9965' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$276_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9966' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$277_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9967' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$278_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9968' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9969' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9970' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9971' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9972' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9973' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9974' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9975' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9976' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9977' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9978' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9979' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9980' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9981' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9982' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9983' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9984' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9985' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9986' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9987' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9988' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9989' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9990' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9991' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9992' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9993' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9994' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9995' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9996' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9997' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9998' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$9999' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10000' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10001' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10002' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10003' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10004' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10005' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10006' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10007' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10008' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10009' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10010' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10011' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10012' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10013' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10014' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10015' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10016' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10017' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10018' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10019' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10020' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10021' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10022' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10023' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10024' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10025' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10026' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10027' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10028' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10029' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10030' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10031' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10032' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10033' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10034' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10035' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10036' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10037' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10038' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10039' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10040' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10041' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10042' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10043' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10044' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10045' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10046' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10047' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10048' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10049' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10050' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10051' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10052' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10053' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10054' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10055' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10056' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10057' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10058' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10059' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10060' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10061' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10062' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10063' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10064' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10065' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10066' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10067' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10068' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10069' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10070' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10071' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10072' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10073' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10074' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10075' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10076' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10077' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10078' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10079' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10080' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10081' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10082' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10083' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10084' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10085' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10086' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10087' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10088' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10089' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10090' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10091' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10092' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10093' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10094' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10095' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10096' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10097' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10098' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10099' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10100' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10101' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10102' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10103' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10104' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10105' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10106' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10107' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10108' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10109' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10110' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10111' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10112' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10113' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10114' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10115' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10116' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10117' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10118' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10119' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10120' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10121' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10122' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10123' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10124' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10125' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10126' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10127' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10128' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10129' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10130' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10131' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10132' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10133' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10134' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10135' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10136' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10137' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10138' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10139' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10140' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10141' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10142' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10143' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10144' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10145' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10146' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10147' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10148' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10149' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10150' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10151' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10152' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10153' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10154' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10155' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10156' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10157' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10158' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10159' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10160' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10161' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10162' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10163' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10164' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10165' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10166' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10167' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10168' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10169' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10170' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10171' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10172' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10173' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10174' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10175' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10176' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10177' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10178' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10179' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10180' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10181' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10182' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10183' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10184' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10185' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10186' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10187' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10188' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10189' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10190' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_DATA' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10191' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10192' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_ADDR' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10193' with positive edge clock. Creating register for signal `\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_EN' using process `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. created $dff cell `$procdff$10194' with positive edge clock. 2.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 149 empty switches in `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. Removing empty process `dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$454'. Found and cleaned up 16 empty switches in `\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$421'. Removing empty process `dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$421'. Cleaned up 165 empty switches. 2.5.12. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.6. Executing CHECK pass (checking for obvious problems). Checking module dependency_manager... Found and reported 0 problems. 2.7. Executing FLATTEN pass (flatten design). 2.8. Executing TRIBUF pass. 2.9. Executing DEMINOUT pass (demote inout ports to input or output). 2.10. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 332 unused cells and 4122 unused wires. 2.12. Executing CHECK pass (checking for obvious problems). Checking module dependency_manager... Found and reported 0 problems. 2.13. Executing OPT pass (performing simple optimizations). 2.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 3417 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 3177 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 3065 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 3017 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 400 cells. 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $procmux$8939. dead port 1/2 on $mux $procmux$8933. dead port 1/2 on $mux $procmux$8927. dead port 1/2 on $mux $procmux$8921. dead port 1/2 on $mux $procmux$8915. dead port 1/2 on $mux $procmux$8909. dead port 1/2 on $mux $procmux$8903. dead port 1/2 on $mux $procmux$8897. dead port 1/2 on $mux $procmux$8891. dead port 1/2 on $mux $procmux$8885. dead port 1/2 on $mux $procmux$8879. dead port 1/2 on $mux $procmux$8873. dead port 1/2 on $mux $procmux$8867. dead port 1/2 on $mux $procmux$8861. dead port 1/2 on $mux $procmux$8855. dead port 1/2 on $mux $procmux$8849. dead port 1/2 on $mux $procmux$8843. dead port 1/2 on $mux $procmux$8837. dead port 1/2 on $mux $procmux$8831. dead port 1/2 on $mux $procmux$8825. dead port 1/2 on $mux $procmux$8819. dead port 1/2 on $mux $procmux$8813. dead port 1/2 on $mux $procmux$8807. dead port 1/2 on $mux $procmux$8801. dead port 1/2 on $mux $procmux$8795. dead port 1/2 on $mux $procmux$8789. dead port 1/2 on $mux $procmux$8783. dead port 1/2 on $mux $procmux$8777. dead port 1/2 on $mux $procmux$8771. dead port 1/2 on $mux $procmux$8759. dead port 1/2 on $mux $procmux$8753. dead port 1/2 on $mux $procmux$8747. dead port 1/2 on $mux $procmux$8741. dead port 1/2 on $mux $procmux$8735. dead port 1/2 on $mux $procmux$8729. dead port 1/2 on $mux $procmux$8723. dead port 1/2 on $mux $procmux$8717. dead port 1/2 on $mux $procmux$8711. dead port 1/2 on $mux $procmux$8705. dead port 1/2 on $mux $procmux$8699. dead port 1/2 on $mux $procmux$8693. dead port 1/2 on $mux $procmux$8687. dead port 1/2 on $mux $procmux$8681. dead port 1/2 on $mux $procmux$8675. dead port 1/2 on $mux $procmux$8669. dead port 1/2 on $mux $procmux$8663. dead port 1/2 on $mux $procmux$8657. dead port 1/2 on $mux $procmux$8651. dead port 1/2 on $mux $procmux$8645. dead port 1/2 on $mux $procmux$8639. dead port 1/2 on $mux $procmux$8633. dead port 1/2 on $mux $procmux$8627. dead port 1/2 on $mux $procmux$8621. dead port 1/2 on $mux $procmux$8615. dead port 1/2 on $mux $procmux$8609. dead port 1/2 on $mux $procmux$8603. dead port 1/2 on $mux $procmux$8597. dead port 1/2 on $mux $procmux$8591. dead port 1/2 on $mux $procmux$8585. dead port 1/2 on $mux $procmux$8579. dead port 1/2 on $mux $procmux$8573. dead port 1/2 on $mux $procmux$8567. dead port 1/2 on $mux $procmux$8561. dead port 1/2 on $mux $procmux$8555. dead port 1/2 on $mux $procmux$8549. dead port 1/2 on $mux $procmux$8543. dead port 1/2 on $mux $procmux$8537. dead port 1/2 on $mux $procmux$8531. dead port 1/2 on $mux $procmux$8525. dead port 1/2 on $mux $procmux$8519. dead port 1/2 on $mux $procmux$8513. dead port 1/2 on $mux $procmux$8507. dead port 1/2 on $mux $procmux$8501. dead port 1/2 on $mux $procmux$8495. dead port 1/2 on $mux $procmux$8489. dead port 1/2 on $mux $procmux$8483. dead port 1/2 on $mux $procmux$8477. dead port 1/2 on $mux $procmux$8471. dead port 1/2 on $mux $procmux$8465. dead port 1/2 on $mux $procmux$8459. dead port 1/2 on $mux $procmux$8453. dead port 1/2 on $mux $procmux$8447. dead port 1/2 on $mux $procmux$8441. dead port 1/2 on $mux $procmux$8435. dead port 1/2 on $mux $procmux$8429. dead port 1/2 on $mux $procmux$8423. dead port 1/2 on $mux $procmux$8417. dead port 1/2 on $mux $procmux$8411. dead port 1/2 on $mux $procmux$8405. dead port 1/2 on $mux $procmux$8399. dead port 1/2 on $mux $procmux$8393. dead port 1/2 on $mux $procmux$8387. dead port 1/2 on $mux $procmux$8381. dead port 1/2 on $mux $procmux$8375. dead port 1/2 on $mux $procmux$8369. dead port 1/2 on $mux $procmux$8363. dead port 1/2 on $mux $procmux$8357. dead port 1/2 on $mux $procmux$8351. dead port 1/2 on $mux $procmux$8345. dead port 1/2 on $mux $procmux$8339. dead port 1/2 on $mux $procmux$8333. dead port 1/2 on $mux $procmux$8327. dead port 1/2 on $mux $procmux$8321. dead port 1/2 on $mux $procmux$8315. dead port 1/2 on $mux $procmux$8309. dead port 1/2 on $mux $procmux$8303. dead port 1/2 on $mux $procmux$8297. dead port 1/2 on $mux $procmux$8291. dead port 1/2 on $mux $procmux$8285. dead port 1/2 on $mux $procmux$8279. dead port 1/2 on $mux $procmux$8273. dead port 1/2 on $mux $procmux$8267. dead port 1/2 on $mux $procmux$8261. dead port 1/2 on $mux $procmux$8255. dead port 1/2 on $mux $procmux$8249. dead port 1/2 on $mux $procmux$8243. dead port 1/2 on $mux $procmux$8237. dead port 1/2 on $mux $procmux$8231. dead port 1/2 on $mux $procmux$8225. dead port 1/2 on $mux $procmux$8219. dead port 1/2 on $mux $procmux$8213. dead port 1/2 on $mux $procmux$8207. dead port 1/2 on $mux $procmux$8201. dead port 1/2 on $mux $procmux$8195. dead port 1/2 on $mux $procmux$8189. dead port 1/2 on $mux $procmux$8183. dead port 1/2 on $mux $procmux$8177. dead port 1/2 on $mux $procmux$8171. dead port 1/2 on $mux $procmux$8165. dead port 1/2 on $mux $procmux$8159. dead port 1/2 on $mux $procmux$8153. dead port 1/2 on $mux $procmux$8147. dead port 1/2 on $mux $procmux$8141. dead port 1/2 on $mux $procmux$8135. dead port 1/2 on $mux $procmux$8129. dead port 1/2 on $mux $procmux$8123. dead port 1/2 on $mux $procmux$8117. dead port 1/2 on $mux $procmux$8111. dead port 1/2 on $mux $procmux$8105. dead port 1/2 on $mux $procmux$8099. dead port 1/2 on $mux $procmux$8093. dead port 1/2 on $mux $procmux$8087. dead port 1/2 on $mux $procmux$8081. dead port 1/2 on $mux $procmux$8075. dead port 1/2 on $mux $procmux$8069. dead port 1/2 on $mux $procmux$8063. dead port 1/2 on $mux $procmux$8057. dead port 1/2 on $mux $procmux$8051. dead port 1/2 on $mux $procmux$8045. dead port 1/2 on $mux $procmux$8039. dead port 1/2 on $mux $procmux$8033. dead port 1/2 on $mux $procmux$8027. dead port 1/2 on $mux $procmux$8021. dead port 1/2 on $mux $procmux$8015. dead port 1/2 on $mux $procmux$8009. dead port 1/2 on $mux $procmux$8003. dead port 1/2 on $mux $procmux$7997. dead port 1/2 on $mux $procmux$7991. dead port 1/2 on $mux $procmux$7985. dead port 1/2 on $mux $procmux$7979. dead port 1/2 on $mux $procmux$7973. dead port 1/2 on $mux $procmux$7967. dead port 1/2 on $mux $procmux$7961. dead port 1/2 on $mux $procmux$7955. dead port 1/2 on $mux $procmux$7949. dead port 1/2 on $mux $procmux$7943. dead port 1/2 on $mux $procmux$7937. dead port 1/2 on $mux $procmux$7931. dead port 1/2 on $mux $procmux$7925. dead port 1/2 on $mux $procmux$7919. dead port 1/2 on $mux $procmux$7913. dead port 1/2 on $mux $procmux$7907. dead port 1/2 on $mux $procmux$7901. dead port 1/2 on $mux $procmux$7895. dead port 1/2 on $mux $procmux$7889. dead port 1/2 on $mux $procmux$7883. dead port 1/2 on $mux $procmux$7877. dead port 1/2 on $mux $procmux$7871. dead port 1/2 on $mux $procmux$7865. dead port 1/2 on $mux $procmux$7859. dead port 1/2 on $mux $procmux$7853. dead port 1/2 on $mux $procmux$7847. dead port 1/2 on $mux $procmux$7841. dead port 1/2 on $mux $procmux$7835. dead port 1/2 on $mux $procmux$7829. dead port 1/2 on $mux $procmux$7823. dead port 1/2 on $mux $procmux$7817. dead port 1/2 on $mux $procmux$7811. dead port 1/2 on $mux $procmux$7805. dead port 1/2 on $mux $procmux$7799. dead port 1/2 on $mux $procmux$7793. dead port 1/2 on $mux $procmux$7787. dead port 1/2 on $mux $procmux$7781. dead port 1/2 on $mux $procmux$7775. dead port 1/2 on $mux $procmux$7769. dead port 1/2 on $mux $procmux$7763. dead port 1/2 on $mux $procmux$7757. dead port 1/2 on $mux $procmux$7751. dead port 1/2 on $mux $procmux$7745. dead port 1/2 on $mux $procmux$7739. dead port 1/2 on $mux $procmux$7733. dead port 1/2 on $mux $procmux$7727. dead port 1/2 on $mux $procmux$7721. dead port 1/2 on $mux $procmux$7715. dead port 1/2 on $mux $procmux$7709. dead port 1/2 on $mux $procmux$7703. dead port 1/2 on $mux $procmux$7697. dead port 1/2 on $mux $procmux$7691. dead port 1/2 on $mux $procmux$7685. dead port 1/2 on $mux $procmux$7679. dead port 1/2 on $mux $procmux$7673. dead port 1/2 on $mux $procmux$7667. dead port 1/2 on $mux $procmux$7655. dead port 1/2 on $mux $procmux$7649. dead port 1/2 on $mux $procmux$7643. dead port 1/2 on $mux $procmux$7637. dead port 1/2 on $mux $procmux$7631. dead port 1/2 on $mux $procmux$7625. dead port 1/2 on $mux $procmux$7619. dead port 1/2 on $mux $procmux$7613. dead port 1/2 on $mux $procmux$7607. dead port 1/2 on $mux $procmux$7601. dead port 1/2 on $mux $procmux$7595. dead port 1/2 on $mux $procmux$7589. dead port 1/2 on $mux $procmux$7577. dead port 2/2 on $mux $procmux$7574. dead port 1/2 on $mux $procmux$7568. dead port 2/2 on $mux $procmux$7565. dead port 1/2 on $mux $procmux$7559. dead port 2/2 on $mux $procmux$7556. dead port 1/2 on $mux $procmux$7550. dead port 2/2 on $mux $procmux$7547. dead port 1/2 on $mux $procmux$7541. dead port 2/2 on $mux $procmux$7538. dead port 1/2 on $mux $procmux$7532. dead port 2/2 on $mux $procmux$7529. dead port 1/2 on $mux $procmux$7523. dead port 2/2 on $mux $procmux$7520. dead port 1/2 on $mux $procmux$7514. dead port 2/2 on $mux $procmux$7511. dead port 1/2 on $mux $procmux$7505. dead port 2/2 on $mux $procmux$7502. dead port 1/2 on $mux $procmux$7496. dead port 2/2 on $mux $procmux$7493. dead port 1/2 on $mux $procmux$7487. dead port 2/2 on $mux $procmux$7484. dead port 1/2 on $mux $procmux$7478. dead port 2/2 on $mux $procmux$7475. dead port 1/2 on $mux $procmux$7460. dead port 2/2 on $mux $procmux$7457. dead port 2/2 on $mux $procmux$7455. dead port 1/2 on $mux $procmux$7448. dead port 2/2 on $mux $procmux$7445. dead port 2/2 on $mux $procmux$7443. dead port 1/2 on $mux $procmux$7436. dead port 2/2 on $mux $procmux$7433. dead port 2/2 on $mux $procmux$7431. dead port 1/2 on $mux $procmux$7424. dead port 2/2 on $mux $procmux$7421. dead port 2/2 on $mux $procmux$7419. dead port 2/2 on $mux $procmux$7417. dead port 1/2 on $mux $procmux$7409. dead port 2/2 on $mux $procmux$7406. dead port 2/2 on $mux $procmux$7404. dead port 1/2 on $mux $procmux$7397. dead port 2/2 on $mux $procmux$7394. dead port 2/2 on $mux $procmux$7392. dead port 1/2 on $mux $procmux$7385. dead port 2/2 on $mux $procmux$7382. dead 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port 2/2 on $mux $procmux$3503. dead port 2/2 on $mux $procmux$3501. dead port 1/2 on $mux $procmux$3494. dead port 2/2 on $mux $procmux$3491. dead port 2/2 on $mux $procmux$3489. dead port 1/2 on $mux $procmux$3482. dead port 2/2 on $mux $procmux$3479. dead port 2/2 on $mux $procmux$3477. dead port 1/2 on $mux $procmux$3470. dead port 2/2 on $mux $procmux$3467. dead port 2/2 on $mux $procmux$3465. dead port 2/2 on $mux $procmux$3463. dead port 1/2 on $mux $procmux$3455. dead port 2/2 on $mux $procmux$3452. dead port 2/2 on $mux $procmux$3450. dead port 1/2 on $mux $procmux$3443. dead port 2/2 on $mux $procmux$3440. dead port 2/2 on $mux $procmux$3438. dead port 1/2 on $mux $procmux$3431. dead port 2/2 on $mux $procmux$3428. dead port 2/2 on $mux $procmux$3426. dead port 1/2 on $mux $procmux$3419. dead port 2/2 on $mux $procmux$3416. dead port 2/2 on $mux $procmux$3414. dead port 2/2 on $mux $procmux$3412. dead port 1/2 on $mux $procmux$3404. dead port 2/2 on $mux $procmux$3401. dead port 1/2 on $mux $procmux$3395. dead port 2/2 on $mux $procmux$3392. dead port 1/2 on $mux $procmux$3386. dead port 2/2 on $mux $procmux$3383. dead port 1/2 on $mux $procmux$3377. dead port 2/2 on $mux $procmux$3374. dead port 1/2 on $mux $procmux$3368. dead port 2/2 on $mux $procmux$3365. dead port 1/2 on $mux $procmux$3359. dead port 2/2 on $mux $procmux$3356. dead port 1/2 on $mux $procmux$3350. dead port 2/2 on $mux $procmux$3347. dead port 1/2 on $mux $procmux$3341. dead port 2/2 on $mux $procmux$3338. dead port 1/2 on $mux $procmux$3332. dead port 2/2 on $mux $procmux$3329. dead port 1/2 on $mux $procmux$3323. dead port 2/2 on $mux $procmux$3320. dead port 1/2 on $mux $procmux$3314. dead port 2/2 on $mux $procmux$3311. dead port 1/2 on $mux $procmux$3305. dead port 2/2 on $mux $procmux$3302. dead port 1/2 on $mux $procmux$3287. dead port 2/2 on $mux $procmux$3284. dead port 2/2 on $mux $procmux$3282. dead port 1/2 on $mux $procmux$3275. dead port 2/2 on $mux $procmux$3272. dead port 2/2 on $mux $procmux$3270. dead port 1/2 on $mux $procmux$3263. dead port 2/2 on $mux $procmux$3260. dead port 2/2 on $mux $procmux$3258. dead port 1/2 on $mux $procmux$3251. dead port 2/2 on $mux $procmux$3248. dead port 2/2 on $mux $procmux$3246. dead port 2/2 on $mux $procmux$3244. dead port 1/2 on $mux $procmux$3236. dead port 2/2 on $mux $procmux$3233. dead port 2/2 on $mux $procmux$3231. dead port 1/2 on $mux $procmux$3224. dead port 2/2 on $mux $procmux$3221. dead port 2/2 on $mux $procmux$3219. dead port 1/2 on $mux $procmux$3212. dead port 2/2 on $mux $procmux$3209. dead port 2/2 on $mux $procmux$3207. dead port 1/2 on $mux $procmux$3200. dead port 2/2 on $mux $procmux$3197. dead port 2/2 on $mux $procmux$3195. dead port 2/2 on $mux $procmux$3193. dead port 1/2 on $mux $procmux$3185. dead port 2/2 on $mux $procmux$3182. dead port 2/2 on $mux $procmux$3180. dead port 1/2 on $mux $procmux$3173. dead port 2/2 on $mux $procmux$3170. dead port 2/2 on $mux $procmux$3168. dead port 1/2 on $mux $procmux$3161. dead port 2/2 on $mux $procmux$3158. dead port 2/2 on $mux $procmux$3156. dead port 1/2 on $mux $procmux$3149. dead port 2/2 on $mux $procmux$3146. dead port 2/2 on $mux $procmux$3144. dead port 2/2 on $mux $procmux$3142. dead port 1/2 on $mux $procmux$3134. dead port 2/2 on $mux $procmux$3131. dead port 2/2 on $mux $procmux$3129. dead port 1/2 on $mux $procmux$3122. dead port 2/2 on $mux $procmux$3119. dead port 2/2 on $mux $procmux$3117. dead port 1/2 on $mux $procmux$3110. dead port 2/2 on $mux $procmux$3107. dead port 2/2 on $mux $procmux$3105. dead port 1/2 on $mux $procmux$3098. dead port 2/2 on $mux $procmux$3095. dead port 2/2 on $mux $procmux$3093. dead port 2/2 on $mux $procmux$3091. dead port 1/2 on $mux $procmux$3083. dead port 2/2 on $mux $procmux$3080. dead port 1/2 on $mux $procmux$3074. dead port 2/2 on $mux $procmux$3071. dead port 1/2 on $mux $procmux$3065. dead port 2/2 on $mux $procmux$3062. dead port 1/2 on $mux $procmux$3056. dead port 2/2 on $mux $procmux$3053. dead port 1/2 on $mux $procmux$3047. dead port 2/2 on $mux $procmux$3044. dead port 1/2 on $mux $procmux$3038. dead port 2/2 on $mux $procmux$3035. dead port 1/2 on $mux $procmux$3029. dead port 2/2 on $mux $procmux$3026. dead port 1/2 on $mux $procmux$3020. dead port 2/2 on $mux $procmux$3017. dead port 1/2 on $mux $procmux$3011. dead port 2/2 on $mux $procmux$3008. dead port 1/2 on $mux $procmux$3002. dead port 2/2 on $mux $procmux$2999. dead port 1/2 on $mux $procmux$2993. dead port 2/2 on $mux $procmux$2990. dead port 1/2 on $mux $procmux$2984. dead port 2/2 on $mux $procmux$2981. dead port 1/2 on $mux $procmux$2966. dead port 2/2 on $mux $procmux$2963. dead port 2/2 on $mux $procmux$2961. dead port 1/2 on $mux $procmux$2954. dead port 2/2 on $mux $procmux$2951. dead port 2/2 on $mux $procmux$2949. dead port 1/2 on $mux $procmux$2942. dead port 2/2 on $mux $procmux$2939. dead port 2/2 on $mux $procmux$2937. dead port 1/2 on $mux $procmux$2930. dead port 2/2 on $mux $procmux$2927. dead port 2/2 on $mux $procmux$2925. dead port 2/2 on $mux $procmux$2923. dead port 1/2 on $mux $procmux$2915. dead port 2/2 on $mux $procmux$2912. dead port 2/2 on $mux $procmux$2910. dead port 1/2 on $mux $procmux$2903. dead port 2/2 on $mux $procmux$2900. dead port 2/2 on $mux $procmux$2898. dead port 1/2 on $mux $procmux$2891. dead port 2/2 on $mux $procmux$2888. dead port 2/2 on $mux $procmux$2886. dead port 1/2 on $mux $procmux$2879. dead port 2/2 on $mux $procmux$2876. dead port 2/2 on $mux $procmux$2874. dead port 2/2 on $mux $procmux$2872. dead port 1/2 on $mux $procmux$2864. dead port 2/2 on $mux $procmux$2861. dead port 2/2 on $mux $procmux$2859. dead port 1/2 on $mux $procmux$2852. dead port 2/2 on $mux $procmux$2849. dead port 2/2 on $mux $procmux$2847. dead port 1/2 on $mux $procmux$2840. dead port 2/2 on $mux $procmux$2837. dead port 2/2 on $mux $procmux$2835. dead port 1/2 on $mux $procmux$2828. dead port 2/2 on $mux $procmux$2825. dead port 2/2 on $mux $procmux$2823. dead port 2/2 on $mux $procmux$2821. dead port 1/2 on $mux $procmux$2813. dead port 2/2 on $mux $procmux$2810. dead port 2/2 on $mux $procmux$2808. dead port 1/2 on $mux $procmux$2801. dead port 2/2 on $mux $procmux$2798. dead port 2/2 on $mux $procmux$2796. dead port 1/2 on $mux $procmux$2789. dead port 2/2 on $mux $procmux$2786. dead port 2/2 on $mux $procmux$2784. dead port 1/2 on $mux $procmux$2777. dead port 2/2 on $mux $procmux$2774. dead port 2/2 on $mux $procmux$2772. dead port 2/2 on $mux $procmux$2770. dead port 1/2 on $mux $procmux$2762. dead port 2/2 on $mux $procmux$2759. dead port 1/2 on $mux $procmux$2753. dead port 2/2 on $mux $procmux$2750. dead port 1/2 on $mux $procmux$2744. dead port 2/2 on $mux $procmux$2741. dead port 1/2 on $mux $procmux$2735. dead port 2/2 on $mux $procmux$2732. dead port 1/2 on $mux $procmux$2726. dead port 2/2 on $mux $procmux$2723. dead port 1/2 on $mux $procmux$2717. dead port 2/2 on $mux $procmux$2714. dead port 1/2 on $mux $procmux$2708. dead port 2/2 on $mux $procmux$2705. dead port 1/2 on $mux $procmux$2699. dead port 2/2 on $mux $procmux$2696. dead port 1/2 on $mux $procmux$2690. dead port 2/2 on $mux $procmux$2687. dead port 1/2 on $mux $procmux$2681. dead port 2/2 on $mux $procmux$2678. dead port 1/2 on $mux $procmux$2672. dead port 2/2 on $mux $procmux$2669. dead port 1/2 on $mux $procmux$2663. dead port 2/2 on $mux $procmux$2660. dead port 1/2 on $mux $procmux$2645. dead port 2/2 on $mux $procmux$2642. dead port 2/2 on $mux $procmux$2640. dead port 1/2 on $mux $procmux$2633. dead port 2/2 on $mux $procmux$2630. dead port 2/2 on $mux $procmux$2628. dead port 1/2 on $mux $procmux$2621. dead port 2/2 on $mux $procmux$2618. dead port 2/2 on $mux $procmux$2616. dead port 1/2 on $mux $procmux$2609. dead port 2/2 on $mux $procmux$2606. dead port 2/2 on $mux $procmux$2604. dead port 2/2 on $mux $procmux$2602. dead port 1/2 on $mux $procmux$2594. dead port 2/2 on $mux $procmux$2591. dead port 2/2 on $mux $procmux$2589. dead port 1/2 on $mux $procmux$2582. dead port 2/2 on $mux $procmux$2579. dead port 2/2 on $mux $procmux$2577. dead port 1/2 on $mux $procmux$2570. dead port 2/2 on $mux $procmux$2567. dead port 2/2 on $mux $procmux$2565. dead port 1/2 on $mux $procmux$2558. dead port 2/2 on $mux $procmux$2555. dead port 2/2 on $mux $procmux$2553. dead port 2/2 on $mux $procmux$2551. dead port 1/2 on $mux $procmux$2543. dead port 2/2 on $mux $procmux$2540. dead port 2/2 on $mux $procmux$2538. dead port 1/2 on $mux $procmux$2531. dead port 2/2 on $mux $procmux$2528. dead port 2/2 on $mux $procmux$2526. dead port 1/2 on $mux $procmux$2519. dead port 2/2 on $mux $procmux$2516. dead port 2/2 on $mux $procmux$2514. dead port 1/2 on $mux $procmux$2507. dead port 2/2 on $mux $procmux$2504. dead port 2/2 on $mux $procmux$2502. dead port 2/2 on $mux $procmux$2500. dead port 1/2 on $mux $procmux$2492. dead port 2/2 on $mux $procmux$2489. dead port 2/2 on $mux $procmux$2487. dead port 1/2 on $mux $procmux$2480. dead port 2/2 on $mux $procmux$2477. dead port 2/2 on $mux $procmux$2475. dead port 1/2 on $mux $procmux$2468. dead port 2/2 on $mux $procmux$2465. dead port 2/2 on $mux $procmux$2463. dead port 1/2 on $mux $procmux$2456. dead port 2/2 on $mux $procmux$2453. dead port 2/2 on $mux $procmux$2451. dead port 2/2 on $mux $procmux$2449. dead port 1/2 on $mux $procmux$2441. dead port 1/2 on $mux $procmux$2435. Removed 1442 multiplexer ports. 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $procmux$6466: Old ports: A=3'000, B=3'111, Y=$procmux$6466_Y New ports: A=1'0, B=1'1, Y=$procmux$6466_Y [0] New connections: $procmux$6466_Y [2:1] = { $procmux$6466_Y [0] $procmux$6466_Y [0] } Consolidated identical input bits for $mux cell $procmux$6452: Old ports: A=2'00, B=2'11, Y=$procmux$6452_Y New ports: A=1'0, B=1'1, Y=$procmux$6452_Y [0] New connections: $procmux$6452_Y [1] = $procmux$6452_Y [0] Consolidated identical input bits for $mux cell $procmux$4759: Old ports: A=3'000, B=3'111, Y=$procmux$4759_Y New ports: A=1'0, B=1'1, Y=$procmux$4759_Y [0] New connections: $procmux$4759_Y [2:1] = { $procmux$4759_Y [0] $procmux$4759_Y [0] } Consolidated identical input bits for $mux cell $procmux$4745: Old ports: A=2'00, B=2'11, Y=$procmux$4745_Y New ports: A=1'0, B=1'1, Y=$procmux$4745_Y [0] New connections: $procmux$4745_Y [1] = $procmux$4745_Y [0] Consolidated identical input bits for $mux cell $procmux$6415: Old ports: A=3'000, B=3'111, Y=$procmux$6415_Y New ports: A=1'0, B=1'1, Y=$procmux$6415_Y [0] New connections: $procmux$6415_Y [2:1] = { $procmux$6415_Y [0] $procmux$6415_Y [0] } Consolidated identical input bits for $mux cell $procmux$4708: Old ports: A=3'000, B=3'111, Y=$procmux$4708_Y New ports: A=1'0, B=1'1, Y=$procmux$4708_Y [0] New connections: $procmux$4708_Y [2:1] = { $procmux$4708_Y [0] $procmux$4708_Y [0] } Consolidated identical input bits for $mux cell $procmux$9086: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$231_EN[1:0]$455 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$231_EN[1:0]$455 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$231_EN[1:0]$455 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$231_EN[1:0]$455 [0] Consolidated identical input bits for $mux cell $procmux$6401: Old ports: A=2'00, B=2'11, Y=$procmux$6401_Y New ports: A=1'0, B=1'1, Y=$procmux$6401_Y [0] New connections: $procmux$6401_Y [1] = $procmux$6401_Y [0] Consolidated identical input bits for $mux cell $procmux$4694: Old ports: A=2'00, B=2'11, Y=$procmux$4694_Y New ports: A=1'0, B=1'1, Y=$procmux$4694_Y [0] New connections: $procmux$4694_Y [1] = $procmux$4694_Y [0] Consolidated identical input bits for $mux cell $procmux$8876: Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$8876_Y New ports: A=1'0, B=1'1, Y=$procmux$8876_Y [0] New connections: $procmux$8876_Y [22:1] = { $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] $procmux$8876_Y [0] } Consolidated identical input bits for $mux cell $procmux$9083: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$232_EN[2:0]$456 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$232_EN[2:0]$456 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$232_EN[2:0]$456 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$232_EN[2:0]$456 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$232_EN[2:0]$456 [0] } Consolidated identical input bits for $mux cell $procmux$6364: Old ports: A=3'000, B=3'111, Y=$procmux$6364_Y New ports: A=1'0, B=1'1, Y=$procmux$6364_Y [0] New connections: $procmux$6364_Y [2:1] = { $procmux$6364_Y [0] $procmux$6364_Y [0] } Consolidated identical input bits for $mux cell $procmux$6350: Old ports: A=2'00, B=2'11, Y=$procmux$6350_Y New ports: A=1'0, B=1'1, Y=$procmux$6350_Y [0] New connections: $procmux$6350_Y [1] = $procmux$6350_Y [0] Consolidated identical input bits for $mux cell $procmux$9080: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$233_EN[2:0]$457 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$233_EN[2:0]$457 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$233_EN[2:0]$457 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$233_EN[2:0]$457 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$233_EN[2:0]$457 [0] } Consolidated identical input bits for $mux cell $procmux$9077: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$234_EN[1:0]$458 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$234_EN[1:0]$458 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$234_EN[1:0]$458 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$234_EN[1:0]$458 [0] Consolidated identical input bits for $mux cell $procmux$6313: Old ports: A=3'000, B=3'111, Y=$procmux$6313_Y New ports: A=1'0, B=1'1, Y=$procmux$6313_Y [0] New connections: $procmux$6313_Y [2:1] = { $procmux$6313_Y [0] $procmux$6313_Y [0] } Consolidated identical input bits for $mux cell $procmux$8858: Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$procmux$8858_Y New ports: A=1'0, B=1'1, Y=$procmux$8858_Y [0] New connections: $procmux$8858_Y [15:1] = { $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] $procmux$8858_Y [0] } Consolidated identical input bits for $mux cell $procmux$6299: Old ports: A=2'00, B=2'11, Y=$procmux$6299_Y New ports: A=1'0, B=1'1, Y=$procmux$6299_Y [0] New connections: $procmux$6299_Y [1] = $procmux$6299_Y [0] Consolidated identical input bits for $mux cell $procmux$4540: Old ports: A=3'000, B=3'111, Y=$procmux$4540_Y New ports: A=1'0, B=1'1, Y=$procmux$4540_Y [0] New connections: $procmux$4540_Y [2:1] = { $procmux$4540_Y [0] $procmux$4540_Y [0] } Consolidated identical input bits for $mux cell $procmux$9074: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$235_EN[2:0]$459 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$235_EN[2:0]$459 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$235_EN[2:0]$459 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$235_EN[2:0]$459 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$235_EN[2:0]$459 [0] } Consolidated identical input bits for $mux cell $procmux$4526: Old ports: A=2'00, B=2'11, Y=$procmux$4526_Y New ports: A=1'0, B=1'1, Y=$procmux$4526_Y [0] New connections: $procmux$4526_Y [1] = $procmux$4526_Y [0] Consolidated identical input bits for $mux cell $procmux$9071: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$236_EN[2:0]$460 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$236_EN[2:0]$460 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$236_EN[2:0]$460 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$236_EN[2:0]$460 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$236_EN[2:0]$460 [0] } Consolidated identical input bits for $mux cell $procmux$4489: Old ports: A=3'000, B=3'111, Y=$procmux$4489_Y New ports: A=1'0, B=1'1, Y=$procmux$4489_Y [0] New connections: $procmux$4489_Y [2:1] = { $procmux$4489_Y [0] $procmux$4489_Y [0] } Consolidated identical input bits for $mux cell $procmux$4475: Old ports: A=2'00, B=2'11, Y=$procmux$4475_Y New ports: A=1'0, B=1'1, Y=$procmux$4475_Y [0] New connections: $procmux$4475_Y [1] = $procmux$4475_Y [0] Consolidated identical input bits for $mux cell $procmux$9068: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$237_EN[1:0]$461 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$237_EN[1:0]$461 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$237_EN[1:0]$461 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$237_EN[1:0]$461 [0] Consolidated identical input bits for $mux cell $procmux$8840: Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$8840_Y New ports: A=1'0, B=1'1, Y=$procmux$8840_Y [0] New connections: $procmux$8840_Y [22:1] = { $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] $procmux$8840_Y [0] } Consolidated identical input bits for $mux cell $procmux$4438: Old ports: A=3'000, B=3'111, Y=$procmux$4438_Y New ports: A=1'0, B=1'1, Y=$procmux$4438_Y [0] New connections: $procmux$4438_Y [2:1] = { $procmux$4438_Y [0] $procmux$4438_Y [0] } Consolidated identical input bits for $mux cell $procmux$9065: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$238_EN[2:0]$462 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$238_EN[2:0]$462 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$238_EN[2:0]$462 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$238_EN[2:0]$462 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$238_EN[2:0]$462 [0] } Consolidated identical input bits for $mux cell $procmux$4424: Old ports: A=2'00, B=2'11, Y=$procmux$4424_Y New ports: A=1'0, B=1'1, Y=$procmux$4424_Y [0] New connections: $procmux$4424_Y [1] = $procmux$4424_Y [0] Consolidated identical input bits for $mux cell $procmux$4387: Old ports: A=3'000, B=3'111, Y=$procmux$4387_Y New ports: A=1'0, B=1'1, Y=$procmux$4387_Y [0] New connections: $procmux$4387_Y [2:1] = { $procmux$4387_Y [0] $procmux$4387_Y [0] } Consolidated identical input bits for $mux cell $procmux$4373: Old ports: A=2'00, B=2'11, Y=$procmux$4373_Y New ports: A=1'0, B=1'1, Y=$procmux$4373_Y [0] New connections: $procmux$4373_Y [1] = $procmux$4373_Y [0] Consolidated identical input bits for $mux cell $procmux$9062: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$239_EN[2:0]$463 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$239_EN[2:0]$463 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$239_EN[2:0]$463 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$239_EN[2:0]$463 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$239_EN[2:0]$463 [0] } Consolidated identical input bits for $mux cell $procmux$6145: Old ports: A=3'000, B=3'111, Y=$procmux$6145_Y New ports: A=1'0, B=1'1, Y=$procmux$6145_Y [0] New connections: $procmux$6145_Y [2:1] = { $procmux$6145_Y [0] $procmux$6145_Y [0] } Consolidated identical input bits for $mux cell $procmux$9059: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$240_EN[1:0]$464 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$240_EN[1:0]$464 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$240_EN[1:0]$464 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$240_EN[1:0]$464 [0] Consolidated identical input bits for $mux cell $procmux$7429: Old ports: A=3'000, B=3'111, Y=$procmux$7429_Y New ports: A=1'0, B=1'1, Y=$procmux$7429_Y [0] New connections: $procmux$7429_Y [2:1] = { $procmux$7429_Y [0] $procmux$7429_Y [0] } Consolidated identical input bits for $mux cell $procmux$8822: Old ports: A=4'0000, B=4'1111, Y=$procmux$8822_Y New ports: A=1'0, B=1'1, Y=$procmux$8822_Y [0] New connections: $procmux$8822_Y [3:1] = { $procmux$8822_Y [0] $procmux$8822_Y [0] $procmux$8822_Y [0] } Consolidated identical input bits for $mux cell $procmux$6131: Old ports: A=2'00, B=2'11, Y=$procmux$6131_Y New ports: A=1'0, B=1'1, Y=$procmux$6131_Y [0] New connections: $procmux$6131_Y [1] = $procmux$6131_Y [0] Consolidated identical input bits for $mux cell $procmux$9056: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$241_EN[2:0]$465 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$241_EN[2:0]$465 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$241_EN[2:0]$465 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$241_EN[2:0]$465 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$241_EN[2:0]$465 [0] } Consolidated identical input bits for $mux cell $procmux$7415: Old ports: A=2'00, B=2'11, Y=$procmux$7415_Y New ports: A=1'0, B=1'1, Y=$procmux$7415_Y [0] New connections: $procmux$7415_Y [1] = $procmux$7415_Y [0] Consolidated identical input bits for $mux cell $procmux$9053: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$242_EN[2:0]$466 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$242_EN[2:0]$466 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$242_EN[2:0]$466 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$242_EN[2:0]$466 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$242_EN[2:0]$466 [0] } Consolidated identical input bits for $mux cell $procmux$6094: Old ports: A=3'000, B=3'111, Y=$procmux$6094_Y New ports: A=1'0, B=1'1, Y=$procmux$6094_Y [0] New connections: $procmux$6094_Y [2:1] = { $procmux$6094_Y [0] $procmux$6094_Y [0] } Consolidated identical input bits for $mux cell $procmux$9050: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$243_EN[1:0]$467 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$243_EN[1:0]$467 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$243_EN[1:0]$467 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$243_EN[1:0]$467 [0] Consolidated identical input bits for $mux cell $procmux$6080: Old ports: A=2'00, B=2'11, Y=$procmux$6080_Y New ports: A=1'0, B=1'1, Y=$procmux$6080_Y [0] New connections: $procmux$6080_Y [1] = $procmux$6080_Y [0] Consolidated identical input bits for $mux cell $procmux$8804: Old ports: A=4'0000, B=4'1111, Y=$procmux$8804_Y New ports: A=1'0, B=1'1, Y=$procmux$8804_Y [0] New connections: $procmux$8804_Y [3:1] = { $procmux$8804_Y [0] $procmux$8804_Y [0] $procmux$8804_Y [0] } Consolidated identical input bits for $mux cell $procmux$7378: Old ports: A=3'000, B=3'111, Y=$procmux$7378_Y New ports: A=1'0, B=1'1, Y=$procmux$7378_Y [0] New connections: $procmux$7378_Y [2:1] = { $procmux$7378_Y [0] $procmux$7378_Y [0] } Consolidated identical input bits for $mux cell $procmux$4219: Old ports: A=3'000, B=3'111, Y=$procmux$4219_Y New ports: A=1'0, B=1'1, Y=$procmux$4219_Y [0] New connections: $procmux$4219_Y [2:1] = { $procmux$4219_Y [0] $procmux$4219_Y [0] } Consolidated identical input bits for $mux cell $procmux$9047: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$244_EN[2:0]$468 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$244_EN[2:0]$468 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$244_EN[2:0]$468 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$244_EN[2:0]$468 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$244_EN[2:0]$468 [0] } Consolidated identical input bits for $mux cell $procmux$4205: Old ports: A=2'00, B=2'11, Y=$procmux$4205_Y New ports: A=1'0, B=1'1, Y=$procmux$4205_Y [0] New connections: $procmux$4205_Y [1] = $procmux$4205_Y [0] Consolidated identical input bits for $mux cell $procmux$7364: Old ports: A=2'00, B=2'11, Y=$procmux$7364_Y New ports: A=1'0, B=1'1, Y=$procmux$7364_Y [0] New connections: $procmux$7364_Y [1] = $procmux$7364_Y [0] Consolidated identical input bits for $mux cell $procmux$6043: Old ports: A=3'000, B=3'111, Y=$procmux$6043_Y New ports: A=1'0, B=1'1, Y=$procmux$6043_Y [0] New connections: $procmux$6043_Y [2:1] = { $procmux$6043_Y [0] $procmux$6043_Y [0] } Consolidated identical input bits for $mux cell $procmux$9044: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$245_EN[2:0]$469 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$245_EN[2:0]$469 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$245_EN[2:0]$469 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$245_EN[2:0]$469 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$245_EN[2:0]$469 [0] } Consolidated identical input bits for $mux cell $procmux$4168: Old ports: A=3'000, B=3'111, Y=$procmux$4168_Y New ports: A=1'0, B=1'1, Y=$procmux$4168_Y [0] New connections: $procmux$4168_Y [2:1] = { $procmux$4168_Y [0] $procmux$4168_Y [0] } Consolidated identical input bits for $mux cell $procmux$6029: Old ports: A=2'00, B=2'11, Y=$procmux$6029_Y New ports: A=1'0, B=1'1, Y=$procmux$6029_Y [0] New connections: $procmux$6029_Y [1] = $procmux$6029_Y [0] Consolidated identical input bits for $mux cell $procmux$9041: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$246_EN[1:0]$470 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$246_EN[1:0]$470 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$246_EN[1:0]$470 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$246_EN[1:0]$470 [0] Consolidated identical input bits for $mux cell $procmux$4154: Old ports: A=2'00, B=2'11, Y=$procmux$4154_Y New ports: A=1'0, B=1'1, Y=$procmux$4154_Y [0] New connections: $procmux$4154_Y [1] = $procmux$4154_Y [0] Consolidated identical input bits for $mux cell $procmux$8786: Old ports: A=4'0000, B=4'1111, Y=$procmux$8786_Y New ports: A=1'0, B=1'1, Y=$procmux$8786_Y [0] New connections: $procmux$8786_Y [3:1] = { $procmux$8786_Y [0] $procmux$8786_Y [0] $procmux$8786_Y [0] } Consolidated identical input bits for $mux cell $procmux$7327: Old ports: A=3'000, B=3'111, Y=$procmux$7327_Y New ports: A=1'0, B=1'1, Y=$procmux$7327_Y [0] New connections: $procmux$7327_Y [2:1] = { $procmux$7327_Y [0] $procmux$7327_Y [0] } Consolidated identical input bits for $mux cell $procmux$9038: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$247_EN[2:0]$471 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$247_EN[2:0]$471 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$247_EN[2:0]$471 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$247_EN[2:0]$471 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$247_EN[2:0]$471 [0] } Consolidated identical input bits for $mux cell $procmux$5992: Old ports: A=3'000, B=3'111, Y=$procmux$5992_Y New ports: A=1'0, B=1'1, Y=$procmux$5992_Y [0] New connections: $procmux$5992_Y [2:1] = { $procmux$5992_Y [0] $procmux$5992_Y [0] } Consolidated identical input bits for $mux cell $procmux$4117: Old ports: A=3'000, B=3'111, Y=$procmux$4117_Y New ports: A=1'0, B=1'1, Y=$procmux$4117_Y [0] New connections: $procmux$4117_Y [2:1] = { $procmux$4117_Y [0] $procmux$4117_Y [0] } Consolidated identical input bits for $mux cell $procmux$7313: Old ports: A=2'00, B=2'11, Y=$procmux$7313_Y New ports: A=1'0, B=1'1, Y=$procmux$7313_Y [0] New connections: $procmux$7313_Y [1] = $procmux$7313_Y [0] Consolidated identical input bits for $mux cell $procmux$9035: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$248_EN[2:0]$472 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$248_EN[2:0]$472 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$248_EN[2:0]$472 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$248_EN[2:0]$472 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$248_EN[2:0]$472 [0] } Consolidated identical input bits for $mux cell $procmux$4103: Old ports: A=2'00, B=2'11, Y=$procmux$4103_Y New ports: A=1'0, B=1'1, Y=$procmux$4103_Y [0] New connections: $procmux$4103_Y [1] = $procmux$4103_Y [0] Consolidated identical input bits for $mux cell $procmux$5978: Old ports: A=2'00, B=2'11, Y=$procmux$5978_Y New ports: A=1'0, B=1'1, Y=$procmux$5978_Y [0] New connections: $procmux$5978_Y [1] = $procmux$5978_Y [0] Consolidated identical input bits for $mux cell $procmux$9032: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$249_EN[1:0]$473 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$249_EN[1:0]$473 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$249_EN[1:0]$473 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$249_EN[1:0]$473 [0] Consolidated identical input bits for $mux cell $procmux$4066: Old ports: A=3'000, B=3'111, Y=$procmux$4066_Y New ports: A=1'0, B=1'1, Y=$procmux$4066_Y [0] New connections: $procmux$4066_Y [2:1] = { $procmux$4066_Y [0] $procmux$4066_Y [0] } Consolidated identical input bits for $mux cell $procmux$8768: Old ports: A=4'0000, B=4'1111, Y=$procmux$8768_Y New ports: A=1'0, B=1'1, Y=$procmux$8768_Y [0] New connections: $procmux$8768_Y [3:1] = { $procmux$8768_Y [0] $procmux$8768_Y [0] $procmux$8768_Y [0] } Consolidated identical input bits for $mux cell $procmux$4052: Old ports: A=2'00, B=2'11, Y=$procmux$4052_Y New ports: A=1'0, B=1'1, Y=$procmux$4052_Y [0] New connections: $procmux$4052_Y [1] = $procmux$4052_Y [0] Consolidated identical input bits for $mux cell $procmux$7276: Old ports: A=3'000, B=3'111, Y=$procmux$7276_Y New ports: A=1'0, B=1'1, Y=$procmux$7276_Y [0] New connections: $procmux$7276_Y [2:1] = { $procmux$7276_Y [0] $procmux$7276_Y [0] } Consolidated identical input bits for $mux cell $procmux$9029: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$250_EN[2:0]$474 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$250_EN[2:0]$474 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$250_EN[2:0]$474 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$250_EN[2:0]$474 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$250_EN[2:0]$474 [0] } Consolidated identical input bits for $mux cell $procmux$7262: Old ports: A=2'00, B=2'11, Y=$procmux$7262_Y New ports: A=1'0, B=1'1, Y=$procmux$7262_Y [0] New connections: $procmux$7262_Y [1] = $procmux$7262_Y [0] Consolidated identical input bits for $mux cell $procmux$9026: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$251_EN[2:0]$475 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$251_EN[2:0]$475 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$251_EN[2:0]$475 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$251_EN[2:0]$475 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$251_EN[2:0]$475 [0] } Consolidated identical input bits for $mux cell $procmux$9023: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$252_EN[1:0]$476 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$252_EN[1:0]$476 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$252_EN[1:0]$476 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$252_EN[1:0]$476 [0] Consolidated identical input bits for $mux cell $procmux$3898: Old ports: A=3'000, B=3'111, Y=$procmux$3898_Y New ports: A=1'0, B=1'1, Y=$procmux$3898_Y [0] New connections: $procmux$3898_Y [2:1] = { $procmux$3898_Y [0] $procmux$3898_Y [0] } Consolidated identical input bits for $mux cell $procmux$8744: Old ports: A=2'00, B=2'11, Y=$procmux$8744_Y New ports: A=1'0, B=1'1, Y=$procmux$8744_Y [0] New connections: $procmux$8744_Y [1] = $procmux$8744_Y [0] Consolidated identical input bits for $mux cell $procmux$3884: Old ports: A=2'00, B=2'11, Y=$procmux$3884_Y New ports: A=1'0, B=1'1, Y=$procmux$3884_Y [0] New connections: $procmux$3884_Y [1] = $procmux$3884_Y [0] Consolidated identical input bits for $mux cell $procmux$9020: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$253_EN[2:0]$477 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$253_EN[2:0]$477 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$253_EN[2:0]$477 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$253_EN[2:0]$477 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$253_EN[2:0]$477 [0] } Consolidated identical input bits for $mux cell $procmux$5824: Old ports: A=3'000, B=3'111, Y=$procmux$5824_Y New ports: A=1'0, B=1'1, Y=$procmux$5824_Y [0] New connections: $procmux$5824_Y [2:1] = { $procmux$5824_Y [0] $procmux$5824_Y [0] } Consolidated identical input bits for $mux cell $procmux$5810: Old ports: A=2'00, B=2'11, Y=$procmux$5810_Y New ports: A=1'0, B=1'1, Y=$procmux$5810_Y [0] New connections: $procmux$5810_Y [1] = $procmux$5810_Y [0] Consolidated identical input bits for $mux cell $procmux$9017: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$254_EN[2:0]$478 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$254_EN[2:0]$478 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$254_EN[2:0]$478 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$254_EN[2:0]$478 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$254_EN[2:0]$478 [0] } Consolidated identical input bits for $mux cell $procmux$3847: Old ports: A=3'000, B=3'111, Y=$procmux$3847_Y New ports: A=1'0, B=1'1, Y=$procmux$3847_Y [0] New connections: $procmux$3847_Y [2:1] = { $procmux$3847_Y [0] $procmux$3847_Y [0] } Consolidated identical input bits for $mux cell $procmux$3833: Old ports: A=2'00, B=2'11, Y=$procmux$3833_Y New ports: A=1'0, B=1'1, Y=$procmux$3833_Y [0] New connections: $procmux$3833_Y [1] = $procmux$3833_Y [0] Consolidated identical input bits for $mux cell $procmux$9014: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$255_EN[1:0]$479 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$255_EN[1:0]$479 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$255_EN[1:0]$479 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$255_EN[1:0]$479 [0] Consolidated identical input bits for $mux cell $procmux$5773: Old ports: A=3'000, B=3'111, Y=$procmux$5773_Y New ports: A=1'0, B=1'1, Y=$procmux$5773_Y [0] New connections: $procmux$5773_Y [2:1] = { $procmux$5773_Y [0] $procmux$5773_Y [0] } Consolidated identical input bits for $mux cell $procmux$3796: Old ports: A=3'000, B=3'111, Y=$procmux$3796_Y New ports: A=1'0, B=1'1, Y=$procmux$3796_Y [0] New connections: $procmux$3796_Y [2:1] = { $procmux$3796_Y [0] $procmux$3796_Y [0] } Consolidated identical input bits for $mux cell $procmux$5759: Old ports: A=2'00, B=2'11, Y=$procmux$5759_Y New ports: A=1'0, B=1'1, Y=$procmux$5759_Y [0] New connections: $procmux$5759_Y [1] = $procmux$5759_Y [0] Consolidated identical input bits for $mux cell $procmux$9011: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$256_EN[2:0]$480 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$256_EN[2:0]$480 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$256_EN[2:0]$480 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$256_EN[2:0]$480 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$256_EN[2:0]$480 [0] } Consolidated identical input bits for $mux cell $procmux$3782: Old ports: A=2'00, B=2'11, Y=$procmux$3782_Y New ports: A=1'0, B=1'1, Y=$procmux$3782_Y [0] New connections: $procmux$3782_Y [1] = $procmux$3782_Y [0] Consolidated identical input bits for $mux cell $procmux$3745: Old ports: A=3'000, B=3'111, Y=$procmux$3745_Y New ports: A=1'0, B=1'1, Y=$procmux$3745_Y [0] New connections: $procmux$3745_Y [2:1] = { $procmux$3745_Y [0] $procmux$3745_Y [0] } Consolidated identical input bits for $mux cell $procmux$5722: Old ports: A=3'000, B=3'111, Y=$procmux$5722_Y New ports: A=1'0, B=1'1, Y=$procmux$5722_Y [0] New connections: $procmux$5722_Y [2:1] = { $procmux$5722_Y [0] $procmux$5722_Y [0] } Consolidated identical input bits for $mux cell $procmux$9008: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$257_EN[2:0]$481 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$257_EN[2:0]$481 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$257_EN[2:0]$481 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$257_EN[2:0]$481 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$257_EN[2:0]$481 [0] } Consolidated identical input bits for $mux cell $procmux$3731: Old ports: A=2'00, B=2'11, Y=$procmux$3731_Y New ports: A=1'0, B=1'1, Y=$procmux$3731_Y [0] New connections: $procmux$3731_Y [1] = $procmux$3731_Y [0] Consolidated identical input bits for $mux cell $procmux$5708: Old ports: A=2'00, B=2'11, Y=$procmux$5708_Y New ports: A=1'0, B=1'1, Y=$procmux$5708_Y [0] New connections: $procmux$5708_Y [1] = $procmux$5708_Y [0] Consolidated identical input bits for $mux cell $procmux$9005: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$258_EN[1:0]$482 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$258_EN[1:0]$482 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$258_EN[1:0]$482 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$258_EN[1:0]$482 [0] Consolidated identical input bits for $mux cell $procmux$7108: Old ports: A=3'000, B=3'111, Y=$procmux$7108_Y New ports: A=1'0, B=1'1, Y=$procmux$7108_Y [0] New connections: $procmux$7108_Y [2:1] = { $procmux$7108_Y [0] $procmux$7108_Y [0] } Consolidated identical input bits for $mux cell $procmux$9002: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$259_EN[2:0]$483 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$259_EN[2:0]$483 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$259_EN[2:0]$483 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$259_EN[2:0]$483 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$259_EN[2:0]$483 [0] } Consolidated identical input bits for $mux cell $procmux$7094: Old ports: A=2'00, B=2'11, Y=$procmux$7094_Y New ports: A=1'0, B=1'1, Y=$procmux$7094_Y [0] New connections: $procmux$7094_Y [1] = $procmux$7094_Y [0] Consolidated identical input bits for $mux cell $procmux$5671: Old ports: A=3'000, B=3'111, Y=$procmux$5671_Y New ports: A=1'0, B=1'1, Y=$procmux$5671_Y [0] New connections: $procmux$5671_Y [2:1] = { $procmux$5671_Y [0] $procmux$5671_Y [0] } Consolidated identical input bits for $mux cell $procmux$8999: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$260_EN[2:0]$484 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$260_EN[2:0]$484 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$260_EN[2:0]$484 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$260_EN[2:0]$484 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$260_EN[2:0]$484 [0] } Consolidated identical input bits for $mux cell $procmux$5657: Old ports: A=2'00, B=2'11, Y=$procmux$5657_Y New ports: A=1'0, B=1'1, Y=$procmux$5657_Y [0] New connections: $procmux$5657_Y [1] = $procmux$5657_Y [0] Consolidated identical input bits for $mux cell $procmux$8996: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$261_EN[1:0]$485 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$261_EN[1:0]$485 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$261_EN[1:0]$485 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$261_EN[1:0]$485 [0] Consolidated identical input bits for $mux cell $procmux$7057: Old ports: A=3'000, B=3'111, Y=$procmux$7057_Y New ports: A=1'0, B=1'1, Y=$procmux$7057_Y [0] New connections: $procmux$7057_Y [2:1] = { $procmux$7057_Y [0] $procmux$7057_Y [0] } Consolidated identical input bits for $mux cell $procmux$8993: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$262_EN[2:0]$486 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$262_EN[2:0]$486 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$262_EN[2:0]$486 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$262_EN[2:0]$486 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$262_EN[2:0]$486 [0] } Consolidated identical input bits for $mux cell $procmux$3577: Old ports: A=3'000, B=3'111, Y=$procmux$3577_Y New ports: A=1'0, B=1'1, Y=$procmux$3577_Y [0] New connections: $procmux$3577_Y [2:1] = { $procmux$3577_Y [0] $procmux$3577_Y [0] } Consolidated identical input bits for $mux cell $procmux$3563: Old ports: A=2'00, B=2'11, Y=$procmux$3563_Y New ports: A=1'0, B=1'1, Y=$procmux$3563_Y [0] New connections: $procmux$3563_Y [1] = $procmux$3563_Y [0] Consolidated identical input bits for $mux cell $procmux$7043: Old ports: A=2'00, B=2'11, Y=$procmux$7043_Y New ports: A=1'0, B=1'1, Y=$procmux$7043_Y [0] New connections: $procmux$7043_Y [1] = $procmux$7043_Y [0] Consolidated identical input bits for $mux cell $procmux$8990: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$263_EN[2:0]$487 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$263_EN[2:0]$487 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$263_EN[2:0]$487 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$263_EN[2:0]$487 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$263_EN[2:0]$487 [0] } Consolidated identical input bits for $mux cell $procmux$3526: Old ports: A=3'000, B=3'111, Y=$procmux$3526_Y New ports: A=1'0, B=1'1, Y=$procmux$3526_Y [0] New connections: $procmux$3526_Y [2:1] = { $procmux$3526_Y [0] $procmux$3526_Y [0] } Consolidated identical input bits for $mux cell $procmux$8987: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$264_EN[1:0]$488 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$264_EN[1:0]$488 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$264_EN[1:0]$488 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$264_EN[1:0]$488 [0] Consolidated identical input bits for $mux cell $procmux$3512: Old ports: A=2'00, B=2'11, Y=$procmux$3512_Y New ports: A=1'0, B=1'1, Y=$procmux$3512_Y [0] New connections: $procmux$3512_Y [1] = $procmux$3512_Y [0] Consolidated identical input bits for $mux cell $procmux$7006: Old ports: A=3'000, B=3'111, Y=$procmux$7006_Y New ports: A=1'0, B=1'1, Y=$procmux$7006_Y [0] New connections: $procmux$7006_Y [2:1] = { $procmux$7006_Y [0] $procmux$7006_Y [0] } Consolidated identical input bits for $mux cell $procmux$3475: Old ports: A=3'000, B=3'111, Y=$procmux$3475_Y New ports: A=1'0, B=1'1, Y=$procmux$3475_Y [0] New connections: $procmux$3475_Y [2:1] = { $procmux$3475_Y [0] $procmux$3475_Y [0] } Consolidated identical input bits for $mux cell $procmux$8984: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$265_EN[2:0]$489 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$265_EN[2:0]$489 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$265_EN[2:0]$489 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$265_EN[2:0]$489 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$265_EN[2:0]$489 [0] } Consolidated identical input bits for $mux cell $procmux$3461: Old ports: A=2'00, B=2'11, Y=$procmux$3461_Y New ports: A=1'0, B=1'1, Y=$procmux$3461_Y [0] New connections: $procmux$3461_Y [1] = $procmux$3461_Y [0] Consolidated identical input bits for $mux cell $procmux$6992: Old ports: A=2'00, B=2'11, Y=$procmux$6992_Y New ports: A=1'0, B=1'1, Y=$procmux$6992_Y [0] New connections: $procmux$6992_Y [1] = $procmux$6992_Y [0] Consolidated identical input bits for $mux cell $procmux$8981: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$266_EN[2:0]$490 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$266_EN[2:0]$490 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$266_EN[2:0]$490 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$266_EN[2:0]$490 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$266_EN[2:0]$490 [0] } Consolidated identical input bits for $mux cell $procmux$5503: Old ports: A=3'000, B=3'111, Y=$procmux$5503_Y New ports: A=1'0, B=1'1, Y=$procmux$5503_Y [0] New connections: $procmux$5503_Y [2:1] = { $procmux$5503_Y [0] $procmux$5503_Y [0] } Consolidated identical input bits for $mux cell $procmux$3424: Old ports: A=3'000, B=3'111, Y=$procmux$3424_Y New ports: A=1'0, B=1'1, Y=$procmux$3424_Y [0] New connections: $procmux$3424_Y [2:1] = { $procmux$3424_Y [0] $procmux$3424_Y [0] } Consolidated identical input bits for $mux cell $procmux$8978: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$267_EN[1:0]$491 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$267_EN[1:0]$491 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$267_EN[1:0]$491 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$267_EN[1:0]$491 [0] Consolidated identical input bits for $mux cell $procmux$5489: Old ports: A=2'00, B=2'11, Y=$procmux$5489_Y New ports: A=1'0, B=1'1, Y=$procmux$5489_Y [0] New connections: $procmux$5489_Y [1] = $procmux$5489_Y [0] Consolidated identical input bits for $mux cell $procmux$3410: Old ports: A=2'00, B=2'11, Y=$procmux$3410_Y New ports: A=1'0, B=1'1, Y=$procmux$3410_Y [0] New connections: $procmux$3410_Y [1] = $procmux$3410_Y [0] Consolidated identical input bits for $mux cell $procmux$8975: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$268_EN[2:0]$492 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$268_EN[2:0]$492 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$268_EN[2:0]$492 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$268_EN[2:0]$492 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$268_EN[2:0]$492 [0] } Consolidated identical input bits for $mux cell $procmux$6955: Old ports: A=3'000, B=3'111, Y=$procmux$6955_Y New ports: A=1'0, B=1'1, Y=$procmux$6955_Y [0] New connections: $procmux$6955_Y [2:1] = { $procmux$6955_Y [0] $procmux$6955_Y [0] } Consolidated identical input bits for $mux cell $procmux$8972: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$269_EN[2:0]$493 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$269_EN[2:0]$493 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$269_EN[2:0]$493 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$269_EN[2:0]$493 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$269_EN[2:0]$493 [0] } Consolidated identical input bits for $mux cell $procmux$5452: Old ports: A=3'000, B=3'111, Y=$procmux$5452_Y New ports: A=1'0, B=1'1, Y=$procmux$5452_Y [0] New connections: $procmux$5452_Y [2:1] = { $procmux$5452_Y [0] $procmux$5452_Y [0] } Consolidated identical input bits for $mux cell $procmux$6941: Old ports: A=2'00, B=2'11, Y=$procmux$6941_Y New ports: A=1'0, B=1'1, Y=$procmux$6941_Y [0] New connections: $procmux$6941_Y [1] = $procmux$6941_Y [0] Consolidated identical input bits for $mux cell $procmux$5438: Old ports: A=2'00, B=2'11, Y=$procmux$5438_Y New ports: A=1'0, B=1'1, Y=$procmux$5438_Y [0] New connections: $procmux$5438_Y [1] = $procmux$5438_Y [0] Consolidated identical input bits for $mux cell $procmux$8969: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$270_EN[1:0]$494 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$270_EN[1:0]$494 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$270_EN[1:0]$494 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$270_EN[1:0]$494 [0] Consolidated identical input bits for $mux cell $procmux$8966: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$271_EN[2:0]$495 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$271_EN[2:0]$495 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$271_EN[2:0]$495 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$271_EN[2:0]$495 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$271_EN[2:0]$495 [0] } Consolidated identical input bits for $mux cell $procmux$5401: Old ports: A=3'000, B=3'111, Y=$procmux$5401_Y New ports: A=1'0, B=1'1, Y=$procmux$5401_Y [0] New connections: $procmux$5401_Y [2:1] = { $procmux$5401_Y [0] $procmux$5401_Y [0] } Consolidated identical input bits for $mux cell $procmux$5387: Old ports: A=2'00, B=2'11, Y=$procmux$5387_Y New ports: A=1'0, B=1'1, Y=$procmux$5387_Y [0] New connections: $procmux$5387_Y [1] = $procmux$5387_Y [0] Consolidated identical input bits for $mux cell $procmux$3256: Old ports: A=3'000, B=3'111, Y=$procmux$3256_Y New ports: A=1'0, B=1'1, Y=$procmux$3256_Y [0] New connections: $procmux$3256_Y [2:1] = { $procmux$3256_Y [0] $procmux$3256_Y [0] } Consolidated identical input bits for $mux cell $procmux$8963: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$272_EN[2:0]$496 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$272_EN[2:0]$496 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$272_EN[2:0]$496 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$272_EN[2:0]$496 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$272_EN[2:0]$496 [0] } Consolidated identical input bits for $mux cell $procmux$3242: Old ports: A=2'00, B=2'11, Y=$procmux$3242_Y New ports: A=1'0, B=1'1, Y=$procmux$3242_Y [0] New connections: $procmux$3242_Y [1] = $procmux$3242_Y [0] Consolidated identical input bits for $mux cell $procmux$8960: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$273_EN[1:0]$497 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$273_EN[1:0]$497 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$273_EN[1:0]$497 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$273_EN[1:0]$497 [0] Consolidated identical input bits for $mux cell $procmux$5350: Old ports: A=3'000, B=3'111, Y=$procmux$5350_Y New ports: A=1'0, B=1'1, Y=$procmux$5350_Y [0] New connections: $procmux$5350_Y [2:1] = { $procmux$5350_Y [0] $procmux$5350_Y [0] } Consolidated identical input bits for $mux cell $procmux$3205: Old ports: A=3'000, B=3'111, Y=$procmux$3205_Y New ports: A=1'0, B=1'1, Y=$procmux$3205_Y [0] New connections: $procmux$3205_Y [2:1] = { $procmux$3205_Y [0] $procmux$3205_Y [0] } Consolidated identical input bits for $mux cell $procmux$8957: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$274_EN[2:0]$498 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$274_EN[2:0]$498 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$274_EN[2:0]$498 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$274_EN[2:0]$498 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$274_EN[2:0]$498 [0] } Consolidated identical input bits for $mux cell $procmux$5336: Old ports: A=2'00, B=2'11, Y=$procmux$5336_Y New ports: A=1'0, B=1'1, Y=$procmux$5336_Y [0] New connections: $procmux$5336_Y [1] = $procmux$5336_Y [0] Consolidated identical input bits for $mux cell $procmux$3191: Old ports: A=2'00, B=2'11, Y=$procmux$3191_Y New ports: A=1'0, B=1'1, Y=$procmux$3191_Y [0] New connections: $procmux$3191_Y [1] = $procmux$3191_Y [0] Consolidated identical input bits for $mux cell $procmux$8954: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$275_EN[2:0]$499 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$275_EN[2:0]$499 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$275_EN[2:0]$499 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$275_EN[2:0]$499 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$275_EN[2:0]$499 [0] } Consolidated identical input bits for $mux cell $procmux$3154: Old ports: A=3'000, B=3'111, Y=$procmux$3154_Y New ports: A=1'0, B=1'1, Y=$procmux$3154_Y [0] New connections: $procmux$3154_Y [2:1] = { $procmux$3154_Y [0] $procmux$3154_Y [0] } Consolidated identical input bits for $mux cell $procmux$3140: Old ports: A=2'00, B=2'11, Y=$procmux$3140_Y New ports: A=1'0, B=1'1, Y=$procmux$3140_Y [0] New connections: $procmux$3140_Y [1] = $procmux$3140_Y [0] Consolidated identical input bits for $mux cell $procmux$8951: Old ports: A=2'00, B=2'11, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$276_EN[1:0]$500 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$276_EN[1:0]$500 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$276_EN[1:0]$500 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$276_EN[1:0]$500 [0] Consolidated identical input bits for $mux cell $procmux$3103: Old ports: A=3'000, B=3'111, Y=$procmux$3103_Y New ports: A=1'0, B=1'1, Y=$procmux$3103_Y [0] New connections: $procmux$3103_Y [2:1] = { $procmux$3103_Y [0] $procmux$3103_Y [0] } Consolidated identical input bits for $mux cell $procmux$3089: Old ports: A=2'00, B=2'11, Y=$procmux$3089_Y New ports: A=1'0, B=1'1, Y=$procmux$3089_Y [0] New connections: $procmux$3089_Y [1] = $procmux$3089_Y [0] Consolidated identical input bits for $mux cell $procmux$8948: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$277_EN[2:0]$501 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$277_EN[2:0]$501 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$277_EN[2:0]$501 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$277_EN[2:0]$501 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$277_EN[2:0]$501 [0] } Consolidated identical input bits for $mux cell $procmux$6787: Old ports: A=3'000, B=3'111, Y=$procmux$6787_Y New ports: A=1'0, B=1'1, Y=$procmux$6787_Y [0] New connections: $procmux$6787_Y [2:1] = { $procmux$6787_Y [0] $procmux$6787_Y [0] } Consolidated identical input bits for $mux cell $procmux$8945: Old ports: A=3'000, B=3'111, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$278_EN[2:0]$502 New ports: A=1'0, B=1'1, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$278_EN[2:0]$502 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$278_EN[2:0]$502 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$278_EN[2:0]$502 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$278_EN[2:0]$502 [0] } Consolidated identical input bits for $mux cell $procmux$6773: Old ports: A=2'00, B=2'11, Y=$procmux$6773_Y New ports: A=1'0, B=1'1, Y=$procmux$6773_Y [0] New connections: $procmux$6773_Y [1] = $procmux$6773_Y [0] Consolidated identical input bits for $mux cell $procmux$5182: Old ports: A=3'000, B=3'111, Y=$procmux$5182_Y New ports: A=1'0, B=1'1, Y=$procmux$5182_Y [0] New connections: $procmux$5182_Y [2:1] = { $procmux$5182_Y [0] $procmux$5182_Y [0] } Consolidated identical input bits for $mux cell $procmux$5168: Old ports: A=2'00, B=2'11, Y=$procmux$5168_Y New ports: A=1'0, B=1'1, Y=$procmux$5168_Y [0] New connections: $procmux$5168_Y [1] = $procmux$5168_Y [0] Consolidated identical input bits for $mux cell $procmux$6736: Old ports: A=3'000, B=3'111, Y=$procmux$6736_Y New ports: A=1'0, B=1'1, Y=$procmux$6736_Y [0] New connections: $procmux$6736_Y [2:1] = { $procmux$6736_Y [0] $procmux$6736_Y [0] } Consolidated identical input bits for $mux cell $procmux$2935: Old ports: A=3'000, B=3'111, Y=$procmux$2935_Y New ports: A=1'0, B=1'1, Y=$procmux$2935_Y [0] New connections: $procmux$2935_Y [2:1] = { $procmux$2935_Y [0] $procmux$2935_Y [0] } Consolidated identical input bits for $mux cell $procmux$2921: Old ports: A=2'00, B=2'11, Y=$procmux$2921_Y New ports: A=1'0, B=1'1, Y=$procmux$2921_Y [0] New connections: $procmux$2921_Y [1] = $procmux$2921_Y [0] Consolidated identical input bits for $mux cell $procmux$6722: Old ports: A=2'00, B=2'11, Y=$procmux$6722_Y New ports: A=1'0, B=1'1, Y=$procmux$6722_Y [0] New connections: $procmux$6722_Y [1] = $procmux$6722_Y [0] Consolidated identical input bits for $mux cell $procmux$5131: Old ports: A=3'000, B=3'111, Y=$procmux$5131_Y New ports: A=1'0, B=1'1, Y=$procmux$5131_Y [0] New connections: $procmux$5131_Y [2:1] = { $procmux$5131_Y [0] $procmux$5131_Y [0] } Consolidated identical input bits for $mux cell $procmux$2884: Old ports: A=3'000, B=3'111, Y=$procmux$2884_Y New ports: A=1'0, B=1'1, Y=$procmux$2884_Y [0] New connections: $procmux$2884_Y [2:1] = { $procmux$2884_Y [0] $procmux$2884_Y [0] } Consolidated identical input bits for $mux cell $procmux$5117: Old ports: A=2'00, B=2'11, Y=$procmux$5117_Y New ports: A=1'0, B=1'1, Y=$procmux$5117_Y [0] New connections: $procmux$5117_Y [1] = $procmux$5117_Y [0] Consolidated identical input bits for $mux cell $procmux$2870: Old ports: A=2'00, B=2'11, Y=$procmux$2870_Y New ports: A=1'0, B=1'1, Y=$procmux$2870_Y [0] New connections: $procmux$2870_Y [1] = $procmux$2870_Y [0] Consolidated identical input bits for $mux cell $procmux$6685: Old ports: A=3'000, B=3'111, Y=$procmux$6685_Y New ports: A=1'0, B=1'1, Y=$procmux$6685_Y [0] New connections: $procmux$6685_Y [2:1] = { $procmux$6685_Y [0] $procmux$6685_Y [0] } Consolidated identical input bits for $mux cell $procmux$5080: Old ports: A=3'000, B=3'111, Y=$procmux$5080_Y New ports: A=1'0, B=1'1, Y=$procmux$5080_Y [0] New connections: $procmux$5080_Y [2:1] = { $procmux$5080_Y [0] $procmux$5080_Y [0] } Consolidated identical input bits for $mux cell $procmux$2833: Old ports: A=3'000, B=3'111, Y=$procmux$2833_Y New ports: A=1'0, B=1'1, Y=$procmux$2833_Y [0] New connections: $procmux$2833_Y [2:1] = { $procmux$2833_Y [0] $procmux$2833_Y [0] } Consolidated identical input bits for $mux cell $procmux$6671: Old ports: A=2'00, B=2'11, Y=$procmux$6671_Y New ports: A=1'0, B=1'1, Y=$procmux$6671_Y [0] New connections: $procmux$6671_Y [1] = $procmux$6671_Y [0] Consolidated identical input bits for $mux cell $procmux$8924: Old ports: A=3'000, B=3'111, Y=$procmux$8924_Y New ports: A=1'0, B=1'1, Y=$procmux$8924_Y [0] New connections: $procmux$8924_Y [2:1] = { $procmux$8924_Y [0] $procmux$8924_Y [0] } Consolidated identical input bits for $mux cell $procmux$2819: Old ports: A=2'00, B=2'11, Y=$procmux$2819_Y New ports: A=1'0, B=1'1, Y=$procmux$2819_Y [0] New connections: $procmux$2819_Y [1] = $procmux$2819_Y [0] Consolidated identical input bits for $mux cell $procmux$5066: Old ports: A=2'00, B=2'11, Y=$procmux$5066_Y New ports: A=1'0, B=1'1, Y=$procmux$5066_Y [0] New connections: $procmux$5066_Y [1] = $procmux$5066_Y [0] Consolidated identical input bits for $mux cell $procmux$2782: Old ports: A=3'000, B=3'111, Y=$procmux$2782_Y New ports: A=1'0, B=1'1, Y=$procmux$2782_Y [0] New connections: $procmux$2782_Y [2:1] = { $procmux$2782_Y [0] $procmux$2782_Y [0] } Consolidated identical input bits for $mux cell $procmux$5029: Old ports: A=3'000, B=3'111, Y=$procmux$5029_Y New ports: A=1'0, B=1'1, Y=$procmux$5029_Y [0] New connections: $procmux$5029_Y [2:1] = { $procmux$5029_Y [0] $procmux$5029_Y [0] } Consolidated identical input bits for $mux cell $procmux$2768: Old ports: A=2'00, B=2'11, Y=$procmux$2768_Y New ports: A=1'0, B=1'1, Y=$procmux$2768_Y [0] New connections: $procmux$2768_Y [1] = $procmux$2768_Y [0] Consolidated identical input bits for $mux cell $procmux$6634: Old ports: A=3'000, B=3'111, Y=$procmux$6634_Y New ports: A=1'0, B=1'1, Y=$procmux$6634_Y [0] New connections: $procmux$6634_Y [2:1] = { $procmux$6634_Y [0] $procmux$6634_Y [0] } Consolidated identical input bits for $mux cell $procmux$5015: Old ports: A=2'00, B=2'11, Y=$procmux$5015_Y New ports: A=1'0, B=1'1, Y=$procmux$5015_Y [0] New connections: $procmux$5015_Y [1] = $procmux$5015_Y [0] Consolidated identical input bits for $mux cell $procmux$6620: Old ports: A=2'00, B=2'11, Y=$procmux$6620_Y New ports: A=1'0, B=1'1, Y=$procmux$6620_Y [0] New connections: $procmux$6620_Y [1] = $procmux$6620_Y [0] Consolidated identical input bits for $mux cell $procmux$8912: Old ports: A=3'000, B=3'111, Y=$procmux$8912_Y New ports: A=1'0, B=1'1, Y=$procmux$8912_Y [0] New connections: $procmux$8912_Y [2:1] = { $procmux$8912_Y [0] $procmux$8912_Y [0] } Consolidated identical input bits for $mux cell $procmux$2614: Old ports: A=3'000, B=3'111, Y=$procmux$2614_Y New ports: A=1'0, B=1'1, Y=$procmux$2614_Y [0] New connections: $procmux$2614_Y [2:1] = { $procmux$2614_Y [0] $procmux$2614_Y [0] } Consolidated identical input bits for $mux cell $procmux$2600: Old ports: A=2'00, B=2'11, Y=$procmux$2600_Y New ports: A=1'0, B=1'1, Y=$procmux$2600_Y [0] New connections: $procmux$2600_Y [1] = $procmux$2600_Y [0] Consolidated identical input bits for $mux cell $procmux$2563: Old ports: A=3'000, B=3'111, Y=$procmux$2563_Y New ports: A=1'0, B=1'1, Y=$procmux$2563_Y [0] New connections: $procmux$2563_Y [2:1] = { $procmux$2563_Y [0] $procmux$2563_Y [0] } Consolidated identical input bits for $mux cell $procmux$2549: Old ports: A=2'00, B=2'11, Y=$procmux$2549_Y New ports: A=1'0, B=1'1, Y=$procmux$2549_Y [0] New connections: $procmux$2549_Y [1] = $procmux$2549_Y [0] Consolidated identical input bits for $mux cell $procmux$4861: Old ports: A=3'000, B=3'111, Y=$procmux$4861_Y New ports: A=1'0, B=1'1, Y=$procmux$4861_Y [0] New connections: $procmux$4861_Y [2:1] = { $procmux$4861_Y [0] $procmux$4861_Y [0] } Consolidated identical input bits for $mux cell $procmux$2512: Old ports: A=3'000, B=3'111, Y=$procmux$2512_Y New ports: A=1'0, B=1'1, Y=$procmux$2512_Y [0] New connections: $procmux$2512_Y [2:1] = { $procmux$2512_Y [0] $procmux$2512_Y [0] } Consolidated identical input bits for $mux cell $procmux$4847: Old ports: A=2'00, B=2'11, Y=$procmux$4847_Y New ports: A=1'0, B=1'1, Y=$procmux$4847_Y [0] New connections: $procmux$4847_Y [1] = $procmux$4847_Y [0] Consolidated identical input bits for $mux cell $procmux$2498: Old ports: A=2'00, B=2'11, Y=$procmux$2498_Y New ports: A=1'0, B=1'1, Y=$procmux$2498_Y [0] New connections: $procmux$2498_Y [1] = $procmux$2498_Y [0] Consolidated identical input bits for $mux cell $procmux$8894: Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$procmux$8894_Y New ports: A=1'0, B=1'1, Y=$procmux$8894_Y [0] New connections: $procmux$8894_Y [22:1] = { $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] $procmux$8894_Y [0] } Consolidated identical input bits for $mux cell $procmux$2461: Old ports: A=3'000, B=3'111, Y=$procmux$2461_Y New ports: A=1'0, B=1'1, Y=$procmux$2461_Y [0] New connections: $procmux$2461_Y [2:1] = { $procmux$2461_Y [0] $procmux$2461_Y [0] } Consolidated identical input bits for $mux cell $procmux$4810: Old ports: A=3'000, B=3'111, Y=$procmux$4810_Y New ports: A=1'0, B=1'1, Y=$procmux$4810_Y [0] New connections: $procmux$4810_Y [2:1] = { $procmux$4810_Y [0] $procmux$4810_Y [0] } Consolidated identical input bits for $mux cell $procmux$2447: Old ports: A=2'00, B=2'11, Y=$procmux$2447_Y New ports: A=1'0, B=1'1, Y=$procmux$2447_Y [0] New connections: $procmux$2447_Y [1] = $procmux$2447_Y [0] Consolidated identical input bits for $mux cell $procmux$4796: Old ports: A=2'00, B=2'11, Y=$procmux$4796_Y New ports: A=1'0, B=1'1, Y=$procmux$4796_Y [0] New connections: $procmux$4796_Y [1] = $procmux$4796_Y [0] Consolidated identical input bits for $mux cell $procmux$2432: Old ports: A=2'00, B=2'11, Y=$procmux$2432_Y New ports: A=1'0, B=1'1, Y=$procmux$2432_Y [0] New connections: $procmux$2432_Y [1] = $procmux$2432_Y [0] Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $procmux$4783: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN[1:0]$1886, Y=$procmux$4783_Y New ports: A=1'0, B=$procmux$4745_Y [0], Y=$procmux$4783_Y [0] New connections: $procmux$4783_Y [1] = $procmux$4783_Y [0] Consolidated identical input bits for $mux cell $procmux$6439: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN[1:0]$1501, Y=$procmux$6439_Y New ports: A=1'0, B=$procmux$6401_Y [0], Y=$procmux$6439_Y [0] New connections: $procmux$6439_Y [1] = $procmux$6439_Y [0] Consolidated identical input bits for $mux cell $procmux$9089: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_EN[1:0]$2424, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_EN[1:0]$728 New ports: A=$procmux$2432_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_EN[1:0]$728 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_EN[1:0]$728 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$418_EN[1:0]$728 [0] Consolidated identical input bits for $mux cell $procmux$4732: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN[1:0]$1901, Y=$procmux$4732_Y New ports: A=1'0, B=$procmux$4694_Y [0], Y=$procmux$4732_Y [0] New connections: $procmux$4732_Y [1] = $procmux$4732_Y [0] Consolidated identical input bits for $mux cell $procmux$6388: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN[1:0]$1516, Y=$procmux$6388_Y New ports: A=1'0, B=$procmux$6350_Y [0], Y=$procmux$6388_Y [0] New connections: $procmux$6388_Y [1] = $procmux$6388_Y [0] Consolidated identical input bits for $mux cell $procmux$4665: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN[2:0]$1925, Y=$procmux$4665_Y New ports: A=1'0, B=$procmux$4540_Y [0], Y=$procmux$4665_Y [0] New connections: $procmux$4665_Y [2:1] = { $procmux$4665_Y [0] $procmux$4665_Y [0] } Consolidated identical input bits for $mux cell $procmux$4638: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN[2:0]$1940, Y=$procmux$4638_Y New ports: A=1'0, B=$procmux$4489_Y [0], Y=$procmux$4638_Y [0] New connections: $procmux$4638_Y [2:1] = { $procmux$4638_Y [0] $procmux$4638_Y [0] } Consolidated identical input bits for $mux cell $procmux$4611: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN[2:0]$1955, Y=$procmux$4611_Y New ports: A=1'0, B=$procmux$4438_Y [0], Y=$procmux$4611_Y [0] New connections: $procmux$4611_Y [2:1] = { $procmux$4611_Y [0] $procmux$4611_Y [0] } Consolidated identical input bits for $mux cell $procmux$6337: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN[1:0]$1531, Y=$procmux$6337_Y New ports: A=1'0, B=$procmux$6299_Y [0], Y=$procmux$6337_Y [0] New connections: $procmux$6337_Y [1] = $procmux$6337_Y [0] Consolidated identical input bits for $mux cell $procmux$4584: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN[2:0]$1970, Y=$procmux$4584_Y New ports: A=1'0, B=$procmux$4387_Y [0], Y=$procmux$4584_Y [0] New connections: $procmux$4584_Y [2:1] = { $procmux$4584_Y [0] $procmux$4584_Y [0] } Consolidated identical input bits for $mux cell $procmux$7554: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN[2:0]$1259, Y=$procmux$7554_Y New ports: A=1'0, B=$procmux$7429_Y [0], Y=$procmux$7554_Y [0] New connections: $procmux$7554_Y [2:1] = { $procmux$7554_Y [0] $procmux$7554_Y [0] } Consolidated identical input bits for $mux cell $procmux$4564: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN[1:0]$1930, Y=$procmux$4564_Y New ports: A=1'0, B=$procmux$4526_Y [0], Y=$procmux$4564_Y [0] New connections: $procmux$4564_Y [1] = $procmux$4564_Y [0] Consolidated identical input bits for $mux cell $procmux$7527: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN[2:0]$1274, Y=$procmux$7527_Y New ports: A=1'0, B=$procmux$7378_Y [0], Y=$procmux$7527_Y [0] New connections: $procmux$7527_Y [2:1] = { $procmux$7527_Y [0] $procmux$7527_Y [0] } Consolidated identical input bits for $mux cell $procmux$4513: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN[1:0]$1945, Y=$procmux$4513_Y New ports: A=1'0, B=$procmux$4475_Y [0], Y=$procmux$4513_Y [0] New connections: $procmux$4513_Y [1] = $procmux$4513_Y [0] Consolidated identical input bits for $mux cell $procmux$6270: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN[2:0]$1555, Y=$procmux$6270_Y New ports: A=1'0, B=$procmux$6145_Y [0], Y=$procmux$6270_Y [0] New connections: $procmux$6270_Y [2:1] = { $procmux$6270_Y [0] $procmux$6270_Y [0] } Consolidated identical input bits for $mux cell $procmux$7500: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN[2:0]$1289, Y=$procmux$7500_Y New ports: A=1'0, B=$procmux$7327_Y [0], Y=$procmux$7500_Y [0] New connections: $procmux$7500_Y [2:1] = { $procmux$7500_Y [0] $procmux$7500_Y [0] } Consolidated identical input bits for $mux cell $procmux$6243: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN[2:0]$1570, Y=$procmux$6243_Y New ports: A=1'0, B=$procmux$6094_Y [0], Y=$procmux$6243_Y [0] New connections: $procmux$6243_Y [2:1] = { $procmux$6243_Y [0] $procmux$6243_Y [0] } Consolidated identical input bits for $mux cell $procmux$4462: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN[1:0]$1960, Y=$procmux$4462_Y New ports: A=1'0, B=$procmux$4424_Y [0], Y=$procmux$4462_Y [0] New connections: $procmux$4462_Y [1] = $procmux$4462_Y [0] Consolidated identical input bits for $mux cell $procmux$6216: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN[2:0]$1585, Y=$procmux$6216_Y New ports: A=1'0, B=$procmux$6043_Y [0], Y=$procmux$6216_Y [0] New connections: $procmux$6216_Y [2:1] = { $procmux$6216_Y [0] $procmux$6216_Y [0] } Consolidated identical input bits for $mux cell $procmux$7473: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN[2:0]$1304, Y=$procmux$7473_Y New ports: A=1'0, B=$procmux$7276_Y [0], Y=$procmux$7473_Y [0] New connections: $procmux$7473_Y [2:1] = { $procmux$7473_Y [0] $procmux$7473_Y [0] } Consolidated identical input bits for $mux cell $procmux$4411: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN[1:0]$1975, Y=$procmux$4411_Y New ports: A=1'0, B=$procmux$4373_Y [0], Y=$procmux$4411_Y [0] New connections: $procmux$4411_Y [1] = $procmux$4411_Y [0] Consolidated identical input bits for $mux cell $procmux$6189: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN[2:0]$1600, Y=$procmux$6189_Y New ports: A=1'0, B=$procmux$5992_Y [0], Y=$procmux$6189_Y [0] New connections: $procmux$6189_Y [2:1] = { $procmux$6189_Y [0] $procmux$6189_Y [0] } Consolidated identical input bits for $mux cell $procmux$6169: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN[1:0]$1560, Y=$procmux$6169_Y New ports: A=1'0, B=$procmux$6131_Y [0], Y=$procmux$6169_Y [0] New connections: $procmux$6169_Y [1] = $procmux$6169_Y [0] Consolidated identical input bits for $mux cell $procmux$7453: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$1264, Y=$procmux$7453_Y New ports: A=1'0, B=$procmux$7415_Y [0], Y=$procmux$7453_Y [0] New connections: $procmux$7453_Y [1] = $procmux$7453_Y [0] Consolidated identical input bits for $mux cell $procmux$4344: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN[2:0]$1999, Y=$procmux$4344_Y New ports: A=1'0, B=$procmux$4219_Y [0], Y=$procmux$4344_Y [0] New connections: $procmux$4344_Y [2:1] = { $procmux$4344_Y [0] $procmux$4344_Y [0] } Consolidated identical input bits for $mux cell $procmux$4317: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN[2:0]$2014, Y=$procmux$4317_Y New ports: A=1'0, B=$procmux$4168_Y [0], Y=$procmux$4317_Y [0] New connections: $procmux$4317_Y [2:1] = { $procmux$4317_Y [0] $procmux$4317_Y [0] } Consolidated identical input bits for $mux cell $procmux$6118: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN[1:0]$1575, Y=$procmux$6118_Y New ports: A=1'0, B=$procmux$6080_Y [0], Y=$procmux$6118_Y [0] New connections: $procmux$6118_Y [1] = $procmux$6118_Y [0] Consolidated identical input bits for $mux cell $procmux$4290: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN[2:0]$2029, Y=$procmux$4290_Y New ports: A=1'0, B=$procmux$4117_Y [0], Y=$procmux$4290_Y [0] New connections: $procmux$4290_Y [2:1] = { $procmux$4290_Y [0] $procmux$4290_Y [0] } Consolidated identical input bits for $mux cell $procmux$7402: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN[1:0]$1279, Y=$procmux$7402_Y New ports: A=1'0, B=$procmux$7364_Y [0], Y=$procmux$7402_Y [0] New connections: $procmux$7402_Y [1] = $procmux$7402_Y [0] Consolidated identical input bits for $mux cell $procmux$4263: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN[2:0]$2044, Y=$procmux$4263_Y New ports: A=1'0, B=$procmux$4066_Y [0], Y=$procmux$4263_Y [0] New connections: $procmux$4263_Y [2:1] = { $procmux$4263_Y [0] $procmux$4263_Y [0] } Consolidated identical input bits for $mux cell $procmux$4243: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN[1:0]$2004, Y=$procmux$4243_Y New ports: A=1'0, B=$procmux$4205_Y [0], Y=$procmux$4243_Y [0] New connections: $procmux$4243_Y [1] = $procmux$4243_Y [0] Consolidated identical input bits for $mux cell $procmux$6067: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN[1:0]$1590, Y=$procmux$6067_Y New ports: A=1'0, B=$procmux$6029_Y [0], Y=$procmux$6067_Y [0] New connections: $procmux$6067_Y [1] = $procmux$6067_Y [0] Consolidated identical input bits for $mux cell $procmux$4192: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN[1:0]$2019, Y=$procmux$4192_Y New ports: A=1'0, B=$procmux$4154_Y [0], Y=$procmux$4192_Y [0] New connections: $procmux$4192_Y [1] = $procmux$4192_Y [0] Consolidated identical input bits for $mux cell $procmux$7351: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN[1:0]$1294, Y=$procmux$7351_Y New ports: A=1'0, B=$procmux$7313_Y [0], Y=$procmux$7351_Y [0] New connections: $procmux$7351_Y [1] = $procmux$7351_Y [0] Consolidated identical input bits for $mux cell $procmux$6016: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN[1:0]$1605, Y=$procmux$6016_Y New ports: A=1'0, B=$procmux$5978_Y [0], Y=$procmux$6016_Y [0] New connections: $procmux$6016_Y [1] = $procmux$6016_Y [0] Consolidated identical input bits for $mux cell $procmux$4141: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN[1:0]$2034, Y=$procmux$4141_Y New ports: A=1'0, B=$procmux$4103_Y [0], Y=$procmux$4141_Y [0] New connections: $procmux$4141_Y [1] = $procmux$4141_Y [0] Consolidated identical input bits for $mux cell $procmux$4090: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN[1:0]$2049, Y=$procmux$4090_Y New ports: A=1'0, B=$procmux$4052_Y [0], Y=$procmux$4090_Y [0] New connections: $procmux$4090_Y [1] = $procmux$4090_Y [0] Consolidated identical input bits for $mux cell $procmux$7300: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN[1:0]$1309, Y=$procmux$7300_Y New ports: A=1'0, B=$procmux$7262_Y [0], Y=$procmux$7300_Y [0] New connections: $procmux$7300_Y [1] = $procmux$7300_Y [0] Consolidated identical input bits for $mux cell $procmux$5949: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN[2:0]$1629, Y=$procmux$5949_Y New ports: A=1'0, B=$procmux$5824_Y [0], Y=$procmux$5949_Y [0] New connections: $procmux$5949_Y [2:1] = { $procmux$5949_Y [0] $procmux$5949_Y [0] } Consolidated identical input bits for $mux cell $procmux$5922: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN[2:0]$1644, Y=$procmux$5922_Y New ports: A=1'0, B=$procmux$5773_Y [0], Y=$procmux$5922_Y [0] New connections: $procmux$5922_Y [2:1] = { $procmux$5922_Y [0] $procmux$5922_Y [0] } Consolidated identical input bits for $mux cell $procmux$4023: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN[2:0]$2073, Y=$procmux$4023_Y New ports: A=1'0, B=$procmux$3898_Y [0], Y=$procmux$4023_Y [0] New connections: $procmux$4023_Y [2:1] = { $procmux$4023_Y [0] $procmux$4023_Y [0] } Consolidated identical input bits for $mux cell $procmux$3996: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN[2:0]$2088, Y=$procmux$3996_Y New ports: A=1'0, B=$procmux$3847_Y [0], Y=$procmux$3996_Y [0] New connections: $procmux$3996_Y [2:1] = { $procmux$3996_Y [0] $procmux$3996_Y [0] } Consolidated identical input bits for $mux cell $procmux$5895: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN[2:0]$1659, Y=$procmux$5895_Y New ports: A=1'0, B=$procmux$5722_Y [0], Y=$procmux$5895_Y [0] New connections: $procmux$5895_Y [2:1] = { $procmux$5895_Y [0] $procmux$5895_Y [0] } Consolidated identical input bits for $mux cell $procmux$3969: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN[2:0]$2103, Y=$procmux$3969_Y New ports: A=1'0, B=$procmux$3796_Y [0], Y=$procmux$3969_Y [0] New connections: $procmux$3969_Y [2:1] = { $procmux$3969_Y [0] $procmux$3969_Y [0] } Consolidated identical input bits for $mux cell $procmux$5868: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN[2:0]$1674, Y=$procmux$5868_Y New ports: A=1'0, B=$procmux$5671_Y [0], Y=$procmux$5868_Y [0] New connections: $procmux$5868_Y [2:1] = { $procmux$5868_Y [0] $procmux$5868_Y [0] } Consolidated identical input bits for $mux cell $procmux$3942: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN[2:0]$2118, Y=$procmux$3942_Y New ports: A=1'0, B=$procmux$3745_Y [0], Y=$procmux$3942_Y [0] New connections: $procmux$3942_Y [2:1] = { $procmux$3942_Y [0] $procmux$3942_Y [0] } Consolidated identical input bits for $mux cell $procmux$3922: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN[1:0]$2078, Y=$procmux$3922_Y New ports: A=1'0, B=$procmux$3884_Y [0], Y=$procmux$3922_Y [0] New connections: $procmux$3922_Y [1] = $procmux$3922_Y [0] Consolidated identical input bits for $mux cell $procmux$7233: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN[2:0]$1333, Y=$procmux$7233_Y New ports: A=1'0, B=$procmux$7108_Y [0], Y=$procmux$7233_Y [0] New connections: $procmux$7233_Y [2:1] = { $procmux$7233_Y [0] $procmux$7233_Y [0] } Consolidated identical input bits for $mux cell $procmux$5848: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN[1:0]$1634, Y=$procmux$5848_Y New ports: A=1'0, B=$procmux$5810_Y [0], Y=$procmux$5848_Y [0] New connections: $procmux$5848_Y [1] = $procmux$5848_Y [0] Consolidated identical input bits for $mux cell $procmux$7206: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN[2:0]$1348, Y=$procmux$7206_Y New ports: A=1'0, B=$procmux$7057_Y [0], Y=$procmux$7206_Y [0] New connections: $procmux$7206_Y [2:1] = { $procmux$7206_Y [0] $procmux$7206_Y [0] } Consolidated identical input bits for $mux cell $procmux$3871: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN[1:0]$2093, Y=$procmux$3871_Y New ports: A=1'0, B=$procmux$3833_Y [0], Y=$procmux$3871_Y [0] New connections: $procmux$3871_Y [1] = $procmux$3871_Y [0] Consolidated identical input bits for $mux cell $procmux$5797: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN[1:0]$1649, Y=$procmux$5797_Y New ports: A=1'0, B=$procmux$5759_Y [0], Y=$procmux$5797_Y [0] New connections: $procmux$5797_Y [1] = $procmux$5797_Y [0] Consolidated identical input bits for $mux cell $procmux$7179: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN[2:0]$1363, Y=$procmux$7179_Y New ports: A=1'0, B=$procmux$7006_Y [0], Y=$procmux$7179_Y [0] New connections: $procmux$7179_Y [2:1] = { $procmux$7179_Y [0] $procmux$7179_Y [0] } Consolidated identical input bits for $mux cell $procmux$3820: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN[1:0]$2108, Y=$procmux$3820_Y New ports: A=1'0, B=$procmux$3782_Y [0], Y=$procmux$3820_Y [0] New connections: $procmux$3820_Y [1] = $procmux$3820_Y [0] Consolidated identical input bits for $mux cell $procmux$7152: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN[2:0]$1378, Y=$procmux$7152_Y New ports: A=1'0, B=$procmux$6955_Y [0], Y=$procmux$7152_Y [0] New connections: $procmux$7152_Y [2:1] = { $procmux$7152_Y [0] $procmux$7152_Y [0] } Consolidated identical input bits for $mux cell $procmux$5746: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN[1:0]$1664, Y=$procmux$5746_Y New ports: A=1'0, B=$procmux$5708_Y [0], Y=$procmux$5746_Y [0] New connections: $procmux$5746_Y [1] = $procmux$5746_Y [0] Consolidated identical input bits for $mux cell $procmux$3769: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN[1:0]$2123, Y=$procmux$3769_Y New ports: A=1'0, B=$procmux$3731_Y [0], Y=$procmux$3769_Y [0] New connections: $procmux$3769_Y [1] = $procmux$3769_Y [0] Consolidated identical input bits for $mux cell $procmux$7132: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN[1:0]$1338, Y=$procmux$7132_Y New ports: A=1'0, B=$procmux$7094_Y [0], Y=$procmux$7132_Y [0] New connections: $procmux$7132_Y [1] = $procmux$7132_Y [0] Consolidated identical input bits for $mux cell $procmux$5695: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN[1:0]$1679, Y=$procmux$5695_Y New ports: A=1'0, B=$procmux$5657_Y [0], Y=$procmux$5695_Y [0] New connections: $procmux$5695_Y [1] = $procmux$5695_Y [0] Consolidated identical input bits for $mux cell $procmux$3702: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN[2:0]$2147, Y=$procmux$3702_Y New ports: A=1'0, B=$procmux$3577_Y [0], Y=$procmux$3702_Y [0] New connections: $procmux$3702_Y [2:1] = { $procmux$3702_Y [0] $procmux$3702_Y [0] } Consolidated identical input bits for $mux cell $procmux$3675: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN[2:0]$2162, Y=$procmux$3675_Y New ports: A=1'0, B=$procmux$3526_Y [0], Y=$procmux$3675_Y [0] New connections: $procmux$3675_Y [2:1] = { $procmux$3675_Y [0] $procmux$3675_Y [0] } Consolidated identical input bits for $mux cell $procmux$7081: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN[1:0]$1353, Y=$procmux$7081_Y New ports: A=1'0, B=$procmux$7043_Y [0], Y=$procmux$7081_Y [0] New connections: $procmux$7081_Y [1] = $procmux$7081_Y [0] Consolidated identical input bits for $mux cell $procmux$3648: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN[2:0]$2177, Y=$procmux$3648_Y New ports: A=1'0, B=$procmux$3475_Y [0], Y=$procmux$3648_Y [0] New connections: $procmux$3648_Y [2:1] = { $procmux$3648_Y [0] $procmux$3648_Y [0] } Consolidated identical input bits for $mux cell $procmux$3621: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN[2:0]$2192, Y=$procmux$3621_Y New ports: A=1'0, B=$procmux$3424_Y [0], Y=$procmux$3621_Y [0] New connections: $procmux$3621_Y [2:1] = { $procmux$3621_Y [0] $procmux$3621_Y [0] } Consolidated identical input bits for $mux cell $procmux$3601: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN[1:0]$2152, Y=$procmux$3601_Y New ports: A=1'0, B=$procmux$3563_Y [0], Y=$procmux$3601_Y [0] New connections: $procmux$3601_Y [1] = $procmux$3601_Y [0] Consolidated identical input bits for $mux cell $procmux$5628: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN[2:0]$1703, Y=$procmux$5628_Y New ports: A=1'0, B=$procmux$5503_Y [0], Y=$procmux$5628_Y [0] New connections: $procmux$5628_Y [2:1] = { $procmux$5628_Y [0] $procmux$5628_Y [0] } Consolidated identical input bits for $mux cell $procmux$5601: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN[2:0]$1718, Y=$procmux$5601_Y New ports: A=1'0, B=$procmux$5452_Y [0], Y=$procmux$5601_Y [0] New connections: $procmux$5601_Y [2:1] = { $procmux$5601_Y [0] $procmux$5601_Y [0] } Consolidated identical input bits for $mux cell $procmux$3550: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN[1:0]$2167, Y=$procmux$3550_Y New ports: A=1'0, B=$procmux$3512_Y [0], Y=$procmux$3550_Y [0] New connections: $procmux$3550_Y [1] = $procmux$3550_Y [0] Consolidated identical input bits for $mux cell $procmux$7030: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN[1:0]$1368, Y=$procmux$7030_Y New ports: A=1'0, B=$procmux$6992_Y [0], Y=$procmux$7030_Y [0] New connections: $procmux$7030_Y [1] = $procmux$7030_Y [0] Consolidated identical input bits for $mux cell $procmux$5574: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN[2:0]$1733, Y=$procmux$5574_Y New ports: A=1'0, B=$procmux$5401_Y [0], Y=$procmux$5574_Y [0] New connections: $procmux$5574_Y [2:1] = { $procmux$5574_Y [0] $procmux$5574_Y [0] } Consolidated identical input bits for $mux cell $procmux$3499: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN[1:0]$2182, Y=$procmux$3499_Y New ports: A=1'0, B=$procmux$3461_Y [0], Y=$procmux$3499_Y [0] New connections: $procmux$3499_Y [1] = $procmux$3499_Y [0] Consolidated identical input bits for $mux cell $procmux$5547: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN[2:0]$1748, Y=$procmux$5547_Y New ports: A=1'0, B=$procmux$5350_Y [0], Y=$procmux$5547_Y [0] New connections: $procmux$5547_Y [2:1] = { $procmux$5547_Y [0] $procmux$5547_Y [0] } Consolidated identical input bits for $mux cell $procmux$5527: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN[1:0]$1708, Y=$procmux$5527_Y New ports: A=1'0, B=$procmux$5489_Y [0], Y=$procmux$5527_Y [0] New connections: $procmux$5527_Y [1] = $procmux$5527_Y [0] Consolidated identical input bits for $mux cell $procmux$3448: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN[1:0]$2197, Y=$procmux$3448_Y New ports: A=1'0, B=$procmux$3410_Y [0], Y=$procmux$3448_Y [0] New connections: $procmux$3448_Y [1] = $procmux$3448_Y [0] Consolidated identical input bits for $mux cell $procmux$6979: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN[1:0]$1383, Y=$procmux$6979_Y New ports: A=1'0, B=$procmux$6941_Y [0], Y=$procmux$6979_Y [0] New connections: $procmux$6979_Y [1] = $procmux$6979_Y [0] Consolidated identical input bits for $mux cell $procmux$5476: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN[1:0]$1723, Y=$procmux$5476_Y New ports: A=1'0, B=$procmux$5438_Y [0], Y=$procmux$5476_Y [0] New connections: $procmux$5476_Y [1] = $procmux$5476_Y [0] Consolidated identical input bits for $mux cell $procmux$3381: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$2221, Y=$procmux$3381_Y New ports: A=1'0, B=$procmux$3256_Y [0], Y=$procmux$3381_Y [0] New connections: $procmux$3381_Y [2:1] = { $procmux$3381_Y [0] $procmux$3381_Y [0] } Consolidated identical input bits for $mux cell $procmux$3354: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$2236, Y=$procmux$3354_Y New ports: A=1'0, B=$procmux$3205_Y [0], Y=$procmux$3354_Y [0] New connections: $procmux$3354_Y [2:1] = { $procmux$3354_Y [0] $procmux$3354_Y [0] } Consolidated identical input bits for $mux cell $procmux$3327: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$2251, Y=$procmux$3327_Y New ports: A=1'0, B=$procmux$3154_Y [0], Y=$procmux$3327_Y [0] New connections: $procmux$3327_Y [2:1] = { $procmux$3327_Y [0] $procmux$3327_Y [0] } Consolidated identical input bits for $mux cell $procmux$5425: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN[1:0]$1738, Y=$procmux$5425_Y New ports: A=1'0, B=$procmux$5387_Y [0], Y=$procmux$5425_Y [0] New connections: $procmux$5425_Y [1] = $procmux$5425_Y [0] Consolidated identical input bits for $mux cell $procmux$6912: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN[2:0]$1407, Y=$procmux$6912_Y New ports: A=1'0, B=$procmux$6787_Y [0], Y=$procmux$6912_Y [0] New connections: $procmux$6912_Y [2:1] = { $procmux$6912_Y [0] $procmux$6912_Y [0] } Consolidated identical input bits for $mux cell $procmux$3300: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$2266, Y=$procmux$3300_Y New ports: A=1'0, B=$procmux$3103_Y [0], Y=$procmux$3300_Y [0] New connections: $procmux$3300_Y [2:1] = { $procmux$3300_Y [0] $procmux$3300_Y [0] } Consolidated identical input bits for $mux cell $procmux$3280: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$2226, Y=$procmux$3280_Y New ports: A=1'0, B=$procmux$3242_Y [0], Y=$procmux$3280_Y [0] New connections: $procmux$3280_Y [1] = $procmux$3280_Y [0] Consolidated identical input bits for $mux cell $procmux$6885: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN[2:0]$1422, Y=$procmux$6885_Y New ports: A=1'0, B=$procmux$6736_Y [0], Y=$procmux$6885_Y [0] New connections: $procmux$6885_Y [2:1] = { $procmux$6885_Y [0] $procmux$6885_Y [0] } Consolidated identical input bits for $mux cell $procmux$5374: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN[1:0]$1753, Y=$procmux$5374_Y New ports: A=1'0, B=$procmux$5336_Y [0], Y=$procmux$5374_Y [0] New connections: $procmux$5374_Y [1] = $procmux$5374_Y [0] Consolidated identical input bits for $mux cell $procmux$3229: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$2241, Y=$procmux$3229_Y New ports: A=1'0, B=$procmux$3191_Y [0], Y=$procmux$3229_Y [0] New connections: $procmux$3229_Y [1] = $procmux$3229_Y [0] Consolidated identical input bits for $mux cell $procmux$6858: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN[2:0]$1437, Y=$procmux$6858_Y New ports: A=1'0, B=$procmux$6685_Y [0], Y=$procmux$6858_Y [0] New connections: $procmux$6858_Y [2:1] = { $procmux$6858_Y [0] $procmux$6858_Y [0] } Consolidated identical input bits for $mux cell $procmux$3178: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$2256, Y=$procmux$3178_Y New ports: A=1'0, B=$procmux$3140_Y [0], Y=$procmux$3178_Y [0] New connections: $procmux$3178_Y [1] = $procmux$3178_Y [0] Consolidated identical input bits for $mux cell $procmux$5307: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN[2:0]$1777, Y=$procmux$5307_Y New ports: A=1'0, B=$procmux$5182_Y [0], Y=$procmux$5307_Y [0] New connections: $procmux$5307_Y [2:1] = { $procmux$5307_Y [0] $procmux$5307_Y [0] } Consolidated identical input bits for $mux cell $procmux$6831: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN[2:0]$1452, Y=$procmux$6831_Y New ports: A=1'0, B=$procmux$6634_Y [0], Y=$procmux$6831_Y [0] New connections: $procmux$6831_Y [2:1] = { $procmux$6831_Y [0] $procmux$6831_Y [0] } Consolidated identical input bits for $mux cell $procmux$3127: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$2271, Y=$procmux$3127_Y New ports: A=1'0, B=$procmux$3089_Y [0], Y=$procmux$3127_Y [0] New connections: $procmux$3127_Y [1] = $procmux$3127_Y [0] Consolidated identical input bits for $mux cell $procmux$5280: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN[2:0]$1792, Y=$procmux$5280_Y New ports: A=1'0, B=$procmux$5131_Y [0], Y=$procmux$5280_Y [0] New connections: $procmux$5280_Y [2:1] = { $procmux$5280_Y [0] $procmux$5280_Y [0] } Consolidated identical input bits for $mux cell $procmux$6811: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN[1:0]$1412, Y=$procmux$6811_Y New ports: A=1'0, B=$procmux$6773_Y [0], Y=$procmux$6811_Y [0] New connections: $procmux$6811_Y [1] = $procmux$6811_Y [0] Consolidated identical input bits for $mux cell $procmux$5253: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN[2:0]$1807, Y=$procmux$5253_Y New ports: A=1'0, B=$procmux$5080_Y [0], Y=$procmux$5253_Y [0] New connections: $procmux$5253_Y [2:1] = { $procmux$5253_Y [0] $procmux$5253_Y [0] } Consolidated identical input bits for $mux cell $procmux$3060: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$2295, Y=$procmux$3060_Y New ports: A=1'0, B=$procmux$2935_Y [0], Y=$procmux$3060_Y [0] New connections: $procmux$3060_Y [2:1] = { $procmux$3060_Y [0] $procmux$3060_Y [0] } Consolidated identical input bits for $mux cell $procmux$5226: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN[2:0]$1822, Y=$procmux$5226_Y New ports: A=1'0, B=$procmux$5029_Y [0], Y=$procmux$5226_Y [0] New connections: $procmux$5226_Y [2:1] = { $procmux$5226_Y [0] $procmux$5226_Y [0] } Consolidated identical input bits for $mux cell $procmux$3033: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$2310, Y=$procmux$3033_Y New ports: A=1'0, B=$procmux$2884_Y [0], Y=$procmux$3033_Y [0] New connections: $procmux$3033_Y [2:1] = { $procmux$3033_Y [0] $procmux$3033_Y [0] } Consolidated identical input bits for $mux cell $procmux$5206: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN[1:0]$1782, Y=$procmux$5206_Y New ports: A=1'0, B=$procmux$5168_Y [0], Y=$procmux$5206_Y [0] New connections: $procmux$5206_Y [1] = $procmux$5206_Y [0] Consolidated identical input bits for $mux cell $procmux$3006: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$2325, Y=$procmux$3006_Y New ports: A=1'0, B=$procmux$2833_Y [0], Y=$procmux$3006_Y [0] New connections: $procmux$3006_Y [2:1] = { $procmux$3006_Y [0] $procmux$3006_Y [0] } Consolidated identical input bits for $mux cell $procmux$6760: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN[1:0]$1427, Y=$procmux$6760_Y New ports: A=1'0, B=$procmux$6722_Y [0], Y=$procmux$6760_Y [0] New connections: $procmux$6760_Y [1] = $procmux$6760_Y [0] Consolidated identical input bits for $mux cell $procmux$2979: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$2340, Y=$procmux$2979_Y New ports: A=1'0, B=$procmux$2782_Y [0], Y=$procmux$2979_Y [0] New connections: $procmux$2979_Y [2:1] = { $procmux$2979_Y [0] $procmux$2979_Y [0] } Consolidated identical input bits for $mux cell $procmux$2959: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$2300, Y=$procmux$2959_Y New ports: A=1'0, B=$procmux$2921_Y [0], Y=$procmux$2959_Y [0] New connections: $procmux$2959_Y [1] = $procmux$2959_Y [0] Consolidated identical input bits for $mux cell $procmux$5155: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN[1:0]$1797, Y=$procmux$5155_Y New ports: A=1'0, B=$procmux$5117_Y [0], Y=$procmux$5155_Y [0] New connections: $procmux$5155_Y [1] = $procmux$5155_Y [0] Consolidated identical input bits for $mux cell $procmux$2908: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$2315, Y=$procmux$2908_Y New ports: A=1'0, B=$procmux$2870_Y [0], Y=$procmux$2908_Y [0] New connections: $procmux$2908_Y [1] = $procmux$2908_Y [0] Consolidated identical input bits for $mux cell $procmux$6709: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN[1:0]$1442, Y=$procmux$6709_Y New ports: A=1'0, B=$procmux$6671_Y [0], Y=$procmux$6709_Y [0] New connections: $procmux$6709_Y [1] = $procmux$6709_Y [0] Consolidated identical input bits for $mux cell $procmux$5104: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN[1:0]$1812, Y=$procmux$5104_Y New ports: A=1'0, B=$procmux$5066_Y [0], Y=$procmux$5104_Y [0] New connections: $procmux$5104_Y [1] = $procmux$5104_Y [0] Consolidated identical input bits for $mux cell $procmux$2857: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$2330, Y=$procmux$2857_Y New ports: A=1'0, B=$procmux$2819_Y [0], Y=$procmux$2857_Y [0] New connections: $procmux$2857_Y [1] = $procmux$2857_Y [0] Consolidated identical input bits for $mux cell $procmux$6658: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN[1:0]$1457, Y=$procmux$6658_Y New ports: A=1'0, B=$procmux$6620_Y [0], Y=$procmux$6658_Y [0] New connections: $procmux$6658_Y [1] = $procmux$6658_Y [0] Consolidated identical input bits for $mux cell $procmux$2806: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$2345, Y=$procmux$2806_Y New ports: A=1'0, B=$procmux$2768_Y [0], Y=$procmux$2806_Y [0] New connections: $procmux$2806_Y [1] = $procmux$2806_Y [0] Consolidated identical input bits for $mux cell $procmux$5053: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN[1:0]$1827, Y=$procmux$5053_Y New ports: A=1'0, B=$procmux$5015_Y [0], Y=$procmux$5053_Y [0] New connections: $procmux$5053_Y [1] = $procmux$5053_Y [0] Consolidated identical input bits for $mux cell $procmux$2739: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$2369, Y=$procmux$2739_Y New ports: A=1'0, B=$procmux$2614_Y [0], Y=$procmux$2739_Y [0] New connections: $procmux$2739_Y [2:1] = { $procmux$2739_Y [0] $procmux$2739_Y [0] } Consolidated identical input bits for $mux cell $procmux$2712: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$2384, Y=$procmux$2712_Y New ports: A=1'0, B=$procmux$2563_Y [0], Y=$procmux$2712_Y [0] New connections: $procmux$2712_Y [2:1] = { $procmux$2712_Y [0] $procmux$2712_Y [0] } Consolidated identical input bits for $mux cell $procmux$4986: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN[2:0]$1851, Y=$procmux$4986_Y New ports: A=1'0, B=$procmux$4861_Y [0], Y=$procmux$4986_Y [0] New connections: $procmux$4986_Y [2:1] = { $procmux$4986_Y [0] $procmux$4986_Y [0] } Consolidated identical input bits for $mux cell $procmux$2685: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$2399, Y=$procmux$2685_Y New ports: A=1'0, B=$procmux$2512_Y [0], Y=$procmux$2685_Y [0] New connections: $procmux$2685_Y [2:1] = { $procmux$2685_Y [0] $procmux$2685_Y [0] } Consolidated identical input bits for $mux cell $procmux$6591: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN[2:0]$1481, Y=$procmux$6591_Y New ports: A=1'0, B=$procmux$6466_Y [0], Y=$procmux$6591_Y [0] New connections: $procmux$6591_Y [2:1] = { $procmux$6591_Y [0] $procmux$6591_Y [0] } Consolidated identical input bits for $mux cell $procmux$4959: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN[2:0]$1866, Y=$procmux$4959_Y New ports: A=1'0, B=$procmux$4810_Y [0], Y=$procmux$4959_Y [0] New connections: $procmux$4959_Y [2:1] = { $procmux$4959_Y [0] $procmux$4959_Y [0] } Consolidated identical input bits for $mux cell $procmux$2658: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$2414, Y=$procmux$2658_Y New ports: A=1'0, B=$procmux$2461_Y [0], Y=$procmux$2658_Y [0] New connections: $procmux$2658_Y [2:1] = { $procmux$2658_Y [0] $procmux$2658_Y [0] } Consolidated identical input bits for $mux cell $procmux$2638: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$2374, Y=$procmux$2638_Y New ports: A=1'0, B=$procmux$2600_Y [0], Y=$procmux$2638_Y [0] New connections: $procmux$2638_Y [1] = $procmux$2638_Y [0] Consolidated identical input bits for $mux cell $procmux$4932: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN[2:0]$1881, Y=$procmux$4932_Y New ports: A=1'0, B=$procmux$4759_Y [0], Y=$procmux$4932_Y [0] New connections: $procmux$4932_Y [2:1] = { $procmux$4932_Y [0] $procmux$4932_Y [0] } Consolidated identical input bits for $mux cell $procmux$6564: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN[2:0]$1496, Y=$procmux$6564_Y New ports: A=1'0, B=$procmux$6415_Y [0], Y=$procmux$6564_Y [0] New connections: $procmux$6564_Y [2:1] = { $procmux$6564_Y [0] $procmux$6564_Y [0] } Consolidated identical input bits for $mux cell $procmux$2587: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$2389, Y=$procmux$2587_Y New ports: A=1'0, B=$procmux$2549_Y [0], Y=$procmux$2587_Y [0] New connections: $procmux$2587_Y [1] = $procmux$2587_Y [0] Consolidated identical input bits for $mux cell $procmux$4905: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN[2:0]$1896, Y=$procmux$4905_Y New ports: A=1'0, B=$procmux$4708_Y [0], Y=$procmux$4905_Y [0] New connections: $procmux$4905_Y [2:1] = { $procmux$4905_Y [0] $procmux$4905_Y [0] } Consolidated identical input bits for $mux cell $procmux$4885: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN[1:0]$1856, Y=$procmux$4885_Y New ports: A=1'0, B=$procmux$4847_Y [0], Y=$procmux$4885_Y [0] New connections: $procmux$4885_Y [1] = $procmux$4885_Y [0] Consolidated identical input bits for $mux cell $procmux$6537: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN[2:0]$1511, Y=$procmux$6537_Y New ports: A=1'0, B=$procmux$6364_Y [0], Y=$procmux$6537_Y [0] New connections: $procmux$6537_Y [2:1] = { $procmux$6537_Y [0] $procmux$6537_Y [0] } Consolidated identical input bits for $mux cell $procmux$2536: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$2404, Y=$procmux$2536_Y New ports: A=1'0, B=$procmux$2498_Y [0], Y=$procmux$2536_Y [0] New connections: $procmux$2536_Y [1] = $procmux$2536_Y [0] Consolidated identical input bits for $mux cell $procmux$6510: Old ports: A=3'000, B=$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN[2:0]$1526, Y=$procmux$6510_Y New ports: A=1'0, B=$procmux$6313_Y [0], Y=$procmux$6510_Y [0] New connections: $procmux$6510_Y [2:1] = { $procmux$6510_Y [0] $procmux$6510_Y [0] } Consolidated identical input bits for $mux cell $procmux$4834: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN[1:0]$1871, Y=$procmux$4834_Y New ports: A=1'0, B=$procmux$4796_Y [0], Y=$procmux$4834_Y [0] New connections: $procmux$4834_Y [1] = $procmux$4834_Y [0] Consolidated identical input bits for $mux cell $procmux$2485: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$2419, Y=$procmux$2485_Y New ports: A=1'0, B=$procmux$2447_Y [0], Y=$procmux$2485_Y [0] New connections: $procmux$2485_Y [1] = $procmux$2485_Y [0] Consolidated identical input bits for $mux cell $procmux$6490: Old ports: A=2'00, B=$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN[1:0]$1486, Y=$procmux$6490_Y New ports: A=1'0, B=$procmux$6452_Y [0], Y=$procmux$6490_Y [0] New connections: $procmux$6490_Y [1] = $procmux$6490_Y [0] Consolidated identical input bits for $mux cell $procmux$9758: Old ports: A=$2$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_EN[2:0]$1006, B=3'000, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_EN[2:0]$505 New ports: A=$procmux$8924_Y [0], B=1'0, Y=$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_EN[2:0]$505 [0] New connections: $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_EN[2:0]$505 [2:1] = { $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_EN[2:0]$505 [0] $0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$279_EN[2:0]$505 [0] } Consolidated identical input bits for $mux cell $procmux$9752: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_EN[2:0]$1008, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_EN[2:0]$507 New ports: A=$procmux$8912_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_EN[2:0]$507 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_EN[2:0]$507 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_EN[2:0]$507 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$280_EN[2:0]$507 [0] } Consolidated identical input bits for $mux cell $procmux$9743: Old ports: A=$2$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$1011, B=23'00000000000000000000000, Y=$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 New ports: A=$procmux$8894_Y [0], B=1'0, Y=$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] New connections: $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [22:1] = { $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] $0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$281_EN[22:0]$510 [0] } Consolidated identical input bits for $mux cell $procmux$9734: Old ports: A=$2$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$1014, B=23'00000000000000000000000, Y=$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 New ports: A=$procmux$8876_Y [0], B=1'0, Y=$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] New connections: $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [22:1] = { $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] $0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$282_EN[22:0]$513 [0] } Consolidated identical input bits for $mux cell $procmux$9725: Old ports: A=$2$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$1017, B=16'0000000000000000, Y=$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 New ports: A=$procmux$8858_Y [0], B=1'0, Y=$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] New connections: $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [15:1] = { $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] $0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$283_EN[15:0]$516 [0] } Consolidated identical input bits for $mux cell $procmux$9716: Old ports: A=$2$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$1020, B=23'00000000000000000000000, Y=$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 New ports: A=$procmux$8840_Y [0], B=1'0, Y=$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] New connections: $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [22:1] = { $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] $0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$284_EN[22:0]$519 [0] } Consolidated identical input bits for $mux cell $procmux$9707: Old ports: A=$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN[3:0]$1023, B=4'0000, Y=$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN[3:0]$522 New ports: A=$procmux$8822_Y [0], B=1'0, Y=$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN[3:0]$522 [0] New connections: $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN[3:0]$522 [3:1] = { $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN[3:0]$522 [0] $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN[3:0]$522 [0] $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_EN[3:0]$522 [0] } Consolidated identical input bits for $mux cell $procmux$9698: Old ports: A=$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN[3:0]$1026, B=4'0000, Y=$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN[3:0]$525 New ports: A=$procmux$8804_Y [0], B=1'0, Y=$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN[3:0]$525 [0] New connections: $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN[3:0]$525 [3:1] = { $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN[3:0]$525 [0] $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN[3:0]$525 [0] $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_EN[3:0]$525 [0] } Consolidated identical input bits for $mux cell $procmux$9689: Old ports: A=$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN[3:0]$1029, B=4'0000, Y=$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN[3:0]$528 New ports: A=$procmux$8786_Y [0], B=1'0, Y=$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN[3:0]$528 [0] New connections: $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN[3:0]$528 [3:1] = { $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN[3:0]$528 [0] $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN[3:0]$528 [0] $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_EN[3:0]$528 [0] } Consolidated identical input bits for $mux cell $procmux$9680: Old ports: A=$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN[3:0]$1032, B=4'0000, Y=$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN[3:0]$531 New ports: A=$procmux$8768_Y [0], B=1'0, Y=$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN[3:0]$531 [0] New connections: $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN[3:0]$531 [3:1] = { $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN[3:0]$531 [0] $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN[3:0]$531 [0] $0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_EN[3:0]$531 [0] } Consolidated identical input bits for $mux cell $procmux$9671: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_EN[1:0]$1035, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_EN[1:0]$534 New ports: A=$procmux$8744_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_EN[1:0]$534 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_EN[1:0]$534 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$289_EN[1:0]$534 [0] Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $procmux$7664: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$2287, Y=$procmux$7664_Y New ports: A=1'0, B=$procmux$2979_Y [0], Y=$procmux$7664_Y [0] New connections: $procmux$7664_Y [2:1] = { $procmux$7664_Y [0] $procmux$7664_Y [0] } Consolidated identical input bits for $mux cell $procmux$8474: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN[2:0]$1470, Y=$procmux$8474_Y New ports: A=1'0, B=$procmux$6537_Y [0], Y=$procmux$8474_Y [0] New connections: $procmux$8474_Y [2:1] = { $procmux$8474_Y [0] $procmux$8474_Y [0] } Consolidated identical input bits for $mux cell $procmux$7640: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$2352, Y=$procmux$7640_Y New ports: A=1'0, B=$procmux$2739_Y [0], Y=$procmux$7640_Y [0] New connections: $procmux$7640_Y [2:1] = { $procmux$7640_Y [0] $procmux$7640_Y [0] } Consolidated identical input bits for $mux cell $procmux$7622: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$2355, Y=$procmux$7622_Y New ports: A=1'0, B=$procmux$2712_Y [0], Y=$procmux$7622_Y [0] New connections: $procmux$7622_Y [2:1] = { $procmux$7622_Y [0] $procmux$7622_Y [0] } Consolidated identical input bits for $mux cell $procmux$8456: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN[2:0]$1473, Y=$procmux$8456_Y New ports: A=1'0, B=$procmux$6510_Y [0], Y=$procmux$8456_Y [0] New connections: $procmux$8456_Y [2:1] = { $procmux$8456_Y [0] $procmux$8456_Y [0] } Consolidated identical input bits for $mux cell $procmux$7604: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$2358, Y=$procmux$7604_Y New ports: A=1'0, B=$procmux$2685_Y [0], Y=$procmux$7604_Y [0] New connections: $procmux$7604_Y [2:1] = { $procmux$7604_Y [0] $procmux$7604_Y [0] } Consolidated identical input bits for $mux cell $procmux$4683: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN[1:0]$1923, Y=$procmux$4683_Y New ports: A=1'0, B=$procmux$4564_Y [0], Y=$procmux$4683_Y [0] New connections: $procmux$4683_Y [1] = $procmux$4683_Y [0] Consolidated identical input bits for $mux cell $procmux$4656: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN[1:0]$1938, Y=$procmux$4656_Y New ports: A=1'0, B=$procmux$4513_Y [0], Y=$procmux$4656_Y [0] New connections: $procmux$4656_Y [1] = $procmux$4656_Y [0] Consolidated identical input bits for $mux cell $procmux$7586: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$2361, Y=$procmux$7586_Y New ports: A=1'0, B=$procmux$2658_Y [0], Y=$procmux$7586_Y [0] New connections: $procmux$7586_Y [2:1] = { $procmux$7586_Y [0] $procmux$7586_Y [0] } Consolidated identical input bits for $mux cell $procmux$4629: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN[1:0]$1953, Y=$procmux$4629_Y New ports: A=1'0, B=$procmux$4462_Y [0], Y=$procmux$4629_Y [0] New connections: $procmux$4629_Y [1] = $procmux$4629_Y [0] Consolidated identical input bits for $mux cell $procmux$7572: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$1257, Y=$procmux$7572_Y New ports: A=1'0, B=$procmux$7453_Y [0], Y=$procmux$7572_Y [0] New connections: $procmux$7572_Y [1] = $procmux$7572_Y [0] Consolidated identical input bits for $mux cell $procmux$8438: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN[2:0]$1538, Y=$procmux$8438_Y New ports: A=1'0, B=$procmux$6270_Y [0], Y=$procmux$8438_Y [0] New connections: $procmux$8438_Y [2:1] = { $procmux$8438_Y [0] $procmux$8438_Y [0] } Consolidated identical input bits for $mux cell $procmux$4602: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN[1:0]$1968, Y=$procmux$4602_Y New ports: A=1'0, B=$procmux$4411_Y [0], Y=$procmux$4602_Y [0] New connections: $procmux$4602_Y [1] = $procmux$4602_Y [0] Consolidated identical input bits for $mux cell $procmux$7545: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN[1:0]$1272, Y=$procmux$7545_Y New ports: A=1'0, B=$procmux$7402_Y [0], Y=$procmux$7545_Y [0] New connections: $procmux$7545_Y [1] = $procmux$7545_Y [0] Consolidated identical input bits for $mux cell $procmux$8420: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN[2:0]$1541, Y=$procmux$8420_Y New ports: A=1'0, B=$procmux$6243_Y [0], Y=$procmux$8420_Y [0] New connections: $procmux$8420_Y [2:1] = { $procmux$8420_Y [0] $procmux$8420_Y [0] } Consolidated identical input bits for $mux cell $procmux$6288: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN[1:0]$1553, Y=$procmux$6288_Y New ports: A=1'0, B=$procmux$6169_Y [0], Y=$procmux$6288_Y [0] New connections: $procmux$6288_Y [1] = $procmux$6288_Y [0] Consolidated identical input bits for $mux cell $procmux$7518: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN[1:0]$1287, Y=$procmux$7518_Y New ports: A=1'0, B=$procmux$7351_Y [0], Y=$procmux$7518_Y [0] New connections: $procmux$7518_Y [1] = $procmux$7518_Y [0] Consolidated identical input bits for $mux cell $procmux$8402: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN[2:0]$1544, Y=$procmux$8402_Y New ports: A=1'0, B=$procmux$6216_Y [0], Y=$procmux$8402_Y [0] New connections: $procmux$8402_Y [2:1] = { $procmux$8402_Y [0] $procmux$8402_Y [0] } Consolidated identical input bits for $mux cell $procmux$6261: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN[1:0]$1568, Y=$procmux$6261_Y New ports: A=1'0, B=$procmux$6118_Y [0], Y=$procmux$6261_Y [0] New connections: $procmux$6261_Y [1] = $procmux$6261_Y [0] Consolidated identical input bits for $mux cell $procmux$6234: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN[1:0]$1583, Y=$procmux$6234_Y New ports: A=1'0, B=$procmux$6067_Y [0], Y=$procmux$6234_Y [0] New connections: $procmux$6234_Y [1] = $procmux$6234_Y [0] Consolidated identical input bits for $mux cell $procmux$7491: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN[1:0]$1302, Y=$procmux$7491_Y New ports: A=1'0, B=$procmux$7300_Y [0], Y=$procmux$7491_Y [0] New connections: $procmux$7491_Y [1] = $procmux$7491_Y [0] Consolidated identical input bits for $mux cell $procmux$8384: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN[2:0]$1547, Y=$procmux$8384_Y New ports: A=1'0, B=$procmux$6189_Y [0], Y=$procmux$8384_Y [0] New connections: $procmux$8384_Y [2:1] = { $procmux$8384_Y [0] $procmux$8384_Y [0] } Consolidated identical input bits for $mux cell $procmux$6207: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN[1:0]$1598, Y=$procmux$6207_Y New ports: A=1'0, B=$procmux$6016_Y [0], Y=$procmux$6207_Y [0] New connections: $procmux$6207_Y [1] = $procmux$6207_Y [0] Consolidated identical input bits for $mux cell $procmux$8366: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN[2:0]$1612, Y=$procmux$8366_Y New ports: A=1'0, B=$procmux$5949_Y [0], Y=$procmux$8366_Y [0] New connections: $procmux$8366_Y [2:1] = { $procmux$8366_Y [0] $procmux$8366_Y [0] } Consolidated identical input bits for $mux cell $procmux$4362: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN[1:0]$1997, Y=$procmux$4362_Y New ports: A=1'0, B=$procmux$4243_Y [0], Y=$procmux$4362_Y [0] New connections: $procmux$4362_Y [1] = $procmux$4362_Y [0] Consolidated identical input bits for $mux cell $procmux$4335: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN[1:0]$2012, Y=$procmux$4335_Y New ports: A=1'0, B=$procmux$4192_Y [0], Y=$procmux$4335_Y [0] New connections: $procmux$4335_Y [1] = $procmux$4335_Y [0] Consolidated identical input bits for $mux cell $procmux$8348: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN[2:0]$1615, Y=$procmux$8348_Y New ports: A=1'0, B=$procmux$5922_Y [0], Y=$procmux$8348_Y [0] New connections: $procmux$8348_Y [2:1] = { $procmux$8348_Y [0] $procmux$8348_Y [0] } Consolidated identical input bits for $mux cell $procmux$4308: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN[1:0]$2027, Y=$procmux$4308_Y New ports: A=1'0, B=$procmux$4141_Y [0], Y=$procmux$4308_Y [0] New connections: $procmux$4308_Y [1] = $procmux$4308_Y [0] Consolidated identical input bits for $mux cell $procmux$8330: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN[2:0]$1618, Y=$procmux$8330_Y New ports: A=1'0, B=$procmux$5895_Y [0], Y=$procmux$8330_Y [0] New connections: $procmux$8330_Y [2:1] = { $procmux$8330_Y [0] $procmux$8330_Y [0] } Consolidated identical input bits for $mux cell $procmux$4281: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN[1:0]$2042, Y=$procmux$4281_Y New ports: A=1'0, B=$procmux$4090_Y [0], Y=$procmux$4281_Y [0] New connections: $procmux$4281_Y [1] = $procmux$4281_Y [0] Consolidated identical input bits for $mux cell $procmux$8312: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN[2:0]$1621, Y=$procmux$8312_Y New ports: A=1'0, B=$procmux$5868_Y [0], Y=$procmux$8312_Y [0] New connections: $procmux$8312_Y [2:1] = { $procmux$8312_Y [0] $procmux$8312_Y [0] } Consolidated identical input bits for $mux cell $procmux$8294: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN[2:0]$1686, Y=$procmux$8294_Y New ports: A=1'0, B=$procmux$5628_Y [0], Y=$procmux$8294_Y [0] New connections: $procmux$8294_Y [2:1] = { $procmux$8294_Y [0] $procmux$8294_Y [0] } Consolidated identical input bits for $mux cell $procmux$8276: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN[2:0]$1689, Y=$procmux$8276_Y New ports: A=1'0, B=$procmux$5601_Y [0], Y=$procmux$8276_Y [0] New connections: $procmux$8276_Y [2:1] = { $procmux$8276_Y [0] $procmux$8276_Y [0] } Consolidated identical input bits for $mux cell $procmux$8258: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN[2:0]$1692, Y=$procmux$8258_Y New ports: A=1'0, B=$procmux$5574_Y [0], Y=$procmux$8258_Y [0] New connections: $procmux$8258_Y [2:1] = { $procmux$8258_Y [0] $procmux$8258_Y [0] } Consolidated identical input bits for $mux cell $procmux$5967: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN[1:0]$1627, Y=$procmux$5967_Y New ports: A=1'0, B=$procmux$5848_Y [0], Y=$procmux$5967_Y [0] New connections: $procmux$5967_Y [1] = $procmux$5967_Y [0] Consolidated identical input bits for $mux cell $procmux$8240: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN[2:0]$1695, Y=$procmux$8240_Y New ports: A=1'0, B=$procmux$5547_Y [0], Y=$procmux$8240_Y [0] New connections: $procmux$8240_Y [2:1] = { $procmux$8240_Y [0] $procmux$8240_Y [0] } Consolidated identical input bits for $mux cell $procmux$5940: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN[1:0]$1642, Y=$procmux$5940_Y New ports: A=1'0, B=$procmux$5797_Y [0], Y=$procmux$5940_Y [0] New connections: $procmux$5940_Y [1] = $procmux$5940_Y [0] Consolidated identical input bits for $mux cell $procmux$4041: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN[1:0]$2071, Y=$procmux$4041_Y New ports: A=1'0, B=$procmux$3922_Y [0], Y=$procmux$4041_Y [0] New connections: $procmux$4041_Y [1] = $procmux$4041_Y [0] Consolidated identical input bits for $mux cell $procmux$8222: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN[2:0]$1760, Y=$procmux$8222_Y New ports: A=1'0, B=$procmux$5307_Y [0], Y=$procmux$8222_Y [0] New connections: $procmux$8222_Y [2:1] = { $procmux$8222_Y [0] $procmux$8222_Y [0] } Consolidated identical input bits for $mux cell $procmux$4014: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN[1:0]$2086, Y=$procmux$4014_Y New ports: A=1'0, B=$procmux$3871_Y [0], Y=$procmux$4014_Y [0] New connections: $procmux$4014_Y [1] = $procmux$4014_Y [0] Consolidated identical input bits for $mux cell $procmux$5913: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN[1:0]$1657, Y=$procmux$5913_Y New ports: A=1'0, B=$procmux$5746_Y [0], Y=$procmux$5913_Y [0] New connections: $procmux$5913_Y [1] = $procmux$5913_Y [0] Consolidated identical input bits for $mux cell $procmux$3987: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN[1:0]$2101, Y=$procmux$3987_Y New ports: A=1'0, B=$procmux$3820_Y [0], Y=$procmux$3987_Y [0] New connections: $procmux$3987_Y [1] = $procmux$3987_Y [0] Consolidated identical input bits for $mux cell $procmux$7251: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN[1:0]$1331, Y=$procmux$7251_Y New ports: A=1'0, B=$procmux$7132_Y [0], Y=$procmux$7251_Y [0] New connections: $procmux$7251_Y [1] = $procmux$7251_Y [0] Consolidated identical input bits for $mux cell $procmux$5886: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN[1:0]$1672, Y=$procmux$5886_Y New ports: A=1'0, B=$procmux$5695_Y [0], Y=$procmux$5886_Y [0] New connections: $procmux$5886_Y [1] = $procmux$5886_Y [0] Consolidated identical input bits for $mux cell $procmux$3960: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN[1:0]$2116, Y=$procmux$3960_Y New ports: A=1'0, B=$procmux$3769_Y [0], Y=$procmux$3960_Y [0] New connections: $procmux$3960_Y [1] = $procmux$3960_Y [0] Consolidated identical input bits for $mux cell $procmux$8204: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN[2:0]$1763, Y=$procmux$8204_Y New ports: A=1'0, B=$procmux$5280_Y [0], Y=$procmux$8204_Y [0] New connections: $procmux$8204_Y [2:1] = { $procmux$8204_Y [0] $procmux$8204_Y [0] } Consolidated identical input bits for $mux cell $procmux$7224: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN[1:0]$1346, Y=$procmux$7224_Y New ports: A=1'0, B=$procmux$7081_Y [0], Y=$procmux$7224_Y [0] New connections: $procmux$7224_Y [1] = $procmux$7224_Y [0] Consolidated identical input bits for $mux cell $procmux$8186: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN[2:0]$1766, Y=$procmux$8186_Y New ports: A=1'0, B=$procmux$5253_Y [0], Y=$procmux$8186_Y [0] New connections: $procmux$8186_Y [2:1] = { $procmux$8186_Y [0] $procmux$8186_Y [0] } Consolidated identical input bits for $mux cell $procmux$7197: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN[1:0]$1361, Y=$procmux$7197_Y New ports: A=1'0, B=$procmux$7030_Y [0], Y=$procmux$7197_Y [0] New connections: $procmux$7197_Y [1] = $procmux$7197_Y [0] Consolidated identical input bits for $mux cell $procmux$8168: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN[2:0]$1769, Y=$procmux$8168_Y New ports: A=1'0, B=$procmux$5226_Y [0], Y=$procmux$8168_Y [0] New connections: $procmux$8168_Y [2:1] = { $procmux$8168_Y [0] $procmux$8168_Y [0] } Consolidated identical input bits for $mux cell $procmux$7170: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN[1:0]$1376, Y=$procmux$7170_Y New ports: A=1'0, B=$procmux$6979_Y [0], Y=$procmux$7170_Y [0] New connections: $procmux$7170_Y [1] = $procmux$7170_Y [0] Consolidated identical input bits for $mux cell $procmux$8726: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN[2:0]$1242, Y=$procmux$8726_Y New ports: A=1'0, B=$procmux$7554_Y [0], Y=$procmux$8726_Y [0] New connections: $procmux$8726_Y [2:1] = { $procmux$8726_Y [0] $procmux$8726_Y [0] } Consolidated identical input bits for $mux cell $procmux$8150: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN[2:0]$1834, Y=$procmux$8150_Y New ports: A=1'0, B=$procmux$4986_Y [0], Y=$procmux$8150_Y [0] New connections: $procmux$8150_Y [2:1] = { $procmux$8150_Y [0] $procmux$8150_Y [0] } Consolidated identical input bits for $mux cell $procmux$8132: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN[2:0]$1837, Y=$procmux$8132_Y New ports: A=1'0, B=$procmux$4959_Y [0], Y=$procmux$8132_Y [0] New connections: $procmux$8132_Y [2:1] = { $procmux$8132_Y [0] $procmux$8132_Y [0] } Consolidated identical input bits for $mux cell $procmux$3720: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN[1:0]$2145, Y=$procmux$3720_Y New ports: A=1'0, B=$procmux$3601_Y [0], Y=$procmux$3720_Y [0] New connections: $procmux$3720_Y [1] = $procmux$3720_Y [0] Consolidated identical input bits for $mux cell $procmux$8708: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN[2:0]$1245, Y=$procmux$8708_Y New ports: A=1'0, B=$procmux$7527_Y [0], Y=$procmux$8708_Y [0] New connections: $procmux$8708_Y [2:1] = { $procmux$8708_Y [0] $procmux$8708_Y [0] } Consolidated identical input bits for $mux cell $procmux$3693: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN[1:0]$2160, Y=$procmux$3693_Y New ports: A=1'0, B=$procmux$3550_Y [0], Y=$procmux$3693_Y [0] New connections: $procmux$3693_Y [1] = $procmux$3693_Y [0] Consolidated identical input bits for $mux cell $procmux$8114: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN[2:0]$1840, Y=$procmux$8114_Y New ports: A=1'0, B=$procmux$4932_Y [0], Y=$procmux$8114_Y [0] New connections: $procmux$8114_Y [2:1] = { $procmux$8114_Y [0] $procmux$8114_Y [0] } Consolidated identical input bits for $mux cell $procmux$3666: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN[1:0]$2175, Y=$procmux$3666_Y New ports: A=1'0, B=$procmux$3499_Y [0], Y=$procmux$3666_Y [0] New connections: $procmux$3666_Y [1] = $procmux$3666_Y [0] Consolidated identical input bits for $mux cell $procmux$8096: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN[2:0]$1843, Y=$procmux$8096_Y New ports: A=1'0, B=$procmux$4905_Y [0], Y=$procmux$8096_Y [0] New connections: $procmux$8096_Y [2:1] = { $procmux$8096_Y [0] $procmux$8096_Y [0] } Consolidated identical input bits for $mux cell $procmux$3639: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN[1:0]$2190, Y=$procmux$3639_Y New ports: A=1'0, B=$procmux$3448_Y [0], Y=$procmux$3639_Y [0] New connections: $procmux$3639_Y [1] = $procmux$3639_Y [0] Consolidated identical input bits for $mux cell $procmux$5646: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN[1:0]$1701, Y=$procmux$5646_Y New ports: A=1'0, B=$procmux$5527_Y [0], Y=$procmux$5646_Y [0] New connections: $procmux$5646_Y [1] = $procmux$5646_Y [0] Consolidated identical input bits for $mux cell $procmux$8690: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN[2:0]$1248, Y=$procmux$8690_Y New ports: A=1'0, B=$procmux$7500_Y [0], Y=$procmux$8690_Y [0] New connections: $procmux$8690_Y [2:1] = { $procmux$8690_Y [0] $procmux$8690_Y [0] } Consolidated identical input bits for $mux cell $procmux$5619: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN[1:0]$1716, Y=$procmux$5619_Y New ports: A=1'0, B=$procmux$5476_Y [0], Y=$procmux$5619_Y [0] New connections: $procmux$5619_Y [1] = $procmux$5619_Y [0] Consolidated identical input bits for $mux cell $procmux$8078: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN[2:0]$1908, Y=$procmux$8078_Y New ports: A=1'0, B=$procmux$4665_Y [0], Y=$procmux$8078_Y [0] New connections: $procmux$8078_Y [2:1] = { $procmux$8078_Y [0] $procmux$8078_Y [0] } Consolidated identical input bits for $mux cell $procmux$5592: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN[1:0]$1731, Y=$procmux$5592_Y New ports: A=1'0, B=$procmux$5425_Y [0], Y=$procmux$5592_Y [0] New connections: $procmux$5592_Y [1] = $procmux$5592_Y [0] Consolidated identical input bits for $mux cell $procmux$8060: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN[2:0]$1911, Y=$procmux$8060_Y New ports: A=1'0, B=$procmux$4638_Y [0], Y=$procmux$8060_Y [0] New connections: $procmux$8060_Y [2:1] = { $procmux$8060_Y [0] $procmux$8060_Y [0] } Consolidated identical input bits for $mux cell $procmux$5565: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN[1:0]$1746, Y=$procmux$5565_Y New ports: A=1'0, B=$procmux$5374_Y [0], Y=$procmux$5565_Y [0] New connections: $procmux$5565_Y [1] = $procmux$5565_Y [0] Consolidated identical input bits for $mux cell $procmux$8672: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN[2:0]$1251, Y=$procmux$8672_Y New ports: A=1'0, B=$procmux$7473_Y [0], Y=$procmux$8672_Y [0] New connections: $procmux$8672_Y [2:1] = { $procmux$8672_Y [0] $procmux$8672_Y [0] } Consolidated identical input bits for $mux cell $procmux$8042: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN[2:0]$1914, Y=$procmux$8042_Y New ports: A=1'0, B=$procmux$4611_Y [0], Y=$procmux$8042_Y [0] New connections: $procmux$8042_Y [2:1] = { $procmux$8042_Y [0] $procmux$8042_Y [0] } Consolidated identical input bits for $mux cell $procmux$8024: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN[2:0]$1917, Y=$procmux$8024_Y New ports: A=1'0, B=$procmux$4584_Y [0], Y=$procmux$8024_Y [0] New connections: $procmux$8024_Y [2:1] = { $procmux$8024_Y [0] $procmux$8024_Y [0] } Consolidated identical input bits for $mux cell $procmux$8654: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN[2:0]$1316, Y=$procmux$8654_Y New ports: A=1'0, B=$procmux$7233_Y [0], Y=$procmux$8654_Y [0] New connections: $procmux$8654_Y [2:1] = { $procmux$8654_Y [0] $procmux$8654_Y [0] } Consolidated identical input bits for $mux cell $procmux$8006: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN[2:0]$1982, Y=$procmux$8006_Y New ports: A=1'0, B=$procmux$4344_Y [0], Y=$procmux$8006_Y [0] New connections: $procmux$8006_Y [2:1] = { $procmux$8006_Y [0] $procmux$8006_Y [0] } Consolidated identical input bits for $mux cell $procmux$3399: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$2219, Y=$procmux$3399_Y New ports: A=1'0, B=$procmux$3280_Y [0], Y=$procmux$3399_Y [0] New connections: $procmux$3399_Y [1] = $procmux$3399_Y [0] Consolidated identical input bits for $mux cell $procmux$3372: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$2234, Y=$procmux$3372_Y New ports: A=1'0, B=$procmux$3229_Y [0], Y=$procmux$3372_Y [0] New connections: $procmux$3372_Y [1] = $procmux$3372_Y [0] Consolidated identical input bits for $mux cell $procmux$7988: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN[2:0]$1985, Y=$procmux$7988_Y New ports: A=1'0, B=$procmux$4317_Y [0], Y=$procmux$7988_Y [0] New connections: $procmux$7988_Y [2:1] = { $procmux$7988_Y [0] $procmux$7988_Y [0] } Consolidated identical input bits for $mux cell $procmux$3345: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$2249, Y=$procmux$3345_Y New ports: A=1'0, B=$procmux$3178_Y [0], Y=$procmux$3345_Y [0] New connections: $procmux$3345_Y [1] = $procmux$3345_Y [0] Consolidated identical input bits for $mux cell $procmux$6930: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN[1:0]$1405, Y=$procmux$6930_Y New ports: A=1'0, B=$procmux$6811_Y [0], Y=$procmux$6930_Y [0] New connections: $procmux$6930_Y [1] = $procmux$6930_Y [0] Consolidated identical input bits for $mux cell $procmux$3318: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$2264, Y=$procmux$3318_Y New ports: A=1'0, B=$procmux$3127_Y [0], Y=$procmux$3318_Y [0] New connections: $procmux$3318_Y [1] = $procmux$3318_Y [0] Consolidated identical input bits for $mux cell $procmux$8636: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN[2:0]$1319, Y=$procmux$8636_Y New ports: A=1'0, B=$procmux$7206_Y [0], Y=$procmux$8636_Y [0] New connections: $procmux$8636_Y [2:1] = { $procmux$8636_Y [0] $procmux$8636_Y [0] } Consolidated identical input bits for $mux cell $procmux$7970: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN[2:0]$1988, Y=$procmux$7970_Y New ports: A=1'0, B=$procmux$4290_Y [0], Y=$procmux$7970_Y [0] New connections: $procmux$7970_Y [2:1] = { $procmux$7970_Y [0] $procmux$7970_Y [0] } Consolidated identical input bits for $mux cell $procmux$6903: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN[1:0]$1420, Y=$procmux$6903_Y New ports: A=1'0, B=$procmux$6760_Y [0], Y=$procmux$6903_Y [0] New connections: $procmux$6903_Y [1] = $procmux$6903_Y [0] Consolidated identical input bits for $mux cell $procmux$7952: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN[2:0]$1991, Y=$procmux$7952_Y New ports: A=1'0, B=$procmux$4263_Y [0], Y=$procmux$7952_Y [0] New connections: $procmux$7952_Y [2:1] = { $procmux$7952_Y [0] $procmux$7952_Y [0] } Consolidated identical input bits for $mux cell $procmux$6876: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN[1:0]$1435, Y=$procmux$6876_Y New ports: A=1'0, B=$procmux$6709_Y [0], Y=$procmux$6876_Y [0] New connections: $procmux$6876_Y [1] = $procmux$6876_Y [0] Consolidated identical input bits for $mux cell $procmux$8618: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN[2:0]$1322, Y=$procmux$8618_Y New ports: A=1'0, B=$procmux$7179_Y [0], Y=$procmux$8618_Y [0] New connections: $procmux$8618_Y [2:1] = { $procmux$8618_Y [0] $procmux$8618_Y [0] } Consolidated identical input bits for $mux cell $procmux$7934: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN[2:0]$2056, Y=$procmux$7934_Y New ports: A=1'0, B=$procmux$4023_Y [0], Y=$procmux$7934_Y [0] New connections: $procmux$7934_Y [2:1] = { $procmux$7934_Y [0] $procmux$7934_Y [0] } Consolidated identical input bits for $mux cell $procmux$6849: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN[1:0]$1450, Y=$procmux$6849_Y New ports: A=1'0, B=$procmux$6658_Y [0], Y=$procmux$6849_Y [0] New connections: $procmux$6849_Y [1] = $procmux$6849_Y [0] Consolidated identical input bits for $mux cell $procmux$5325: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN[1:0]$1775, Y=$procmux$5325_Y New ports: A=1'0, B=$procmux$5206_Y [0], Y=$procmux$5325_Y [0] New connections: $procmux$5325_Y [1] = $procmux$5325_Y [0] Consolidated identical input bits for $mux cell $procmux$5298: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN[1:0]$1790, Y=$procmux$5298_Y New ports: A=1'0, B=$procmux$5155_Y [0], Y=$procmux$5298_Y [0] New connections: $procmux$5298_Y [1] = $procmux$5298_Y [0] Consolidated identical input bits for $mux cell $procmux$7916: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN[2:0]$2059, Y=$procmux$7916_Y New ports: A=1'0, B=$procmux$3996_Y [0], Y=$procmux$7916_Y [0] New connections: $procmux$7916_Y [2:1] = { $procmux$7916_Y [0] $procmux$7916_Y [0] } Consolidated identical input bits for $mux cell $procmux$5271: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN[1:0]$1805, Y=$procmux$5271_Y New ports: A=1'0, B=$procmux$5104_Y [0], Y=$procmux$5271_Y [0] New connections: $procmux$5271_Y [1] = $procmux$5271_Y [0] Consolidated identical input bits for $mux cell $procmux$8600: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN[2:0]$1325, Y=$procmux$8600_Y New ports: A=1'0, B=$procmux$7152_Y [0], Y=$procmux$8600_Y [0] New connections: $procmux$8600_Y [2:1] = { $procmux$8600_Y [0] $procmux$8600_Y [0] } Consolidated identical input bits for $mux cell $procmux$7898: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN[2:0]$2062, Y=$procmux$7898_Y New ports: A=1'0, B=$procmux$3969_Y [0], Y=$procmux$7898_Y [0] New connections: $procmux$7898_Y [2:1] = { $procmux$7898_Y [0] $procmux$7898_Y [0] } Consolidated identical input bits for $mux cell $procmux$3078: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$2293, Y=$procmux$3078_Y New ports: A=1'0, B=$procmux$2959_Y [0], Y=$procmux$3078_Y [0] New connections: $procmux$3078_Y [1] = $procmux$3078_Y [0] Consolidated identical input bits for $mux cell $procmux$5244: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN[1:0]$1820, Y=$procmux$5244_Y New ports: A=1'0, B=$procmux$5053_Y [0], Y=$procmux$5244_Y [0] New connections: $procmux$5244_Y [1] = $procmux$5244_Y [0] Consolidated identical input bits for $mux cell $procmux$3051: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$2308, Y=$procmux$3051_Y New ports: A=1'0, B=$procmux$2908_Y [0], Y=$procmux$3051_Y [0] New connections: $procmux$3051_Y [1] = $procmux$3051_Y [0] Consolidated identical input bits for $mux cell $procmux$3024: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$2323, Y=$procmux$3024_Y New ports: A=1'0, B=$procmux$2857_Y [0], Y=$procmux$3024_Y [0] New connections: $procmux$3024_Y [1] = $procmux$3024_Y [0] Consolidated identical input bits for $mux cell $procmux$7880: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN[2:0]$2065, Y=$procmux$7880_Y New ports: A=1'0, B=$procmux$3942_Y [0], Y=$procmux$7880_Y [0] New connections: $procmux$7880_Y [2:1] = { $procmux$7880_Y [0] $procmux$7880_Y [0] } Consolidated identical input bits for $mux cell $procmux$2997: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$2338, Y=$procmux$2997_Y New ports: A=1'0, B=$procmux$2806_Y [0], Y=$procmux$2997_Y [0] New connections: $procmux$2997_Y [1] = $procmux$2997_Y [0] Consolidated identical input bits for $mux cell $procmux$8582: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN[2:0]$1390, Y=$procmux$8582_Y New ports: A=1'0, B=$procmux$6912_Y [0], Y=$procmux$8582_Y [0] New connections: $procmux$8582_Y [2:1] = { $procmux$8582_Y [0] $procmux$8582_Y [0] } Consolidated identical input bits for $mux cell $procmux$7862: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN[2:0]$2130, Y=$procmux$7862_Y New ports: A=1'0, B=$procmux$3702_Y [0], Y=$procmux$7862_Y [0] New connections: $procmux$7862_Y [2:1] = { $procmux$7862_Y [0] $procmux$7862_Y [0] } Consolidated identical input bits for $mux cell $procmux$7844: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN[2:0]$2133, Y=$procmux$7844_Y New ports: A=1'0, B=$procmux$3675_Y [0], Y=$procmux$7844_Y [0] New connections: $procmux$7844_Y [2:1] = { $procmux$7844_Y [0] $procmux$7844_Y [0] } Consolidated identical input bits for $mux cell $procmux$8564: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN[2:0]$1393, Y=$procmux$8564_Y New ports: A=1'0, B=$procmux$6885_Y [0], Y=$procmux$8564_Y [0] New connections: $procmux$8564_Y [2:1] = { $procmux$8564_Y [0] $procmux$8564_Y [0] } Consolidated identical input bits for $mux cell $procmux$7826: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN[2:0]$2136, Y=$procmux$7826_Y New ports: A=1'0, B=$procmux$3648_Y [0], Y=$procmux$7826_Y [0] New connections: $procmux$7826_Y [2:1] = { $procmux$7826_Y [0] $procmux$7826_Y [0] } Consolidated identical input bits for $mux cell $procmux$7808: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN[2:0]$2139, Y=$procmux$7808_Y New ports: A=1'0, B=$procmux$3621_Y [0], Y=$procmux$7808_Y [0] New connections: $procmux$7808_Y [2:1] = { $procmux$7808_Y [0] $procmux$7808_Y [0] } Consolidated identical input bits for $mux cell $procmux$8546: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN[2:0]$1396, Y=$procmux$8546_Y New ports: A=1'0, B=$procmux$6858_Y [0], Y=$procmux$8546_Y [0] New connections: $procmux$8546_Y [2:1] = { $procmux$8546_Y [0] $procmux$8546_Y [0] } Consolidated identical input bits for $mux cell $procmux$7790: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$2204, Y=$procmux$7790_Y New ports: A=1'0, B=$procmux$3381_Y [0], Y=$procmux$7790_Y [0] New connections: $procmux$7790_Y [2:1] = { $procmux$7790_Y [0] $procmux$7790_Y [0] } Consolidated identical input bits for $mux cell $procmux$7772: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$2207, Y=$procmux$7772_Y New ports: A=1'0, B=$procmux$3354_Y [0], Y=$procmux$7772_Y [0] New connections: $procmux$7772_Y [2:1] = { $procmux$7772_Y [0] $procmux$7772_Y [0] } Consolidated identical input bits for $mux cell $procmux$2757: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$2367, Y=$procmux$2757_Y New ports: A=1'0, B=$procmux$2638_Y [0], Y=$procmux$2757_Y [0] New connections: $procmux$2757_Y [1] = $procmux$2757_Y [0] Consolidated identical input bits for $mux cell $procmux$5004: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN[1:0]$1849, Y=$procmux$5004_Y New ports: A=1'0, B=$procmux$4885_Y [0], Y=$procmux$5004_Y [0] New connections: $procmux$5004_Y [1] = $procmux$5004_Y [0] Consolidated identical input bits for $mux cell $procmux$2730: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$2382, Y=$procmux$2730_Y New ports: A=1'0, B=$procmux$2587_Y [0], Y=$procmux$2730_Y [0] New connections: $procmux$2730_Y [1] = $procmux$2730_Y [0] Consolidated identical input bits for $mux cell $procmux$8528: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN[2:0]$1399, Y=$procmux$8528_Y New ports: A=1'0, B=$procmux$6831_Y [0], Y=$procmux$8528_Y [0] New connections: $procmux$8528_Y [2:1] = { $procmux$8528_Y [0] $procmux$8528_Y [0] } Consolidated identical input bits for $mux cell $procmux$6609: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN[1:0]$1479, Y=$procmux$6609_Y New ports: A=1'0, B=$procmux$6490_Y [0], Y=$procmux$6609_Y [0] New connections: $procmux$6609_Y [1] = $procmux$6609_Y [0] Consolidated identical input bits for $mux cell $procmux$7754: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$2210, Y=$procmux$7754_Y New ports: A=1'0, B=$procmux$3327_Y [0], Y=$procmux$7754_Y [0] New connections: $procmux$7754_Y [2:1] = { $procmux$7754_Y [0] $procmux$7754_Y [0] } Consolidated identical input bits for $mux cell $procmux$2703: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$2397, Y=$procmux$2703_Y New ports: A=1'0, B=$procmux$2536_Y [0], Y=$procmux$2703_Y [0] New connections: $procmux$2703_Y [1] = $procmux$2703_Y [0] Consolidated identical input bits for $mux cell $procmux$4977: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN[1:0]$1864, Y=$procmux$4977_Y New ports: A=1'0, B=$procmux$4834_Y [0], Y=$procmux$4977_Y [0] New connections: $procmux$4977_Y [1] = $procmux$4977_Y [0] Consolidated identical input bits for $mux cell $procmux$2676: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$2412, Y=$procmux$2676_Y New ports: A=1'0, B=$procmux$2485_Y [0], Y=$procmux$2676_Y [0] New connections: $procmux$2676_Y [1] = $procmux$2676_Y [0] Consolidated identical input bits for $mux cell $procmux$6582: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN[1:0]$1494, Y=$procmux$6582_Y New ports: A=1'0, B=$procmux$6439_Y [0], Y=$procmux$6582_Y [0] New connections: $procmux$6582_Y [1] = $procmux$6582_Y [0] Consolidated identical input bits for $mux cell $procmux$4950: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN[1:0]$1879, Y=$procmux$4950_Y New ports: A=1'0, B=$procmux$4783_Y [0], Y=$procmux$4950_Y [0] New connections: $procmux$4950_Y [1] = $procmux$4950_Y [0] Consolidated identical input bits for $mux cell $procmux$7736: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$2213, Y=$procmux$7736_Y New ports: A=1'0, B=$procmux$3300_Y [0], Y=$procmux$7736_Y [0] New connections: $procmux$7736_Y [2:1] = { $procmux$7736_Y [0] $procmux$7736_Y [0] } Consolidated identical input bits for $mux cell $procmux$4923: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN[1:0]$1894, Y=$procmux$4923_Y New ports: A=1'0, B=$procmux$4732_Y [0], Y=$procmux$4923_Y [0] New connections: $procmux$4923_Y [1] = $procmux$4923_Y [0] Consolidated identical input bits for $mux cell $procmux$8510: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN[2:0]$1464, Y=$procmux$8510_Y New ports: A=1'0, B=$procmux$6591_Y [0], Y=$procmux$8510_Y [0] New connections: $procmux$8510_Y [2:1] = { $procmux$8510_Y [0] $procmux$8510_Y [0] } Consolidated identical input bits for $mux cell $procmux$6555: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN[1:0]$1509, Y=$procmux$6555_Y New ports: A=1'0, B=$procmux$6388_Y [0], Y=$procmux$6555_Y [0] New connections: $procmux$6555_Y [1] = $procmux$6555_Y [0] Consolidated identical input bits for $mux cell $procmux$7718: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$2278, Y=$procmux$7718_Y New ports: A=1'0, B=$procmux$3060_Y [0], Y=$procmux$7718_Y [0] New connections: $procmux$7718_Y [2:1] = { $procmux$7718_Y [0] $procmux$7718_Y [0] } Consolidated identical input bits for $mux cell $procmux$6528: Old ports: A=2'00, B=$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN[1:0]$1524, Y=$procmux$6528_Y New ports: A=1'0, B=$procmux$6337_Y [0], Y=$procmux$6528_Y [0] New connections: $procmux$6528_Y [1] = $procmux$6528_Y [0] Consolidated identical input bits for $mux cell $procmux$7700: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$2281, Y=$procmux$7700_Y New ports: A=1'0, B=$procmux$3033_Y [0], Y=$procmux$7700_Y [0] New connections: $procmux$7700_Y [2:1] = { $procmux$7700_Y [0] $procmux$7700_Y [0] } Consolidated identical input bits for $mux cell $procmux$8492: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN[2:0]$1467, Y=$procmux$8492_Y New ports: A=1'0, B=$procmux$6564_Y [0], Y=$procmux$8492_Y [0] New connections: $procmux$8492_Y [2:1] = { $procmux$8492_Y [0] $procmux$8492_Y [0] } Consolidated identical input bits for $mux cell $procmux$7682: Old ports: A=3'000, B=$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$2284, Y=$procmux$7682_Y New ports: A=1'0, B=$procmux$3006_Y [0], Y=$procmux$7682_Y [0] New connections: $procmux$7682_Y [2:1] = { $procmux$7682_Y [0] $procmux$7682_Y [0] } Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $procmux$7652: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$2350, Y=$procmux$7652_Y New ports: A=1'0, B=$procmux$2757_Y [0], Y=$procmux$7652_Y [0] New connections: $procmux$7652_Y [1] = $procmux$7652_Y [0] Consolidated identical input bits for $mux cell $procmux$7634: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$2353, Y=$procmux$7634_Y New ports: A=1'0, B=$procmux$2730_Y [0], Y=$procmux$7634_Y [0] New connections: $procmux$7634_Y [1] = $procmux$7634_Y [0] Consolidated identical input bits for $mux cell $procmux$8468: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN[1:0]$1471, Y=$procmux$8468_Y New ports: A=1'0, B=$procmux$6528_Y [0], Y=$procmux$8468_Y [0] New connections: $procmux$8468_Y [1] = $procmux$8468_Y [0] Consolidated identical input bits for $mux cell $procmux$7616: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$2356, Y=$procmux$7616_Y New ports: A=1'0, B=$procmux$2703_Y [0], Y=$procmux$7616_Y [0] New connections: $procmux$7616_Y [1] = $procmux$7616_Y [0] Consolidated identical input bits for $mux cell $procmux$7598: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$2359, Y=$procmux$7598_Y New ports: A=1'0, B=$procmux$2676_Y [0], Y=$procmux$7598_Y [0] New connections: $procmux$7598_Y [1] = $procmux$7598_Y [0] Consolidated identical input bits for $mux cell $procmux$8450: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN[1:0]$1536, Y=$procmux$8450_Y New ports: A=1'0, B=$procmux$6288_Y [0], Y=$procmux$8450_Y [0] New connections: $procmux$8450_Y [1] = $procmux$8450_Y [0] Consolidated identical input bits for $mux cell $procmux$8432: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN[1:0]$1539, Y=$procmux$8432_Y New ports: A=1'0, B=$procmux$6261_Y [0], Y=$procmux$8432_Y [0] New connections: $procmux$8432_Y [1] = $procmux$8432_Y [0] Consolidated identical input bits for $mux cell $procmux$8414: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN[1:0]$1542, Y=$procmux$8414_Y New ports: A=1'0, B=$procmux$6234_Y [0], Y=$procmux$8414_Y [0] New connections: $procmux$8414_Y [1] = $procmux$8414_Y [0] Consolidated identical input bits for $mux cell $procmux$8396: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN[1:0]$1545, Y=$procmux$8396_Y New ports: A=1'0, B=$procmux$6207_Y [0], Y=$procmux$8396_Y [0] New connections: $procmux$8396_Y [1] = $procmux$8396_Y [0] Consolidated identical input bits for $mux cell $procmux$8378: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN[1:0]$1610, Y=$procmux$8378_Y New ports: A=1'0, B=$procmux$5967_Y [0], Y=$procmux$8378_Y [0] New connections: $procmux$8378_Y [1] = $procmux$8378_Y [0] Consolidated identical input bits for $mux cell $procmux$8360: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN[1:0]$1613, Y=$procmux$8360_Y New ports: A=1'0, B=$procmux$5940_Y [0], Y=$procmux$8360_Y [0] New connections: $procmux$8360_Y [1] = $procmux$8360_Y [0] Consolidated identical input bits for $mux cell $procmux$8342: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN[1:0]$1616, Y=$procmux$8342_Y New ports: A=1'0, B=$procmux$5913_Y [0], Y=$procmux$8342_Y [0] New connections: $procmux$8342_Y [1] = $procmux$8342_Y [0] Consolidated identical input bits for $mux cell $procmux$8324: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN[1:0]$1619, Y=$procmux$8324_Y New ports: A=1'0, B=$procmux$5886_Y [0], Y=$procmux$8324_Y [0] New connections: $procmux$8324_Y [1] = $procmux$8324_Y [0] Consolidated identical input bits for $mux cell $procmux$8306: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN[1:0]$1684, Y=$procmux$8306_Y New ports: A=1'0, B=$procmux$5646_Y [0], Y=$procmux$8306_Y [0] New connections: $procmux$8306_Y [1] = $procmux$8306_Y [0] Consolidated identical input bits for $mux cell $procmux$8288: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN[1:0]$1687, Y=$procmux$8288_Y New ports: A=1'0, B=$procmux$5619_Y [0], Y=$procmux$8288_Y [0] New connections: $procmux$8288_Y [1] = $procmux$8288_Y [0] Consolidated identical input bits for $mux cell $procmux$8270: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN[1:0]$1690, Y=$procmux$8270_Y New ports: A=1'0, B=$procmux$5592_Y [0], Y=$procmux$8270_Y [0] New connections: $procmux$8270_Y [1] = $procmux$8270_Y [0] Consolidated identical input bits for $mux cell $procmux$8252: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN[1:0]$1693, Y=$procmux$8252_Y New ports: A=1'0, B=$procmux$5565_Y [0], Y=$procmux$8252_Y [0] New connections: $procmux$8252_Y [1] = $procmux$8252_Y [0] Consolidated identical input bits for $mux cell $procmux$8234: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN[1:0]$1758, Y=$procmux$8234_Y New ports: A=1'0, B=$procmux$5325_Y [0], Y=$procmux$8234_Y [0] New connections: $procmux$8234_Y [1] = $procmux$8234_Y [0] Consolidated identical input bits for $mux cell $procmux$8216: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN[1:0]$1761, Y=$procmux$8216_Y New ports: A=1'0, B=$procmux$5298_Y [0], Y=$procmux$8216_Y [0] New connections: $procmux$8216_Y [1] = $procmux$8216_Y [0] Consolidated identical input bits for $mux cell $procmux$8198: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN[1:0]$1764, Y=$procmux$8198_Y New ports: A=1'0, B=$procmux$5271_Y [0], Y=$procmux$8198_Y [0] New connections: $procmux$8198_Y [1] = $procmux$8198_Y [0] Consolidated identical input bits for $mux cell $procmux$8180: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN[1:0]$1767, Y=$procmux$8180_Y New ports: A=1'0, B=$procmux$5244_Y [0], Y=$procmux$8180_Y [0] New connections: $procmux$8180_Y [1] = $procmux$8180_Y [0] Consolidated identical input bits for $mux cell $procmux$8738: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$1240, Y=$procmux$8738_Y New ports: A=1'0, B=$procmux$7572_Y [0], Y=$procmux$8738_Y [0] New connections: $procmux$8738_Y [1] = $procmux$8738_Y [0] Consolidated identical input bits for $mux cell $procmux$8162: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN[1:0]$1832, Y=$procmux$8162_Y New ports: A=1'0, B=$procmux$5004_Y [0], Y=$procmux$8162_Y [0] New connections: $procmux$8162_Y [1] = $procmux$8162_Y [0] Consolidated identical input bits for $mux cell $procmux$8144: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN[1:0]$1835, Y=$procmux$8144_Y New ports: A=1'0, B=$procmux$4977_Y [0], Y=$procmux$8144_Y [0] New connections: $procmux$8144_Y [1] = $procmux$8144_Y [0] Consolidated identical input bits for $mux cell $procmux$8720: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN[1:0]$1243, Y=$procmux$8720_Y New ports: A=1'0, B=$procmux$7545_Y [0], Y=$procmux$8720_Y [0] New connections: $procmux$8720_Y [1] = $procmux$8720_Y [0] Consolidated identical input bits for $mux cell $procmux$8126: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN[1:0]$1838, Y=$procmux$8126_Y New ports: A=1'0, B=$procmux$4950_Y [0], Y=$procmux$8126_Y [0] New connections: $procmux$8126_Y [1] = $procmux$8126_Y [0] Consolidated identical input bits for $mux cell $procmux$8108: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN[1:0]$1841, Y=$procmux$8108_Y New ports: A=1'0, B=$procmux$4923_Y [0], Y=$procmux$8108_Y [0] New connections: $procmux$8108_Y [1] = $procmux$8108_Y [0] Consolidated identical input bits for $mux cell $procmux$8702: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN[1:0]$1246, Y=$procmux$8702_Y New ports: A=1'0, B=$procmux$7518_Y [0], Y=$procmux$8702_Y [0] New connections: $procmux$8702_Y [1] = $procmux$8702_Y [0] Consolidated identical input bits for $mux cell $procmux$8090: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN[1:0]$1906, Y=$procmux$8090_Y New ports: A=1'0, B=$procmux$4683_Y [0], Y=$procmux$8090_Y [0] New connections: $procmux$8090_Y [1] = $procmux$8090_Y [0] Consolidated identical input bits for $mux cell $procmux$8072: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN[1:0]$1909, Y=$procmux$8072_Y New ports: A=1'0, B=$procmux$4656_Y [0], Y=$procmux$8072_Y [0] New connections: $procmux$8072_Y [1] = $procmux$8072_Y [0] Consolidated identical input bits for $mux cell $procmux$8684: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN[1:0]$1249, Y=$procmux$8684_Y New ports: A=1'0, B=$procmux$7491_Y [0], Y=$procmux$8684_Y [0] New connections: $procmux$8684_Y [1] = $procmux$8684_Y [0] Consolidated identical input bits for $mux cell $procmux$8054: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN[1:0]$1912, Y=$procmux$8054_Y New ports: A=1'0, B=$procmux$4629_Y [0], Y=$procmux$8054_Y [0] New connections: $procmux$8054_Y [1] = $procmux$8054_Y [0] Consolidated identical input bits for $mux cell $procmux$8036: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN[1:0]$1915, Y=$procmux$8036_Y New ports: A=1'0, B=$procmux$4602_Y [0], Y=$procmux$8036_Y [0] New connections: $procmux$8036_Y [1] = $procmux$8036_Y [0] Consolidated identical input bits for $mux cell $procmux$8666: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN[1:0]$1314, Y=$procmux$8666_Y New ports: A=1'0, B=$procmux$7251_Y [0], Y=$procmux$8666_Y [0] New connections: $procmux$8666_Y [1] = $procmux$8666_Y [0] Consolidated identical input bits for $mux cell $procmux$8018: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN[1:0]$1980, Y=$procmux$8018_Y New ports: A=1'0, B=$procmux$4362_Y [0], Y=$procmux$8018_Y [0] New connections: $procmux$8018_Y [1] = $procmux$8018_Y [0] Consolidated identical input bits for $mux cell $procmux$8000: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN[1:0]$1983, Y=$procmux$8000_Y New ports: A=1'0, B=$procmux$4335_Y [0], Y=$procmux$8000_Y [0] New connections: $procmux$8000_Y [1] = $procmux$8000_Y [0] Consolidated identical input bits for $mux cell $procmux$8648: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN[1:0]$1317, Y=$procmux$8648_Y New ports: A=1'0, B=$procmux$7224_Y [0], Y=$procmux$8648_Y [0] New connections: $procmux$8648_Y [1] = $procmux$8648_Y [0] Consolidated identical input bits for $mux cell $procmux$7982: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN[1:0]$1986, Y=$procmux$7982_Y New ports: A=1'0, B=$procmux$4308_Y [0], Y=$procmux$7982_Y [0] New connections: $procmux$7982_Y [1] = $procmux$7982_Y [0] Consolidated identical input bits for $mux cell $procmux$7964: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN[1:0]$1989, Y=$procmux$7964_Y New ports: A=1'0, B=$procmux$4281_Y [0], Y=$procmux$7964_Y [0] New connections: $procmux$7964_Y [1] = $procmux$7964_Y [0] Consolidated identical input bits for $mux cell $procmux$8630: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN[1:0]$1320, Y=$procmux$8630_Y New ports: A=1'0, B=$procmux$7197_Y [0], Y=$procmux$8630_Y [0] New connections: $procmux$8630_Y [1] = $procmux$8630_Y [0] Consolidated identical input bits for $mux cell $procmux$7946: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN[1:0]$2054, Y=$procmux$7946_Y New ports: A=1'0, B=$procmux$4041_Y [0], Y=$procmux$7946_Y [0] New connections: $procmux$7946_Y [1] = $procmux$7946_Y [0] Consolidated identical input bits for $mux cell $procmux$7928: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN[1:0]$2057, Y=$procmux$7928_Y New ports: A=1'0, B=$procmux$4014_Y [0], Y=$procmux$7928_Y [0] New connections: $procmux$7928_Y [1] = $procmux$7928_Y [0] Consolidated identical input bits for $mux cell $procmux$8612: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN[1:0]$1323, Y=$procmux$8612_Y New ports: A=1'0, B=$procmux$7170_Y [0], Y=$procmux$8612_Y [0] New connections: $procmux$8612_Y [1] = $procmux$8612_Y [0] Consolidated identical input bits for $mux cell $procmux$7910: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN[1:0]$2060, Y=$procmux$7910_Y New ports: A=1'0, B=$procmux$3987_Y [0], Y=$procmux$7910_Y [0] New connections: $procmux$7910_Y [1] = $procmux$7910_Y [0] Consolidated identical input bits for $mux cell $procmux$7892: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN[1:0]$2063, Y=$procmux$7892_Y New ports: A=1'0, B=$procmux$3960_Y [0], Y=$procmux$7892_Y [0] New connections: $procmux$7892_Y [1] = $procmux$7892_Y [0] Consolidated identical input bits for $mux cell $procmux$8594: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN[1:0]$1388, Y=$procmux$8594_Y New ports: A=1'0, B=$procmux$6930_Y [0], Y=$procmux$8594_Y [0] New connections: $procmux$8594_Y [1] = $procmux$8594_Y [0] Consolidated identical input bits for $mux cell $procmux$7874: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN[1:0]$2128, Y=$procmux$7874_Y New ports: A=1'0, B=$procmux$3720_Y [0], Y=$procmux$7874_Y [0] New connections: $procmux$7874_Y [1] = $procmux$7874_Y [0] Consolidated identical input bits for $mux cell $procmux$7856: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN[1:0]$2131, Y=$procmux$7856_Y New ports: A=1'0, B=$procmux$3693_Y [0], Y=$procmux$7856_Y [0] New connections: $procmux$7856_Y [1] = $procmux$7856_Y [0] Consolidated identical input bits for $mux cell $procmux$8576: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN[1:0]$1391, Y=$procmux$8576_Y New ports: A=1'0, B=$procmux$6903_Y [0], Y=$procmux$8576_Y [0] New connections: $procmux$8576_Y [1] = $procmux$8576_Y [0] Consolidated identical input bits for $mux cell $procmux$7838: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN[1:0]$2134, Y=$procmux$7838_Y New ports: A=1'0, B=$procmux$3666_Y [0], Y=$procmux$7838_Y [0] New connections: $procmux$7838_Y [1] = $procmux$7838_Y [0] Consolidated identical input bits for $mux cell $procmux$9113: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$1231, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$720 New ports: A=$procmux$7622_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$720 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$720 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$720 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$413_EN[2:0]$720 [0] } Consolidated identical input bits for $mux cell $procmux$7820: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN[1:0]$2137, Y=$procmux$7820_Y New ports: A=1'0, B=$procmux$3639_Y [0], Y=$procmux$7820_Y [0] New connections: $procmux$7820_Y [1] = $procmux$7820_Y [0] Consolidated identical input bits for $mux cell $procmux$8558: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN[1:0]$1394, Y=$procmux$8558_Y New ports: A=1'0, B=$procmux$6876_Y [0], Y=$procmux$8558_Y [0] New connections: $procmux$8558_Y [1] = $procmux$8558_Y [0] Consolidated identical input bits for $mux cell $procmux$7802: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$2202, Y=$procmux$7802_Y New ports: A=1'0, B=$procmux$3399_Y [0], Y=$procmux$7802_Y [0] New connections: $procmux$7802_Y [1] = $procmux$7802_Y [0] Consolidated identical input bits for $mux cell $procmux$7784: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$2205, Y=$procmux$7784_Y New ports: A=1'0, B=$procmux$3372_Y [0], Y=$procmux$7784_Y [0] New connections: $procmux$7784_Y [1] = $procmux$7784_Y [0] Consolidated identical input bits for $mux cell $procmux$8540: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN[1:0]$1397, Y=$procmux$8540_Y New ports: A=1'0, B=$procmux$6849_Y [0], Y=$procmux$8540_Y [0] New connections: $procmux$8540_Y [1] = $procmux$8540_Y [0] Consolidated identical input bits for $mux cell $procmux$7766: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$2208, Y=$procmux$7766_Y New ports: A=1'0, B=$procmux$3345_Y [0], Y=$procmux$7766_Y [0] New connections: $procmux$7766_Y [1] = $procmux$7766_Y [0] Consolidated identical input bits for $mux cell $procmux$9104: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$1234, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$723 New ports: A=$procmux$7604_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$723 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$723 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$723 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$415_EN[2:0]$723 [0] } Consolidated identical input bits for $mux cell $procmux$7748: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$2211, Y=$procmux$7748_Y New ports: A=1'0, B=$procmux$3318_Y [0], Y=$procmux$7748_Y [0] New connections: $procmux$7748_Y [1] = $procmux$7748_Y [0] Consolidated identical input bits for $mux cell $procmux$8522: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN[1:0]$1462, Y=$procmux$8522_Y New ports: A=1'0, B=$procmux$6609_Y [0], Y=$procmux$8522_Y [0] New connections: $procmux$8522_Y [1] = $procmux$8522_Y [0] Consolidated identical input bits for $mux cell $procmux$7730: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$2276, Y=$procmux$7730_Y New ports: A=1'0, B=$procmux$3078_Y [0], Y=$procmux$7730_Y [0] New connections: $procmux$7730_Y [1] = $procmux$7730_Y [0] Consolidated identical input bits for $mux cell $procmux$7712: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$2279, Y=$procmux$7712_Y New ports: A=1'0, B=$procmux$3051_Y [0], Y=$procmux$7712_Y [0] New connections: $procmux$7712_Y [1] = $procmux$7712_Y [0] Consolidated identical input bits for $mux cell $procmux$8504: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN[1:0]$1465, Y=$procmux$8504_Y New ports: A=1'0, B=$procmux$6582_Y [0], Y=$procmux$8504_Y [0] New connections: $procmux$8504_Y [1] = $procmux$8504_Y [0] Consolidated identical input bits for $mux cell $procmux$7694: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$2282, Y=$procmux$7694_Y New ports: A=1'0, B=$procmux$3024_Y [0], Y=$procmux$7694_Y [0] New connections: $procmux$7694_Y [1] = $procmux$7694_Y [0] Consolidated identical input bits for $mux cell $procmux$9095: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$1237, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$726 New ports: A=$procmux$7586_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$726 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$726 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$726 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$417_EN[2:0]$726 [0] } Consolidated identical input bits for $mux cell $procmux$7676: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$2285, Y=$procmux$7676_Y New ports: A=1'0, B=$procmux$2997_Y [0], Y=$procmux$7676_Y [0] New connections: $procmux$7676_Y [1] = $procmux$7676_Y [0] Consolidated identical input bits for $mux cell $procmux$8486: Old ports: A=2'00, B=$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN[1:0]$1468, Y=$procmux$8486_Y New ports: A=1'0, B=$procmux$6555_Y [0], Y=$procmux$8486_Y [0] New connections: $procmux$8486_Y [1] = $procmux$8486_Y [0] Consolidated identical input bits for $mux cell $procmux$9590: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN[2:0]$1072, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN[2:0]$561 New ports: A=$procmux$8582_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN[2:0]$561 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN[2:0]$561 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN[2:0]$561 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$307_EN[2:0]$561 [0] } Consolidated identical input bits for $mux cell $procmux$9257: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN[2:0]$1183, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN[2:0]$672 New ports: A=$procmux$7916_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN[2:0]$672 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN[2:0]$672 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN[2:0]$672 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$381_EN[2:0]$672 [0] } Consolidated identical input bits for $mux cell $procmux$9581: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN[2:0]$1075, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN[2:0]$564 New ports: A=$procmux$8564_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN[2:0]$564 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN[2:0]$564 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN[2:0]$564 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$309_EN[2:0]$564 [0] } Consolidated identical input bits for $mux cell $procmux$9572: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN[2:0]$1078, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN[2:0]$567 New ports: A=$procmux$8546_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN[2:0]$567 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN[2:0]$567 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN[2:0]$567 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$311_EN[2:0]$567 [0] } Consolidated identical input bits for $mux cell $procmux$9248: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN[2:0]$1186, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN[2:0]$675 New ports: A=$procmux$7898_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN[2:0]$675 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN[2:0]$675 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN[2:0]$675 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$383_EN[2:0]$675 [0] } Consolidated identical input bits for $mux cell $procmux$9563: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN[2:0]$1081, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN[2:0]$570 New ports: A=$procmux$8528_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN[2:0]$570 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN[2:0]$570 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN[2:0]$570 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$313_EN[2:0]$570 [0] } Consolidated identical input bits for $mux cell $procmux$9554: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN[2:0]$1084, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN[2:0]$573 New ports: A=$procmux$8510_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN[2:0]$573 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN[2:0]$573 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN[2:0]$573 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$315_EN[2:0]$573 [0] } Consolidated identical input bits for $mux cell $procmux$9545: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN[2:0]$1087, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN[2:0]$576 New ports: A=$procmux$8492_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN[2:0]$576 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN[2:0]$576 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN[2:0]$576 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$317_EN[2:0]$576 [0] } Consolidated identical input bits for $mux cell $procmux$9239: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN[2:0]$1189, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN[2:0]$678 New ports: A=$procmux$7880_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN[2:0]$678 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN[2:0]$678 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN[2:0]$678 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$385_EN[2:0]$678 [0] } Consolidated identical input bits for $mux cell $procmux$9536: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN[2:0]$1090, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN[2:0]$579 New ports: A=$procmux$8474_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN[2:0]$579 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN[2:0]$579 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN[2:0]$579 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$319_EN[2:0]$579 [0] } Consolidated identical input bits for $mux cell $procmux$9527: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN[2:0]$1093, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN[2:0]$582 New ports: A=$procmux$8456_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN[2:0]$582 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN[2:0]$582 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN[2:0]$582 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$321_EN[2:0]$582 [0] } Consolidated identical input bits for $mux cell $procmux$9230: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN[2:0]$1192, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN[2:0]$681 New ports: A=$procmux$7862_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN[2:0]$681 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN[2:0]$681 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN[2:0]$681 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$387_EN[2:0]$681 [0] } Consolidated identical input bits for $mux cell $procmux$9518: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN[2:0]$1096, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN[2:0]$585 New ports: A=$procmux$8438_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN[2:0]$585 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN[2:0]$585 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN[2:0]$585 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$323_EN[2:0]$585 [0] } Consolidated identical input bits for $mux cell $procmux$9509: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN[2:0]$1099, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN[2:0]$588 New ports: A=$procmux$8420_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN[2:0]$588 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN[2:0]$588 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN[2:0]$588 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$325_EN[2:0]$588 [0] } Consolidated identical input bits for $mux cell $procmux$9221: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN[2:0]$1195, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN[2:0]$684 New ports: A=$procmux$7844_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN[2:0]$684 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN[2:0]$684 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN[2:0]$684 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$389_EN[2:0]$684 [0] } Consolidated identical input bits for $mux cell $procmux$9500: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN[2:0]$1102, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN[2:0]$591 New ports: A=$procmux$8402_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN[2:0]$591 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN[2:0]$591 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN[2:0]$591 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$327_EN[2:0]$591 [0] } Consolidated identical input bits for $mux cell $procmux$9491: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN[2:0]$1105, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN[2:0]$594 New ports: A=$procmux$8384_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN[2:0]$594 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN[2:0]$594 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN[2:0]$594 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$329_EN[2:0]$594 [0] } Consolidated identical input bits for $mux cell $procmux$9482: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN[2:0]$1108, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN[2:0]$597 New ports: A=$procmux$8366_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN[2:0]$597 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN[2:0]$597 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN[2:0]$597 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$331_EN[2:0]$597 [0] } Consolidated identical input bits for $mux cell $procmux$9212: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN[2:0]$1198, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN[2:0]$687 New ports: A=$procmux$7826_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN[2:0]$687 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN[2:0]$687 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN[2:0]$687 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$391_EN[2:0]$687 [0] } Consolidated identical input bits for $mux cell $procmux$9473: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN[2:0]$1111, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN[2:0]$600 New ports: A=$procmux$8348_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN[2:0]$600 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN[2:0]$600 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN[2:0]$600 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$333_EN[2:0]$600 [0] } Consolidated identical input bits for $mux cell $procmux$9464: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN[2:0]$1114, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN[2:0]$603 New ports: A=$procmux$8330_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN[2:0]$603 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN[2:0]$603 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN[2:0]$603 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$335_EN[2:0]$603 [0] } Consolidated identical input bits for $mux cell $procmux$9203: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN[2:0]$1201, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN[2:0]$690 New ports: A=$procmux$7808_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN[2:0]$690 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN[2:0]$690 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN[2:0]$690 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$393_EN[2:0]$690 [0] } Consolidated identical input bits for $mux cell $procmux$9455: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN[2:0]$1117, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN[2:0]$606 New ports: A=$procmux$8312_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN[2:0]$606 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN[2:0]$606 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN[2:0]$606 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$337_EN[2:0]$606 [0] } Consolidated identical input bits for $mux cell $procmux$9446: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN[2:0]$1120, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN[2:0]$609 New ports: A=$procmux$8294_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN[2:0]$609 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN[2:0]$609 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN[2:0]$609 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$339_EN[2:0]$609 [0] } Consolidated identical input bits for $mux cell $procmux$9194: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$1204, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$693 New ports: A=$procmux$7790_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$693 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$693 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$693 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$395_EN[2:0]$693 [0] } Consolidated identical input bits for $mux cell $procmux$9437: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN[2:0]$1123, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN[2:0]$612 New ports: A=$procmux$8276_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN[2:0]$612 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN[2:0]$612 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN[2:0]$612 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$341_EN[2:0]$612 [0] } Consolidated identical input bits for $mux cell $procmux$9428: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN[2:0]$1126, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN[2:0]$615 New ports: A=$procmux$8258_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN[2:0]$615 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN[2:0]$615 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN[2:0]$615 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$343_EN[2:0]$615 [0] } Consolidated identical input bits for $mux cell $procmux$9419: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN[2:0]$1129, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN[2:0]$618 New ports: A=$procmux$8240_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN[2:0]$618 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN[2:0]$618 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN[2:0]$618 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$345_EN[2:0]$618 [0] } Consolidated identical input bits for $mux cell $procmux$9185: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$1207, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$696 New ports: A=$procmux$7772_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$696 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$696 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$696 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$397_EN[2:0]$696 [0] } Consolidated identical input bits for $mux cell $procmux$9410: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN[2:0]$1132, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN[2:0]$621 New ports: A=$procmux$8222_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN[2:0]$621 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN[2:0]$621 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN[2:0]$621 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$347_EN[2:0]$621 [0] } Consolidated identical input bits for $mux cell $procmux$9401: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN[2:0]$1135, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN[2:0]$624 New ports: A=$procmux$8204_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN[2:0]$624 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN[2:0]$624 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN[2:0]$624 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$349_EN[2:0]$624 [0] } Consolidated identical input bits for $mux cell $procmux$9176: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$1210, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$699 New ports: A=$procmux$7754_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$699 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$699 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$699 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$399_EN[2:0]$699 [0] } Consolidated identical input bits for $mux cell $procmux$9392: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN[2:0]$1138, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN[2:0]$627 New ports: A=$procmux$8186_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN[2:0]$627 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN[2:0]$627 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN[2:0]$627 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$351_EN[2:0]$627 [0] } Consolidated identical input bits for $mux cell $procmux$9383: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN[2:0]$1141, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN[2:0]$630 New ports: A=$procmux$8168_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN[2:0]$630 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN[2:0]$630 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN[2:0]$630 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$353_EN[2:0]$630 [0] } Consolidated identical input bits for $mux cell $procmux$9167: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$1213, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$702 New ports: A=$procmux$7736_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$702 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$702 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$702 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$401_EN[2:0]$702 [0] } Consolidated identical input bits for $mux cell $procmux$9374: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN[2:0]$1144, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN[2:0]$633 New ports: A=$procmux$8150_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN[2:0]$633 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN[2:0]$633 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN[2:0]$633 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$355_EN[2:0]$633 [0] } Consolidated identical input bits for $mux cell $procmux$9365: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN[2:0]$1147, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN[2:0]$636 New ports: A=$procmux$8132_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN[2:0]$636 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN[2:0]$636 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN[2:0]$636 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$357_EN[2:0]$636 [0] } Consolidated identical input bits for $mux cell $procmux$9356: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN[2:0]$1150, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN[2:0]$639 New ports: A=$procmux$8114_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN[2:0]$639 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN[2:0]$639 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN[2:0]$639 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$359_EN[2:0]$639 [0] } Consolidated identical input bits for $mux cell $procmux$9158: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$1216, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$705 New ports: A=$procmux$7718_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$705 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$705 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$705 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$403_EN[2:0]$705 [0] } Consolidated identical input bits for $mux cell $procmux$9347: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN[2:0]$1153, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN[2:0]$642 New ports: A=$procmux$8096_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN[2:0]$642 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN[2:0]$642 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN[2:0]$642 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$361_EN[2:0]$642 [0] } Consolidated identical input bits for $mux cell $procmux$9338: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN[2:0]$1156, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN[2:0]$645 New ports: A=$procmux$8078_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN[2:0]$645 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN[2:0]$645 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN[2:0]$645 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$363_EN[2:0]$645 [0] } Consolidated identical input bits for $mux cell $procmux$9149: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$1219, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$708 New ports: A=$procmux$7700_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$708 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$708 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$708 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$405_EN[2:0]$708 [0] } Consolidated identical input bits for $mux cell $procmux$9329: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN[2:0]$1159, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN[2:0]$648 New ports: A=$procmux$8060_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN[2:0]$648 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN[2:0]$648 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN[2:0]$648 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$365_EN[2:0]$648 [0] } Consolidated identical input bits for $mux cell $procmux$9320: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN[2:0]$1162, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN[2:0]$651 New ports: A=$procmux$8042_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN[2:0]$651 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN[2:0]$651 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN[2:0]$651 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$367_EN[2:0]$651 [0] } Consolidated identical input bits for $mux cell $procmux$9140: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$1222, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$711 New ports: A=$procmux$7682_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$711 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$711 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$711 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$407_EN[2:0]$711 [0] } Consolidated identical input bits for $mux cell $procmux$9311: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN[2:0]$1165, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN[2:0]$654 New ports: A=$procmux$8024_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN[2:0]$654 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN[2:0]$654 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN[2:0]$654 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$369_EN[2:0]$654 [0] } Consolidated identical input bits for $mux cell $procmux$9302: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN[2:0]$1168, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN[2:0]$657 New ports: A=$procmux$8006_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN[2:0]$657 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN[2:0]$657 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN[2:0]$657 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$371_EN[2:0]$657 [0] } Consolidated identical input bits for $mux cell $procmux$9293: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN[2:0]$1171, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN[2:0]$660 New ports: A=$procmux$7988_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN[2:0]$660 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN[2:0]$660 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN[2:0]$660 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$373_EN[2:0]$660 [0] } Consolidated identical input bits for $mux cell $procmux$9131: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$1225, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$714 New ports: A=$procmux$7664_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$714 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$714 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$714 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$409_EN[2:0]$714 [0] } Consolidated identical input bits for $mux cell $procmux$9284: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN[2:0]$1174, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN[2:0]$663 New ports: A=$procmux$7970_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN[2:0]$663 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN[2:0]$663 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN[2:0]$663 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$375_EN[2:0]$663 [0] } Consolidated identical input bits for $mux cell $procmux$9275: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN[2:0]$1177, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN[2:0]$666 New ports: A=$procmux$7952_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN[2:0]$666 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN[2:0]$666 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN[2:0]$666 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$377_EN[2:0]$666 [0] } Consolidated identical input bits for $mux cell $procmux$9122: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$1228, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$717 New ports: A=$procmux$7640_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$717 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$717 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$717 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$411_EN[2:0]$717 [0] } Consolidated identical input bits for $mux cell $procmux$9662: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN[2:0]$1048, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN[2:0]$537 New ports: A=$procmux$8726_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN[2:0]$537 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN[2:0]$537 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN[2:0]$537 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$291_EN[2:0]$537 [0] } Consolidated identical input bits for $mux cell $procmux$9266: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN[2:0]$1180, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN[2:0]$669 New ports: A=$procmux$7934_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN[2:0]$669 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN[2:0]$669 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN[2:0]$669 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$379_EN[2:0]$669 [0] } Consolidated identical input bits for $mux cell $procmux$9653: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN[2:0]$1051, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN[2:0]$540 New ports: A=$procmux$8708_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN[2:0]$540 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN[2:0]$540 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN[2:0]$540 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$293_EN[2:0]$540 [0] } Consolidated identical input bits for $mux cell $procmux$9644: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN[2:0]$1054, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN[2:0]$543 New ports: A=$procmux$8690_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN[2:0]$543 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN[2:0]$543 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN[2:0]$543 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$295_EN[2:0]$543 [0] } Consolidated identical input bits for $mux cell $procmux$9635: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN[2:0]$1057, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN[2:0]$546 New ports: A=$procmux$8672_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN[2:0]$546 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN[2:0]$546 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN[2:0]$546 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$297_EN[2:0]$546 [0] } Consolidated identical input bits for $mux cell $procmux$9626: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN[2:0]$1060, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN[2:0]$549 New ports: A=$procmux$8654_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN[2:0]$549 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN[2:0]$549 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN[2:0]$549 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$299_EN[2:0]$549 [0] } Consolidated identical input bits for $mux cell $procmux$9617: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN[2:0]$1063, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN[2:0]$552 New ports: A=$procmux$8636_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN[2:0]$552 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN[2:0]$552 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN[2:0]$552 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$301_EN[2:0]$552 [0] } Consolidated identical input bits for $mux cell $procmux$9608: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN[2:0]$1066, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN[2:0]$555 New ports: A=$procmux$8618_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN[2:0]$555 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN[2:0]$555 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN[2:0]$555 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$303_EN[2:0]$555 [0] } Consolidated identical input bits for $mux cell $procmux$9599: Old ports: A=$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN[2:0]$1069, B=3'000, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN[2:0]$558 New ports: A=$procmux$8600_Y [0], B=1'0, Y=$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN[2:0]$558 [0] New connections: $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN[2:0]$558 [2:1] = { $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN[2:0]$558 [0] $0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$305_EN[2:0]$558 [0] } Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $procmux$9110: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$1232, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$721 New ports: A=$procmux$7616_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$721 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$721 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$414_EN[1:0]$721 [0] Consolidated identical input bits for $mux cell $procmux$9101: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$1235, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$724 New ports: A=$procmux$7598_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$724 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$724 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$416_EN[1:0]$724 [0] Consolidated identical input bits for $mux cell $procmux$9596: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN[1:0]$1070, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN[1:0]$559 New ports: A=$procmux$8594_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN[1:0]$559 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN[1:0]$559 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$306_EN[1:0]$559 [0] Consolidated identical input bits for $mux cell $procmux$9587: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN[1:0]$1073, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN[1:0]$562 New ports: A=$procmux$8576_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN[1:0]$562 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN[1:0]$562 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$308_EN[1:0]$562 [0] Consolidated identical input bits for $mux cell $procmux$9254: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN[1:0]$1184, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN[1:0]$673 New ports: A=$procmux$7910_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN[1:0]$673 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN[1:0]$673 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$382_EN[1:0]$673 [0] Consolidated identical input bits for $mux cell $procmux$9578: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN[1:0]$1076, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN[1:0]$565 New ports: A=$procmux$8558_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN[1:0]$565 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN[1:0]$565 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$310_EN[1:0]$565 [0] Consolidated identical input bits for $mux cell $procmux$9569: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN[1:0]$1079, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN[1:0]$568 New ports: A=$procmux$8540_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN[1:0]$568 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN[1:0]$568 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$312_EN[1:0]$568 [0] Consolidated identical input bits for $mux cell $procmux$9560: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN[1:0]$1082, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN[1:0]$571 New ports: A=$procmux$8522_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN[1:0]$571 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN[1:0]$571 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$314_EN[1:0]$571 [0] Consolidated identical input bits for $mux cell $procmux$9245: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN[1:0]$1187, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN[1:0]$676 New ports: A=$procmux$7892_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN[1:0]$676 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN[1:0]$676 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$384_EN[1:0]$676 [0] Consolidated identical input bits for $mux cell $procmux$9551: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN[1:0]$1085, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN[1:0]$574 New ports: A=$procmux$8504_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN[1:0]$574 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN[1:0]$574 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$316_EN[1:0]$574 [0] Consolidated identical input bits for $mux cell $procmux$9542: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN[1:0]$1088, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN[1:0]$577 New ports: A=$procmux$8486_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN[1:0]$577 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN[1:0]$577 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$318_EN[1:0]$577 [0] Consolidated identical input bits for $mux cell $procmux$9236: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN[1:0]$1190, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN[1:0]$679 New ports: A=$procmux$7874_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN[1:0]$679 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN[1:0]$679 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$386_EN[1:0]$679 [0] Consolidated identical input bits for $mux cell $procmux$9533: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN[1:0]$1091, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN[1:0]$580 New ports: A=$procmux$8468_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN[1:0]$580 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN[1:0]$580 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$320_EN[1:0]$580 [0] Consolidated identical input bits for $mux cell $procmux$9524: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN[1:0]$1094, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN[1:0]$583 New ports: A=$procmux$8450_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN[1:0]$583 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN[1:0]$583 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$322_EN[1:0]$583 [0] Consolidated identical input bits for $mux cell $procmux$9227: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN[1:0]$1193, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN[1:0]$682 New ports: A=$procmux$7856_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN[1:0]$682 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN[1:0]$682 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$388_EN[1:0]$682 [0] Consolidated identical input bits for $mux cell $procmux$9515: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN[1:0]$1097, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN[1:0]$586 New ports: A=$procmux$8432_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN[1:0]$586 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN[1:0]$586 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$324_EN[1:0]$586 [0] Consolidated identical input bits for $mux cell $procmux$9506: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN[1:0]$1100, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN[1:0]$589 New ports: A=$procmux$8414_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN[1:0]$589 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN[1:0]$589 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$326_EN[1:0]$589 [0] Consolidated identical input bits for $mux cell $procmux$9497: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN[1:0]$1103, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN[1:0]$592 New ports: A=$procmux$8396_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN[1:0]$592 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN[1:0]$592 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$328_EN[1:0]$592 [0] Consolidated identical input bits for $mux cell $procmux$9218: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN[1:0]$1196, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN[1:0]$685 New ports: A=$procmux$7838_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN[1:0]$685 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN[1:0]$685 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$390_EN[1:0]$685 [0] Consolidated identical input bits for $mux cell $procmux$9488: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN[1:0]$1106, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN[1:0]$595 New ports: A=$procmux$8378_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN[1:0]$595 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN[1:0]$595 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$330_EN[1:0]$595 [0] Consolidated identical input bits for $mux cell $procmux$9479: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN[1:0]$1109, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN[1:0]$598 New ports: A=$procmux$8360_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN[1:0]$598 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN[1:0]$598 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$332_EN[1:0]$598 [0] Consolidated identical input bits for $mux cell $procmux$9209: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN[1:0]$1199, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN[1:0]$688 New ports: A=$procmux$7820_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN[1:0]$688 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN[1:0]$688 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$392_EN[1:0]$688 [0] Consolidated identical input bits for $mux cell $procmux$9470: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN[1:0]$1112, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN[1:0]$601 New ports: A=$procmux$8342_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN[1:0]$601 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN[1:0]$601 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$334_EN[1:0]$601 [0] Consolidated identical input bits for $mux cell $procmux$9461: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN[1:0]$1115, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN[1:0]$604 New ports: A=$procmux$8324_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN[1:0]$604 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN[1:0]$604 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$336_EN[1:0]$604 [0] Consolidated identical input bits for $mux cell $procmux$9200: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$1202, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$691 New ports: A=$procmux$7802_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$691 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$691 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$394_EN[1:0]$691 [0] Consolidated identical input bits for $mux cell $procmux$9452: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN[1:0]$1118, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN[1:0]$607 New ports: A=$procmux$8306_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN[1:0]$607 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN[1:0]$607 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$338_EN[1:0]$607 [0] Consolidated identical input bits for $mux cell $procmux$9443: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN[1:0]$1121, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN[1:0]$610 New ports: A=$procmux$8288_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN[1:0]$610 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN[1:0]$610 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$340_EN[1:0]$610 [0] Consolidated identical input bits for $mux cell $procmux$9434: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN[1:0]$1124, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN[1:0]$613 New ports: A=$procmux$8270_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN[1:0]$613 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN[1:0]$613 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$342_EN[1:0]$613 [0] Consolidated identical input bits for $mux cell $procmux$9191: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$1205, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$694 New ports: A=$procmux$7784_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$694 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$694 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$396_EN[1:0]$694 [0] Consolidated identical input bits for $mux cell $procmux$9425: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN[1:0]$1127, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN[1:0]$616 New ports: A=$procmux$8252_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN[1:0]$616 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN[1:0]$616 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$344_EN[1:0]$616 [0] Consolidated identical input bits for $mux cell $procmux$9416: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN[1:0]$1130, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN[1:0]$619 New ports: A=$procmux$8234_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN[1:0]$619 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN[1:0]$619 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$346_EN[1:0]$619 [0] Consolidated identical input bits for $mux cell $procmux$9182: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$1208, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$697 New ports: A=$procmux$7766_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$697 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$697 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$398_EN[1:0]$697 [0] Consolidated identical input bits for $mux cell $procmux$9407: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN[1:0]$1133, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN[1:0]$622 New ports: A=$procmux$8216_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN[1:0]$622 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN[1:0]$622 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$348_EN[1:0]$622 [0] Consolidated identical input bits for $mux cell $procmux$9398: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN[1:0]$1136, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN[1:0]$625 New ports: A=$procmux$8198_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN[1:0]$625 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN[1:0]$625 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$350_EN[1:0]$625 [0] Consolidated identical input bits for $mux cell $procmux$9173: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$1211, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$700 New ports: A=$procmux$7748_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$700 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$700 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$400_EN[1:0]$700 [0] Consolidated identical input bits for $mux cell $procmux$9389: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN[1:0]$1139, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN[1:0]$628 New ports: A=$procmux$8180_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN[1:0]$628 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN[1:0]$628 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$352_EN[1:0]$628 [0] Consolidated identical input bits for $mux cell $procmux$9380: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN[1:0]$1142, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN[1:0]$631 New ports: A=$procmux$8162_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN[1:0]$631 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN[1:0]$631 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$354_EN[1:0]$631 [0] Consolidated identical input bits for $mux cell $procmux$9371: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN[1:0]$1145, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN[1:0]$634 New ports: A=$procmux$8144_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN[1:0]$634 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN[1:0]$634 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$356_EN[1:0]$634 [0] Consolidated identical input bits for $mux cell $procmux$9164: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$1214, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$703 New ports: A=$procmux$7730_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$703 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$703 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$402_EN[1:0]$703 [0] Consolidated identical input bits for $mux cell $procmux$9362: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN[1:0]$1148, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN[1:0]$637 New ports: A=$procmux$8126_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN[1:0]$637 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN[1:0]$637 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$358_EN[1:0]$637 [0] Consolidated identical input bits for $mux cell $procmux$9353: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN[1:0]$1151, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN[1:0]$640 New ports: A=$procmux$8108_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN[1:0]$640 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN[1:0]$640 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$360_EN[1:0]$640 [0] Consolidated identical input bits for $mux cell $procmux$9155: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$1217, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$706 New ports: A=$procmux$7712_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$706 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$706 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$404_EN[1:0]$706 [0] Consolidated identical input bits for $mux cell $procmux$9344: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN[1:0]$1154, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN[1:0]$643 New ports: A=$procmux$8090_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN[1:0]$643 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN[1:0]$643 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$362_EN[1:0]$643 [0] Consolidated identical input bits for $mux cell $procmux$9335: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN[1:0]$1157, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN[1:0]$646 New ports: A=$procmux$8072_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN[1:0]$646 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN[1:0]$646 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$364_EN[1:0]$646 [0] Consolidated identical input bits for $mux cell $procmux$9146: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$1220, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$709 New ports: A=$procmux$7694_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$709 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$709 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$406_EN[1:0]$709 [0] Consolidated identical input bits for $mux cell $procmux$9326: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN[1:0]$1160, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN[1:0]$649 New ports: A=$procmux$8054_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN[1:0]$649 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN[1:0]$649 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$366_EN[1:0]$649 [0] Consolidated identical input bits for $mux cell $procmux$9317: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN[1:0]$1163, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN[1:0]$652 New ports: A=$procmux$8036_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN[1:0]$652 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN[1:0]$652 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$368_EN[1:0]$652 [0] Consolidated identical input bits for $mux cell $procmux$9308: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN[1:0]$1166, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN[1:0]$655 New ports: A=$procmux$8018_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN[1:0]$655 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN[1:0]$655 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$370_EN[1:0]$655 [0] Consolidated identical input bits for $mux cell $procmux$9137: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$1223, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$712 New ports: A=$procmux$7676_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$712 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$712 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$408_EN[1:0]$712 [0] Consolidated identical input bits for $mux cell $procmux$9299: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN[1:0]$1169, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN[1:0]$658 New ports: A=$procmux$8000_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN[1:0]$658 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN[1:0]$658 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$372_EN[1:0]$658 [0] Consolidated identical input bits for $mux cell $procmux$9290: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN[1:0]$1172, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN[1:0]$661 New ports: A=$procmux$7982_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN[1:0]$661 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN[1:0]$661 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$374_EN[1:0]$661 [0] Consolidated identical input bits for $mux cell $procmux$9128: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$1226, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$715 New ports: A=$procmux$7652_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$715 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$715 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$410_EN[1:0]$715 [0] Consolidated identical input bits for $mux cell $procmux$9281: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN[1:0]$1175, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN[1:0]$664 New ports: A=$procmux$7964_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN[1:0]$664 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN[1:0]$664 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$376_EN[1:0]$664 [0] Consolidated identical input bits for $mux cell $procmux$9272: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN[1:0]$1178, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN[1:0]$667 New ports: A=$procmux$7946_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN[1:0]$667 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN[1:0]$667 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$378_EN[1:0]$667 [0] Consolidated identical input bits for $mux cell $procmux$9668: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$1046, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$535 New ports: A=$procmux$8738_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$535 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$535 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$290_EN[1:0]$535 [0] Consolidated identical input bits for $mux cell $procmux$9659: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN[1:0]$1049, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN[1:0]$538 New ports: A=$procmux$8720_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN[1:0]$538 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN[1:0]$538 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$292_EN[1:0]$538 [0] Consolidated identical input bits for $mux cell $procmux$9119: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$1229, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$718 New ports: A=$procmux$7634_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$718 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$718 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$412_EN[1:0]$718 [0] Consolidated identical input bits for $mux cell $procmux$9263: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN[1:0]$1181, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN[1:0]$670 New ports: A=$procmux$7928_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN[1:0]$670 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN[1:0]$670 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$380_EN[1:0]$670 [0] Consolidated identical input bits for $mux cell $procmux$9650: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN[1:0]$1052, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN[1:0]$541 New ports: A=$procmux$8702_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN[1:0]$541 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN[1:0]$541 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$294_EN[1:0]$541 [0] Consolidated identical input bits for $mux cell $procmux$9641: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN[1:0]$1055, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN[1:0]$544 New ports: A=$procmux$8684_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN[1:0]$544 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN[1:0]$544 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$296_EN[1:0]$544 [0] Consolidated identical input bits for $mux cell $procmux$9632: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN[1:0]$1058, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN[1:0]$547 New ports: A=$procmux$8666_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN[1:0]$547 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN[1:0]$547 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$298_EN[1:0]$547 [0] Consolidated identical input bits for $mux cell $procmux$9623: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN[1:0]$1061, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN[1:0]$550 New ports: A=$procmux$8648_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN[1:0]$550 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN[1:0]$550 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$300_EN[1:0]$550 [0] Consolidated identical input bits for $mux cell $procmux$9614: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN[1:0]$1064, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN[1:0]$553 New ports: A=$procmux$8630_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN[1:0]$553 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN[1:0]$553 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$302_EN[1:0]$553 [0] Consolidated identical input bits for $mux cell $procmux$9605: Old ports: A=$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN[1:0]$1067, B=2'00, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN[1:0]$556 New ports: A=$procmux$8612_Y [0], B=1'0, Y=$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN[1:0]$556 [0] New connections: $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN[1:0]$556 [1] = $0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$304_EN[1:0]$556 [0] Optimizing cells in module \dependency_manager. Performed a total of 648 changes. 2.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1575 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 1464 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 1448 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 127 cells. 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 1969 unused wires. 2.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.13.9. Rerunning OPT passes. (Maybe there is more to do..) 2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1448 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.13.13. Executing OPT_DFF pass (perform DFF optimizations). 2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. 2.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.13.16. Finished fast OPT passes. (There is nothing left to do.) 2.14. Executing FSM pass (extract and optimize FSM). 2.14.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking dependency_manager.ready_node_id as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. 2.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. 2.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.15. Executing OPT pass (performing simple optimizations). 2.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1448 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1448 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.15.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$9913 ($dff) from module dependency_manager (D = $procmux$9809_Y, Q = \ready_valid, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$10383 ($sdff) from module dependency_manager (D = 1'1, Q = \ready_valid). Adding EN signal on $procdff$9914 ($dff) from module dependency_manager (D = \first_ready_idx, Q = \ready_node_id). Adding EN signal on $procdff$9915 ($dff) from module dependency_manager (D = $memrd$\node_x_base$hardware/v2/rtl/dependency_manager.v:184$2427_DATA, Q = \ready_x_base). Adding EN signal on $procdff$9916 ($dff) from module dependency_manager (D = $memrd$\node_w_base$hardware/v2/rtl/dependency_manager.v:185$2428_DATA, Q = \ready_w_base). Adding EN signal on $procdff$9917 ($dff) from module dependency_manager (D = $memrd$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:186$2429_DATA, Q = \ready_n_tiles). Adding EN signal on $procdff$9918 ($dff) from module dependency_manager (D = $memrd$\node_result_addr$hardware/v2/rtl/dependency_manager.v:187$2430_DATA, Q = \ready_result_addr). 2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 18 unused cells and 18 unused wires. 2.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.15.9. Rerunning OPT passes. (Maybe there is more to do..) 2.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1446 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 1438 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 1434 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 12 cells. 2.15.13. Executing OPT_DFF pass (perform DFF optimizations). 2.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 12 unused wires. 2.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.15.16. Rerunning OPT passes. (Maybe there is more to do..) 2.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.15.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1434 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.15.20. Executing OPT_DFF pass (perform DFF optimizations). 2.15.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. 2.15.22. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.15.23. Finished fast OPT passes. (There is nothing left to do.) 2.16. Executing WREDUCE pass (reducing word size of cells). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10360 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10361 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10362 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10324 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10325 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10363 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10364 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10365 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10345 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10346 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10347 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10328 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10329 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10333 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10334 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10335 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10326 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10366 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10367 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10368 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10327 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10348 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10349 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10350 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10357 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10358 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10359 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10369 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10370 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10371 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10336 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10337 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10338 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10351 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10352 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10353 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10323 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10372 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10373 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10374 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10375 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10376 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10377 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10354 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10355 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10356 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10339 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10340 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10341 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$2420 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$2417 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10195 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2409 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10196 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10197 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10198 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10199 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2394 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10200 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10201 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10202 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10203 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2379 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10204 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10205 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10206 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10207 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2364 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10208 (node_required). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$2348 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$2346 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$2343 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10209 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2335 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10210 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10211 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10212 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10213 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2320 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10214 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10215 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10216 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10217 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2305 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10218 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10219 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10220 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10221 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2290 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10222 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$2274 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$2272 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$2269 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10223 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2261 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10224 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10225 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10226 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10227 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2246 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10228 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10229 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10230 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10231 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2231 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10232 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10233 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10234 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10235 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2216 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10236 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$2200 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$2198 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$2195 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10237 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2187 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10238 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10239 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10240 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10241 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2172 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10242 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2157 (node_producer_ids). Removed top 26 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10249 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2142 (node_producer_ids). Removed top 26 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10250 (node_producer_ids). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$2126 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$2124 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$2121 (node_required). Removed top 26 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10251 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2113 (node_producer_ids). Removed top 26 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10252 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10254 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10255 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2098 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10256 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10257 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10258 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10259 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2083 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10260 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10261 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10262 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10263 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2068 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10264 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$2052 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$2050 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$2047 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10265 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2039 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10266 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10267 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10268 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10269 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2024 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10270 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10271 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10272 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10273 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$2009 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10274 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10275 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10276 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10277 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1994 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10278 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1978 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1976 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1973 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10279 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1965 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10280 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10281 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10282 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10283 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1950 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10284 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10285 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10286 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10287 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1935 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10288 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10289 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10290 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10291 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1920 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10292 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1904 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1902 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1899 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10293 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1891 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10294 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10295 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10296 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10297 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1876 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10298 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10299 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10300 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10301 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1861 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10302 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10303 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10304 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10305 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1846 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10306 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1830 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1828 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1825 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10307 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1817 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10308 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10309 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10310 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10311 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1802 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10312 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10313 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10314 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10315 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1787 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10316 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10317 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10318 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10319 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1772 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10320 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1756 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1754 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1751 (node_required). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10321 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1743 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1728 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1713 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1698 (node_producer_ids). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1682 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1680 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1677 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1669 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1654 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1639 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1624 (node_producer_ids). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1608 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1606 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1603 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1595 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1580 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1565 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10331 (node_resolved). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1550 (node_producer_ids). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1534 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1532 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1529 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1521 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10332 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1506 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10342 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1491 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10343 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10344 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1476 (node_producer_ids). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1460 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1458 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1455 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1447 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10322 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1432 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1417 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1402 (node_producer_ids). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1386 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1384 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1381 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1373 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1358 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1343 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1328 (node_producer_ids). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1312 (node_state). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$1310 (node_resolved). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$1307 (node_required). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1299 (node_producer_ids). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10330 (node_state). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1284 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1269 (node_producer_ids). Removed top 26 address bits (of 32) from memory read port dependency_manager.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$1254 (node_producer_ids). Removed top 28 address bits (of 32) from memory read port dependency_manager.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$1238 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10379 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10380 (node_state). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10381 (node_resolved). Removed top 28 address bits (of 32) from memory init port dependency_manager.$auto$proc_memwr.cc:45:proc_memwr$10378 (node_state). Removed top 26 bits (of 32) from port A of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1039 ($add). Removed top 31 bits (of 32) from port B of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1039 ($add). Removed top 25 bits (of 32) from port Y of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1039 ($add). Removed top 26 bits (of 32) from port A of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1041 ($add). Removed top 30 bits (of 32) from port B of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1041 ($add). Removed top 25 bits (of 32) from port Y of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1041 ($add). Removed top 26 bits (of 32) from port A of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1043 ($add). Removed top 30 bits (of 32) from port B of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1043 ($add). Removed top 25 bits (of 32) from port Y of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1043 ($add). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1239 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1253 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1268 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1283 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1298 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1313 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1327 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1342 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1357 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1372 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1387 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1401 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1416 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1431 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1446 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1461 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1475 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1490 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1505 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1520 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1535 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1549 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1564 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1579 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1594 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1609 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1623 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1638 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1653 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1668 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1683 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1697 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1712 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1727 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1742 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1757 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1771 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1786 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1801 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1816 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1831 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1845 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1860 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1875 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1890 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1905 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1919 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1934 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1949 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1964 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$1979 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$1993 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2008 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2023 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2038 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$2053 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2067 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2082 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2097 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2112 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$2127 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2141 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2156 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2171 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2186 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$2201 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2215 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2230 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2245 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2260 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$2275 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2289 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2304 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2319 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2334 ($lt). Removed top 1 bits (of 2) from port B of cell dependency_manager.$eq$hardware/v2/rtl/dependency_manager.v:148$2349 ($eq). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2363 ($lt). Removed top 31 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2378 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2393 ($lt). Removed top 30 bits (of 32) from port A of cell dependency_manager.$lt$hardware/v2/rtl/dependency_manager.v:150$2408 ($lt). Removed top 26 bits (of 32) from mux cell dependency_manager.$procmux$9686 ($mux). Removed top 26 bits (of 32) from mux cell dependency_manager.$procmux$9695 ($mux). Removed top 26 bits (of 32) from mux cell dependency_manager.$procmux$9704 ($mux). Removed top 26 bits (of 32) from mux cell dependency_manager.$procmux$9713 ($mux). Removed top 26 bits (of 32) from mux cell dependency_manager.$procmux$8780 ($mux). Removed top 26 bits (of 32) from mux cell dependency_manager.$procmux$8798 ($mux). Removed top 26 bits (of 32) from mux cell dependency_manager.$procmux$8816 ($mux). Removed top 26 bits (of 32) from mux cell dependency_manager.$procmux$8834 ($mux). Removed top 1 bits (of 7) from port Y of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1039 ($add). Removed top 1 bits (of 7) from port Y of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1041 ($add). Removed top 1 bits (of 7) from port Y of cell dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1043 ($add). Removed top 26 bits (of 32) from wire dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1043_Y. Removed top 26 bits (of 32) from wire dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1041_Y. Removed top 26 bits (of 32) from wire dependency_manager.$add$hardware/v2/rtl/dependency_manager.v:136$1039_Y. Removed top 26 bits (of 32) from wire dependency_manager.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_ADDR[31:0]$1030. Removed top 26 bits (of 32) from wire dependency_manager.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_ADDR[31:0]$1027. Removed top 26 bits (of 32) from wire dependency_manager.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_ADDR[31:0]$1024. Removed top 26 bits (of 32) from wire dependency_manager.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_ADDR[31:0]$1021. Removed top 26 bits (of 32) from wire dependency_manager.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$288_ADDR[31:0]$529. Removed top 26 bits (of 32) from wire dependency_manager.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$287_ADDR[31:0]$526. Removed top 26 bits (of 32) from wire dependency_manager.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$286_ADDR[31:0]$523. Removed top 26 bits (of 32) from wire dependency_manager.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$285_ADDR[31:0]$520. 2.17. Executing PEEPOPT pass (run peephole optimizers). 2.18. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 11 unused wires. 2.19. Executing SHARE pass (SAT-based resource sharing). 2.20. Executing TECHMAP pass (map to technology primitives). 2.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.20.2. Continuing TECHMAP pass. Using template $paramod$4a6470414f44d7bfc80a561af8ae86943c9d8e44\_90_lut_cmp_ for cells of type $lt. Using template $paramod$b33ffabab7f76e9eea93de0eb72e92e30b4f65b6\_90_lut_cmp_ for cells of type $lt. Using template $paramod$00b6cfa7627efb096a4db0169df5297bfaf657d7\_90_lut_cmp_ for cells of type $lt. Using template $paramod$21bd1e49a66742dbdaaf45a85521ce9d28e5f3df\_90_lut_cmp_ for cells of type $lt. No more expansions possible. 2.21. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.22. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 192 unused wires. 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 2.23.2. Continuing TECHMAP pass. No more expansions possible. 2.24. Executing TECHMAP pass (map to technology primitives). 2.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 2.24.2. Continuing TECHMAP pass. No more expansions possible. 2.25. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module dependency_manager: creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$2421 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$2347 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$2273 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$2199 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$2125 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$2051 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1977 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1903 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1829 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1755 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1681 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1607 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1533 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1459 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1385 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:154$1311 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:136$1043 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:136$1041 ($add). creating $macc model for $add$hardware/v2/rtl/dependency_manager.v:136$1039 ($add). creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:136$1039. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:136$1041. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:136$1043. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1311. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1385. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1459. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1533. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1607. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1681. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1755. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1829. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1903. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$1977. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$2051. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$2125. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$2199. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$2273. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$2347. creating $alu model for $macc $add$hardware/v2/rtl/dependency_manager.v:154$2421. creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$2418 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$2344 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$2270 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$2196 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$2122 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$2048 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1974 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1900 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1826 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1752 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1678 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1604 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1530 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1456 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1382 ($ge): new $alu creating $alu model for $ge$hardware/v2/rtl/dependency_manager.v:152$1308 ($ge): new $alu creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1308: $auto$alumacc.cc:548:replace_alu$10518 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1382: $auto$alumacc.cc:548:replace_alu$10531 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1456: $auto$alumacc.cc:548:replace_alu$10544 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1530: $auto$alumacc.cc:548:replace_alu$10557 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1604: $auto$alumacc.cc:548:replace_alu$10570 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1678: $auto$alumacc.cc:548:replace_alu$10583 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1752: $auto$alumacc.cc:548:replace_alu$10596 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1826: $auto$alumacc.cc:548:replace_alu$10609 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1900: $auto$alumacc.cc:548:replace_alu$10622 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$1974: $auto$alumacc.cc:548:replace_alu$10635 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$2048: $auto$alumacc.cc:548:replace_alu$10648 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$2122: $auto$alumacc.cc:548:replace_alu$10661 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$2196: $auto$alumacc.cc:548:replace_alu$10674 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$2270: $auto$alumacc.cc:548:replace_alu$10687 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$2344: $auto$alumacc.cc:548:replace_alu$10700 creating $alu cell for $ge$hardware/v2/rtl/dependency_manager.v:152$2418: $auto$alumacc.cc:548:replace_alu$10713 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$2421: $auto$alumacc.cc:548:replace_alu$10726 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$2347: $auto$alumacc.cc:548:replace_alu$10729 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$2273: $auto$alumacc.cc:548:replace_alu$10732 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$2199: $auto$alumacc.cc:548:replace_alu$10735 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$2125: $auto$alumacc.cc:548:replace_alu$10738 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$2051: $auto$alumacc.cc:548:replace_alu$10741 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1977: $auto$alumacc.cc:548:replace_alu$10744 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1903: $auto$alumacc.cc:548:replace_alu$10747 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1829: $auto$alumacc.cc:548:replace_alu$10750 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1755: $auto$alumacc.cc:548:replace_alu$10753 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1681: $auto$alumacc.cc:548:replace_alu$10756 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1607: $auto$alumacc.cc:548:replace_alu$10759 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1533: $auto$alumacc.cc:548:replace_alu$10762 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1459: $auto$alumacc.cc:548:replace_alu$10765 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1385: $auto$alumacc.cc:548:replace_alu$10768 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:154$1311: $auto$alumacc.cc:548:replace_alu$10771 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:136$1043: $auto$alumacc.cc:548:replace_alu$10774 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:136$1041: $auto$alumacc.cc:548:replace_alu$10777 creating $alu cell for $add$hardware/v2/rtl/dependency_manager.v:136$1039: $auto$alumacc.cc:548:replace_alu$10780 created 35 $alu and 0 $macc cells. 2.26. Executing OPT pass (performing simple optimizations). 2.26.1. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.26.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1514 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.26.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1514 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.26.6. Executing OPT_DFF pass (perform DFF optimizations). 2.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 16 unused wires. 2.26.8. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.26.9. Rerunning OPT passes. (Maybe there is more to do..) 2.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.26.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1514 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.26.13. Executing OPT_DFF pass (perform DFF optimizations). 2.26.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. 2.26.15. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.26.16. Finished fast OPT passes. (There is nothing left to do.) 2.27. Executing MEMORY pass. 2.27.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 4206 transformations. 2.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing dependency_manager.node_result_addr write port 0. Analyzing dependency_manager.node_n_tiles write port 0. Analyzing dependency_manager.node_w_base write port 0. Analyzing dependency_manager.node_x_base write port 0. Analyzing dependency_manager.node_producer_ids write port 0. Analyzing dependency_manager.node_producer_ids write port 1. Analyzing dependency_manager.node_producer_ids write port 2. Analyzing dependency_manager.node_producer_ids write port 3. Analyzing dependency_manager.node_resolved write port 0. Analyzing dependency_manager.node_resolved write port 1. Analyzing dependency_manager.node_resolved write port 2. Analyzing dependency_manager.node_resolved write port 3. Analyzing dependency_manager.node_resolved write port 4. Analyzing dependency_manager.node_resolved write port 5. Analyzing dependency_manager.node_resolved write port 6. Analyzing dependency_manager.node_resolved write port 7. Analyzing dependency_manager.node_resolved write port 8. Analyzing dependency_manager.node_resolved write port 9. Analyzing dependency_manager.node_resolved write port 10. Analyzing dependency_manager.node_resolved write port 11. Analyzing dependency_manager.node_resolved write port 12. Analyzing dependency_manager.node_resolved write port 13. Analyzing dependency_manager.node_resolved write port 14. Analyzing dependency_manager.node_resolved write port 15. Analyzing dependency_manager.node_resolved write port 16. Analyzing dependency_manager.node_resolved write port 17. Analyzing dependency_manager.node_resolved write port 18. Analyzing dependency_manager.node_resolved write port 19. Analyzing dependency_manager.node_resolved write port 20. Analyzing dependency_manager.node_resolved write port 21. Analyzing dependency_manager.node_resolved write port 22. Analyzing dependency_manager.node_resolved write port 23. Analyzing dependency_manager.node_resolved write port 24. Analyzing dependency_manager.node_resolved write port 25. Analyzing dependency_manager.node_resolved write port 26. Analyzing dependency_manager.node_resolved write port 27. Analyzing dependency_manager.node_resolved write port 28. Analyzing dependency_manager.node_resolved write port 29. Analyzing dependency_manager.node_resolved write port 30. Analyzing dependency_manager.node_resolved write port 31. Analyzing dependency_manager.node_resolved write port 32. Analyzing dependency_manager.node_resolved write port 33. Analyzing dependency_manager.node_resolved write port 34. Analyzing dependency_manager.node_resolved write port 35. Analyzing dependency_manager.node_resolved write port 36. Analyzing dependency_manager.node_resolved write port 37. Analyzing dependency_manager.node_resolved write port 38. Analyzing dependency_manager.node_resolved write port 39. Analyzing dependency_manager.node_resolved write port 40. Analyzing dependency_manager.node_resolved write port 41. Analyzing dependency_manager.node_resolved write port 42. Analyzing dependency_manager.node_resolved write port 43. Analyzing dependency_manager.node_resolved write port 44. Analyzing dependency_manager.node_resolved write port 45. Analyzing dependency_manager.node_resolved write port 46. Analyzing dependency_manager.node_resolved write port 47. Analyzing dependency_manager.node_resolved write port 48. Analyzing dependency_manager.node_resolved write port 49. Analyzing dependency_manager.node_resolved write port 50. Analyzing dependency_manager.node_resolved write port 51. Analyzing dependency_manager.node_resolved write port 52. Analyzing dependency_manager.node_resolved write port 53. Analyzing dependency_manager.node_resolved write port 54. Analyzing dependency_manager.node_resolved write port 55. Analyzing dependency_manager.node_resolved write port 56. Analyzing dependency_manager.node_resolved write port 57. Analyzing dependency_manager.node_resolved write port 58. Analyzing dependency_manager.node_resolved write port 59. Analyzing dependency_manager.node_resolved write port 60. Analyzing dependency_manager.node_resolved write port 61. Analyzing dependency_manager.node_resolved write port 62. Analyzing dependency_manager.node_resolved write port 63. Analyzing dependency_manager.node_resolved write port 64. Analyzing dependency_manager.node_resolved write port 65. Analyzing dependency_manager.node_resolved write port 66. Analyzing dependency_manager.node_resolved write port 67. Analyzing dependency_manager.node_resolved write port 68. Analyzing dependency_manager.node_resolved write port 69. Analyzing dependency_manager.node_resolved write port 70. Analyzing dependency_manager.node_resolved write port 71. Analyzing dependency_manager.node_resolved write port 72. Analyzing dependency_manager.node_resolved write port 73. Analyzing dependency_manager.node_resolved write port 74. Analyzing dependency_manager.node_resolved write port 75. Analyzing dependency_manager.node_resolved write port 76. Analyzing dependency_manager.node_resolved write port 77. Analyzing dependency_manager.node_resolved write port 78. Analyzing dependency_manager.node_resolved write port 79. Analyzing dependency_manager.node_resolved write port 80. Analyzing dependency_manager.node_required write port 0. Analyzing dependency_manager.node_required write port 1. Analyzing dependency_manager.node_required write port 2. Analyzing dependency_manager.node_required write port 3. Analyzing dependency_manager.node_required write port 4. Analyzing dependency_manager.node_required write port 5. Analyzing dependency_manager.node_required write port 6. Analyzing dependency_manager.node_required write port 7. Analyzing dependency_manager.node_required write port 8. Analyzing dependency_manager.node_required write port 9. Analyzing dependency_manager.node_required write port 10. Analyzing dependency_manager.node_required write port 11. Analyzing dependency_manager.node_required write port 12. Analyzing dependency_manager.node_required write port 13. Analyzing dependency_manager.node_required write port 14. Analyzing dependency_manager.node_required write port 15. Analyzing dependency_manager.node_required write port 16. Analyzing dependency_manager.node_state write port 0. Analyzing dependency_manager.node_state write port 1. Analyzing dependency_manager.node_state write port 2. Analyzing dependency_manager.node_state write port 3. Analyzing dependency_manager.node_state write port 4. Analyzing dependency_manager.node_state write port 5. Analyzing dependency_manager.node_state write port 6. Analyzing dependency_manager.node_state write port 7. Analyzing dependency_manager.node_state write port 8. Analyzing dependency_manager.node_state write port 9. Analyzing dependency_manager.node_state write port 10. Analyzing dependency_manager.node_state write port 11. Analyzing dependency_manager.node_state write port 12. Analyzing dependency_manager.node_state write port 13. Analyzing dependency_manager.node_state write port 14. Analyzing dependency_manager.node_state write port 15. Analyzing dependency_manager.node_state write port 16. Analyzing dependency_manager.node_state write port 17. Analyzing dependency_manager.node_state write port 18. Analyzing dependency_manager.node_state write port 19. Analyzing dependency_manager.node_state write port 20. Analyzing dependency_manager.node_state write port 21. Analyzing dependency_manager.node_state write port 22. Analyzing dependency_manager.node_state write port 23. Analyzing dependency_manager.node_state write port 24. Analyzing dependency_manager.node_state write port 25. Analyzing dependency_manager.node_state write port 26. Analyzing dependency_manager.node_state write port 27. Analyzing dependency_manager.node_state write port 28. Analyzing dependency_manager.node_state write port 29. Analyzing dependency_manager.node_state write port 30. Analyzing dependency_manager.node_state write port 31. Analyzing dependency_manager.node_state write port 32. Analyzing dependency_manager.node_state write port 33. Analyzing dependency_manager.node_state write port 34. Analyzing dependency_manager.node_state write port 35. Analyzing dependency_manager.node_state write port 36. Analyzing dependency_manager.node_state write port 37. Analyzing dependency_manager.node_state write port 38. Analyzing dependency_manager.node_state write port 39. Analyzing dependency_manager.node_state write port 40. Analyzing dependency_manager.node_state write port 41. Analyzing dependency_manager.node_state write port 42. Analyzing dependency_manager.node_state write port 43. Analyzing dependency_manager.node_state write port 44. Analyzing dependency_manager.node_state write port 45. Analyzing dependency_manager.node_state write port 46. Analyzing dependency_manager.node_state write port 47. Analyzing dependency_manager.node_state write port 48. Analyzing dependency_manager.node_state write port 49. Analyzing dependency_manager.node_state write port 50. Analyzing dependency_manager.node_state write port 51. Analyzing dependency_manager.node_state write port 52. Analyzing dependency_manager.node_state write port 53. Analyzing dependency_manager.node_state write port 54. Analyzing dependency_manager.node_state write port 55. Analyzing dependency_manager.node_state write port 56. Analyzing dependency_manager.node_state write port 57. Analyzing dependency_manager.node_state write port 58. Analyzing dependency_manager.node_state write port 59. Analyzing dependency_manager.node_state write port 60. Analyzing dependency_manager.node_state write port 61. Analyzing dependency_manager.node_state write port 62. Analyzing dependency_manager.node_state write port 63. Analyzing dependency_manager.node_state write port 64. Analyzing dependency_manager.node_state write port 65. Analyzing dependency_manager.node_state write port 66. Analyzing dependency_manager.node_state write port 67. Analyzing dependency_manager.node_state write port 68. Analyzing dependency_manager.node_state write port 69. Analyzing dependency_manager.node_state write port 70. Analyzing dependency_manager.node_state write port 71. Analyzing dependency_manager.node_state write port 72. Analyzing dependency_manager.node_state write port 73. Analyzing dependency_manager.node_state write port 74. Analyzing dependency_manager.node_state write port 75. Analyzing dependency_manager.node_state write port 76. Analyzing dependency_manager.node_state write port 77. Analyzing dependency_manager.node_state write port 78. Analyzing dependency_manager.node_state write port 79. Analyzing dependency_manager.node_state write port 80. Analyzing dependency_manager.node_state write port 81. 2.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\node_result_addr'[0] in module `\dependency_manager': merging output FF to cell. Write port 0: non-transparent. Checking read port `\node_n_tiles'[0] in module `\dependency_manager': merging output FF to cell. Write port 0: non-transparent. Checking read port `\node_w_base'[0] in module `\dependency_manager': merging output FF to cell. Write port 0: non-transparent. Checking read port `\node_x_base'[0] in module `\dependency_manager': merging output FF to cell. Write port 0: non-transparent. Checking read port `\node_producer_ids'[0] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[1] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[2] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[3] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[4] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[5] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[6] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[7] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[8] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[9] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[10] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[11] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[12] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[13] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[14] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[15] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[16] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[17] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[18] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[19] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[20] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[21] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[22] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[23] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[24] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[25] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[26] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[27] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[28] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[29] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[30] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[31] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[32] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[33] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[34] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[35] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[36] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[37] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[38] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[39] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[40] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[41] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[42] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[43] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[44] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[45] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[46] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[47] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[48] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[49] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[50] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[51] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[52] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[53] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[54] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[55] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[56] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[57] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[58] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[59] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[60] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[61] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[62] in module `\dependency_manager': no output FF found. Checking read port `\node_producer_ids'[63] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[0] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[1] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[2] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[3] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[4] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[5] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[6] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[7] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[8] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[9] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[10] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[11] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[12] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[13] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[14] in module `\dependency_manager': no output FF found. Checking read port `\node_resolved'[15] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[0] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[1] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[2] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[3] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[4] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[5] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[6] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[7] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[8] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[9] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[10] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[11] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[12] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[13] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[14] in module `\dependency_manager': no output FF found. Checking read port `\node_required'[15] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[0] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[1] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[2] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[3] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[4] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[5] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[6] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[7] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[8] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[9] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[10] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[11] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[12] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[13] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[14] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[15] in module `\dependency_manager': no output FF found. Checking read port `\node_state'[16] in module `\dependency_manager': no output FF found. Checking read port address `\node_producer_ids'[0] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[1] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[2] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[3] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[4] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[5] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[6] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[7] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[8] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[9] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[10] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[11] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[12] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[13] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[14] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[15] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[16] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[17] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[18] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[19] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[20] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[21] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[22] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[23] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[24] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[25] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[26] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[27] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[28] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[29] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[30] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[31] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[32] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[33] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[34] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[35] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[36] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[37] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[38] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[39] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[40] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[41] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[42] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[43] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[44] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[45] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[46] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[47] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[48] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[49] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[50] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[51] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[52] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[53] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[54] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[55] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[56] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[57] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[58] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[59] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[60] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[61] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[62] in module `\dependency_manager': no address FF found. Checking read port address `\node_producer_ids'[63] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[0] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[1] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[2] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[3] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[4] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[5] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[6] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[7] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[8] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[9] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[10] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[11] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[12] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[13] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[14] in module `\dependency_manager': no address FF found. Checking read port address `\node_resolved'[15] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[0] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[1] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[2] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[3] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[4] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[5] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[6] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[7] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[8] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[9] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[10] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[11] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[12] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[13] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[14] in module `\dependency_manager': no address FF found. Checking read port address `\node_required'[15] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[0] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[1] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[2] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[3] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[4] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[5] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[6] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[7] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[8] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[9] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[10] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[11] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[12] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[13] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[14] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[15] in module `\dependency_manager': no address FF found. Checking read port address `\node_state'[16] in module `\dependency_manager': no address FF found. 2.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 4 unused cells and 89 unused wires. 2.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory dependency_manager.node_producer_ids by address: Merging ports 0, 1 (address 6'000000). Merging ports 0, 2 (address 6'000000). Merging ports 0, 3 (address 6'000000). Merging ports 0, 4 (address 6'000000). Merging ports 0, 5 (address 6'000000). Merging ports 0, 6 (address 6'000000). Merging ports 0, 7 (address 6'000000). Merging ports 0, 8 (address 6'000000). Merging ports 0, 9 (address 6'000000). Merging ports 0, 10 (address 6'000000). Merging ports 0, 11 (address 6'000000). Merging ports 0, 12 (address 6'000000). Merging ports 0, 13 (address 6'000000). Merging ports 0, 14 (address 6'000000). Merging ports 0, 15 (address 6'000000). Merging ports 0, 16 (address 6'000000). Merging ports 0, 17 (address 6'000000). Merging ports 0, 18 (address 6'000000). Merging ports 0, 19 (address 6'000000). Merging ports 0, 20 (address 6'000000). Merging ports 0, 21 (address 6'000000). Merging ports 0, 22 (address 6'000000). Merging ports 0, 23 (address 6'000000). Merging ports 0, 24 (address 6'000000). Merging ports 0, 25 (address 6'000000). Merging ports 0, 26 (address 6'000000). Merging ports 0, 27 (address 6'000000). Merging ports 0, 28 (address 6'000000). Merging ports 0, 29 (address 6'000000). Merging ports 0, 30 (address 6'000000). Merging ports 0, 31 (address 6'000000). Merging ports 0, 32 (address 6'000000). Merging ports 34, 35 (address 6'100010). Merging ports 36, 37 (address 6'100100). Merging ports 36, 38 (address 6'100100). Merging ports 36, 39 (address 6'100100). Merging ports 40, 41 (address 6'101000). Merging ports 40, 42 (address 6'101000). Merging ports 40, 43 (address 6'101000). Merging ports 40, 44 (address 6'101000). Merging ports 40, 45 (address 6'101000). Merging ports 40, 46 (address 6'101000). Merging ports 40, 47 (address 6'101000). Merging ports 48, 49 (address 6'110000). Merging ports 48, 50 (address 6'110000). Merging ports 48, 51 (address 6'110000). Merging ports 48, 52 (address 6'110000). Merging ports 48, 53 (address 6'110000). Merging ports 48, 54 (address 6'110000). Merging ports 48, 55 (address 6'110000). Merging ports 48, 56 (address 6'110000). Merging ports 48, 57 (address 6'110000). Merging ports 48, 58 (address 6'110000). Merging ports 48, 59 (address 6'110000). Merging ports 48, 60 (address 6'110000). Merging ports 48, 61 (address 6'110000). Merging ports 48, 62 (address 6'110000). Merging ports 48, 63 (address 6'110000). Consolidating read ports of memory dependency_manager.node_producer_ids by address: Merging ports 1, 2 (address 6'100001). Merging ports 1, 3 (address 6'100000). Merging ports 1, 4 (address 6'100000). Merging ports 1, 5 (address 6'100000). Consolidating read ports of memory dependency_manager.node_producer_ids by address: Consolidating write ports of memory dependency_manager.node_producer_ids by address: Consolidating read ports of memory dependency_manager.node_resolved by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Consolidating read ports of memory dependency_manager.node_resolved by address: Merging ports 1, 2 (address 4'1001). Merging ports 1, 3 (address 4'1000). Consolidating read ports of memory dependency_manager.node_resolved by address: Consolidating write ports of memory dependency_manager.node_resolved by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 9, 49 (address 4'1001). Merging ports 9, 50 (address 4'1000). Merging ports 9, 51 (address 4'1000). Merging ports 9, 52 (address 4'1000). Merging ports 9, 53 (address 4'1000). Merging ports 9, 54 (address 4'1000). Merging ports 9, 55 (address 4'1000). Merging ports 9, 56 (address 4'1000). Merging ports 9, 57 (address 4'1000). Merging ports 9, 58 (address 4'1000). Merging ports 9, 59 (address 4'1000). Merging ports 9, 60 (address 4'1000). Merging ports 9, 61 (address 4'1000). Merging ports 9, 62 (address 4'1000). Merging ports 9, 63 (address 4'1000). Merging ports 9, 64 (address 4'1000). Merging ports 9, 65 (address 4'1000). Merging ports 9, 66 (address 4'1000). Merging ports 9, 67 (address 4'1000). Merging ports 9, 68 (address 4'1000). Merging ports 9, 69 (address 4'1000). Merging ports 9, 70 (address 4'1000). Merging ports 9, 71 (address 4'1000). Merging ports 9, 72 (address 4'1000). Merging ports 9, 73 (address 4'1000). Merging ports 9, 74 (address 4'1000). Merging ports 9, 75 (address 4'1000). Merging ports 9, 76 (address 4'1000). Merging ports 9, 77 (address 4'1000). Merging ports 9, 78 (address 4'1000). Merging ports 9, 79 (address 4'1000). Merging ports 9, 80 (address 4'1000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Merging ports 17, 18 (address 4'0000). Merging ports 17, 19 (address 4'0000). Merging ports 17, 20 (address 4'0000). Merging ports 17, 21 (address 4'0000). Merging ports 17, 22 (address 4'0000). Merging ports 17, 23 (address 4'0000). Merging ports 17, 24 (address 4'0000). Merging ports 17, 25 (address 4'0000). Merging ports 17, 26 (address 4'0000). Merging ports 17, 27 (address 4'0000). Merging ports 17, 28 (address 4'0000). Merging ports 17, 29 (address 4'0000). Merging ports 17, 30 (address 4'0000). Merging ports 17, 31 (address 4'0000). Merging ports 17, 32 (address 4'0000). Merging ports 17, 33 (address 4'0000). Merging ports 17, 34 (address 4'0000). Merging ports 17, 35 (address 4'0000). Merging ports 17, 36 (address 4'0000). Merging ports 17, 37 (address 4'0000). Merging ports 17, 38 (address 4'0000). Merging ports 17, 39 (address 4'0000). Merging ports 17, 40 (address 4'0000). Merging ports 17, 41 (address 4'0000). Merging ports 17, 42 (address 4'0000). Merging ports 17, 43 (address 4'0000). Merging ports 17, 44 (address 4'0000). Merging ports 17, 45 (address 4'0000). Merging ports 17, 46 (address 4'0000). Merging ports 17, 47 (address 4'0000). Merging ports 17, 48 (address 4'0000). Consolidating write ports of memory dependency_manager.node_resolved by address: Merging ports 1, 2 (address 4'1000). Merging ports 1, 3 (address 4'1000). Merging ports 1, 5 (address 4'1000). Consolidating write ports of memory dependency_manager.node_resolved by address: Consolidating read ports of memory dependency_manager.node_required by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Consolidating read ports of memory dependency_manager.node_required by address: Merging ports 1, 2 (address 4'1001). Merging ports 1, 3 (address 4'1000). Consolidating read ports of memory dependency_manager.node_required by address: Consolidating write ports of memory dependency_manager.node_required by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Consolidating write ports of memory dependency_manager.node_required by address: Merging ports 1, 2 (address 4'1001). Merging ports 1, 3 (address 4'1000). Consolidating write ports of memory dependency_manager.node_required by address: Consolidating read ports of memory dependency_manager.node_state by address: Merging ports 1, 2 (address 4'0000). Merging ports 1, 3 (address 4'0000). Merging ports 1, 4 (address 4'0000). Merging ports 1, 5 (address 4'0000). Merging ports 1, 6 (address 4'0000). Merging ports 1, 7 (address 4'0000). Merging ports 1, 8 (address 4'0000). Merging ports 1, 9 (address 4'0000). Merging ports 11, 12 (address 4'1010). Merging ports 13, 14 (address 4'1100). Merging ports 13, 15 (address 4'1100). Merging ports 13, 16 (address 4'1100). Consolidating read ports of memory dependency_manager.node_state by address: Merging ports 2, 3 (address 4'1001). Merging ports 2, 4 (address 4'1000). Consolidating read ports of memory dependency_manager.node_state by address: Consolidating write ports of memory dependency_manager.node_state by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 9, 49 (address 4'1001). Merging ports 9, 50 (address 4'1000). Merging ports 9, 51 (address 4'1000). Merging ports 9, 52 (address 4'1000). Merging ports 9, 53 (address 4'1000). Merging ports 9, 54 (address 4'1000). Merging ports 9, 55 (address 4'1000). Merging ports 9, 56 (address 4'1000). Merging ports 9, 57 (address 4'1000). Merging ports 9, 58 (address 4'1000). Merging ports 9, 59 (address 4'1000). Merging ports 9, 60 (address 4'1000). Merging ports 9, 61 (address 4'1000). Merging ports 9, 62 (address 4'1000). Merging ports 9, 63 (address 4'1000). Merging ports 9, 64 (address 4'1000). Merging ports 9, 65 (address 4'1000). Merging ports 9, 66 (address 4'1000). Merging ports 9, 67 (address 4'1000). Merging ports 9, 68 (address 4'1000). Merging ports 9, 69 (address 4'1000). Merging ports 9, 70 (address 4'1000). Merging ports 9, 71 (address 4'1000). Merging ports 9, 72 (address 4'1000). Merging ports 9, 73 (address 4'1000). Merging ports 9, 74 (address 4'1000). Merging ports 9, 75 (address 4'1000). Merging ports 9, 76 (address 4'1000). Merging ports 9, 77 (address 4'1000). Merging ports 9, 78 (address 4'1000). Merging ports 9, 79 (address 4'1000). Merging ports 9, 80 (address 4'1000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Merging ports 17, 18 (address 4'0000). Merging ports 17, 19 (address 4'0000). Merging ports 17, 20 (address 4'0000). Merging ports 17, 21 (address 4'0000). Merging ports 17, 22 (address 4'0000). Merging ports 17, 23 (address 4'0000). Merging ports 17, 24 (address 4'0000). Merging ports 17, 25 (address 4'0000). Merging ports 17, 26 (address 4'0000). Merging ports 17, 27 (address 4'0000). Merging ports 17, 28 (address 4'0000). Merging ports 17, 29 (address 4'0000). Merging ports 17, 30 (address 4'0000). Merging ports 17, 31 (address 4'0000). Merging ports 17, 32 (address 4'0000). Merging ports 17, 33 (address 4'0000). Merging ports 17, 34 (address 4'0000). Merging ports 17, 35 (address 4'0000). Merging ports 17, 36 (address 4'0000). Merging ports 17, 37 (address 4'0000). Merging ports 17, 38 (address 4'0000). Merging ports 17, 39 (address 4'0000). Merging ports 17, 40 (address 4'0000). Merging ports 17, 41 (address 4'0000). Merging ports 17, 42 (address 4'0000). Merging ports 17, 43 (address 4'0000). Merging ports 17, 44 (address 4'0000). Merging ports 17, 45 (address 4'0000). Merging ports 17, 46 (address 4'0000). Merging ports 17, 47 (address 4'0000). Merging ports 17, 48 (address 4'0000). Consolidating write ports of memory dependency_manager.node_state by address: Merging ports 1, 2 (address 4'1000). Merging ports 1, 3 (address 4'1000). Merging ports 1, 5 (address 4'1000). Consolidating write ports of memory dependency_manager.node_state by address: Consolidating write ports of memory dependency_manager.node_producer_ids using sat-based resource sharing: Checking group clocked with posedge \clk, width 4: ports 0, 1, 2, 3. Common input cone for all EN signals: 4 cells. Size of unconstrained SAT problem: 29 variables, 63 clauses According to SAT solver sharing of port 0 with port 1 is not possible. According to SAT solver sharing of port 0 with port 2 is not possible. According to SAT solver sharing of port 0 with port 3 is not possible. According to SAT solver sharing of port 1 with port 2 is not possible. According to SAT solver sharing of port 1 with port 3 is not possible. According to SAT solver sharing of port 2 with port 3 is not possible. Consolidating write ports of memory dependency_manager.node_resolved using sat-based resource sharing: Checking group clocked with posedge \clk, width 48: ports 0, 1. Common input cone for all EN signals: 520 cells. Size of unconstrained SAT problem: 4291 variables, 10931 clauses According to SAT solver sharing of port 0 with port 1 is not possible. Consolidating write ports of memory dependency_manager.node_required using sat-based resource sharing: Consolidating write ports of memory dependency_manager.node_state using sat-based resource sharing: Checking group clocked with posedge \clk, width 32: ports 0, 1. Common input cone for all EN signals: 648 cells. Size of unconstrained SAT problem: 6675 variables, 17267 clauses According to SAT solver sharing of port 0 with port 1 is not possible. Checking group clocked with posedge \clk, width 2: ports 2, 3. Common input cone for all EN signals: 785 cells. Size of unconstrained SAT problem: 7362 variables, 19047 clauses According to SAT solver sharing of port 2 with port 3 is not possible. 2.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 165 unused wires. 2.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. 2.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory dependency_manager.node_result_addr via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of dependency_manager.node_result_addr: $\node_result_addr$rdreg[0] mapping memory dependency_manager.node_n_tiles via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of dependency_manager.node_n_tiles: $\node_n_tiles$rdreg[0] mapping memory dependency_manager.node_w_base via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of dependency_manager.node_w_base: $\node_w_base$rdreg[0] mapping memory dependency_manager.node_x_base via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of dependency_manager.node_x_base: $\node_x_base$rdreg[0] using FF mapping for memory dependency_manager.node_resolved using FF mapping for memory dependency_manager.node_required using FF mapping for memory dependency_manager.node_producer_ids using FF mapping for memory dependency_manager.node_state 2.30. Executing TECHMAP pass (map to technology primitives). 2.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 2.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 2.30.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. 2.31. Executing OPT pass (performing simple optimizations). 2.31.1. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.31.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1312 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 1242 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 70 cells. 2.31.3. Executing OPT_DFF pass (perform DFF optimizations). 2.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 692 unused wires. 2.31.5. Finished fast OPT passes. 2.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \node_resolved in module \dependency_manager: created 16 $dff cells and 0 static cells of width 3. read interface: 0 $dff and 1 $mux cells. write interface: 48 write mux blocks. Mapping memory \node_required in module \dependency_manager: created 16 $dff cells and 0 static cells of width 3. read interface: 0 $dff and 1 $mux cells. write interface: 48 write mux blocks. Mapping memory \node_producer_ids in module \dependency_manager: created 64 $dff cells and 0 static cells of width 4. read interface: 0 $dff and 1 $mux cells. write interface: 256 write mux blocks. Mapping memory \node_state in module \dependency_manager: created 16 $dff cells and 0 static cells of width 2. read interface: 0 $dff and 16 $mux cells. write interface: 64 write mux blocks. 2.33. Executing OPT pass (performing simple optimizations). 2.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1814 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 1766 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 1718 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 96 cells. 2.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$12214: Old ports: A=2'10, B=2'00, Y=$auto$rtlil.cc:3402:Mux$12195 New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:3402:Mux$12195 [1] New connections: $auto$rtlil.cc:3402:Mux$12195 [0] = 1'0 Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$11794: Old ports: A=2'00, B=2'10, Y=$auto$rtlil.cc:3402:Mux$11795 New ports: A=1'0, B=1'1, Y=$auto$rtlil.cc:3402:Mux$11795 [1] New connections: $auto$rtlil.cc:3402:Mux$11795 [0] = 1'0 Consolidated identical input bits for $mux cell $procmux$9911: Old ports: A=4'0000, B=4'1111, Y=$1\first_ready_idx[3:0] New ports: A=1'0, B=1'1, Y=$1\first_ready_idx[3:0] [0] New connections: $1\first_ready_idx[3:0] [3:1] = { $1\first_ready_idx[3:0] [0] $1\first_ready_idx[3:0] [0] $1\first_ready_idx[3:0] [0] } Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$11806: Old ports: A=$auto$rtlil.cc:3402:Mux$11795, B=2'10, Y=$auto$rtlil.cc:3402:Mux$11807 New ports: A=$auto$rtlil.cc:3402:Mux$11795 [1], B=1'1, Y=$auto$rtlil.cc:3402:Mux$11807 [1] New connections: $auto$rtlil.cc:3402:Mux$11807 [0] = 1'0 Consolidated identical input bits for $mux cell $procmux$9905: Old ports: A=$1\first_ready_idx[3:0], B=4'1110, Y=$2\first_ready_idx[3:0] New ports: A={ $1\first_ready_idx[3:0] [0] $1\first_ready_idx[3:0] [0] }, B=2'10, Y=$2\first_ready_idx[3:0] [1:0] New connections: $2\first_ready_idx[3:0] [3:2] = { $2\first_ready_idx[3:0] [1] $2\first_ready_idx[3:0] [1] } Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$11818: Old ports: A=$auto$rtlil.cc:3402:Mux$11807, B=2'10, Y=$auto$rtlil.cc:3402:Mux$11819 New ports: A=$auto$rtlil.cc:3402:Mux$11807 [1], B=1'1, Y=$auto$rtlil.cc:3402:Mux$11819 [1] New connections: $auto$rtlil.cc:3402:Mux$11819 [0] = 1'0 Consolidated identical input bits for $mux cell $procmux$9899: Old ports: A=$2\first_ready_idx[3:0], B=4'1101, Y=$3\first_ready_idx[3:0] New ports: A={ $2\first_ready_idx[3:0] [1] $2\first_ready_idx[3:0] [1:0] }, B=3'101, Y=$3\first_ready_idx[3:0] [2:0] New connections: $3\first_ready_idx[3:0] [3] = $3\first_ready_idx[3:0] [2] Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$11830: Old ports: A=$auto$rtlil.cc:3402:Mux$11819, B=2'10, Y=$auto$rtlil.cc:3402:Mux$11831 New ports: A=$auto$rtlil.cc:3402:Mux$11819 [1], B=1'1, Y=$auto$rtlil.cc:3402:Mux$11831 [1] New connections: $auto$rtlil.cc:3402:Mux$11831 [0] = 1'0 Consolidated identical input bits for $mux cell $procmux$9893: Old ports: A=$3\first_ready_idx[3:0], B=4'1100, Y=$4\first_ready_idx[3:0] New ports: A=$3\first_ready_idx[3:0] [2:0], B=3'100, Y=$4\first_ready_idx[3:0] [2:0] New connections: $4\first_ready_idx[3:0] [3] = $4\first_ready_idx[3:0] [2] Optimizing cells in module \dependency_manager. Performed a total of 9 changes. 2.33.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1718 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.33.6. Executing OPT_DFF pass (perform DFF optimizations). 2.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 1038 unused wires. 2.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.33.9. Rerunning OPT passes. (Maybe there is more to do..) 2.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.33.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1716 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.33.13. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $memory\node_resolved[0]$12459 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[0][1][0]$y$12503, Q = \node_resolved[0], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15150 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[0][1][0]$y$12503, Q = \node_resolved[0]). Adding SRST signal on $memory\node_resolved[1]$12461 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[1][1][0]$y$12529, Q = \node_resolved[1], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15154 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[1][1][0]$y$12529, Q = \node_resolved[1]). Adding SRST signal on $memory\node_resolved[2]$12463 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[2][1][0]$y$12547, Q = \node_resolved[2], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15158 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[2][1][0]$y$12547, Q = \node_resolved[2]). Adding SRST signal on $memory\node_resolved[3]$12465 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[3][1][0]$y$12565, Q = \node_resolved[3], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15162 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[3][1][0]$y$12565, Q = \node_resolved[3]). Adding SRST signal on $memory\node_resolved[4]$12467 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[4][1][0]$y$12581, Q = \node_resolved[4], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15166 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[4][1][0]$y$12581, Q = \node_resolved[4]). Adding SRST signal on $memory\node_resolved[5]$12469 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[5][1][0]$y$12599, Q = \node_resolved[5], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15170 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[5][1][0]$y$12599, Q = \node_resolved[5]). Adding SRST signal on $memory\node_resolved[6]$12471 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[6][1][0]$y$12613, Q = \node_resolved[6], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15174 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[6][1][0]$y$12613, Q = \node_resolved[6]). Adding SRST signal on $memory\node_resolved[7]$12473 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[7][1][0]$y$12627, Q = \node_resolved[7], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15178 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[7][1][0]$y$12627, Q = \node_resolved[7]). Adding SRST signal on $memory\node_resolved[8]$12475 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[8][1][0]$y$12641, Q = \node_resolved[8], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15182 ($sdff) from module dependency_manager (D = $memory\node_resolved$wrmux[8][1][0]$y$12641, Q = \node_resolved[8]). Adding SRST signal on $memory\node_resolved[9]$12477 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[9][1][0]$y$12659, Q = \node_resolved[9], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15186 ($sdff) from module dependency_manager (D = $auto$rtlil.cc:3402:Mux$11263, Q = \node_resolved[9]). Adding SRST signal on $memory\node_resolved[10]$12479 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[10][1][0]$y$12673, Q = \node_resolved[10], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15188 ($sdff) from module dependency_manager (D = $auto$rtlil.cc:3402:Mux$11627, Q = \node_resolved[10]). Adding SRST signal on $memory\node_resolved[11]$12481 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[11][1][0]$y$12687, Q = \node_resolved[11], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15190 ($sdff) from module dependency_manager (D = $auto$rtlil.cc:3402:Mux$11631, Q = \node_resolved[11]). Adding SRST signal on $memory\node_resolved[12]$12483 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[12][1][0]$y$12701, Q = \node_resolved[12], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15192 ($sdff) from module dependency_manager (D = $auto$rtlil.cc:3402:Mux$11635, Q = \node_resolved[12]). Adding SRST signal on $memory\node_resolved[13]$12485 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[13][1][0]$y$12717, Q = \node_resolved[13], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15194 ($sdff) from module dependency_manager (D = $auto$rtlil.cc:3402:Mux$11639, Q = \node_resolved[13]). Adding SRST signal on $memory\node_resolved[14]$12487 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[14][1][0]$y$12731, Q = \node_resolved[14], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15196 ($sdff) from module dependency_manager (D = $auto$rtlil.cc:3402:Mux$11643, Q = \node_resolved[14]). Adding SRST signal on $memory\node_resolved[15]$12489 ($dff) from module dependency_manager (D = $memory\node_resolved$wrmux[15][1][0]$y$12745, Q = \node_resolved[15], rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$15198 ($sdff) from module dependency_manager (D = $auto$rtlil.cc:3402:Mux$11647, Q = \node_resolved[15]). Adding SRST signal on $memory\node_state[15]$14780 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[15][2][0]$y$15143, Q = \node_state[15], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15200 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[15][2][0]$y$15143, Q = \node_state[15]). Adding SRST signal on $memory\node_state[7]$14764 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[7][2][0]$y$14993, Q = \node_state[7], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15204 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[7][2][0]$y$14993, Q = \node_state[7]). Adding EN signal on $memory\node_required[0]$12752 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[0][2][0]$y$12800, Q = \node_required[0]). Adding EN signal on $memory\node_required[1]$12754 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[1][2][0]$y$12812, Q = \node_required[1]). Adding EN signal on $memory\node_required[2]$12756 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[2][2][0]$y$12824, Q = \node_required[2]). Adding EN signal on $memory\node_required[3]$12758 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[3][2][0]$y$12836, Q = \node_required[3]). Adding EN signal on $memory\node_required[4]$12760 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[4][2][0]$y$12848, Q = \node_required[4]). Adding EN signal on $memory\node_required[5]$12762 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[5][2][0]$y$12860, Q = \node_required[5]). Adding EN signal on $memory\node_required[6]$12764 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[6][2][0]$y$12872, Q = \node_required[6]). Adding EN signal on $memory\node_required[7]$12766 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[7][2][0]$y$12884, Q = \node_required[7]). Adding EN signal on $memory\node_required[8]$12768 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[8][2][0]$y$12898, Q = \node_required[8]). Adding EN signal on $memory\node_required[9]$12770 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[9][2][0]$y$12910, Q = \node_required[9]). Adding EN signal on $memory\node_required[10]$12772 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[10][2][0]$y$12922, Q = \node_required[10]). Adding EN signal on $memory\node_required[11]$12774 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[11][2][0]$y$12934, Q = \node_required[11]). Adding EN signal on $memory\node_required[12]$12776 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[12][2][0]$y$12946, Q = \node_required[12]). Adding EN signal on $memory\node_required[13]$12778 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[13][2][0]$y$12958, Q = \node_required[13]). Adding EN signal on $memory\node_required[14]$12780 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[14][2][0]$y$12970, Q = \node_required[14]). Adding EN signal on $memory\node_required[15]$12782 ($dff) from module dependency_manager (D = $memory\node_required$wrmux[15][2][0]$y$12982, Q = \node_required[15]). Adding SRST signal on $memory\node_state[9]$14768 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[9][2][0]$y$15033, Q = \node_state[9], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15256 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[9][2][0]$y$15033, Q = \node_state[9]). Adding SRST signal on $memory\node_state[4]$14758 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[4][2][0]$y$14935, Q = \node_state[4], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15260 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[4][2][0]$y$14935, Q = \node_state[4]). Adding EN signal on $memory\node_producer_ids[0]$12983 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[0]). Adding EN signal on $memory\node_producer_ids[1]$12985 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[1]). Adding EN signal on $memory\node_producer_ids[2]$12987 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[2]). Adding EN signal on $memory\node_producer_ids[3]$12989 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[3]). Adding EN signal on $memory\node_producer_ids[4]$12991 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[4]). Adding EN signal on $memory\node_producer_ids[5]$12993 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[5]). Adding EN signal on $memory\node_producer_ids[6]$12995 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[6]). Adding EN signal on $memory\node_producer_ids[7]$12997 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[7]). Adding EN signal on $memory\node_producer_ids[8]$12999 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[8]). Adding EN signal on $memory\node_producer_ids[9]$13001 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[9]). Adding EN signal on $memory\node_producer_ids[10]$13003 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[10]). Adding EN signal on $memory\node_producer_ids[11]$13005 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[11]). Adding EN signal on $memory\node_producer_ids[12]$13007 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[12]). Adding EN signal on $memory\node_producer_ids[13]$13009 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[13]). Adding EN signal on $memory\node_producer_ids[14]$13011 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[14]). Adding EN signal on $memory\node_producer_ids[15]$13013 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[15]). Adding EN signal on $memory\node_producer_ids[16]$13015 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[16]). Adding EN signal on $memory\node_producer_ids[17]$13017 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[17]). Adding EN signal on $memory\node_producer_ids[18]$13019 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[18]). Adding EN signal on $memory\node_producer_ids[19]$13021 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[19]). Adding EN signal on $memory\node_producer_ids[20]$13023 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[20]). Adding EN signal on $memory\node_producer_ids[21]$13025 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[21]). Adding EN signal on $memory\node_producer_ids[22]$13027 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[22]). Adding EN signal on $memory\node_producer_ids[23]$13029 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[23]). Adding EN signal on $memory\node_producer_ids[24]$13031 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[24]). Adding EN signal on $memory\node_producer_ids[25]$13033 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[25]). Adding EN signal on $memory\node_producer_ids[26]$13035 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[26]). Adding EN signal on $memory\node_producer_ids[27]$13037 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[27]). Adding EN signal on $memory\node_producer_ids[28]$13039 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[28]). Adding EN signal on $memory\node_producer_ids[29]$13041 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[29]). Adding EN signal on $memory\node_producer_ids[30]$13043 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[30]). Adding EN signal on $memory\node_producer_ids[31]$13045 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[31]). Adding EN signal on $memory\node_producer_ids[32]$13047 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[32]). Adding EN signal on $memory\node_producer_ids[33]$13049 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[33]). Adding EN signal on $memory\node_producer_ids[34]$13051 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[34]). Adding EN signal on $memory\node_producer_ids[35]$13053 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[35]). Adding EN signal on $memory\node_producer_ids[36]$13055 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[36]). Adding EN signal on $memory\node_producer_ids[37]$13057 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[37]). Adding EN signal on $memory\node_producer_ids[38]$13059 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[38]). Adding EN signal on $memory\node_producer_ids[39]$13061 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[39]). Adding EN signal on $memory\node_producer_ids[40]$13063 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[40]). Adding EN signal on $memory\node_producer_ids[41]$13065 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[41]). Adding EN signal on $memory\node_producer_ids[42]$13067 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[42]). Adding EN signal on $memory\node_producer_ids[43]$13069 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[43]). Adding EN signal on $memory\node_producer_ids[44]$13071 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[44]). Adding EN signal on $memory\node_producer_ids[45]$13073 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[45]). Adding EN signal on $memory\node_producer_ids[46]$13075 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[46]). Adding EN signal on $memory\node_producer_ids[47]$13077 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[47]). Adding EN signal on $memory\node_producer_ids[48]$13079 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[48]). Adding EN signal on $memory\node_producer_ids[49]$13081 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[49]). Adding EN signal on $memory\node_producer_ids[50]$13083 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[50]). Adding EN signal on $memory\node_producer_ids[51]$13085 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[51]). Adding EN signal on $memory\node_producer_ids[52]$13087 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[52]). Adding EN signal on $memory\node_producer_ids[53]$13089 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[53]). Adding EN signal on $memory\node_producer_ids[54]$13091 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[54]). Adding EN signal on $memory\node_producer_ids[55]$13093 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[55]). Adding EN signal on $memory\node_producer_ids[56]$13095 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[56]). Adding EN signal on $memory\node_producer_ids[57]$13097 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[57]). Adding EN signal on $memory\node_producer_ids[58]$13099 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[58]). Adding EN signal on $memory\node_producer_ids[59]$13101 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[59]). Adding EN signal on $memory\node_producer_ids[60]$13103 ($dff) from module dependency_manager (D = \reg_producer_ids [3:0], Q = \node_producer_ids[60]). Adding EN signal on $memory\node_producer_ids[61]$13105 ($dff) from module dependency_manager (D = \reg_producer_ids [7:4], Q = \node_producer_ids[61]). Adding EN signal on $memory\node_producer_ids[62]$13107 ($dff) from module dependency_manager (D = \reg_producer_ids [11:8], Q = \node_producer_ids[62]). Adding EN signal on $memory\node_producer_ids[63]$13109 ($dff) from module dependency_manager (D = \reg_producer_ids [15:12], Q = \node_producer_ids[63]). Adding SRST signal on $memory\node_state[3]$14756 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[3][2][0]$y$14915, Q = \node_state[3], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15328 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[3][2][0]$y$14915, Q = \node_state[3]). Adding SRST signal on $memory\node_state[14]$14778 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[14][2][0]$y$15125, Q = \node_state[14], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15332 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[14][2][0]$y$15125, Q = \node_state[14]). Adding SRST signal on $memory\node_state[10]$14770 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[10][2][0]$y$15051, Q = \node_state[10], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15336 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[10][2][0]$y$15051, Q = \node_state[10]). Adding SRST signal on $memory\node_state[2]$14754 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[2][2][0]$y$14893, Q = \node_state[2], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15340 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[2][2][0]$y$14893, Q = \node_state[2]). Adding SRST signal on $memory\node_state[1]$14752 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[1][2][0]$y$14871, Q = \node_state[1], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15344 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[1][2][0]$y$14871, Q = \node_state[1]). Adding SRST signal on $memory\node_state[0]$14750 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[0][2][0]$y$14841, Q = \node_state[0], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15348 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[0][2][0]$y$14841, Q = \node_state[0]). Adding SRST signal on $memory\node_state[8]$14766 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[8][2][0]$y$15011, Q = \node_state[8], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15352 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[8][2][0]$y$15011, Q = \node_state[8]). Adding SRST signal on $memory\node_state[13]$14776 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[13][2][0]$y$15107, Q = \node_state[13], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15356 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[13][2][0]$y$15107, Q = \node_state[13]). Adding SRST signal on $memory\node_state[6]$14762 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[6][2][0]$y$14975, Q = \node_state[6], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15360 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[6][2][0]$y$14975, Q = \node_state[6]). Adding SRST signal on $memory\node_state[12]$14774 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[12][2][0]$y$15087, Q = \node_state[12], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15364 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[12][2][0]$y$15087, Q = \node_state[12]). Adding SRST signal on $memory\node_state[5]$14760 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[5][2][0]$y$14957, Q = \node_state[5], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15368 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[5][2][0]$y$14957, Q = \node_state[5]). Adding SRST signal on $memory\node_state[11]$14772 ($dff) from module dependency_manager (D = $memory\node_state$wrmux[11][2][0]$y$15069, Q = \node_state[11], rval = 2'11). Adding EN signal on $auto$ff.cc:337:slice$15372 ($sdff) from module dependency_manager (D = $memory\node_state$wrmux[11][2][0]$y$15069, Q = \node_state[11]). 2.33.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 103 unused cells and 105 unused wires. 2.33.15. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.33.16. Rerunning OPT passes. (Maybe there is more to do..) 2.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Consolidated identical input bits for $mux cell $memory\node_state$wrmux[5][1][0]$14952: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[5][1][0]$y$14953 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[5][1][0]$y$14953 [1] New connections: $memory\node_state$wrmux[5][1][0]$y$14953 [0] = 1'0 Consolidated identical input bits for $mux cell $memory\node_state$wrmux[3][1][0]$14910: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[3][1][0]$y$14911 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[3][1][0]$y$14911 [1] New connections: $memory\node_state$wrmux[3][1][0]$y$14911 [0] = 1'0 Consolidated identical input bits for $mux cell $memory\node_state$wrmux[6][1][0]$14970: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[6][1][0]$y$14971 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[6][1][0]$y$14971 [1] New connections: $memory\node_state$wrmux[6][1][0]$y$14971 [0] = 1'0 Consolidated identical input bits for $mux cell $memory\node_state$wrmux[4][1][0]$14930: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[4][1][0]$y$14931 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[4][1][0]$y$14931 [1] New connections: $memory\node_state$wrmux[4][1][0]$y$14931 [0] = 1'0 Consolidated identical input bits for $mux cell $memory\node_state$wrmux[7][1][0]$14988: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[7][1][0]$y$14989 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[7][1][0]$y$14989 [1] New connections: $memory\node_state$wrmux[7][1][0]$y$14989 [0] = 1'0 Consolidated identical input bits for $mux cell $memory\node_state$wrmux[1][1][0]$14866: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[1][1][0]$y$14867 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[1][1][0]$y$14867 [1] New connections: $memory\node_state$wrmux[1][1][0]$y$14867 [0] = 1'0 Consolidated identical input bits for $mux cell $memory\node_state$wrmux[0][1][0]$14836: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[0][1][0]$y$14837 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[0][1][0]$y$14837 [1] New connections: $memory\node_state$wrmux[0][1][0]$y$14837 [0] = 1'0 Consolidated identical input bits for $mux cell $memory\node_state$wrmux[8][1][0]$15006: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[8][1][0]$y$15007 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[8][1][0]$y$15007 [1] New connections: $memory\node_state$wrmux[8][1][0]$y$15007 [0] = 1'0 Consolidated identical input bits for $mux cell $memory\node_state$wrmux[2][1][0]$14888: Old ports: A=2'00, B=2'10, Y=$memory\node_state$wrmux[2][1][0]$y$14889 New ports: A=1'0, B=1'1, Y=$memory\node_state$wrmux[2][1][0]$y$14889 [1] New connections: $memory\node_state$wrmux[2][1][0]$y$14889 [0] = 1'0 Optimizing cells in module \dependency_manager. Performed a total of 9 changes. 2.33.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1613 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.33.20. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$15208 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[0], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15211 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[1], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15214 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[2], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15217 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[3], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15220 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[4], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15223 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[5], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15226 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[6], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15229 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[7], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15232 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[8], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15235 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[9], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15238 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[10], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15241 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[11], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15244 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[12], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15247 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[13], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15250 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[14], rval = 3'000). Adding SRST signal on $auto$ff.cc:337:slice$15253 ($dffe) from module dependency_manager (D = \reg_required, Q = \node_required[15], rval = 3'000). 2.33.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 16 unused cells and 57 unused wires. 2.33.22. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.33.23. Rerunning OPT passes. (Maybe there is more to do..) 2.33.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.33.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1588 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.33.27. Executing OPT_DFF pass (perform DFF optimizations). 2.33.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 9 unused wires. 2.33.29. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.33.30. Rerunning OPT passes. (Maybe there is more to do..) 2.33.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.33.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 1588 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.33.34. Executing OPT_DFF pass (perform DFF optimizations). 2.33.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. 2.33.36. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.33.37. Finished fast OPT passes. (There is nothing left to do.) 2.34. Executing TECHMAP pass (map to technology primitives). 2.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 2.34.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $lut. Using extmapper simplemap for cells of type $xor. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using extmapper simplemap for cells of type $pos. No more expansions possible. 2.35. Executing OPT pass (performing simple optimizations). 2.35.1. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.35.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 3059 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 3002 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 2983 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 2982 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 2981 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 2980 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 2979 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 2978 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 81 cells. 2.35.3. Executing OPT_DFF pass (perform DFF optimizations). 2.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 127 unused cells and 1829 unused wires. 2.35.5. Finished fast OPT passes. 2.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. 2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 2947 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 2915 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Computing hashes of 2883 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 64 cells. 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. No more expansions possible. 2.40. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in dependency_manager. 2.43. Executing ATTRMVCP pass (move or copy attributes). 2.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. Removed 0 unused cells and 2563 unused wires. 2.45. Executing CHECK pass (checking for obvious problems). Checking module dependency_manager... Found and reported 0 problems. 2.46. Executing TECHMAP pass (map to technology primitives). 2.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 2.46.2. Continuing TECHMAP pass. No more expansions possible. 2.47. Executing ABC9 pass. 2.47.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.3. Executing PROC pass (convert processes to netlists). 2.47.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$21527'. Cleaned up 1 empty switch. 2.47.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$21528 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 2.47.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 2.47.3.4. Executing PROC_INIT pass (extract init attributes). 2.47.3.5. Executing PROC_ARST pass (detect async resets in processes). 2.47.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.47.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$21528'. 1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$21526_EN[3:0]$21534 2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$21526_DATA[3:0]$21533 3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$21526_ADDR[3:0]$21532 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$21527'. 2.47.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21510_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21511_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21512_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21513_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21514_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21515_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21516_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21517_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21518_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21519_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21520_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21521_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21522_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21523_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21524_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$21525_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$21527'. 2.47.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$21526_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$21528'. created $dff cell `$procdff$21578' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$21526_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$21528'. created $dff cell `$procdff$21579' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$21526_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$21528'. created $dff cell `$procdff$21580' with positive edge clock. 2.47.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.47.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$21552'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$21528'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$21528'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$21527'. Cleaned up 1 empty switch. 2.47.4. Executing SCC pass (detecting logic loops). Found an SCC: $auto$ff.cc:337:slice$16840 $auto$simplemap.cc:157:simplemap_reduce$16842 $auto$simplemap.cc:256:simplemap_logbin$18838 Found 1 SCCs in module dependency_manager. Found 1 SCCs. 2.47.5. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.6. Executing TECHMAP pass (map to technology primitives). 2.47.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.47.6.2. Continuing TECHMAP pass. No more expansions possible. 2.47.7. Executing OPT pass (performing simple optimizations). 2.47.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 2.47.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 2.47.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.47.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Performed a total of 0 changes. 2.47.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 2.47.7.6. Executing OPT_DFF pass (perform DFF optimizations). 2.47.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. 2.47.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 2.47.7.9. Finished fast OPT passes. (There is nothing left to do.) 2.47.8. Executing TECHMAP pass (map to technology primitives). 2.47.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 2.47.8.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. 2.47.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 2.47.10. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.11. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.12. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.13. Executing TECHMAP pass (map to technology primitives). 2.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.47.13.2. Continuing TECHMAP pass. No more expansions possible. 2.47.14. Executing OPT pass (performing simple optimizations). 2.47.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.47.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 0 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.47.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \dependency_manager.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.47.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \dependency_manager. Performed a total of 0 changes. 2.47.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\dependency_manager'. Computing hashes of 0 cells of `\dependency_manager'. Finding duplicate cells in `\dependency_manager'. Removed a total of 0 cells. 2.47.14.6. Executing OPT_DFF pass (perform DFF optimizations). 2.47.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \dependency_manager.. 2.47.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module dependency_manager. 2.47.14.9. Finished fast OPT passes. (There is nothing left to do.) 2.47.15. Executing AIGMAP pass (map logic to AIG). 2.47.16. Executing AIGMAP pass (map logic to AIG). Module dependency_manager: replaced 1560 cells with 9380 new cells, skipped 1346 cells. replaced 4 cell types: 716 $_MUX_ 16 $_ORNOT_ 492 $_OR_ 336 $_XOR_ not replaced 6 cell types: 509 $_AND_ 318 $_NOT_ 1 $__ABC9_SCC_BREAKER 474 TRELLIS_FF 22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 22 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 2.47.16.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.16.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.16.3. Executing XAIGER backend. Extracted 4173 AND gates and 11107 wires from module `dependency_manager' to a netlist network with 680 inputs and 377 outputs. 2.47.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). 2.47.16.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 680/ 377 and = 2857 lev = 58 (12.78) mem = 0.05 MB box = 22 bb = 22 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 680/ 377 and = 3062 lev = 16 (4.47) mem = 0.06 MB ch = 367 box = 22 bb = 22 ABC: cst = 0 cls = 295 lit = 367 unused = 3168 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 3062. Ch = 295. Total mem = 0.72 MB. Peak cut mem = 0.08 MB. ABC: P: Del = 2668.00. Ar = 1478.0. Edge = 2209. Cut = 30807. T = 0.00 sec ABC: P: Del = 2668.00. Ar = 1553.0. Edge = 2241. Cut = 30500. T = 0.00 sec ABC: P: Del = 2668.00. Ar = 1053.0. Edge = 2123. Cut = 40978. T = 0.00 sec ABC: F: Del = 2668.00. Ar = 819.0. Edge = 2181. Cut = 30495. T = 0.00 sec ABC: A: Del = 2668.00. Ar = 770.0. Edge = 2031. Cut = 30818. T = 0.00 sec ABC: A: Del = 2668.00. Ar = 763.0. Edge = 2020. Cut = 30963. T = 0.00 sec ABC: Total time = 0.02 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: + &ps -l ABC: /input : i/o = 680/ 377 and = 2224 lev = 17 (4.72) mem = 0.05 MB box = 22 bb = 22 ABC: Mapping (K=7) : lut = 521 edge = 2014 lev = 5 (2.21) levB = 6 mem = 0.03 MB ABC: LUT = 521 : 2=92 17.7 % 3=66 12.7 % 4=229 44.0 % 5=96 18.4 % 6=30 5.8 % 7=8 1.5 % Ave = 3.87 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.04 sec ABC: + time ABC: elapse: 0.19 seconds, total: 0.19 seconds 2.47.16.6. Executing AIGER frontend. Removed 3418 unused cells and 4616 unused wires. 2.47.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 521 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 22 ABC RESULTS: input signals: 147 ABC RESULTS: output signals: 161 Removing temp directory. 2.47.17. Executing TECHMAP pass (map to technology primitives). 2.47.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 2.47.17.2. Continuing TECHMAP pass. Using template $paramod$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000001 for cells of type $__ABC9_SCC_BREAKER. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. No more expansions possible. Removed 59 unused cells and 12873 unused wires. 2.48. Executing TECHMAP pass (map to technology primitives). 2.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 2.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057$lut for cells of type $lut. Using template $paramod$f2409a78973bdb892cfda5332812120de70b5ace$lut for cells of type $lut. Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc$lut for cells of type $lut. Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233$lut for cells of type $lut. Using template $paramod$d5c7dda3e544463bf43ed73dadb51262f5dcf2fe$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$12879138d1e376f344e47ea40be66b776233be75$lut for cells of type $lut. Using template $paramod$c1b1e295769db1b6655cd9fa7f1823a266fa6d67$lut for cells of type $lut. Using template $paramod$8091f1055b08cf62a067eb9c712980d4ac8978e3$lut for cells of type $lut. Using template $paramod$a988852add2bdce7c1dfac786401ba7c7bc832c1$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut. Using template $paramod$5c7d886f3b88971ac55fed4bca034a87bf180f7d$lut for cells of type $lut. Using template $paramod$7c9798725c20dab7d8a0e537927912d07d4ec8fa$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d$lut for cells of type $lut. Using template $paramod$640f9af1f69f4960d66566286bcb286b3fc037b9$lut for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08$lut for cells of type $lut. Using template $paramod$8614da24b3846fe751594d00fba789cfcb7b874c$lut for cells of type $lut. Using template $paramod$549a24c0b77071744eefd28bf11342e15d6bc181$lut for cells of type $lut. Using template $paramod$83c1b6108170249166239e09804c5f4542556524$lut for cells of type $lut. Using template $paramod$3f33fe908080b7d9a498c66343198586ea8ad106$lut for cells of type $lut. Using template $paramod$0943324992873f68d548adee292d09c6d57581d1$lut for cells of type $lut. Using template $paramod$7dc58ad16a6cd9ff5d5c9e92905e6d358e33db50$lut for cells of type $lut. Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$a6adeedfec2e5bb742b995ca9fb4d831f6655113$lut for cells of type $lut. Using template $paramod$3b99cc5838cca2d48a325293ea8b86b65ab41116$lut for cells of type $lut. Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$51ae49eb1125e98a7f16c893282e1aafc51b723d$lut for cells of type $lut. Using template $paramod$797d866167df3a8c4e1aa8edd8722133c7535936$lut for cells of type $lut. Using template $paramod$db85cac9b36977710f9657a368f30c4079b2320d$lut for cells of type $lut. Using template $paramod$eaece168d83a79b145f3756092b895fb31832237$lut for cells of type $lut. Using template $paramod$46c2fded91ea398138169361fac1350d24198e47$lut for cells of type $lut. Using template $paramod$ae3a43343511e19fb300feaa5c0de22b62b0fa1b$lut for cells of type $lut. Using template $paramod$da8506f47f742e881b922814186ffb6479b7a435$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304$lut for cells of type $lut. Using template $paramod$2901db385db9c9ed336329e529961d8bab9446d5$lut for cells of type $lut. Using template $paramod$047d0df6c87b7042d6d894454cb0917def4e9363$lut for cells of type $lut. Using template $paramod$e42980d53b766d0a39ada68e91e0832013c57536$lut for cells of type $lut. Using template $paramod$63689a1f51fa4ace9c1017788dac46fc4219c96b$lut for cells of type $lut. Using template $paramod$9ed1a75a1f11ae6371ce277fec5df772c636b4a4$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$b5babc618720ace64bafddb303d6f59fd10af395$lut for cells of type $lut. Using template $paramod$3dda0f29a2eb726310bf192049ebe6243c89618e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$622fbfda84ce879ffe81ed64fe7c9ef091242ae3$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7$lut for cells of type $lut. Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$c71ed138d834112b80a85f4478e2e21f72e5c48b$lut for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$c0b24172d263163a8e6b59024cdb9dfb57b52d61$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$175c5bb328c5ad2a4dee65e0ff64057ceea2d9cc$lut for cells of type $lut. Using template $paramod$19451f719aa4a75f15cb977ed4212a1c1a1550e9$lut for cells of type $lut. Using template $paramod$346c28c83d9959bca22fab8e9a88e63920be2e4c$lut for cells of type $lut. Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673$lut for cells of type $lut. Using template $paramod$5bbc8d49c3fc31cf6661312d1516e2aaafe308a4$lut for cells of type $lut. Using template $paramod$9f73a6a70b2d67fc647ae4625325482451e11575$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$62fb31b1a783eac472264027492b859f55ad08ed$lut for cells of type $lut. Using template $paramod$732e1780b927811a5c042d297e1a8e86e2cb3916$lut for cells of type $lut. Using template $paramod$5c8b6e0d7e1b6a9fadb9a7991bc1ece6c25b6dfb$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$08e562a212f1e537ce802717d4f264d53e41885e$lut for cells of type $lut. Using template $paramod$3d8b1d2823b58e370a3b602aca741f53b5190c93$lut for cells of type $lut. Using template $paramod$d3949f71f49fbc586e9767c35be678f9222e5866$lut for cells of type $lut. Using template $paramod$9bceaa1436937d85e20857d4867f2d504c090d0a$lut for cells of type $lut. Using template $paramod$851c1553b5da8901ec70f8623e0f4dea847d10fc$lut for cells of type $lut. Using template $paramod$303607065f6eb15d8928442960164bdd7e8c8c39$lut for cells of type $lut. Using template $paramod$64036e71871a4e1b268136afcadb37a975c7f3f3$lut for cells of type $lut. Using template $paramod$1d011ff2ab9ccc22e07492add25c377b826acd29$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$2123094b4b0fe0a30d7b2f69d44d3ef2d8432d91$lut for cells of type $lut. Using template $paramod$ab094b913c8577c5f2832b643512265172607114$lut for cells of type $lut. Using template $paramod$5c0e311adc8e90042eb0e6bfbc1c041ce1eeb28e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f$lut for cells of type $lut. Using template $paramod$15efa44280f2a77bf023b68f95d9df5681d9dd99$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut. Using template $paramod$74df2f9dfbf9dda55baea98786f1e045b91361c7$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut. Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$27dd7ea71d2126c74d85758e5a06b7f432d9242f$lut for cells of type $lut. Using template $paramod$e4a0bc6f7c8807731b7a86bc08b543c66ad175a2$lut for cells of type $lut. Using template $paramod$6f3f060a82077d7722793a80a7f81ffcda8e7f4d$lut for cells of type $lut. Using template $paramod$f5d1c5d5f77f45ffe17befc28ba399e703b6f0a5$lut for cells of type $lut. Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93$lut for cells of type $lut. Using template $paramod$df5999ec14d68f76a12ccd5d94c718f688537d4e$lut for cells of type $lut. Using template $paramod$0ff01026eec9ed942b622e70f78bddd5ce57b567$lut for cells of type $lut. Using template $paramod$5b911088c85be940c5536ba95ae420a4b2e24f13$lut for cells of type $lut. Using template $paramod$4c4b2c4bf2d3c5eef5c4097f5b20d3dd751e966c$lut for cells of type $lut. Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0$lut for cells of type $lut. Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9$lut for cells of type $lut. Using template $paramod$903905cca899aab473483ca27c3db12d7108e3a5$lut for cells of type $lut. No more expansions possible. 2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in dependency_manager. Optimizing lut $abc$40517$lut$aiger$o462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$855.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$1664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$1250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$40517$lut$aiger$o313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$2122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$2475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger$o364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$1232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$1455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger$o359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$2234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger$o357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$1326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$40517$lut$aiger40516$2620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger$o226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1513.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$1472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger$o349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger$o347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1589.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$40517$lut$aiger$o342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$40517$lut$aiger40516$1007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$40517$lut$aiger40516$1811.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$40517$lut$aiger40516$1040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$40571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Removed 0 unused cells and 1232 unused wires. 2.50. Executing AUTONAME pass. Renamed 2248 objects in module dependency_manager. 2.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `dependency_manager'. Setting top module to dependency_manager. 2.51.1. Analyzing design hierarchy.. Top module: \dependency_manager 2.51.2. Analyzing design hierarchy.. Top module: \dependency_manager Removed 0 unused modules. 2.52. Printing statistics. === dependency_manager === +----------Local Count, excluding submodules. | 903 wires 2127 wire bits 903 public wires 2127 public wire bits 20 ports 208 port bits 1501 submodules 54 L6MUX21 763 LUT4 188 PFUMX 22 TRELLIS_DPR16X4 474 TRELLIS_FF === design hierarchy === +----------Count including submodules. | - dependency_manager +----------Count including submodules. | 903 wires 2127 wire bits 903 public wires 2127 public wire bits 20 ports 208 port bits - memories - memory bits - processes - cells 1501 submodules 54 L6MUX21 763 LUT4 188 PFUMX 22 TRELLIS_DPR16X4 474 TRELLIS_FF 2.53. Executing CHECK pass (checking for obvious problems). Checking module dependency_manager... Found and reported 0 problems. 2.54. Executing JSON backend. End of script. Logfile hash: 4a7c0270d6, time: 1.35s, user: 1.12s, system: 0.04s, MEM: 87.84 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 14% 1x abc9_exe (0 sec), 13% 21x read_verilog (0 sec), ...