Info: Logic utilisation before packing: Info: Total LUT4s: 308/43848 0% Info: logic LUTs: 284/43848 0% Info: carry LUTs: 24/43848 0% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 184/43848 0% Info: Packing IOs.. Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_9.Y Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_8.Y Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_7.Y Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_6.Y Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_5.Y Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_4.Y Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_3.Y Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_2.Y Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_1.Y Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_15.Y Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_14.Y Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_13.Y Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_12.Y Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_11.Y Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_10.Y Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 92 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x6432f0fa Info: Device utilisation: Info: TRELLIS_IO: 107/ 245 43% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 184/ 43848 0% Info: TRELLIS_COMB: 334/ 43848 0% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 337 cells, random placement wirelen = 30937. Info: at initial placer iter 0, wirelen = 7548 Info: at initial placer iter 1, wirelen = 7178 Info: at initial placer iter 2, wirelen = 6972 Info: at initial placer iter 3, wirelen = 6965 Info: Running main analytical placer, max placement attempts per cell = 48984. Info: at iteration #1, type ALL: wirelen solved = 6930, spread = 7503, legal = 7561; time = 0.01s Info: HeAP Placer Time: 0.03s Info: of which solving equations: 0.01s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 7561 Info: at iteration #5: temp = 0.000000, timing cost = 59, wirelen = 6348 Info: at iteration #9: temp = 0.000000, timing cost = 101, wirelen = 6395 Info: SA placement time 0.06s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 236.80 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.98 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 6.40 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 8277, 8435) |****** Info: [ 8435, 8593) |*********** Info: [ 8593, 8751) |***************** Info: [ 8751, 8909) |*************** Info: [ 8909, 9067) |****************** Info: [ 9067, 9225) |**************************************** Info: [ 9225, 9383) |************************************ Info: [ 9383, 9541) |********************************************** Info: [ 9541, 9699) |********************** Info: [ 9699, 9857) |********************** Info: [ 9857, 10015) |************************ Info: [ 10015, 10173) |***** Info: [ 10173, 10331) |********** Info: [ 10331, 10489) |******* Info: [ 10489, 10647) |**** Info: [ 10647, 10805) |***** Info: [ 10805, 10963) |******* Info: [ 10963, 11121) | Info: [ 11121, 11279) |** Info: [ 11279, 11437) |*** Info: Checksum: 0xa39bec75 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 1732 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 270 721 | 270 721 | 1030| 0.09 0.09| Info: 2000 | 389 1543 | 119 822 | 154| 0.19 0.28| Info: 2162 | 398 1695 | 9 152 | 0| 0.03 0.31| Info: Routing complete. Info: Router1 time 0.31s Info: Checksum: 0xd6f72769 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.40 0.40 Source state_TRELLIS_FF_Q_5.Q Info: routing 0.59 0.99 Net page_hit_reg_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_LUT4_Z_C[1] (36,20) -> (37,20) Info: Sink req_pending_LUT4_D.C Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 1.17 Source req_pending_LUT4_D.F Info: routing 0.75 1.91 Net req_pending_LUT4_D_Z[2] (37,20) -> (35,20) Info: Sink psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 2.09 Source psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F Info: routing 0.45 2.54 Net psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D[3] (35,20) -> (35,20) Info: Sink psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 2.72 Source psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.F Info: routing 1.06 3.79 Net psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C[2] (35,20) -> (34,17) Info: Sink psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z.C Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 3.97 Source psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z.F Info: routing 0.12 4.09 Net psram_oe_n_TRELLIS_FF_Q_DI (34,17) -> (34,17) Info: Sink psram_oe_n_TRELLIS_FF_Q.DI Info: setup 0.00 4.09 Source psram_oe_n_TRELLIS_FF_Q.DI Info: 1.12 ns logic, 2.97 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source mem_addr[13]$tr_io.O Info: routing 4.11 4.11 Net mem_addr[13]$TRELLIS_IO_IN (15,71) -> (38,20) Info: Sink page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.B Info: Defined in: Info: rtl/psram_controller.v:15.35-15.43 Info: logic 0.18 4.30 Source page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.F Info: routing 0.16 4.45 Net page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D[3] (38,20) -> (38,20) Info: Sink page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 4.63 Source page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z.F Info: routing 0.63 5.27 Net page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D[2] (38,20) -> (39,20) Info: Sink page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 5.45 Source page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1.F Info: routing 0.66 6.10 Net page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D[2] (39,20) -> (39,19) Info: Sink page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z.C Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 6.28 Source page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z.F Info: routing 0.12 6.40 Net page_hit_reg_TRELLIS_FF_Q_DI (39,19) -> (39,19) Info: Sink page_hit_reg_TRELLIS_FF_Q.DI Info: setup 0.00 6.40 Source page_hit_reg_TRELLIS_FF_Q.DI Info: 0.72 ns logic, 5.68 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source dq_oe_TRELLIS_FF_Q.Q Info: routing 3.49 3.89 Net dq_oe (35,20) -> (18,67) Info: Sink psram_dq[1]$tr_io$invert_T.A Info: Defined in: Info: rtl/psram_controller.v:188.27-188.32 Info: logic 0.18 4.07 Source psram_dq[1]$tr_io$invert_T.F Info: routing 0.67 4.74 Net psram_dq[1]$tr_io$invert_T$conn$Z (18,67) -> (18,71) Info: Sink psram_dq[1]$tr_io.T Info: 0.57 ns logic, 4.16 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 244.74 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.40 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.74 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 8414, 8558) |***** Info: [ 8558, 8702) |**** Info: [ 8702, 8846) |**************** Info: [ 8846, 8990) |************************** Info: [ 8990, 9134) |********************** Info: [ 9134, 9278) |********************************************** Info: [ 9278, 9422) |********************** Info: [ 9422, 9566) |******************** Info: [ 9566, 9710) |************************** Info: [ 9710, 9854) |******************************** Info: [ 9854, 9998) |***************** Info: [ 9998, 10142) |************* Info: [ 10142, 10286) |********** Info: [ 10286, 10430) |******** Info: [ 10430, 10574) |*********** Info: [ 10574, 10718) |****** Info: [ 10718, 10862) |******** Info: [ 10862, 11006) |**** Info: [ 11006, 11150) |* Info: [ 11150, 11294) |*** Info: Program finished normally.