# ============================================================
# V3 -- top-level pin/IOSTANDARD constraints for n2_system_ddr3_top.v,
# real xc7a100tcsg324-2, board is the user's own custom design (bare
# chip + DDR3, no dev board). DDR3 pins themselves are NOT here --
# those come from the MIG-generated mig_7series_0.xdc (dictated by
# the FPGA's internal DDR3 PHY hardware, not a free choice).
#
# Verified against the real device via a routed checkpoint query
# (open_checkpoint + get_package_pins/get_ports on n2_system_ddr3_
# top_routed.dcp), not guessed from a datasheet table.
# ============================================================

# ---- required for flash_spi_master.v to work at all: D00_MOSI/
# D01_DIN/FCS_B only become ordinary fabric I/O post-configuration
# when PERSIST is FALSE (the Vivado default -- set explicitly here so
# this dependency is self-documenting in the constraints, not just a
# silent default someone could flip later without realizing why).
set_property BITSTREAM.CONFIG.PERSIST FALSE [current_design]

# ---- config-flash passthrough (-> flash_spi_master.v, EXP-0077):
# D00_MOSI/D01_DIN/FCS_B are the SAME physical pins the FPGA's own
# dedicated Master-SPI config hardware uses AT BOOT to self-load its
# bitstream -- post-configuration they become ordinary fabric I/O
# (real Xilinx behavior, PERSIST=FALSE, the Vivado default) and this
# design deliberately reclaims them for the flash_spi_master.v bridge
# (the board wires the config flash EXCLUSIVELY to the FPGA -- see
# that module's own header). CCLK is NOT constrained here -- it's
# driven via STARTUPE2 internally, never a plain top-level port.
set_property PACKAGE_PIN K17 [get_ports flash_mosi]
set_property PACKAGE_PIN K18 [get_ports flash_miso]
set_property PACKAGE_PIN L13 [get_ports flash_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports flash_mosi]
set_property IOSTANDARD LVCMOS33 [get_ports flash_miso]
set_property IOSTANDARD LVCMOS33 [get_ports flash_cs_n]

# ---- EMCCLK/RDWR_B/CSI_B (bank 14): not used by this design at all
# (this project's Master SPI config mode never needed them -- they're
# only relevant to modes this board doesn't use, e.g. BPI or Quad-SPI
# extra data lines) -- PROHIBITed so Vivado's auto-placement never
# lands an unrelated port there by accident (it already had once,
# before this constraint existed, on a result-data bit).
set_property PROHIBIT true [get_package_pins {L16 R16 V15}]

# ---- neural-processor management SPI (-> spi_host_bridge_v3.v):
# job submission + register file. Bank 15, column A/B (package edge,
# physically adjacent pins for short/easy PCB routing), well clear of
# both DDR3 (banks 34/35) and the reserved config-flash pins above.
# IOSTANDARD assumes bank 15 is powered at 3.3V on the custom board --
# change to match whatever VCCO the user's own power plan uses for
# that bank.
set_property PACKAGE_PIN A15 [get_ports sclk]
set_property PACKAGE_PIN B16 [get_ports mosi]
set_property PACKAGE_PIN B17 [get_ports miso]
set_property PACKAGE_PIN A16 [get_ports cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports sclk]
set_property IOSTANDARD LVCMOS33 [get_ports mosi]
set_property IOSTANDARD LVCMOS33 [get_ports miso]
set_property IOSTANDARD LVCMOS33 [get_ports cs_n]

# ---- sys_rst: not part of the DDR3 MIG's own pin set (that's
# sys_rst too, but MIG's XDC only constrains the DDR3-facing timing,
# not necessarily IOSTANDARD for every board variant) -- pin left to
# auto-placement for now (low pin-count, no real board decision yet
# on where the reset source sits); explicitly constrain once the PCB
# layout for the reset circuit (button/supervisor IC) is decided.