/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Parsing `hardware/v2/rtl/weight_buffer.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: hardware/v2/rtl/weight_buffer.v Parsing Verilog input from `hardware/v2/rtl/weight_buffer.v' to AST representation. Storing AST representation for module `$abstract\weight_buffer'. Successfully finished Verilog frontend. -- Running command `synth_ecp5 -json hardware/v2/synthesis/weight_buffer_d512/top.json -top weight_buffer' -- 2. Executing SYNTH_LATTICE pass. 2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 2.3. Executing HIERARCHY pass (managing design hierarchy). 2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\weight_buffer'. Generating RTLIL representation for module `\weight_buffer'. 2.4.1. Analyzing design hierarchy.. Top module: \weight_buffer 2.4.2. Analyzing design hierarchy.. Top module: \weight_buffer Removing unused module `$abstract\weight_buffer'. Removed 1 unused modules. 2.5. Executing PROC pass (convert processes to netlists). 2.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/weight_buffer.v:39$227 in module weight_buffer. Removed a total of 0 dead cases. 2.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 4 assignments to connections. 2.5.4. Executing PROC_INIT pass (extract init attributes). 2.5.5. Executing PROC_ARST pass (detect async resets in processes). 2.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$234'. Creating decoders for process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. 1/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$233 2/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_DATA[63:0]$232 3/3: $1$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_ADDR[8:0]$231 2.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\weight_buffer.\rd_data' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$234'. created $dff cell `$procdff$245' with positive edge clock. Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_ADDR' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. created $dff cell `$procdff$246' with positive edge clock. Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_DATA' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. created $dff cell `$procdff$247' with positive edge clock. Creating register for signal `\weight_buffer.$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN' using process `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. created $dff cell `$procdff$248' with positive edge clock. 2.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:44$234'. Found and cleaned up 1 empty switch in `\weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. Removing empty process `weight_buffer.$proc$hardware/v2/rtl/weight_buffer.v:39$227'. Cleaned up 1 empty switch. 2.5.12. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.6. Executing CHECK pass (checking for obvious problems). Checking module weight_buffer... Found and reported 0 problems. 2.7. Executing FLATTEN pass (flatten design). 2.8. Executing TRIBUF pass. 2.9. Executing DEMINOUT pass (demote inout ports to input or output). 2.10. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. Removed 3 unused cells and 13 unused wires. 2.12. Executing CHECK pass (checking for obvious problems). Checking module weight_buffer... Found and reported 0 problems. 2.13. Executing OPT pass (performing simple optimizations). 2.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 6 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \weight_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \weight_buffer. Consolidated identical input bits for $mux cell $procmux$237: Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] New connections: $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [63:1] = { $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] $0$memwr$\mem$hardware/v2/rtl/weight_buffer.v:41$226_EN[63:0]$230 [0] } Optimizing cells in module \weight_buffer. Performed a total of 1 changes. 2.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 6 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.13.9. Rerunning OPT passes. (Maybe there is more to do..) 2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \weight_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \weight_buffer. Performed a total of 0 changes. 2.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 6 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.13.13. Executing OPT_DFF pass (perform DFF optimizations). 2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.13.16. Finished fast OPT passes. (There is nothing left to do.) 2.14. Executing FSM pass (extract and optimize FSM). 2.14.1. Executing FSM_DETECT pass (finding FSMs in design). 2.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.15. Executing OPT pass (performing simple optimizations). 2.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 6 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \weight_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \weight_buffer. Performed a total of 0 changes. 2.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 6 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.15.6. Executing OPT_DFF pass (perform DFF optimizations). 2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.15.9. Finished fast OPT passes. (There is nothing left to do.) 2.16. Executing WREDUCE pass (reducing word size of cells). 2.17. Executing PEEPOPT pass (run peephole optimizers). 2.18. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.19. Executing SHARE pass (SAT-based resource sharing). 2.20. Executing TECHMAP pass (map to technology primitives). 2.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.20.2. Continuing TECHMAP pass. No more expansions possible. 2.21. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.22. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 2.23.2. Continuing TECHMAP pass. No more expansions possible. 2.24. Executing TECHMAP pass (map to technology primitives). 2.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 2.24.2. Continuing TECHMAP pass. No more expansions possible. 2.25. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module weight_buffer: created 0 $alu and 0 $macc cells. 2.26. Executing OPT pass (performing simple optimizations). 2.26.1. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.26.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 6 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \weight_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \weight_buffer. Performed a total of 0 changes. 2.26.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 6 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.26.6. Executing OPT_DFF pass (perform DFF optimizations). 2.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.26.8. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.26.9. Finished fast OPT passes. (There is nothing left to do.) 2.27. Executing MEMORY pass. 2.27.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing weight_buffer.mem write port 0. 2.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\mem'[0] in module `\weight_buffer': merging output FF to cell. Write port 0: non-transparent. 2.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. Removed 1 unused cells and 65 unused wires. 2.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory weight_buffer.mem via $__PDPW16KD_ 2.30. Executing TECHMAP pass (map to technology primitives). 2.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 2.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 2.30.3. Continuing TECHMAP pass. Using template $paramod$02d10cc8049219b734b94ed56325542341e7b150$__PDPW16KD_ for cells of type $__PDPW16KD_. No more expansions possible. 2.31. Executing OPT pass (performing simple optimizations). 2.31.1. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.31.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 10 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.31.3. Executing OPT_DFF pass (perform DFF optimizations). Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$323 ($dffe) from module weight_buffer. 2.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. Removed 0 unused cells and 30 unused wires. 2.31.5. Rerunning OPT passes. (Removed registers in this run.) 2.31.6. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.31.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 10 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.31.8. Executing OPT_DFF pass (perform DFF optimizations). 2.31.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.31.10. Finished fast OPT passes. 2.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.33. Executing OPT pass (performing simple optimizations). 2.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 10 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \weight_buffer.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \weight_buffer. Performed a total of 0 changes. 2.33.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 10 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.33.6. Executing OPT_DFF pass (perform DFF optimizations). 2.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.33.9. Finished fast OPT passes. (There is nothing left to do.) 2.34. Executing TECHMAP pass (map to technology primitives). 2.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 2.34.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $eq. No more expansions possible. 2.35. Executing OPT pass (performing simple optimizations). 2.35.1. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.35.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 224 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.35.3. Executing OPT_DFF pass (perform DFF optimizations). 2.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. Removed 0 unused cells and 1 unused wires. 2.35.5. Finished fast OPT passes. 2.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. 2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\weight_buffer'. Computing hashes of 224 cells of `\weight_buffer'. Finding duplicate cells in `\weight_buffer'. Removed a total of 0 cells. 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. No more expansions possible. 2.40. Executing OPT_EXPR pass (perform const folding). Optimizing module weight_buffer. 2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in weight_buffer. 2.43. Executing ATTRMVCP pass (move or copy attributes). 2.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \weight_buffer.. Removed 0 unused cells and 556 unused wires. 2.45. Executing CHECK pass (checking for obvious problems). Checking module weight_buffer... Found and reported 0 problems. 2.46. Executing TECHMAP pass (map to technology primitives). 2.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 2.46.2. Continuing TECHMAP pass. No more expansions possible. 2.47. Executing ABC9 pass. 2.47.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module weight_buffer. Found 0 SCCs. 2.47.4. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.5. Executing TECHMAP pass (map to technology primitives). 2.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.47.5.2. Continuing TECHMAP pass. No more expansions possible. 2.47.6. Executing OPT pass (performing simple optimizations). 2.47.6.1. Executing OPT_EXPR pass (perform const folding). 2.47.6.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 2.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 2.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 2.47.6.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 2.47.6.6. Executing OPT_DFF pass (perform DFF optimizations). 2.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2.47.6.8. Executing OPT_EXPR pass (perform const folding). 2.47.6.9. Finished fast OPT passes. (There is nothing left to do.) 2.47.7. Executing TECHMAP pass (map to technology primitives). 2.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 2.47.7.2. Continuing TECHMAP pass. No more expansions possible. 2.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 2.47.9. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.10. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.11. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.12. Executing AIGMAP pass (map logic to AIG). Module weight_buffer: replaced 81 cells with 543 new cells, skipped 143 cells. replaced 3 cell types: 64 $_MUX_ 8 $_OR_ 9 $_XOR_ not replaced 4 cell types: 1 $_AND_ 1 $_NOT_ 139 TRELLIS_FF 2 DP16KD 2.47.12.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.12.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.12.3. Executing XAIGER backend. Extracted 228 AND gates and 834 wires from module `weight_buffer' to a netlist network with 287 inputs and 139 outputs. 2.47.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). 2.47.12.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 287/ 139 and = 228 lev = 7 (0.97) mem = 0.01 MB box = 0 bb = 0 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 287/ 139 and = 423 lev = 6 (0.96) mem = 0.01 MB ch = 65 box = 0 bb = 0 ABC: cst = 0 cls = 65 lit = 65 unused = 580 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 423. Ch = 65. Total mem = 0.14 MB. Peak cut mem = 0.01 MB. ABC: P: Del = 1749.00. Ar = 90.0. Edge = 227. Cut = 993. T = 0.00 sec ABC: P: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 993. T = 0.00 sec ABC: P: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 1074. T = 0.00 sec ABC: F: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 988. T = 0.00 sec ABC: A: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 999. T = 0.00 sec ABC: A: Del = 1749.00. Ar = 88.0. Edge = 228. Cut = 999. T = 0.00 sec ABC: Total time = 0.00 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: Timing manager is given but there is no GIA of boxes. ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. ABC: + &ps -l ABC: /input : i/o = 287/ 139 and = 228 lev = 6 (0.96) mem = 0.01 MB box = 0 bb = 0 ABC: Mapping (K=7) : lut = 74 edge = 228 lev = 3 (0.48) mem = 0.00 MB ABC: LUT = 74 : 2=5 6.8 % 3=64 86.5 % 4=3 4.1 % 5=0 0.0 % 6=0 0.0 % 7=2 2.7 % Ave = 3.08 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.01 sec ABC: + time ABC: elapse: 0.01 seconds, total: 0.01 seconds 2.47.12.6. Executing AIGER frontend. Removed 319 unused cells and 671 unused wires. 2.47.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 74 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 5 Removing temp directory. 2.47.13. Executing TECHMAP pass (map to technology primitives). 2.47.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 2.47.13.2. Continuing TECHMAP pass. No more expansions possible. Removed 64 unused cells and 976 unused wires. 2.48. Executing TECHMAP pass (map to technology primitives). 2.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 2.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$9b75b992f20cd900c37cf6bf55004e096e50f153$lut for cells of type $lut. Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673$lut for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. Using template $paramod$5eae2dbc9c4e3a8910b7bdd34d688ce915a90667$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. No more expansions possible. 2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in weight_buffer. Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$2156$lut$aiger2155$320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 98 unused wires. 2.50. Executing AUTONAME pass. Renamed 407 objects in module weight_buffer. 2.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `weight_buffer'. Setting top module to weight_buffer. 2.51.1. Analyzing design hierarchy.. Top module: \weight_buffer 2.51.2. Analyzing design hierarchy.. Top module: \weight_buffer Removed 0 unused modules. 2.52. Printing statistics. === weight_buffer === +----------Local Count, excluding submodules. | 172 wires 499 wire bits 172 public wires 499 public wire bits 6 ports 148 port bits 2 cells 2 DP16KD 241 submodules 6 L6MUX21 88 LUT4 8 PFUMX 139 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 2 weight_buffer +----------Count including submodules. | 172 wires 499 wire bits 172 public wires 499 public wire bits 6 ports 148 port bits - memories - memory bits - processes 2 cells 2 DP16KD 241 submodules 6 L6MUX21 88 LUT4 8 PFUMX 139 TRELLIS_FF 2.53. Executing CHECK pass (checking for obvious problems). Checking module weight_buffer... Found and reported 0 problems. 2.54. Executing JSON backend. End of script. Logfile hash: bf6d270351, time: 0.32s, user: 0.29s, system: 0.01s, MEM: 30.56 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 54% 20x read_verilog (0 sec), 22% 11x techmap (0 sec), ...