# ============================================================
# V3 -- top-level pin/IOSTANDARD constraints for n2_system_ddr3_top.v,
# real xc7a100tcsg324-2, board is the user's own custom design (bare
# chip + DDR3, no dev board). DDR3 pins themselves are NOT here --
# those come from the MIG-generated mig_7series_0.xdc (dictated by
# the FPGA's internal DDR3 PHY hardware, not a free choice).
#
# Verified against the real device via a routed checkpoint query
# (open_checkpoint + get_package_pins/get_ports on n2_system_ddr3_
# top_routed.dcp), not guessed from a datasheet table.
# ============================================================

# ---- required for flash_spi_master.v to work at all: D00_MOSI/
# D01_DIN/FCS_B only become ordinary fabric I/O post-configuration
# when PERSIST is FALSE (the Vivado default -- set explicitly here so
# this dependency is self-documenting in the constraints, not just a
# silent default someone could flip later without realizing why).
set_property BITSTREAM.CONFIG.PERSIST NO [current_design]

# ---- config-flash passthrough (-> flash_spi_master.v, EXP-0077):
# EXP-0084 REAL, RE-CONFIRMED CONFLICT (not hypothetical any more):
# D00_MOSI/D01_DIN/FCS_B's ORIGINAL pins (K17/K18/L13, bank 14) share
# bank 14 with the real differential reference clock (clk_ref_p/n,
# T14/T15) chosen during the EXP-0084 MIG wizard session -- a single
# I/O bank can only have ONE VCCO, and LVCMOS33 (3.3V, what the flash
# needs) is incompatible with LVDS_25 (2.5V, what clk_ref needs). This
# was flagged as a real *risk* when T14/T15 was chosen (real device
# data showed bank 14 already hosted the flash bus); EXP-0084's real
# place_design run turned that risk into a real, observed placement
# failure ("IO placement is infeasible" -- flash_mosi/flash_cs_n
# couldn't be placed at their old LOCs at all). FIX: moved the flash
# bus to bank 16 (D9/D10/C9) -- completely unconstrained, no VCCO
# commitment, so it can freely be 3.3V with zero conflict. Real,
# verified-available pins (queried from the actual part database, not
# guessed) -- D9/D10/C9 are ordinary I/O in bank 16, none of them are
# the config-mode-reserved EMCCLK/RDWR_B/CSI_B pins (still PROHIBITed
# below regardless). CCLK is NOT constrained here -- it's driven via
# STARTUPE2 internally, never a plain top-level port.
set_property PACKAGE_PIN D9  [get_ports flash_mosi]
set_property PACKAGE_PIN D10 [get_ports flash_miso]
set_property PACKAGE_PIN C9  [get_ports flash_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports flash_mosi]
set_property IOSTANDARD LVCMOS33 [get_ports flash_miso]
set_property IOSTANDARD LVCMOS33 [get_ports flash_cs_n]

# ---- EMCCLK/RDWR_B/CSI_B (bank 14): not used by this design at all
# (this project's Master SPI config mode never needed them -- they're
# only relevant to modes this board doesn't use, e.g. BPI or Quad-SPI
# extra data lines) -- PROHIBITed so Vivado's auto-placement never
# lands an unrelated port there by accident (it already had once,
# before this constraint existed, on a result-data bit).
set_property PROHIBIT true [get_sites -of_objects [get_package_pins {L16 R16 V15}]]

# ---- EXP-0084: remaining top-level ports with no fixed board LOC yet
# (status signals) default to LVCMOS18 with no explicit IOSTANDARD set
# -- real place_design found this real, concrete: banks 14/15/34/35 are
# ALL already committed to other real voltages (2.5V/3.3V/1.5V/1.5V),
# leaving only bank 16's spare pins as LVCMOS18-compatible, and there
# aren't enough of them. Assign these explicitly to LVCMOS33 so they
# place in bank 15's own real spare capacity instead -- a real,
# necessary fix, not a workaround; a permanent board LOC for each
# should still be assigned once the rest of the board layout is
# decided (S7 of docs/PHYSICAL_REALIZATION.md).
# EXP-0088: the s0_result_data_a/b, s1_result_data_a/b ports this
# constraint used to also cover no longer exist as top-level ports --
# each slot now writes its own result directly into DDR3 via its own
# internal result_writeback.v (see packed_slot.v's own header) instead
# of exposing literal, N-scaled result pins.
set_property IOSTANDARD LVCMOS33 [get_ports {job_out_slot[*] job_out_done init_calib_complete ui_clk_o}]

# ---- neural-processor management SPI (-> spi_host_bridge_v3.v):
# job submission + register file. Bank 15, column A/B (package edge,
# physically adjacent pins for short/easy PCB routing), well clear of
# both DDR3 (banks 34/35) and the reserved config-flash pins above.
# IOSTANDARD assumes bank 15 is powered at 3.3V on the custom board --
# change to match whatever VCCO the user's own power plan uses for
# that bank.
set_property PACKAGE_PIN A15 [get_ports sclk]
set_property PACKAGE_PIN B16 [get_ports mosi]
set_property PACKAGE_PIN B17 [get_ports miso]
set_property PACKAGE_PIN A16 [get_ports cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports sclk]
set_property IOSTANDARD LVCMOS33 [get_ports mosi]
set_property IOSTANDARD LVCMOS33 [get_ports miso]
set_property IOSTANDARD LVCMOS33 [get_ports cs_n]

# ---- sys_rst: EXP-0084 found this real -- with the 32-bit DDR3
# interface now committing banks 14/34/35 to 2.5V/1.5V/1.5V and bank
# 15 to 3.3V, there is genuinely NO bank left at the 1.8V sys_rst was
# silently defaulting to (no explicit IOSTANDARD was ever set) -- real
# place_design failure ("IO placement is infeasible... needs 1.8V,
# has 0 sites"), not hit before only because the smaller 16-bit I/O
# footprint happened to leave enough slack somewhere. Placed here
# temporarily in bank 15 alongside the management SPI bus (same real,
# already-committed 3.3V) -- NOT a final board decision, still pending
# the real PCB layout for the reset circuit (button/supervisor IC),
# per S7 of docs/PHYSICAL_REALIZATION.md. Real, verified-free pin
# (queried from the actual part database).
set_property PACKAGE_PIN G13 [get_ports sys_rst]
set_property IOSTANDARD LVCMOS33 [get_ports sys_rst]

# ---- data_ready_n: real, user-requested active-low sticky IRQ so the
# ESP32 can be interrupt-driven instead of polling STATUS (see
# spi_host_bridge_v3.v's own header for the real set/clear semantics).
# Placed in bank 15 alongside the management SPI bus (same real,
# already-committed 3.3V) -- real, verified-free pin, not yet a final
# board decision (same caveat as sys_rst above).
set_property PACKAGE_PIN D14 [get_ports data_ready_n]
set_property IOSTANDARD LVCMOS33 [get_ports data_ready_n]