# V2 synthesis log -- solo append, mai troncato/sovrascritto (vedi README.md)
# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.

[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
LUT: 55  FF: 533  DSP(MULT18X18D): 8  BRAM: 0  CCU2C: 96
CHECK: 0 problems. 36 warnings, all "multiple conflicting drivers for
  neural_processor.\gi" -- benign Yosys quirk for an `integer` used as
  a synthesizable for-loop index in stage 0's unrolled always block,
  not a real multi-driver conflict (cross-verified functionally
  correct on 2 independent simulators). Log: hardware/v2/synthesis/
  neural_processor_p8/yosys.log

[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
LUT: 49  FF: 509  DSP(MULT18X18D): 8  BRAM: 0  CCU2C: 88
CHECK: 0 problems, same 36 benign warnings as EXP-0001.
Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log

[2026-09-05] EXP-0003 -- neural_processor_array via
  harness_neural_processor_array.v (synthesis-only wrapper, see
  errors.log ERR-0005), N_PROCESSORS in {1,2,4,8}, P_IN=8
N=1: LUT=59  FF=409  MULT18X18D=8   CCU2C=96
N=2: LUT=106 FF=786  MULT18X18D=16  CCU2C=192
N=4: LUT=207 FF=1540 MULT18X18D=32  CCU2C=384
N=8: LUT=374 FF=3048 MULT18X18D=64  CCU2C=768
CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
  N confirms no unintended cross-processor resource sharing (a first,
  flawed harness attempt fed identical data to every processor/lane
  and Yosys silently deduplicated down to 1x regardless of N -- caught
  by checking for exactly this linearity before trusting the numbers).

[2026-09-05] EXP-0004 -- activation_buffer/weight_buffer/result_buffer,
2 depths each
activation_buffer D=4096: LUT=37 FF=30  DP16KD=2  (D=256: LUT=21 FF=26 DP16KD=1)
weight_buffer     D=512:  LUT=88 FF=139 DP16KD=2  (D=64:  LUT=73 FF=136 DP16KD=2)
result_buffer     D=4096: LUT=37 FF=30  DP16KD=2  (D=256: LUT=21 FF=26 DP16KD=1)
CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM
  fallback). weight_buffer's DP16KD count does NOT drop with depth
  (width-bound, not depth-bound -- see decisions.log / benchmark.log).

[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (standalone)
LUT4=851  TRELLIS_FF=789  CCU2C=108  MULT18X18D=0 (expected, no
  multiplication in this module). CHECK: 0 problems.

[2026-09-05] EXP-0006 -- neural_director (N_SLOTS=4, standalone)
LUT4=382  TRELLIS_FF=366  CCU2C=4  DSP=0. CHECK: 0 problems.

[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, MAX_DEPS=4)
LUT4=763  TRELLIS_FF=474  CCU2C=0  DSP=0. CHECK: 0 problems.

[2026-09-05] EXP-0008 -- dataflow_core (M7 full integration, via
harness_dataflow_core.v -- see errors.log ERR-0005 for why a harness
is needed: bare per-slot Memory Backend Interface ports alone total
280 bits at N_SLOTS=4, exceeding the LFE5U-45F-8BG381's ~245 TRELLIS_IO
budget)
N_SLOTS=2: LUT4=2127  CCU2C=248  TRELLIS_FF=2505  MULT18X18D=16  DP16KD=0
N_SLOTS=4: LUT4=3953  CCU2C=500  TRELLIS_FF=4688  MULT18X18D=32  DP16KD=0
CHECK: 0 problems on both configs (same 32 benign "multiple conflicting
  drivers for ...neural_processor.\gi" warnings per neural_processor
  instance already documented in EXP-0001 -- an `integer` for-loop
  index shared across two of neural_processor's own always blocks, not
  a real multi-driver conflict). DP16KD=0 on both is expected: M3's
  BRAM-backed buffers (activation/weight/result_buffer) are
  deliberately NOT instantiated inside dataflow_core yet (decisions.log
  DEC-0009). DSP scales exactly 8/slot (matches P_IN=8, consistent with
  every prior per-processor DSP measurement since M1/M2).