# FPGA-Neural V3 — Bill of Materials

Real component list for the custom PCB (bare **XC7A100T-CSG324-2** + DDR3,
no dev board). Every line below is either **confirmed real and in-stock**
(part number + LCSC link, verified) or explicitly flagged as **needs the
user's own real sourcing check** — never a guessed/invented part number,
per this project's own standing discipline (CLAUDE.md: "verify real
component availability before committing to a part"). See
`docs/PINOUT.md` for how each part's pins map to the FPGA, and
`docs/PHYSICAL_REALIZATION.md` §1/§3 for the real, closed timing signoff
these frequency requirements are derived from (EXP-0086).

## Core, confirmed parts (verified in earlier sessions)

| # | Component | Part | Qty | Notes |
|---|---|---|---|---|
| 1 | FPGA | **XC7A100T-CSG324-2** | 1 | Speed grade -2. Real, closed timing signoff at this exact part (EXP-0086, WNS=+0.096ns). |
| 2 | DDR3 SDRAM | **Micron MT41J128M16JT-125:K** (2Gb, x16, DDR3-1600-rated) | **2** | Two chips ganged in parallel for the real 32-bit channel (EXP-0084/0086) — address/command/control shared, DQ/DQS/DM split 16 bits each. Verified in-stock on LCSC (earlier session). |
| 3 | Config flash | **Winbond W25Q32JVSSIQ** (32Mbit, SOIC-8) | 1 | Verified in-stock on LCSC (earlier session). Wired exclusively to the FPGA (no direct ESP32 connection). |

## Clocking — real, firm frequency requirements from the closed MIG config

| # | Component | Requirement | Status |
|---|---|---|---|
| 4 | `sys_clk_p/n` differential oscillator | **310.077 MHz**, differential (DIFF_SSTL15-compatible I/O, e.g. LVDS/LVPECL/HCSL) | **Not a stock catalog part at this exact frequency.** Real candidate family: **SiTime SiT9122** (220–625 MHz MEMS oscillator, factory-programmable to any exact in-band frequency including 310.077 MHz) — but a custom-programmed frequency is order-to-spec, not an off-the-shelf SKU; typical low-MOQ, ~1–2 week lead time. **Needs the user's own real quote/order to get a firm LCSC SKU.** This exact frequency is a real, non-negotiable output of the Vivado MIG JEDEC/PLL calculator — do not substitute a different frequency without re-running the real MIG wizard (TimePeriod/InputClkFreq are tied together). |
| 5 | `clk_ref_p/n` differential oscillator | **200 MHz**, differential, LVDS (matches the LVDS_25 IOSTANDARD already assigned in the XDC) | **Confirmed real, in-stock**: **SiTime SiT9121AC-2CF-33E-200.00000**, LCSC **[C835051](https://lcsc.com/product-detail/programmable-oscillators_sitime-sit9121ac-2cf-33e-200-00000_C835051.html)**, 3.3V LVDS, factory-preset at exactly 200.000000 MHz, "In Stock". |

## Host MCU

| # | Component | Part | Status |
|---|---|---|---|
| 6 | ESP32 module (host/central processor) | **ESP32-S3-WROOM-1-N16R8** | **Confirmed real, in-stock**: LCSC **[C2913202](https://www.lcsc.com/product-detail/WiFi-Modules_Espressif-Systems-ESP32-S3-WROOM-1-N16R8_C2913202.html)**, ~8,375 units in stock at time of check, ~$5.09 ea. 45 GPIOs (real design needs only ~10: 4 for management SPI + sys_rst + data_ready_n + 4 for JTAG bit-banging, leaving generous headroom for debug UART etc.), 16MB flash + 8MB PSRAM, dual-core. No specific ESP32 module had been chosen anywhere in this project before now — this is a new real recommendation, not a previously-verified part. |

## DDR3 support (real design consideration, not yet a firm requirement)

| # | Component | Purpose | Status |
|---|---|---|---|
| 7 | VTT termination regulator (optional) | Sink/source termination for the DDR3 address/command/control/clock bus in fly-by topology — DQ/DQS lines use on-die termination and need no external parts. With 2 chips extending the fly-by chain, signal integrity margin may benefit from this. | Real, standard part for this role: **TI TPS51200**. Whether it's genuinely *needed* here is a **real, design-dependent judgment call** — depends on trace lengths, not established by this project's own work (no SI simulation has been done). One TPS51200 can typically supply 2 DDR3 chips sharing a rail per TI's own guidance, though thermal margin may favor one per chip. **Not confirmed in-stock this pass — treat as optional/TBD**, not a committed BOM line. |

## Power regulation (starting point only, not a full power-tree design)

| # | Component | Purpose | Status |
|---|---|---|---|
| 8 | VCCINT 1.0V regulator | FPGA core rail, the tightest-tolerance (~±5% per the Xilinx datasheet) and highest-current rail | Real, commonly-used candidate for Artix-7 designs: **Infineon IR38060** (integrated SupIRBuck, up to 6A) — appears in real Xilinx 7-series reference designs. **Stock not confirmed this pass.** |
| 9 | VCCAUX 1.8V, VCCO per-bank (1.5V DDR3 banks 34/35, 2.5V bank 14, 3.3V banks 15/16) | Remaining FPGA/DDR3 rails | **Not yet sourced** — only the tightest rail (VCCINT) was researched this pass; the rest of the power tree is a real, remaining task. |

## Known open items (honestly disclosed)

- **Line 4 (sys_clk oscillator)** is the real, highest-risk sourcing item —
  no confirmed off-the-shelf SKU exists at the exact required frequency.
  Get a real quote from SiTime (or an equivalent programmable-oscillator
  vendor) before finalizing the BOM; a firm lead time affects build
  scheduling.
- **Lines 7, 8, 9** need a real stock/price check before ordering — parts
  named are real, plausible candidates, not yet individually confirmed
  in-stock the way lines 1–3, 5, 6 are.
- Passive components (decoupling capacitors, pull-up/pull-down resistors
  for the mode pins M[2:0]/CFGBVS, JTAG series resistors) are not itemized
  here — standard values per the Xilinx UG470/UG483 reference design
  guidance, not yet compiled into this BOM.
- This BOM does not include PCB fabrication, connectors, or enclosure
  items — scope is components only.