# V2 timing log -- solo append, mai troncato/sovrascritto (vedi README.md) # Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2. [2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32) nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained Fmax: 183.12 MHz -- PASS at 80 MHz (real place&route measurement) Critical path: job_ready -> TRELLIS_IO output pad (i.e. the design's own logic is NOT the bottleneck at this Fmax -- an unconstrained output pin dominates; a real system-level Fmax will differ once this signal is consumed on-chip instead of driven to a pad in isolation). Log: hardware/v2/synthesis/neural_processor_p8/nextpnr.log WNS/TNS: not reported by this nextpnr version in this invocation. [2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24) Same command as above, ACC_WIDTH=24 build. Fmax: 176.21 MHz -- PASS at 80 MHz (real place&route measurement) Delta vs ACC_WIDTH=32: -6.91 MHz (-3.8%) despite FEWER resources -- attributed to placement noise, not a real architectural effect (no seed sweep run to confirm either way -- see experiments.log EXP-0002 and benchmark.log). Log: hardware/v2/synthesis/ neural_processor_p8_acc24/nextpnr.log [2026-09-05] EXP-0003 -- N_PROCESSORS sweep (P_IN=8), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained N=1: Fmax=159.11 MHz PASS MULT18X18D 8/72 (11%) N=2: Fmax=149.59 MHz PASS MULT18X18D 16/72 (22%) N=4: Fmax=151.01 MHz PASS MULT18X18D 32/72 (44%) N=8: Fmax=134.70 MHz PASS MULT18X18D 64/72 (88%) TRELLIS_IO stays at 18/245 (7%) throughout (harness has only clk/rst/seed/checksum as real pins, by design -- see ERR-0005). See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource that will first prevent scaling N_PROCESSORS further at P_IN=8. [2026-09-05] EXP-0004 -- default-depth buffer configs, real nextpnr-ecp5 activation_buffer (D=4096): Fmax=325.20 MHz PASS weight_buffer (D=512): Fmax=339.67 MHz PASS result_buffer (D=4096): Fmax=325.20 MHz PASS All far above the 80MHz target -- buffers are not a timing concern in isolation at these depths. [2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (via harness_memory_manager.v, see errors.log ERR-0005 for why a harness was needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained Fmax: 165.86 MHz -- PASS at 80MHz (real place&route measurement) [2026-09-05] EXP-0006 -- neural_director (via harness_neural_director.v, see errors.log ERR-0005 for why), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained Fmax: 250.50 MHz -- PASS at 80MHz (real place&route measurement) [2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, standalone, no harness needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained Fmax: 155.30 MHz -- PASS at 80MHz (real place&route measurement) [2026-09-05] EXP-0008 -- dataflow_core (via harness_dataflow_core.v, see errors.log ERR-0005 for why a harness was needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained N_SLOTS=2: Fmax = 165.15 MHz -- PASS at 80MHz (real place&route) N_SLOTS=4: Fmax = 133.19 MHz -- PASS at 80MHz (real place&route) Fmax drops as N_SLOTS grows (more concurrent memory_manager+ neural_processor instances competing for the same routing fabric around the shared neural_director/dependency_manager hub) -- both configs still clear the 80MHz target with real margin. [2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real standalone synthesis, no harness needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained Fmax: 142.45 MHz -- PASS at 80MHz (real place&route measurement) [2026-09-05] EXP-0011 -- dataflow_core N_SLOTS=8 (via harness_dataflow_core.v), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained Fmax: 92.63 MHz -- PASS at 80MHz (real place&route measurement), but with a much thinner margin than N_SLOTS=2 (165.15 MHz) or N_SLOTS=4 (133.19 MHz) -- Fmax falls monotonically with N_SLOTS (165.15 -> 133.19 -> 92.63 MHz for N_SLOTS=2/4/8) as routing congestion around the shared neural_director/dependency_manager hub grows, while DSP usage (88.9% at N_SLOTS=8) approaches its hard ceiling at the same time -- see decisions.log DEC-0012. [2026-09-05] EXP-0012 -- ACC_WIDTH 24 vs 32 real placement-seed sweep (M10, "pipeline" axis, resolving EXP-0002's single-seed inconclusiveness), 5 additional real nextpnr-ecp5 seeds (1-5) plus the original default-seed run (EXP-0001/EXP-0002), same synthesized netlists (hardware/v2/synthesis/neural_processor_p8/top.json and neural_processor_p8_acc24/top.json), --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained ACC_WIDTH=32: seeds [default,1,2,3,4,5] -> [183.12, 164.85, 174.25, 168.83, 183.96, 145.73] MHz. n=6, mean=170.12 MHz, min=145.73 MHz, max=183.96 MHz, stdev=14.16 MHz. ACC_WIDTH=24: seeds [default,1,2,3,4,5] -> [176.21, 183.72, 180.57, 183.08, 185.49, 175.16] MHz. n=6, mean=180.71 MHz, min=175.16 MHz, max=185.49 MHz, stdev=4.21 MHz. Conclusion: over 6 real placement seeds, ACC_WIDTH=24 has a HIGHER mean Fmax (+10.6 MHz, +6.2%) AND a much lower seed-to-seed variance (stdev 4.21 vs 14.16 MHz, ~3.4x tighter) than ACC_WIDTH=32 -- EXP-0002's single-seed result (176.21 < 183.12, i.e. ACC=24 looked WORSE) was placement-seed noise, not a real trend. See decisions.log DEC-0013. [2026-09-05] EXP-0014 -- neural_multiprocessor N_SLOTS=1 and N_SLOTS=4 (final benchmark campaign), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained N_SLOTS=1: Fmax = 152.46 MHz -- PASS at 80MHz N_SLOTS=4: Fmax = 113.38 MHz -- PASS at 80MHz (N_SLOTS=2 reference, EXP-0009: 142.45 MHz) Full real N_SLOTS sweep for the complete system (dataflow_core + real V1 PSRAM chain + slot_mem_arbiter): 1 -> 152.46 MHz, 2 -> 142.45 MHz, 4 -> 113.38 MHz. Fmax falls monotonically as N_SLOTS grows (more routing congestion around the shared director/dependency_manager/ arbiter hub), exactly the same trend already observed for dataflow_core alone (M7/M10, EXP-0008/EXP-0011) but now measured for the REAL FULL SYSTEM including the real PSRAM backend. [2026-09-05] EXP-0015 -- neural_multiprocessor N_SLOTS=1/2/4 after the word-level burst-read rewrite (DEC-0015), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained N_SLOTS=1: Fmax = 152.44 MHz -- PASS at 80MHz (was 152.46 MHz, unchanged) N_SLOTS=2: Fmax = 133.58 MHz -- PASS at 80MHz (was 142.45 MHz, -6.2%) N_SLOTS=4: Fmax = 112.07 MHz -- PASS at 80MHz (was 113.38 MHz, -1.2%) Small, real Fmax cost from widening the shared arbiter/backend to 16-bit + lb_n/ub_n (extra routing), overwhelmingly outweighed by the real cycle-count reduction (EXP-0015 in experiments.log/benchmark.log): D-Stress real wall-clock improves 2.24-2.37x at every N_SLOTS. [2026-09-05] EXP-0016 -- neural_multiprocessor N_SLOTS=1/2/4 after adding activation_cache.v (DEC-0016), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained N_SLOTS=1: Fmax = 131.79 MHz -- PASS at 80MHz (was 152.44 MHz, -13.5%) N_SLOTS=2: Fmax = 87.72 MHz -- PASS at 80MHz (was 133.58 MHz, -34.3%) N_SLOTS=4: Fmax = 65.01 MHz -- FAILS at 80MHz (was 112.07 MHz, -42.0%) Real, substantial Fmax cost from the shared activation_cache -- a single central resource with N_SLOTS request ports, a broadcast- capable hit-check evaluated every cycle for every port, and a shared tile_store array. Cost grows much faster with N_SLOTS than DEC-0015's own arbiter widening did. N_SLOTS=4 is no longer a passing 80MHz design point with the cache active -- see decisions.log DEC-0016 for the full analysis and why N_SLOTS=2 (the recommended default, DEC-0014) is unaffected in its own recommendation. [2026-09-15] EXP-0049 -- fpga_neural_v2_top (real board-level top, N_SLOTS=4), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 --lpf hardware/v2/constraints/v2_board_top.lpf (real ball-assigned pins; internal 64MHz clock domain derived from EHXPLLL's own FREQUENCY_PIN_CLKI=16/CLKOP=64 attributes, no --freq needed), fresh 8-seed sweep Fmax (clock net off sdram_clk/EHXPLLL CLKOP, PASS bar 64MHz): seed0 81.20, seed1 98.82, seed2 88.25, seed3 92.43, seed4 94.22, seed5 86.95, seed6 96.01, seed7 90.55 MHz. n=8, worst=81.20 MHz, mean=91.05 MHz, 8/8 PASS at 64MHz. BASELINE row for the new N=8-timing/85F-retarget/SDRAM-bank-sweep brief (Phase 0). RTL is bit-identical to DEC-0042's own frozen N_SLOTS=4 production state (no RTL changes since, only docs commits) -- this measurement is against the SAME dependency_manager.v pending_count fix DEC-0042 itself introduced. DISCLOSED, UNRESOLVED DISCREPANCY vs DEC-0042's own recorded N_SLOTS=4 @ 64MHz numbers (worst-seed 64.55MHz, best-seed 77.21MHz, 8/8 PASS): this session's worst-seed (81.20MHz) exceeds DEC-0042's own best-seed. Both this session's ERR-0030 (stale 80MHz LPF frequency) and ERR-0031 (wrong top-level target, the obsolete nms_neural_multiprocessor_ sdram_unified.v wrapper) were real, found-and-fixed mistakes made earlier in this same session while trying to reproduce the baseline -- but after correcting BOTH (real fpga_neural_v2_top.v target, real v2_board_top.lpf, verified 8/8 PASS at 64MHz, single-seed sanity check of 72.23MHz independently reproduced close to DEC-0042's range before this full 8-seed run), the full sweep still came out systematically higher than DEC-0042's historical numbers. No further RTL/config difference was found (same file list role, same default parameters: N_NODES=16, MAX_TILES=16, QUEUE_DEPTH=8, PREFETCH_DISTANCE=8). Leading hypothesis, NOT verified: nextpnr-ecp5 build/version difference between this session's toolchain (OSS CAD Suite, nextpnr-0.11.1-27-g6030081a) and whatever build produced DEC-0042's numbers (version not recorded in any prior log entry) -- placer heuristics/effort can genuinely differ across nextpnr releases for the same netlist+constraints. DECISION: treat THIS session's 8-seed numbers (worst 81.20MHz, mean 91.05MHz, 8/8 PASS) as the operative Phase-0 BASELINE for judging Phase 1 interventions going forward, since they are the ones this session's own toolchain will keep reproducing -- but do not claim DEC-0042's specific historical numbers are wrong; both may be real under their own respective toolchains. See sweep_results.md (Phase 4) BASELINE row. STATUS: N_SLOTS=4 baseline established (8/8 PASS @ 64MHz, real board-level top+constraints). N_SLOTS=8 baseline deferred (user request, 2026-09-15) after an N=8 P&R run against the WRONG target (the obsolete wrapper, since discarded) stalled for 2h42m without converging on a single seed -- to be re-attempted against the correct fpga_neural_v2_top target, with a time budget decided before re-running.