/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Parsing `rtl/spi_neuron_top.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: rtl/spi_neuron_top.v Parsing Verilog input from `rtl/spi_neuron_top.v' to AST representation. Storing AST representation for module `$abstract\spi_neuron_top'. Successfully finished Verilog frontend. -- Parsing `rtl/spi_slave.v' using frontend ` -vlog2k' -- 2. Executing Verilog-2005 frontend: rtl/spi_slave.v Parsing Verilog input from `rtl/spi_slave.v' to AST representation. Storing AST representation for module `$abstract\spi_slave'. Successfully finished Verilog frontend. -- Parsing `rtl/spi_engine.v' using frontend ` -vlog2k' -- 3. Executing Verilog-2005 frontend: rtl/spi_engine.v Parsing Verilog input from `rtl/spi_engine.v' to AST representation. Storing AST representation for module `$abstract\spi_engine'. Successfully finished Verilog frontend. -- Parsing `rtl/flash_slot_manager.v' using frontend ` -vlog2k' -- 4. Executing Verilog-2005 frontend: rtl/flash_slot_manager.v Parsing Verilog input from `rtl/flash_slot_manager.v' to AST representation. Storing AST representation for module `$abstract\flash_slot_manager'. Successfully finished Verilog frontend. -- Parsing `rtl/flash_copy_engine.v' using frontend ` -vlog2k' -- 5. Executing Verilog-2005 frontend: rtl/flash_copy_engine.v Parsing Verilog input from `rtl/flash_copy_engine.v' to AST representation. Storing AST representation for module `$abstract\flash_copy_engine'. Successfully finished Verilog frontend. -- Parsing `rtl/crc32.v' using frontend ` -vlog2k' -- 6. Executing Verilog-2005 frontend: rtl/crc32.v Parsing Verilog input from `rtl/crc32.v' to AST representation. Storing AST representation for module `$abstract\crc32_byte'. Successfully finished Verilog frontend. -- Parsing `rtl/spi_flash_master.v' using frontend ` -vlog2k' -- 7. Executing Verilog-2005 frontend: rtl/spi_flash_master.v Parsing Verilog input from `rtl/spi_flash_master.v' to AST representation. Storing AST representation for module `$abstract\spi_flash_master'. Successfully finished Verilog frontend. -- Parsing `rtl/layer_sequencer.v' using frontend ` -vlog2k' -- 8. Executing Verilog-2005 frontend: rtl/layer_sequencer.v Parsing Verilog input from `rtl/layer_sequencer.v' to AST representation. Storing AST representation for module `$abstract\layer_sequencer'. Successfully finished Verilog frontend. -- Parsing `rtl/graph_engine.v' using frontend ` -vlog2k' -- 9. Executing Verilog-2005 frontend: rtl/graph_engine.v Parsing Verilog input from `rtl/graph_engine.v' to AST representation. Storing AST representation for module `$abstract\graph_engine'. Successfully finished Verilog frontend. -- Parsing `rtl/act_buffer.v' using frontend ` -vlog2k' -- 10. Executing Verilog-2005 frontend: rtl/act_buffer.v Parsing Verilog input from `rtl/act_buffer.v' to AST representation. Storing AST representation for module `$abstract\act_buffer'. Successfully finished Verilog frontend. -- Parsing `rtl/neuron_memory.v' using frontend ` -vlog2k' -- 11. Executing Verilog-2005 frontend: rtl/neuron_memory.v Parsing Verilog input from `rtl/neuron_memory.v' to AST representation. Storing AST representation for module `$abstract\neuron_memory'. Successfully finished Verilog frontend. -- Parsing `rtl/neuron_parallel.v' using frontend ` -vlog2k' -- 12. Executing Verilog-2005 frontend: rtl/neuron_parallel.v Parsing Verilog input from `rtl/neuron_parallel.v' to AST representation. Storing AST representation for module `$abstract\neuron_parallel'. Successfully finished Verilog frontend. -- Parsing `rtl/mac8.v' using frontend ` -vlog2k' -- 13. Executing Verilog-2005 frontend: rtl/mac8.v Parsing Verilog input from `rtl/mac8.v' to AST representation. Storing AST representation for module `$abstract\mac8'. Successfully finished Verilog frontend. -- Parsing `rtl/mac_unit.v' using frontend ` -vlog2k' -- 14. Executing Verilog-2005 frontend: rtl/mac_unit.v Parsing Verilog input from `rtl/mac_unit.v' to AST representation. Storing AST representation for module `$abstract\mac_unit'. Successfully finished Verilog frontend. -- Parsing `rtl/layer.v' using frontend ` -vlog2k' -- 15. Executing Verilog-2005 frontend: rtl/layer.v Parsing Verilog input from `rtl/layer.v' to AST representation. Storing AST representation for module `$abstract\layer'. Successfully finished Verilog frontend. -- Parsing `rtl/mem_arbiter.v' using frontend ` -vlog2k' -- 16. Executing Verilog-2005 frontend: rtl/mem_arbiter.v Parsing Verilog input from `rtl/mem_arbiter.v' to AST representation. Storing AST representation for module `$abstract\mem_arbiter'. Successfully finished Verilog frontend. -- Parsing `rtl/int8_memory_access.v' using frontend ` -vlog2k' -- 17. Executing Verilog-2005 frontend: rtl/int8_memory_access.v Parsing Verilog input from `rtl/int8_memory_access.v' to AST representation. Storing AST representation for module `$abstract\int8_memory_access'. Successfully finished Verilog frontend. -- Parsing `rtl/memory_interface.v' using frontend ` -vlog2k' -- 18. Executing Verilog-2005 frontend: rtl/memory_interface.v Parsing Verilog input from `rtl/memory_interface.v' to AST representation. Storing AST representation for module `$abstract\memory_interface'. Successfully finished Verilog frontend. -- Parsing `rtl/psram_controller.v' using frontend ` -vlog2k' -- 19. Executing Verilog-2005 frontend: rtl/psram_controller.v Parsing Verilog input from `rtl/psram_controller.v' to AST representation. rtl/psram_controller.v:191: Warning: Yosys has only limited support for tri-state logic at the moment. Storing AST representation for module `$abstract\psram_controller'. Successfully finished Verilog frontend. -- Running command `synth_ecp5 -json synth/ecp5/post_fix_verify/top.json -top spi_neuron_top' -- 20. Executing SYNTH_LATTICE pass. 20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 20.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 20.3. Executing HIERARCHY pass (managing design hierarchy). 20.4. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_neuron_top'. Generating RTLIL representation for module `\spi_neuron_top'. 20.4.1. Analyzing design hierarchy.. Top module: \spi_neuron_top Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 16 Parameter \CLK_FREQ_MHZ = 80 20.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\psram_controller'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 16 Parameter \CLK_FREQ_MHZ = 80 Generating RTLIL representation for module `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 16 20.4.3. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_interface'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 16 Generating RTLIL representation for module `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface'. Parameter \ADDR_WIDTH = 23 20.4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\int8_memory_access'. Parameter \ADDR_WIDTH = 23 Generating RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'. Parameter \ADDR_WIDTH = 23 20.4.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_arbiter'. Parameter \ADDR_WIDTH = 23 Generating RTLIL representation for module `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \N_NEURONS = 1 Parameter \PARALLEL = 8 Parameter \ACC_WIDTH = 32 20.4.6. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_memory'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \N_NEURONS = 1 Parameter \PARALLEL = 8 Parameter \ACC_WIDTH = 32 Generating RTLIL representation for module `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Parameter \PARALLEL = 8 Parameter \MAX_CONN = 32 Parameter \N_TOTAL = 4096 20.4.7. Executing AST frontend in derive mode using pre-parsed AST for module `\graph_engine'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Parameter \PARALLEL = 8 Parameter \MAX_CONN = 32 Parameter \N_TOTAL = 4096 Generating RTLIL representation for module `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 8 Parameter \N_WIDTH = 1 Parameter \N_LAYERS = 4 20.4.8. Executing AST frontend in derive mode using pre-parsed AST for module `\layer_sequencer'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 8 Parameter \N_WIDTH = 1 Parameter \N_LAYERS = 4 Generating RTLIL representation for module `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer'. Parameter \PSRAM_ADDR_WIDTH = 23 Parameter \CLK_FREQ_MHZ = 80 20.4.9. Executing AST frontend in derive mode using pre-parsed AST for module `\flash_slot_manager'. Parameter \PSRAM_ADDR_WIDTH = 23 Parameter \CLK_FREQ_MHZ = 80 Generating RTLIL representation for module `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \N_NEURONS = 1 Parameter \PARALLEL = 8 Parameter \N_TOTAL = 4096 20.4.10. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_engine'. Parameter \ADDR_WIDTH = 23 Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \N_NEURONS = 1 Parameter \PARALLEL = 8 Parameter \N_TOTAL = 4096 Generating RTLIL representation for module `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine'. 20.4.11. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_slave'. Generating RTLIL representation for module `\spi_slave'. 20.4.12. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer Used module: $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine Used module: \spi_slave Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \PARALLEL = 8 Parameter \ACC_WIDTH = 32 20.4.13. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'. Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \PARALLEL = 8 Parameter \ACC_WIDTH = 32 Generating RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'. Parameter \ADDR_WIDTH = 23 Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'. Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \PARALLEL = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'. Parameter \N_TOTAL = 4096 Parameter \DATA_WIDTH = 8 20.4.14. Executing AST frontend in derive mode using pre-parsed AST for module `\act_buffer'. Parameter \N_TOTAL = 4096 Parameter \DATA_WIDTH = 8 Generating RTLIL representation for module `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer'. 20.4.15. Executing AST frontend in derive mode using pre-parsed AST for module `\crc32_byte'. Generating RTLIL representation for module `\crc32_byte'. Parameter \PSRAM_ADDR_WIDTH = 23 Parameter \CLK_FREQ_MHZ = 80 Parameter \SCLK_DIV = 2 20.4.16. Executing AST frontend in derive mode using pre-parsed AST for module `\flash_copy_engine'. Parameter \PSRAM_ADDR_WIDTH = 23 Parameter \CLK_FREQ_MHZ = 80 Parameter \SCLK_DIV = 2 Generating RTLIL representation for module `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine'. 20.4.17. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer Used module: $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager Used module: \crc32_byte Used module: $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine Used module: \spi_slave Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Parameter \PARALLEL = 8 20.4.18. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Parameter \PARALLEL = 8 Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'. Parameter \CLK_FREQ_MHZ = 80 Parameter \SCLK_DIV = 2 20.4.19. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_flash_master'. Parameter \CLK_FREQ_MHZ = 80 Parameter \SCLK_DIV = 2 Generating RTLIL representation for module `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master'. 20.4.20. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer Used module: $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager Used module: \crc32_byte Used module: $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine Used module: $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine Used module: \spi_slave Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 20.4.21. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Generating RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Reprocessing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 because instantiated module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit has become available. Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'. 20.4.22. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer Used module: $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager Used module: \crc32_byte Used module: $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine Used module: $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine Used module: \spi_slave Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. 20.4.23. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer Used module: $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager Used module: \crc32_byte Used module: $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine Used module: $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine Used module: \spi_slave 20.4.24. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111 Used module: $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory Used module: $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit Used module: $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer Used module: $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager Used module: \crc32_byte Used module: $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine Used module: $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master Used module: $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine Used module: \spi_slave Removing unused module `$abstract\psram_controller'. Removing unused module `$abstract\memory_interface'. Removing unused module `$abstract\int8_memory_access'. Removing unused module `$abstract\mem_arbiter'. Removing unused module `$abstract\layer'. Removing unused module `$abstract\mac_unit'. Removing unused module `$abstract\mac8'. Removing unused module `$abstract\neuron_parallel'. Removing unused module `$abstract\neuron_memory'. Removing unused module `$abstract\act_buffer'. Removing unused module `$abstract\graph_engine'. Removing unused module `$abstract\layer_sequencer'. Removing unused module `$abstract\spi_flash_master'. Removing unused module `$abstract\crc32_byte'. Removing unused module `$abstract\flash_copy_engine'. Removing unused module `$abstract\flash_slot_manager'. Removing unused module `$abstract\spi_engine'. Removing unused module `$abstract\spi_slave'. Removing unused module `$abstract\spi_neuron_top'. Removed 19 unused modules. 20.5. Executing PROC pass (convert processes to netlists). 20.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 20.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 9 switch rules as full_case in process $proc$rtl/spi_flash_master.v:193$1535 in module $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master. Marked 2 switch rules as full_case in process $proc$rtl/spi_flash_master.v:152$1524 in module $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master. Marked 13 switch rules as full_case in process $proc$rtl/flash_copy_engine.v:270$1459 in module $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine. Marked 8 switch rules as full_case in process $proc$rtl/crc32.v:48$1413 in module crc32_byte. Marked 1 switch rules as full_case in process $proc$rtl/act_buffer.v:55$1402 in module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer. Marked 5 switch rules as full_case in process $proc$rtl/neuron_parallel.v:205$1394 in module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel. Marked 6 switch rules as full_case in process $proc$rtl/spi_slave.v:119$1369 in module spi_slave. Marked 1 switch rules as full_case in process $proc$rtl/spi_slave.v:93$1359 in module spi_slave. Marked 1 switch rules as full_case in process $proc$rtl/spi_slave.v:71$1358 in module spi_slave. Marked 14 switch rules as full_case in process $proc$rtl/spi_engine.v:511$1323 in module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine. Marked 5 switch rules as full_case in process $proc$rtl/spi_engine.v:434$1317 in module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine. Marked 4 switch rules as full_case in process $proc$rtl/spi_engine.v:403$1313 in module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine. Marked 13 switch rules as full_case in process $proc$rtl/flash_slot_manager.v:314$881 in module $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager. Marked 2 switch rules as full_case in process $proc$rtl/flash_slot_manager.v:270$876 in module $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager. Marked 6 switch rules as full_case in process $proc$rtl/layer_sequencer.v:137$742 in module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer. Marked 12 switch rules as full_case in process $proc$rtl/graph_engine.v:247$497 in module $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine. Marked 9 switch rules as full_case in process $proc$rtl/neuron_memory.v:283$303 in module $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory. Marked 5 switch rules as full_case in process $proc$rtl/mem_arbiter.v:117$297 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111. Marked 4 switch rules as full_case in process $proc$rtl/int8_memory_access.v:55$293 in module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111. Marked 2 switch rules as full_case in process $proc$rtl/memory_interface.v:33$291 in module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface. Marked 13 switch rules as full_case in process $proc$rtl/psram_controller.v:197$254 in module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller. Removed a total of 0 dead cases. 20.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 46 redundant assignments. Promoted 243 assignments to connections. 20.5.4. Executing PROC_INIT pass (extract init attributes). 20.5.5. Executing PROC_ARST pass (detect async resets in processes). 20.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 1 switch. 20.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1624'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1622'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1620'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1618'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1616'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1614'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1612'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1611'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1610'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1609'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1608'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1607'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1606'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1605'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1604'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1603'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1602'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1601'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1600'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1599'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1598'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1597'. Creating decoders for process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1596'. Creating decoders for process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. 1/15: $0\done[0:0] 2/15: $0\rdata_valid[0:0] 3/15: $0\wdata_req[0:0] 4/15: $0\cur_dir[1:0] 5/15: $0\data_total[15:0] 6/15: $0\data_idx[15:0] 7/15: $0\byte_shift[7:0] 8/15: $0\bit_idx[5:0] 9/15: $0\hdr_len[5:0] 10/15: $0\hdr_shift[31:0] 11/15: $0\shifting[0:0] 12/15: $0\state[3:0] 13/15: $0\rdata[7:0] 14/15: $0\cs_n[0:0] 15/15: $0\mosi[0:0] Creating decoders for process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:152$1524'. 1/2: $0\div_cnt[15:0] 2/2: $0\sclk_reg[0:0] Creating decoders for process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. 1/26: $0\fm_wdata_valid[0:0] 2/26: $0\fm_rdata_ack[0:0] 3/26: $0\fm_start[0:0] 4/26: $0\done[0:0] 5/26: $0\erase_only[0:0] 6/26: $0\wip_busy[0:0] 7/26: $0\prog_remaining[23:0] 8/26: $0\prog_psram_addr[22:0] 9/26: $0\prog_addr[23:0] 10/26: $0\erase_addr[23:0] 11/26: $0\save_end[24:0] 12/26: $0\save_phase[0:0] 13/26: $0\cur_psram_addr[22:0] 14/26: $0\cur_flash_addr[23:0] 15/26: $0\remaining[23:0] 16/26: $0\fm_wdata[7:0] 17/26: $0\fm_n_data[15:0] 18/26: $0\fm_dir[1:0] 19/26: $0\fm_addr[23:0] 20/26: $0\fm_has_addr[0:0] 21/26: $0\fm_opcode[7:0] 22/26: $0\state[4:0] 23/26: $0\d_wdata[7:0] 24/26: $0\d_addr[22:0] 25/26: $0\d_wr[0:0] 26/26: $0\err[0:0] Creating decoders for process `\crc32_byte.$proc$rtl/crc32.v:48$1413'. 1/8: $8\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1449 2/8: $7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 3/8: $6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 4/8: $5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 5/8: $4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 6/8: $3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 7/8: $2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 8/8: $1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:60$1409'. Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:55$1402'. 1/3: $1$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1408 2/3: $1$memwr$\mem$rtl/act_buffer.v:57$1401_DATA[7:0]$1407 3/3: $1$memwr$\mem$rtl/act_buffer.v:57$1401_ADDR[11:0]$1406 Creating decoders for process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. 1/6: $0\done[0:0] 2/6: $0\finishing[0:0] 3/6: $0\acc[31:0] 4/6: $0\group_index[1:0] 5/6: $0\busy[0:0] 6/6: $0\y[7:0] Creating decoders for process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. 1/9: $0\cs_end[0:0] 2/9: $0\cs_start[0:0] 3/9: $0\tx_byte_req[0:0] 4/9: $0\rx_valid[0:0] 5/9: $0\tx_shift[7:0] 6/9: $0\rx_shift[7:0] 7/9: $0\bit_count[2:0] 8/9: $0\rx_byte[7:0] 9/9: $0\miso[0:0] Creating decoders for process `\spi_slave.$proc$rtl/spi_slave.v:93$1359'. 1/2: $0\cs_n_prev[0:0] 2/2: $0\sclk_prev[0:0] Creating decoders for process `\spi_slave.$proc$rtl/spi_slave.v:71$1358'. 1/3: $0\cs_n_sync[2:0] 2/3: $0\mosi_sync[2:0] 3/3: $0\sclk_sync[2:0] Creating decoders for process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. 1/49: $0\len_acc[15:0] [15:8] 2/49: $0\len_acc[15:0] [7:0] 3/49: $0\nm_soft_rst[0:0] 4/49: $0\nm_start[0:0] 5/49: $0\ram_req[0:0] 6/49: $0\flash_op_start[0:0] 7/49: $0\status_snapshot[7:0] 8/49: $0\graph_mode[0:0] 9/49: $0\net_mode[0:0] 10/49: $0\resp_len[4:0] 11/49: $0\resp_index[4:0] 12/49: $0\cur_read_byte[7:0] 13/49: $0\pending_write[0:0] 14/49: $0\cur_addr[22:0] 15/49: $0\len_remaining[15:0] 16/49: $0\run_start[0:0] 17/49: $0\addr_acc[23:0] 18/49: $0\byte_pos[1:0] 19/49: $0\flash_payload_len[3:0] 20/49: $0\flash_byte_pos[3:0] 21/49: $0\flash_payload[71:0] 22/49: $0\opcode[7:0] 23/49: $0\pending_wdata[7:0] 24/49: $0\state[3:0] 25/49: $0\ram_wdata[7:0] 26/49: $0\ram_addr[22:0] 27/49: $0\ram_wr[0:0] 28/49: $0\flash_cat_read_sel[3:0] 29/49: $0\flash_raw_flash_addr[23:0] 30/49: $0\flash_ext_length[23:0] 31/49: $0\flash_ext_psram_addr[22:0] 32/49: $0\flash_new_type[7:0] 33/49: $0\flash_new_length[23:0] 34/49: $0\flash_new_offset[23:0] 35/49: $0\flash_slot_id[3:0] 36/49: $0\flash_op_code[2:0] 37/49: $0\n_out[15:0] 38/49: $0\num_neurons_graph[15:0] 39/49: $0\net_type[7:0] 40/49: $0\run_num_layers[7:0] 41/49: $0\buf_b_base[22:0] 42/49: $0\buf_a_base[22:0] 43/49: $0\table_base[22:0] 44/49: $0\n_neurons_real[15:0] 45/49: $0\n_inputs_real[15:0] 46/49: $0\activation[1:0] 47/49: $0\bias_addr[22:0] 48/49: $0\w_base[22:0] 49/49: $0\x_base[22:0] Creating decoders for process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:434$1317'. 1/5: $5\tx_byte_comb[7:0] 2/5: $4\tx_byte_comb[7:0] 3/5: $3\tx_byte_comb[7:0] 4/5: $2\tx_byte_comb[7:0] 5/5: $1\tx_byte_comb[7:0] Creating decoders for process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:403$1313'. 1/2: $0\flash_err_sticky[0:0] 2/2: $0\status_done_sticky[0:0] Creating decoders for process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. 1/281: $5$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_EN[0:0]$1302 2/281: $5$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_ADDR[3:0]$1301 3/281: $5$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1300 4/281: $5$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_DATA[31:0]$1299 5/281: $5$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_ADDR[3:0]$1298 6/281: $5$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1297 7/281: $5$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_DATA[23:0]$1296 8/281: $5$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_ADDR[3:0]$1295 9/281: $4$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_EN[0:0]$1290 10/281: $4$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_ADDR[3:0]$1289 11/281: $4$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1288 12/281: $4$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_DATA[31:0]$1287 13/281: $4$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_ADDR[3:0]$1286 14/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1285 15/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_DATA[23:0]$1284 16/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_ADDR[3:0]$1283 17/281: $3$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_EN[0:0]$1282 18/281: $3$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_ADDR[3:0]$1281 19/281: $3$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1280 20/281: $3$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_DATA[31:0]$1279 21/281: $3$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_ADDR[3:0]$1278 22/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1277 23/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_DATA[23:0]$1276 24/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_ADDR[3:0]$1275 25/281: $3$mem2bits$\cat_offset$rtl/flash_slot_manager.v:521$853[23:0]$1247 26/281: $3$mem2bits$\cat_crc$rtl/flash_slot_manager.v:532$862[31:0]$1256 27/281: $3$mem2bits$\cat_crc$rtl/flash_slot_manager.v:531$861[31:0]$1255 28/281: $3$mem2bits$\cat_crc$rtl/flash_slot_manager.v:530$860[31:0]$1254 29/281: $3$mem2bits$\cat_crc$rtl/flash_slot_manager.v:529$859[31:0]$1253 30/281: $3$mem2bits$\cat_length$rtl/flash_slot_manager.v:526$858[23:0]$1252 31/281: $3$mem2bits$\cat_length$rtl/flash_slot_manager.v:525$857[23:0]$1251 32/281: $3$mem2bits$\cat_length$rtl/flash_slot_manager.v:524$856[23:0]$1250 33/281: $3$mem2bits$\cat_offset$rtl/flash_slot_manager.v:523$855[23:0]$1249 34/281: $3$mem2bits$\cat_offset$rtl/flash_slot_manager.v:522$854[23:0]$1248 35/281: $4$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$1242 36/281: $4$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_DATA[31:0]$1241 37/281: $4$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR[4:0]$1240 38/281: $4$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_EN[0:0]$1239 39/281: $4$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_DATA[0:0]$1238 40/281: $4$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_ADDR[4:0]$1237 41/281: $4$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$1236 42/281: $4$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_DATA[7:0]$1235 43/281: $4$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_ADDR[4:0]$1234 44/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$1233 45/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_DATA[23:0]$1232 46/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_ADDR[4:0]$1231 47/281: $4$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$1230 48/281: $4$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_DATA[23:0]$1229 49/281: $4$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_ADDR[4:0]$1228 50/281: $3$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$1226 51/281: $3$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_DATA[31:0]$1225 52/281: $3$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR[4:0]$1224 53/281: $3$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_EN[0:0]$1223 54/281: $3$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_DATA[0:0]$1222 55/281: $3$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_ADDR[4:0]$1221 56/281: $3$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$1220 57/281: $3$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_DATA[7:0]$1219 58/281: $3$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_ADDR[4:0]$1218 59/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$1217 60/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_DATA[23:0]$1216 61/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_ADDR[4:0]$1215 62/281: $3$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$1214 63/281: $3$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_DATA[23:0]$1213 64/281: $3$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_ADDR[4:0]$1212 65/281: $4$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$1205 66/281: $4$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_ADDR[3:0]$1204 67/281: $4$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_EN[0:0]$1203 68/281: $4$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_ADDR[3:0]$1202 69/281: $4$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$1201 70/281: $4$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_DATA[7:0]$1200 71/281: $4$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_ADDR[3:0]$1199 72/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$1198 73/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_DATA[23:0]$1197 74/281: $4$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_ADDR[3:0]$1196 75/281: $4$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$1195 76/281: $4$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_DATA[23:0]$1194 77/281: $4$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_ADDR[3:0]$1193 78/281: $3$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$1192 79/281: $3$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_ADDR[3:0]$1191 80/281: $3$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_EN[0:0]$1190 81/281: $3$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_ADDR[3:0]$1189 82/281: $3$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$1188 83/281: $3$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_DATA[7:0]$1187 84/281: $3$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_ADDR[3:0]$1186 85/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$1185 86/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_DATA[23:0]$1184 87/281: $3$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_ADDR[3:0]$1183 88/281: $3$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$1182 89/281: $3$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_DATA[23:0]$1181 90/281: $3$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_ADDR[3:0]$1180 91/281: $2$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$1146 92/281: $2$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_ADDR[3:0]$1145 93/281: $2$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_EN[0:0]$1144 94/281: $2$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_ADDR[3:0]$1143 95/281: $2$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$1142 96/281: $2$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_DATA[7:0]$1141 97/281: $2$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_ADDR[3:0]$1140 98/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$1139 99/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_DATA[23:0]$1138 100/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_ADDR[3:0]$1137 101/281: $2$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$1136 102/281: $2$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_DATA[23:0]$1135 103/281: $2$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_ADDR[3:0]$1134 104/281: $2$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_EN[0:0]$1179 105/281: $2$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_ADDR[3:0]$1178 106/281: $2$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1177 107/281: $2$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_DATA[31:0]$1176 108/281: $2$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_ADDR[3:0]$1175 109/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1174 110/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_DATA[23:0]$1173 111/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_ADDR[3:0]$1172 112/281: $2$mem2bits$\cat_crc$rtl/flash_slot_manager.v:532$862[31:0]$1171 113/281: $2$mem2bits$\cat_crc$rtl/flash_slot_manager.v:531$861[31:0]$1170 114/281: $2$mem2bits$\cat_crc$rtl/flash_slot_manager.v:530$860[31:0]$1169 115/281: $2$mem2bits$\cat_crc$rtl/flash_slot_manager.v:529$859[31:0]$1168 116/281: $2$mem2bits$\cat_length$rtl/flash_slot_manager.v:526$858[23:0]$1167 117/281: $2$mem2bits$\cat_length$rtl/flash_slot_manager.v:525$857[23:0]$1166 118/281: $2$mem2bits$\cat_length$rtl/flash_slot_manager.v:524$856[23:0]$1165 119/281: $2$mem2bits$\cat_offset$rtl/flash_slot_manager.v:523$855[23:0]$1164 120/281: $2$mem2bits$\cat_offset$rtl/flash_slot_manager.v:522$854[23:0]$1163 121/281: $2$mem2bits$\cat_offset$rtl/flash_slot_manager.v:521$853[23:0]$1162 122/281: $2$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$1161 123/281: $2$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_DATA[31:0]$1160 124/281: $2$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR[4:0]$1159 125/281: $2$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_EN[0:0]$1158 126/281: $2$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_DATA[0:0]$1157 127/281: $2$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_ADDR[4:0]$1156 128/281: $2$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$1155 129/281: $2$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_DATA[7:0]$1154 130/281: $2$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_ADDR[4:0]$1153 131/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$1152 132/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_DATA[23:0]$1151 133/281: $2$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_ADDR[4:0]$1150 134/281: $2$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$1149 135/281: $2$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_DATA[23:0]$1148 136/281: $2$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_ADDR[4:0]$1147 137/281: $1\rst_i[31:0] 138/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$1087 139/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$841_EN[0:0]$1086 140/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$1085 141/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$1084 142/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$1083 143/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$1082 144/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$836_EN[0:0]$1081 145/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$1080 146/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$1079 147/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$1078 148/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$1077 149/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$831_EN[0:0]$1076 150/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$1075 151/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$1074 152/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$1073 153/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$1072 154/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$826_EN[0:0]$1071 155/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$1070 156/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$1069 157/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$1068 158/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$1067 159/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$821_EN[0:0]$1066 160/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$1065 161/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$1064 162/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$1063 163/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$1062 164/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$816_EN[0:0]$1061 165/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$1060 166/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$1059 167/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$1058 168/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$1057 169/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$811_EN[0:0]$1056 170/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$1055 171/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$1054 172/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$1053 173/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$1052 174/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$806_EN[0:0]$1051 175/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$1050 176/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$1049 177/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$1048 178/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$1047 179/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$801_EN[0:0]$1046 180/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$1045 181/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$1044 182/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$1043 183/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$1042 184/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$796_EN[0:0]$1041 185/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$1040 186/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$1039 187/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$1038 188/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$1037 189/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$791_EN[0:0]$1036 190/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$1035 191/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$1034 192/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$1033 193/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$1032 194/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$786_EN[0:0]$1031 195/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$1030 196/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$1029 197/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$1028 198/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$1027 199/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$781_EN[0:0]$1026 200/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$1025 201/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$1024 202/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$1023 203/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$1022 204/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$776_EN[0:0]$1021 205/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$1020 206/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$1019 207/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$1018 208/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$1017 209/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$771_EN[0:0]$1016 210/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$1015 211/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$1014 212/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$1013 213/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$1012 214/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:341$766_EN[0:0]$1011 215/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$1010 216/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$1009 217/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$1008 218/281: $0\fsm_d_req[0:0] 219/281: $0\fce_start[0:0] 220/281: $0\done[0:0] 221/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_EN[0:0]$1133 222/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_ADDR[3:0]$1132 223/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1131 224/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_DATA[31:0]$1130 225/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_ADDR[3:0]$1129 226/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1128 227/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_DATA[23:0]$1127 228/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_ADDR[3:0]$1126 229/281: $1$mem2bits$\cat_crc$rtl/flash_slot_manager.v:532$862[31:0]$1125 230/281: $1$mem2bits$\cat_crc$rtl/flash_slot_manager.v:531$861[31:0]$1124 231/281: $1$mem2bits$\cat_crc$rtl/flash_slot_manager.v:530$860[31:0]$1123 232/281: $1$mem2bits$\cat_crc$rtl/flash_slot_manager.v:529$859[31:0]$1122 233/281: $1$mem2bits$\cat_length$rtl/flash_slot_manager.v:526$858[23:0]$1121 234/281: $1$mem2bits$\cat_length$rtl/flash_slot_manager.v:525$857[23:0]$1120 235/281: $1$mem2bits$\cat_length$rtl/flash_slot_manager.v:524$856[23:0]$1119 236/281: $1$mem2bits$\cat_offset$rtl/flash_slot_manager.v:523$855[23:0]$1118 237/281: $1$mem2bits$\cat_offset$rtl/flash_slot_manager.v:522$854[23:0]$1117 238/281: $1$mem2bits$\cat_offset$rtl/flash_slot_manager.v:521$853[23:0]$1116 239/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$1115 240/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_DATA[31:0]$1114 241/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR[4:0]$1113 242/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_EN[0:0]$1112 243/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_DATA[0:0]$1111 244/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_ADDR[4:0]$1110 245/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$1109 246/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_DATA[7:0]$1108 247/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_ADDR[4:0]$1107 248/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$1106 249/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_DATA[23:0]$1105 250/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_ADDR[4:0]$1104 251/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$1103 252/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_DATA[23:0]$1102 253/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_ADDR[4:0]$1101 254/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$1100 255/281: $1$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_ADDR[3:0]$1099 256/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_EN[0:0]$1098 257/281: $1$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_ADDR[3:0]$1097 258/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$1096 259/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_DATA[7:0]$1095 260/281: $1$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_ADDR[3:0]$1094 261/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$1093 262/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_DATA[23:0]$1092 263/281: $1$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_ADDR[3:0]$1091 264/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$1090 265/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_DATA[23:0]$1089 266/281: $1$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_ADDR[3:0]$1088 267/281: $0\active_slot[3:0] 268/281: $0\active_op[2:0] 269/281: $0\entry_shift[127:0] 270/281: $0\cur_slot[3:0] 271/281: $0\byte_idx[8:0] 272/281: $0\crc_active[0:0] 273/281: $0\fsm_d_wdata[7:0] 274/281: $0\fsm_d_addr[22:0] 275/281: $0\fsm_d_wr[0:0] 276/281: $0\fce_len[23:0] 277/281: $0\fce_psram_addr[22:0] 278/281: $0\fce_flash_addr[23:0] 279/281: $0\fce_dir[1:0] 280/281: $0\state[3:0] 281/281: $0\err[0:0] Creating decoders for process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:270$876'. 1/1: $0\crc_acc[31:0] Creating decoders for process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. 1/32: $0\n_neurons_acc[15:0] [15:8] 2/32: $0\n_neurons_acc[15:0] [7:0] 3/32: $0\n_inputs_acc[15:0] [7:0] 4/32: $0\bias_addr_acc[23:0] [7:0] 5/32: $0\bias_addr_acc[23:0] [23:16] 6/32: $0\w_base_acc[23:0] [7:0] 7/32: $0\w_base_acc[23:0] [23:16] 8/32: $0\ram_req[0:0] 9/32: $0\nm_start[0:0] 10/32: $0\copy_idx[0:0] 11/32: $0\write_sel[0:0] 12/32: $0\cur_sel[0:0] 13/32: $0\n_inputs_acc[15:0] [15:8] 14/32: $0\bias_addr_acc[23:0] [15:8] 15/32: $0\activation_acc[7:0] 16/32: $0\w_base_acc[23:0] [15:8] 17/32: $0\seq_done[0:0] 18/32: $0\desc_table_addr[22:0] 19/32: $0\num_layers_reg[7:0] 20/32: $0\layer_idx[7:0] 21/32: $0\desc_byte_idx[3:0] 22/32: $0\state[3:0] 23/32: $0\nm_n_neurons[15:0] 24/32: $0\nm_n_inputs[15:0] 25/32: $0\nm_activation[1:0] 26/32: $0\nm_bias_addr[22:0] 27/32: $0\nm_w_base[22:0] 28/32: $0\nm_x_base[22:0] 29/32: $0\ram_wdata[7:0] 30/32: $0\ram_addr[22:0] 31/32: $0\ram_wr[0:0] 32/32: $0\seq_busy[0:0] Creating decoders for process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. 1/108: $0\src_id_acc[15:0] [15:8] 2/108: $0\src_id_acc[15:0] [7:0] 3/108: $0\out_id_acc[15:0] [7:0] 4/108: $0\n_conn_acc[15:0] [7:0] 5/108: $0\conn_ptr_acc[23:0] [7:0] 6/108: $0\conn_ptr_acc[23:0] [23:16] 7/108: $2$memwr$\w_mem$rtl/graph_engine.v:521$493_DATA[7:0]$642 8/108: $2$memwr$\w_mem$rtl/graph_engine.v:521$493_ADDR[5:0]$641 9/108: $2$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$640 10/108: $2$memwr$\x_mem$rtl/graph_engine.v:520$492_DATA[7:0]$639 11/108: $2$memwr$\x_mem$rtl/graph_engine.v:520$492_ADDR[5:0]$638 12/108: $1\ri[31:0] 13/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$631 14/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$630 15/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$629 16/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$628 17/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$627 18/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$626 19/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$625 20/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$624 21/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$623 22/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$622 23/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$621 24/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$620 25/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$619 26/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$618 27/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$617 28/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$616 29/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$615 30/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$614 31/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$613 32/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$612 33/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$611 34/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$610 35/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$609 36/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$608 37/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$607 38/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$606 39/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$605 40/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$604 41/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$603 42/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$602 43/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$601 44/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$600 45/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$599 46/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$598 47/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$597 48/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$596 49/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$595 50/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$594 51/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$593 52/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$592 53/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$591 54/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$590 55/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$589 56/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$588 57/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$587 58/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$586 59/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$585 60/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$584 61/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$583 62/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$582 63/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$581 64/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$580 65/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$579 66/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$578 67/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$577 68/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$576 69/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$575 70/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$574 71/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$573 72/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$572 73/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$571 74/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$570 75/108: $1$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$569 76/108: $1$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$568 77/108: $0\ram_req[0:0] 78/108: $0\neuron_start[0:0] 79/108: $0\act_wr_en[0:0] 80/108: $0\done[0:0] 81/108: $1$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$637 82/108: $1$memwr$\w_mem$rtl/graph_engine.v:521$493_DATA[7:0]$636 83/108: $1$memwr$\w_mem$rtl/graph_engine.v:521$493_ADDR[5:0]$635 84/108: $1$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$634 85/108: $1$memwr$\x_mem$rtl/graph_engine.v:520$492_DATA[7:0]$633 86/108: $1$memwr$\x_mem$rtl/graph_engine.v:520$492_ADDR[5:0]$632 87/108: $0\n_conn_padded_reg[15:0] 88/108: $0\activation_reg[1:0] 89/108: $0\act_wr_data[7:0] 90/108: $0\act_wr_addr[11:0] 91/108: $0\weight_acc[7:0] 92/108: $0\out_id_acc[15:0] [15:8] 93/108: $0\edge_byte_idx[1:0] 94/108: $0\conn_i[5:0] 95/108: $0\n_conn_acc[15:0] [15:8] 96/108: $0\conn_ptr_acc[23:0] [15:8] 97/108: $2$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$643 98/108: $0\desc_byte_idx[3:0] 99/108: $0\desc_addr[22:0] 100/108: $0\neuron_idx[15:0] 101/108: $0\in_idx[15:0] 102/108: $0\bias_reg[7:0] 103/108: $0\state[3:0] 104/108: $0\err[0:0] 105/108: $0\busy[0:0] 106/108: $0\ram_wdata[7:0] 107/108: $0\ram_addr[22:0] 108/108: $0\ram_wr[0:0] Creating decoders for process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. 1/42: $3$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$356 2/42: $3$memwr$\y_reg$rtl/neuron_memory.v:500$301_DATA[7:0]$355 3/42: $3$memwr$\y_reg$rtl/neuron_memory.v:500$301_ADDR[0:0]$354 4/42: $3$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$346 5/42: $3$memwr$\w_mem$rtl/neuron_memory.v:434$300_DATA[7:0]$345 6/42: $3$memwr$\w_mem$rtl/neuron_memory.v:434$300_ADDR[5:0]$344 7/42: $3$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$335 8/42: $3$memwr$\x_mem$rtl/neuron_memory.v:367$299_DATA[7:0]$334 9/42: $3$memwr$\x_mem$rtl/neuron_memory.v:367$299_ADDR[5:0]$333 10/42: $2$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$332 11/42: $2$memwr$\y_reg$rtl/neuron_memory.v:500$301_DATA[7:0]$331 12/42: $2$memwr$\y_reg$rtl/neuron_memory.v:500$301_ADDR[0:0]$330 13/42: $2$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$329 14/42: $2$memwr$\w_mem$rtl/neuron_memory.v:434$300_DATA[7:0]$328 15/42: $2$memwr$\w_mem$rtl/neuron_memory.v:434$300_ADDR[5:0]$327 16/42: $2$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$326 17/42: $2$memwr$\x_mem$rtl/neuron_memory.v:367$299_DATA[7:0]$325 18/42: $2$memwr$\x_mem$rtl/neuron_memory.v:367$299_ADDR[5:0]$324 19/42: $0\done[0:0] 20/42: $1\rst_i[31:0] 21/42: $1$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$314 22/42: $0\neuron_start[0:0] 23/42: $0\access_req[0:0] 24/42: $1$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$323 25/42: $1$memwr$\y_reg$rtl/neuron_memory.v:500$301_DATA[7:0]$322 26/42: $1$memwr$\y_reg$rtl/neuron_memory.v:500$301_ADDR[0:0]$321 27/42: $1$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$320 28/42: $1$memwr$\w_mem$rtl/neuron_memory.v:434$300_DATA[7:0]$319 29/42: $1$memwr$\w_mem$rtl/neuron_memory.v:434$300_ADDR[5:0]$318 30/42: $1$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$317 31/42: $1$memwr$\x_mem$rtl/neuron_memory.v:367$299_DATA[7:0]$316 32/42: $1$memwr$\x_mem$rtl/neuron_memory.v:367$299_ADDR[5:0]$315 33/42: $0\access_wdata[7:0] 34/42: $0\access_addr[22:0] 35/42: $0\access_wr[0:0] 36/42: $0\bias_reg[7:0] 37/42: $0\bias_group_addr[22:0] 38/42: $0\w_group_base[22:0] 39/42: $0\neuron_index[0:0] 40/42: $0\index[5:0] 41/42: $0\state[3:0] 42/42: $0\busy[0:0] Creating decoders for process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. 1/13: $0\d_ready[0:0] 2/13: $0\c_ready[0:0] 3/13: $0\b_ready[0:0] 4/13: $0\a_ready[0:0] 5/13: $0\m_req[0:0] 6/13: $0\owner[2:0] 7/13: $0\m_wdata[7:0] 8/13: $0\m_addr[22:0] 9/13: $0\m_wr[0:0] 10/13: $0\c_rdata[7:0] 11/13: $0\b_rdata[7:0] 12/13: $0\a_rdata[7:0] 13/13: $0\d_rdata[7:0] Creating decoders for process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. 1/10: $0\mem_req[0:0] 2/10: $0\ready[0:0] 3/10: $0\addr_reg[22:0] 4/10: $0\state[1:0] 5/10: $0\mem_ub_n[0:0] 6/10: $0\mem_lb_n[0:0] 7/10: $0\rdata[7:0] 8/10: $0\mem_wdata[15:0] 9/10: $0\mem_addr[22:0] 10/10: $0\mem_wr[0:0] Creating decoders for process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. 1/9: $0\mem_req[0:0] 2/9: $0\ready[0:0] 3/9: $0\state[1:0] 4/9: $0\mem_ub_n[0:0] 5/9: $0\mem_lb_n[0:0] 6/9: $0\rdata[15:0] 7/9: $0\mem_wdata[15:0] 8/9: $0\mem_addr[22:0] 9/9: $0\mem_wr[0:0] Creating decoders for process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. 1/28: $0\mem_ready[0:0] 2/28: $0\dq_oe[0:0] 3/28: $0\dq_out[15:0] 4/28: $0\pending_ub_n[0:0] 5/28: $0\pending_lb_n[0:0] 6/28: $0\pending_wr[0:0] 7/28: $0\pending_wdata[15:0] 8/28: $0\pending_addr[22:0] 9/28: $0\req_pending[0:0] 10/28: $0\cr_step[2:0] 11/28: $0\cr_init_active[0:0] 12/28: $0\hold_cycles[8:0] 13/28: $0\page_hit_reg[0:0] 14/28: $0\ub_reg[0:0] 15/28: $0\lb_reg[0:0] 16/28: $0\wr_reg[0:0] 17/28: $0\wdata_reg[15:0] 18/28: $0\address_reg[22:0] 19/28: $0\counter[13:0] 20/28: $0\state[3:0] 21/28: $0\mem_rdata[15:0] 22/28: $0\psram_zz_n[0:0] 23/28: $0\psram_ub_n[0:0] 24/28: $0\psram_lb_n[0:0] 25/28: $0\psram_we_n[0:0] 26/28: $0\psram_oe_n[0:0] 27/28: $0\psram_ce_n[0:0] 28/28: $0\psram_a[22:0] 20.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[24]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1624'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[17]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1622'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[16]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1620'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[11]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1618'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[10]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1616'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[9]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1614'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[8]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1612'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1611'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1610'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1609'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1608'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1607'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1606'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1605'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\tree[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1604'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[7]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1603'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[6]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1602'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[5]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1601'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[4]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1600'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[3]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1599'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[2]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1598'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[1]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1597'. No latch inferred for signal `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.\products[0]' from process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1596'. No latch inferred for signal `\crc32_byte.\next_crc$func$rtl/crc32.v:48$1411.$result' from process `\crc32_byte.$proc$rtl/crc32.v:48$1413'. No latch inferred for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\tx_byte_comb' from process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:434$1317'. 20.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\mosi' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10360' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\cs_n' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10361' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\done' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10362' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\rdata' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10363' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\state' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10364' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\wdata_req' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10365' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\rdata_valid' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10366' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\shifting' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10367' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\hdr_shift' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10368' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\hdr_len' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10369' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\bit_idx' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10370' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\byte_shift' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10371' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\data_idx' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10372' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\data_total' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10373' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\cur_dir' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. created $dff cell `$procdff$10374' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\div_cnt' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:152$1524'. created $dff cell `$procdff$10375' with positive edge clock. Creating register for signal `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.\sclk_reg' using process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:152$1524'. created $dff cell `$procdff$10376' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\done' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10377' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\err' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10378' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\d_wr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10379' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\d_addr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10380' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\d_wdata' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10381' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\state' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10382' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_start' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10383' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_opcode' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10384' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_has_addr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10385' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_addr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10386' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_dir' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10387' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_n_data' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10388' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_wdata' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10389' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_wdata_valid' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10390' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\fm_rdata_ack' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10391' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\remaining' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10392' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\cur_flash_addr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10393' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\cur_psram_addr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10394' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\save_phase' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10395' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\save_end' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10396' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\erase_addr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10397' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\prog_addr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10398' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\prog_psram_addr' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10399' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\prog_remaining' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10400' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\wip_busy' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10401' with positive edge clock. Creating register for signal `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.\erase_only' using process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. created $dff cell `$procdff$10402' with positive edge clock. Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.\rd_data' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:60$1409'. created $dff cell `$procdff$10403' with positive edge clock. Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$rtl/act_buffer.v:57$1401_ADDR' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:55$1402'. created $dff cell `$procdff$10404' with positive edge clock. Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$rtl/act_buffer.v:57$1401_DATA' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:55$1402'. created $dff cell `$procdff$10405' with positive edge clock. Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$rtl/act_buffer.v:57$1401_EN' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:55$1402'. created $dff cell `$procdff$10406' with positive edge clock. Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\y' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. created $dff cell `$procdff$10407' with positive edge clock. Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\busy' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. created $dff cell `$procdff$10408' with positive edge clock. Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\done' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. created $dff cell `$procdff$10409' with positive edge clock. Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\group_index' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. created $dff cell `$procdff$10410' with positive edge clock. Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\acc' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. created $dff cell `$procdff$10411' with positive edge clock. Creating register for signal `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.\finishing' using process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. created $dff cell `$procdff$10412' with positive edge clock. Creating register for signal `\spi_slave.\miso' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10413' with positive edge clock. Creating register for signal `\spi_slave.\rx_byte' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10414' with positive edge clock. Creating register for signal `\spi_slave.\rx_valid' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10415' with positive edge clock. Creating register for signal `\spi_slave.\cs_start' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10416' with positive edge clock. Creating register for signal `\spi_slave.\cs_end' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10417' with positive edge clock. Creating register for signal `\spi_slave.\tx_byte_req' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10418' with positive edge clock. Creating register for signal `\spi_slave.\bit_count' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10419' with positive edge clock. Creating register for signal `\spi_slave.\rx_shift' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10420' with positive edge clock. Creating register for signal `\spi_slave.\tx_shift' using process `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. created $dff cell `$procdff$10421' with positive edge clock. Creating register for signal `\spi_slave.\sclk_prev' using process `\spi_slave.$proc$rtl/spi_slave.v:93$1359'. created $dff cell `$procdff$10422' with positive edge clock. Creating register for signal `\spi_slave.\cs_n_prev' using process `\spi_slave.$proc$rtl/spi_slave.v:93$1359'. created $dff cell `$procdff$10423' with positive edge clock. Creating register for signal `\spi_slave.\sclk_sync' using process `\spi_slave.$proc$rtl/spi_slave.v:71$1358'. created $dff cell `$procdff$10424' with positive edge clock. Creating register for signal `\spi_slave.\mosi_sync' using process `\spi_slave.$proc$rtl/spi_slave.v:71$1358'. created $dff cell `$procdff$10425' with positive edge clock. Creating register for signal `\spi_slave.\cs_n_sync' using process `\spi_slave.$proc$rtl/spi_slave.v:71$1358'. created $dff cell `$procdff$10426' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\x_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10427' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\w_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10428' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\bias_addr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10429' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\activation' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10430' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\n_inputs_real' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10431' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\n_neurons_real' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10432' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\nm_start' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10433' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\nm_soft_rst' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10434' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\table_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10435' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\buf_a_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10436' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\buf_b_base' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10437' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\run_start' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10438' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\run_num_layers' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10439' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\net_type' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10440' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\num_neurons_graph' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10441' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\n_out' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10442' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_op_start' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10443' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_op_code' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10444' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_slot_id' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10445' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_new_offset' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10446' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_new_length' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10447' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_new_type' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10448' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_ext_psram_addr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10449' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_ext_length' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10450' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_raw_flash_addr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10451' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_cat_read_sel' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10452' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\ram_req' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10453' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\ram_wr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10454' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\ram_addr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10455' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\ram_wdata' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10456' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\state' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10457' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\pending_wdata' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10458' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\opcode' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10459' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_payload' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10460' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_byte_pos' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10461' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_payload_len' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10462' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\byte_pos' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10463' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\addr_acc' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10464' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\len_acc' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10465' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\len_remaining' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10466' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\cur_addr' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10467' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\pending_write' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10468' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\cur_read_byte' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10469' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\resp_index' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10470' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\resp_len' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10471' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\net_mode' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10472' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\graph_mode' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10473' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\status_snapshot' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. created $dff cell `$procdff$10474' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\status_done_sticky' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:403$1313'. created $dff cell `$procdff$10475' with positive edge clock. Creating register for signal `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.\flash_err_sticky' using process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:403$1313'. created $dff cell `$procdff$10476' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\done' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10477' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\err' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10478' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\state' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10479' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\rst_i' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10480' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fce_start' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10481' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fce_dir' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10482' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fce_flash_addr' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10483' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fce_psram_addr' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10484' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fce_len' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10485' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fsm_d_req' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10486' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fsm_d_wr' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10487' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fsm_d_addr' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10488' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\fsm_d_wdata' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10489' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\crc_active' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10490' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\byte_idx' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10491' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\cur_slot' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10492' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\entry_shift' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10493' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\active_op' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10494' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\active_slot' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10495' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10496' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10497' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10498' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$766_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10499' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10500' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10501' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10502' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10503' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$771_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10504' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10505' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10506' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10507' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10508' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$776_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10509' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10510' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10511' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10512' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10513' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$781_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10514' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10515' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10516' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10517' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10518' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$786_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10519' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10520' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10521' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10522' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10523' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$791_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10524' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10525' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10526' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10527' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10528' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$796_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10529' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10530' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10531' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10532' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10533' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$801_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10534' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10535' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10536' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10537' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10538' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$806_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10539' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10540' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10541' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10542' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10543' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$811_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10544' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10545' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10546' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10547' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10548' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$816_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10549' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10550' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10551' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10552' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10553' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$821_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10554' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10555' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10556' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10557' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10558' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$826_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10559' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10560' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10561' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10562' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10563' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$831_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10564' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10565' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10566' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10567' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10568' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$836_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10569' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10570' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10571' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10572' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10573' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:341$841_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10574' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10575' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10576' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10577' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10578' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10579' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10580' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10581' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10582' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10583' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10584' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10585' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:377$846_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10586' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10587' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10588' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10589' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10590' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10591' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10592' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10593' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10594' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10595' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10596' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10597' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10598' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10599' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:490$851_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10600' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10601' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10602' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10603' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_offset$rtl/flash_slot_manager.v:521$853' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10604' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_offset$rtl/flash_slot_manager.v:522$854' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10605' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_offset$rtl/flash_slot_manager.v:523$855' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10606' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_length$rtl/flash_slot_manager.v:524$856' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10607' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_length$rtl/flash_slot_manager.v:525$857' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10608' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_length$rtl/flash_slot_manager.v:526$858' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10609' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_crc$rtl/flash_slot_manager.v:529$859' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10610' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_crc$rtl/flash_slot_manager.v:530$860' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10611' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_crc$rtl/flash_slot_manager.v:531$861' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10612' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$mem2bits$\cat_crc$rtl/flash_slot_manager.v:532$862' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10613' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10614' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10615' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10616' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10617' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_DATA' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10618' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10619' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_ADDR' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10620' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$memwr$\cat_valid$rtl/flash_slot_manager.v:610$865_EN' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. created $dff cell `$procdff$10621' with positive edge clock. Creating register for signal `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.\crc_acc' using process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:270$876'. created $dff cell `$procdff$10622' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_start' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10623' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\seq_busy' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10624' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\seq_done' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10625' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_req' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10626' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_wr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10627' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10628' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_wdata' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10629' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_x_base' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10630' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_w_base' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10631' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_bias_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10632' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_activation' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10633' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_n_inputs' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10634' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_n_neurons' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10635' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\state' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10636' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\desc_byte_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10637' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\layer_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10638' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\num_layers_reg' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10639' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\desc_table_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10640' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\w_base_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10641' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\bias_addr_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10642' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\activation_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10643' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\n_inputs_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10644' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\n_neurons_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10645' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\cur_sel' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10646' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\write_sel' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10647' with positive edge clock. Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\copy_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. created $dff cell `$procdff$10648' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ram_req' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10649' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ram_wr' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10650' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ram_addr' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10651' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ram_wdata' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10652' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\busy' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10653' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\done' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10654' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\err' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10655' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\state' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10656' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\bias_reg' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10657' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\neuron_start' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10658' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\in_idx' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10659' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\neuron_idx' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10660' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\desc_addr' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10661' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\desc_byte_idx' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10662' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\conn_ptr_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10663' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\n_conn_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10664' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\out_id_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10665' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\conn_i' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10666' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\edge_byte_idx' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10667' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\src_id_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10668' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\weight_acc' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10669' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\act_wr_en' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10670' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\act_wr_addr' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10671' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\act_wr_data' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10672' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\activation_reg' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10673' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\n_conn_padded_reg' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10674' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.\ri' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10675' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$428_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10676' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$429_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10677' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$430_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10678' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$431_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10679' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$432_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10680' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$433_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10681' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$434_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10682' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$435_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10683' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$436_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10684' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$437_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10685' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$438_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10686' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$439_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10687' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$440_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10688' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$441_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10689' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$442_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10690' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$443_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10691' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$444_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10692' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$445_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10693' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$446_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10694' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$447_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10695' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$448_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10696' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$449_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10697' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$450_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10698' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$451_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10699' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$452_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10700' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$453_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10701' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$454_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10702' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$455_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10703' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$456_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10704' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$457_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10705' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$458_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10706' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$459_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10707' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$460_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10708' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$461_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10709' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$462_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10710' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$463_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10711' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$464_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10712' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$465_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10713' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$466_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10714' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$467_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10715' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$468_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10716' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$469_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10717' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$470_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10718' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$471_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10719' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$472_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10720' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$473_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10721' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$474_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10722' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$475_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10723' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$476_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10724' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$477_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10725' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$478_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10726' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$479_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10727' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$480_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10728' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$481_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10729' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$482_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10730' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$483_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10731' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$484_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10732' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$485_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10733' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$486_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10734' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$487_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10735' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$488_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10736' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$489_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10737' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:286$490_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10738' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:287$491_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10739' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:520$492_ADDR' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10740' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:520$492_DATA' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10741' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\x_mem$rtl/graph_engine.v:520$492_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10742' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:521$493_ADDR' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10743' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:521$493_DATA' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10744' with positive edge clock. Creating register for signal `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$memwr$\w_mem$rtl/graph_engine.v:521$493_EN' using process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. created $dff cell `$procdff$10745' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\busy' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10746' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\done' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10747' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\state' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10748' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\index' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10749' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\neuron_index' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10750' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\w_group_base' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10751' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\bias_group_addr' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10752' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\bias_reg' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10753' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\access_req' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10754' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\access_wr' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10755' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\access_addr' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10756' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\access_wdata' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10757' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\neuron_start' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10758' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.\rst_i' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10759' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10760' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\x_mem$rtl/neuron_memory.v:367$299_ADDR' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10761' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\x_mem$rtl/neuron_memory.v:367$299_DATA' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10762' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10763' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\w_mem$rtl/neuron_memory.v:434$300_ADDR' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10764' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\w_mem$rtl/neuron_memory.v:434$300_DATA' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10765' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10766' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\y_reg$rtl/neuron_memory.v:500$301_ADDR' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10767' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\y_reg$rtl/neuron_memory.v:500$301_DATA' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10768' with positive edge clock. Creating register for signal `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN' using process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. created $dff cell `$procdff$10769' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\d_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10770' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\d_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10771' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\a_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10772' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\a_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10773' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\b_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10774' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\b_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10775' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\c_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10776' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\c_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10777' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_req' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10778' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_wr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10779' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_addr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10780' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_wdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10781' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\owner' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. created $dff cell `$procdff$10782' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_req' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10783' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_wr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10784' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_addr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10785' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_wdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10786' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\rdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10787' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\ready' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10788' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_lb_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10789' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_ub_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10790' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\state' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10791' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\addr_reg' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. created $dff cell `$procdff$10792' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_req' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10793' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_wr' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10794' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_addr' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10795' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_wdata' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10796' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\rdata' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10797' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\ready' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10798' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_lb_n' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10799' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_ub_n' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10800' with positive edge clock. Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\state' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. created $dff cell `$procdff$10801' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_a' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10802' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_ce_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10803' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_oe_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10804' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_we_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10805' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_lb_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10806' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_ub_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10807' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_zz_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10808' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\mem_rdata' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10809' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\mem_ready' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10810' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\state' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10811' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\counter' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10812' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\address_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10813' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\wdata_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10814' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\wr_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10815' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\lb_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10816' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\ub_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10817' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\page_hit_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10818' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\hold_cycles' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10819' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\cr_init_active' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10820' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\cr_step' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10821' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\req_pending' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10822' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\pending_addr' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10823' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\pending_wdata' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10824' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\pending_wr' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10825' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\pending_lb_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10826' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\pending_ub_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10827' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\dq_out' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10828' with positive edge clock. Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\dq_oe' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. created $dff cell `$procdff$10829' with positive edge clock. 20.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 20.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1624'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1622'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1620'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1618'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1616'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1614'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:100$1612'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1611'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1610'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1609'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1608'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1607'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1606'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1605'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:81$1604'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1603'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1602'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1601'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1600'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1599'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1598'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1597'. Removing empty process `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8.$proc$rtl/mac8.v:40$1596'. Found and cleaned up 19 empty switches in `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. Removing empty process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:193$1535'. Found and cleaned up 2 empty switches in `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:152$1524'. Removing empty process `$paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master.$proc$rtl/spi_flash_master.v:152$1524'. Found and cleaned up 23 empty switches in `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. Removing empty process `$paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine.$proc$rtl/flash_copy_engine.v:270$1459'. Found and cleaned up 8 empty switches in `\crc32_byte.$proc$rtl/crc32.v:48$1413'. Removing empty process `crc32_byte.$proc$rtl/crc32.v:48$1413'. Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:60$1409'. Found and cleaned up 1 empty switch in `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:55$1402'. Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$rtl/act_buffer.v:55$1402'. Found and cleaned up 6 empty switches in `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. Removing empty process `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel.$proc$rtl/neuron_parallel.v:205$1394'. Found and cleaned up 8 empty switches in `\spi_slave.$proc$rtl/spi_slave.v:119$1369'. Removing empty process `spi_slave.$proc$rtl/spi_slave.v:119$1369'. Found and cleaned up 1 empty switch in `\spi_slave.$proc$rtl/spi_slave.v:93$1359'. Removing empty process `spi_slave.$proc$rtl/spi_slave.v:93$1359'. Found and cleaned up 1 empty switch in `\spi_slave.$proc$rtl/spi_slave.v:71$1358'. Removing empty process `spi_slave.$proc$rtl/spi_slave.v:71$1358'. Found and cleaned up 40 empty switches in `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. Removing empty process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:511$1323'. Found and cleaned up 5 empty switches in `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:434$1317'. Removing empty process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:434$1317'. Found and cleaned up 6 empty switches in `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:403$1313'. Removing empty process `$paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine.$proc$rtl/spi_engine.v:403$1313'. Found and cleaned up 17 empty switches in `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. Removing empty process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:314$881'. Found and cleaned up 3 empty switches in `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:270$876'. Removing empty process `$paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager.$proc$rtl/flash_slot_manager.v:270$876'. Found and cleaned up 11 empty switches in `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. Removing empty process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$rtl/layer_sequencer.v:137$742'. Found and cleaned up 20 empty switches in `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. Removing empty process `$paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine.$proc$rtl/graph_engine.v:247$497'. Found and cleaned up 11 empty switches in `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. Removing empty process `$paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory.$proc$rtl/neuron_memory.v:283$303'. Found and cleaned up 10 empty switches in `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. Removing empty process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/mem_arbiter.v:117$297'. Found and cleaned up 6 empty switches in `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. Removing empty process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$rtl/int8_memory_access.v:55$293'. Found and cleaned up 5 empty switches in `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. Removing empty process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$rtl/memory_interface.v:33$291'. Found and cleaned up 17 empty switches in `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. Removing empty process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$rtl/psram_controller.v:197$254'. Cleaned up 220 empty switches. 20.5.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8. Optimizing module $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master. Optimizing module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit. Optimizing module $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine. Optimizing module crc32_byte. Optimizing module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer. Optimizing module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel. Optimizing module spi_slave. Optimizing module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine. Optimizing module $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager. Optimizing module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer. Optimizing module $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine. Optimizing module $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory. Optimizing module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111. Optimizing module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111. Optimizing module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface. Optimizing module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller. Optimizing module spi_neuron_top. 20.6. Executing CHECK pass (checking for obvious problems). Checking module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8... Checking module $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master... Checking module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit... Checking module $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine... Checking module crc32_byte... Checking module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer... Checking module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel... Checking module spi_slave... Checking module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine... Checking module $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager... Checking module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer... Checking module $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine... Checking module $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory... Checking module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111... Checking module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111... Checking module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface... Checking module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller... Checking module spi_neuron_top... Found and reported 0 problems. 20.7. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8. Deleting now unused module $paramod$307abf87d70778edc6f63221b972b477b5df49d0\spi_flash_master. Deleting now unused module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit. Deleting now unused module $paramod$4490f70a6665bb1a8cb7af649c8ec0d26585ac45\flash_copy_engine. Deleting now unused module crc32_byte. Deleting now unused module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer. Deleting now unused module $paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel. Deleting now unused module spi_slave. Deleting now unused module $paramod$27eed3c1dcb70aef7656a7ffb04c90811c462e88\spi_engine. Deleting now unused module $paramod$10d1d3cf18749bbce381472067d9d00d5aef4adc\flash_slot_manager. Deleting now unused module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer. Deleting now unused module $paramod$c942483ddb5b18696b35d148284868f1b2fa8b64\graph_engine. Deleting now unused module $paramod$79958c098f4e7efe85e0f2fccdc4f496fe8d2f0b\neuron_memory. Deleting now unused module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111. Deleting now unused module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111. Deleting now unused module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface. Deleting now unused module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller. 20.8. Executing TRIBUF pass. 20.9. Executing DEMINOUT pass (demote inout ports to input or output). 20.10. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 365 unused cells and 3399 unused wires. 20.12. Executing CHECK pass (checking for obvious problems). Checking module spi_neuron_top... Found and reported 0 problems. 20.13. Executing OPT pass (performing simple optimizations). 20.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 4096 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3279 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3269 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3268 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 828 cells. 20.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\u_graph_engine.\u_neuron.$procmux$2620: \u_graph_engine.u_neuron.finishing -> 1'0 Replacing known input bits on port A of cell $flatten\u_graph_engine.\u_neuron.$procmux$2618: \u_graph_engine.u_neuron.finishing -> 1'0 Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$2620: \u_neuron_memory.u_neuron.finishing -> 1'0 Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$2618: \u_neuron_memory.u_neuron.finishing -> 1'0 Analyzing evaluation results. dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$8594. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4439. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4441. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4443. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4446. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4456. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4458. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4460. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4463. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8884. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4473. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4475. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8887. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4477. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4480. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4490. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4492. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4494. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4497. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8893. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4507. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4509. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8896. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4511. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4514. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4524. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4526. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4528. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4531. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8902. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4541. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4543. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8905. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4545. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4548. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4558. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4560. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4562. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4565. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8914. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4574. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8917. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4576. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4579. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4588. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4590. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4593. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8926. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4602. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8929. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4604. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4607. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4616. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4618. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4621. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8938. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4630. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8941. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4632. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4635. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4644. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4646. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4649. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8951. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4658. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8954. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4660. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4663. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4672. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4674. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4677. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8964. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4685. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4688. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8967. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4696. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4699. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4707. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4710. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4718. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4721. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$8977. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4729. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4732. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8980. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4740. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4743. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4751. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4754. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4762. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4765. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8986. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8992. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$8998. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$9007. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$9016. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$9025. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4975. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4977. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4980. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4993. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$9035. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$4995. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$4998. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5011. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5013. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5016. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5029. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5031. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5034. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5047. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$9045. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5049. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5052. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5065. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5067. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5070. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5083. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5085. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5088. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5101. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$9055. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5103. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5106. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5119. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5121. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5124. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5137. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5139. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5142. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5155. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5157. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5160. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5173. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5175. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5178. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5191. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5193. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5196. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5209. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5211. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5214. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5227. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5229. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5232. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5244. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5247. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5259. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5262. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5274. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5277. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5289. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5292. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5304. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5307. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5319. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5322. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5334. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5337. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5349. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5352. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5364. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5367. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5379. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5382. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5394. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5397. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5409. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5412. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5424. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5427. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5439. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5442. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5454. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5457. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5478. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5480. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5483. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5504. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5506. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5509. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5530. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5532. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5535. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5556. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5558. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5561. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5582. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5584. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5587. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5608. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5610. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5613. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5634. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5636. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5639. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5660. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5662. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5665. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5686. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5688. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5691. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5712. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5714. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5717. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5738. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5740. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5743. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5764. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5766. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5769. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5790. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5792. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5795. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5810. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5813. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5828. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5831. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5846. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5849. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5864. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5867. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5882. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5885. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5900. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5903. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5918. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5921. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5936. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5939. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5954. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5957. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5972. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5975. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$5990. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$5993. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$6008. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6011. dead port 2/2 on $mux $flatten\u_flash_slot_manager.$procmux$6026. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6029. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6044. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6059. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6074. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6089. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6104. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6119. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6134. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6149. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6164. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6179. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6194. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6209. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6224. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6232. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6240. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6248. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6256. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6264. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6272. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6280. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6288. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6410. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6422. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6434. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6446. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6458. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6470. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6482. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6494. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6506. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6518. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6530. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6542. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6554. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6566. dead port 1/2 on $mux $flatten\u_flash_slot_manager.$procmux$6578. dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$8083. dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$8093. dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$8103. dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$8113. dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$8123. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4371. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4373. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4381. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4383. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4392. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4394. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4403. Removed 288 multiplexer ports. 20.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$10306: { $auto$opt_reduce.cc:137:opt_pmux$11041 $flatten\u_psram_ctrl.$procmux$10349_CMP $flatten\u_psram_ctrl.$procmux$10327_CMP $flatten\u_psram_ctrl.$procmux$10352_CMP $flatten\u_psram_ctrl.$procmux$10356_CMP } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.\u_act_buffer.$procmux$2600: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [0] New connections: $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [7:1] = { $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$rtl/act_buffer.v:57$1401_EN[7:0]$1405 [0] } New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$7581: $auto$opt_reduce.cc:137:opt_pmux$11043 Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8309: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$431_EN[7:0]$501 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8312: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$430_EN[7:0]$500 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8315: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$429_EN[7:0]$499 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8318: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$428_EN[7:0]$498 [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$8882: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$8882_Y New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$8882_Y [0] New connections: $flatten\u_neuron_memory.$procmux$8882_Y [7:1] = { $flatten\u_neuron_memory.$procmux$8882_Y [0] $flatten\u_neuron_memory.$procmux$8882_Y [0] $flatten\u_neuron_memory.$procmux$8882_Y [0] $flatten\u_neuron_memory.$procmux$8882_Y [0] $flatten\u_neuron_memory.$procmux$8882_Y [0] $flatten\u_neuron_memory.$procmux$8882_Y [0] $flatten\u_neuron_memory.$procmux$8882_Y [0] } New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8322: { $auto$opt_reduce.cc:137:opt_pmux$11045 $flatten\u_graph_engine.$procmux$8327_CMP } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$4471: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\u_flash_slot_manager.$procmux$4471_Y New ports: A=1'1, B=1'0, Y=$flatten\u_flash_slot_manager.$procmux$4471_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$4471_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] $flatten\u_flash_slot_manager.$procmux$4471_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$4522: Old ports: A=24'111111111111111111111111, B=24'000000000000000000000000, Y=$flatten\u_flash_slot_manager.$procmux$4522_Y New ports: A=1'1, B=1'0, Y=$flatten\u_flash_slot_manager.$procmux$4522_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$4522_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] $flatten\u_flash_slot_manager.$procmux$4522_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$8912: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$8912_Y New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$8912_Y [0] New connections: $flatten\u_neuron_memory.$procmux$8912_Y [7:1] = { $flatten\u_neuron_memory.$procmux$8912_Y [0] $flatten\u_neuron_memory.$procmux$8912_Y [0] $flatten\u_neuron_memory.$procmux$8912_Y [0] $flatten\u_neuron_memory.$procmux$8912_Y [0] $flatten\u_neuron_memory.$procmux$8912_Y [0] $flatten\u_neuron_memory.$procmux$8912_Y [0] $flatten\u_neuron_memory.$procmux$8912_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$8949: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$8949_Y New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$8949_Y [0] New connections: $flatten\u_neuron_memory.$procmux$8949_Y [7:1] = { $flatten\u_neuron_memory.$procmux$8949_Y [0] $flatten\u_neuron_memory.$procmux$8949_Y [0] $flatten\u_neuron_memory.$procmux$8949_Y [0] $flatten\u_neuron_memory.$procmux$8949_Y [0] $flatten\u_neuron_memory.$procmux$8949_Y [0] $flatten\u_neuron_memory.$procmux$8949_Y [0] $flatten\u_neuron_memory.$procmux$8949_Y [0] } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$10206: { $auto$opt_reduce.cc:137:opt_pmux$11047 $flatten\u_psram_ctrl.$procmux$10349_CMP $flatten\u_psram_ctrl.$procmux$10327_CMP $flatten\u_psram_ctrl.$procmux$10352_CMP $flatten\u_psram_ctrl.$procmux$10356_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$10174: { $auto$opt_reduce.cc:137:opt_pmux$11049 $flatten\u_psram_ctrl.$procmux$10349_CMP $flatten\u_psram_ctrl.$procmux$10327_CMP $flatten\u_psram_ctrl.$procmux$10352_CMP $flatten\u_psram_ctrl.$procmux$10356_CMP } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$4973: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$procmux$4973_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$4973_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$4973_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] $flatten\u_flash_slot_manager.$procmux$4973_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8591: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$procmux$8591_Y New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$procmux$8591_Y [0] New connections: $flatten\u_graph_engine.$procmux$8591_Y [7:1] = { $flatten\u_graph_engine.$procmux$8591_Y [0] $flatten\u_graph_engine.$procmux$8591_Y [0] $flatten\u_graph_engine.$procmux$8591_Y [0] $flatten\u_graph_engine.$procmux$8591_Y [0] $flatten\u_graph_engine.$procmux$8591_Y [0] $flatten\u_graph_engine.$procmux$8591_Y [0] $flatten\u_graph_engine.$procmux$8591_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8306: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$432_EN[7:0]$502 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5081: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$procmux$5081_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$5081_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5081_Y [7:1] = { $flatten\u_flash_slot_manager.$procmux$5081_Y [0] $flatten\u_flash_slot_manager.$procmux$5081_Y [0] $flatten\u_flash_slot_manager.$procmux$5081_Y [0] $flatten\u_flash_slot_manager.$procmux$5081_Y [0] $flatten\u_flash_slot_manager.$procmux$5081_Y [0] $flatten\u_flash_slot_manager.$procmux$5081_Y [0] $flatten\u_flash_slot_manager.$procmux$5081_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5135: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$procmux$5135_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$5135_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5135_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] $flatten\u_flash_slot_manager.$procmux$5135_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5189: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$procmux$5189_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$5189_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5189_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] $flatten\u_flash_slot_manager.$procmux$5189_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8273: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$443_EN[7:0]$513 [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$9083: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [0] New connections: $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:304$298_EN[7:0]$304 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8276: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$442_EN[7:0]$512 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5476: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$procmux$5476_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$5476_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5476_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] $flatten\u_flash_slot_manager.$procmux$5476_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5580: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$procmux$5580_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$5580_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5580_Y [7:1] = { $flatten\u_flash_slot_manager.$procmux$5580_Y [0] $flatten\u_flash_slot_manager.$procmux$5580_Y [0] $flatten\u_flash_slot_manager.$procmux$5580_Y [0] $flatten\u_flash_slot_manager.$procmux$5580_Y [0] $flatten\u_flash_slot_manager.$procmux$5580_Y [0] $flatten\u_flash_slot_manager.$procmux$5580_Y [0] $flatten\u_flash_slot_manager.$procmux$5580_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8279: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$441_EN[7:0]$511 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5658: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$procmux$5658_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$5658_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5658_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] $flatten\u_flash_slot_manager.$procmux$5658_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8282: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$440_EN[7:0]$510 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5736: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$procmux$5736_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$5736_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5736_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] $flatten\u_flash_slot_manager.$procmux$5736_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8285: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$439_EN[7:0]$509 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8288: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$438_EN[7:0]$508 [0] } New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8869: { $flatten\u_graph_engine.$procmux$8323_CMP $flatten\u_graph_engine.$procmux$8327_CMP $auto$opt_reduce.cc:137:opt_pmux$11051 } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8303: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$433_EN[7:0]$503 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6584: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$842_EN[31:0]$961 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6590: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$840_EN[7:0]$959 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6593: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$839_EN[23:0]$958 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6596: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$838_EN[23:0]$957 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6599: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$837_EN[31:0]$956 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6605: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$835_EN[7:0]$954 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6608: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$834_EN[23:0]$953 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6611: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$833_EN[23:0]$952 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6614: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$832_EN[31:0]$951 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6620: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$830_EN[7:0]$949 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6623: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$829_EN[23:0]$948 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6626: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$828_EN[23:0]$947 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6629: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$827_EN[31:0]$946 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6635: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$825_EN[7:0]$944 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6638: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$824_EN[23:0]$943 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6641: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$823_EN[23:0]$942 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6644: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$822_EN[31:0]$941 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6650: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$820_EN[7:0]$939 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6653: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$819_EN[23:0]$938 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6656: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$818_EN[23:0]$937 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6659: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$817_EN[31:0]$936 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6665: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$815_EN[7:0]$934 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6668: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$814_EN[23:0]$933 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6671: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$813_EN[23:0]$932 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6674: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$812_EN[31:0]$931 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6680: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$810_EN[7:0]$929 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6683: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$809_EN[23:0]$928 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6686: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$808_EN[23:0]$927 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6689: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$807_EN[31:0]$926 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6695: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$805_EN[7:0]$924 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6698: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$804_EN[23:0]$923 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6701: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$803_EN[23:0]$922 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6704: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$802_EN[31:0]$921 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6710: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$800_EN[7:0]$919 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6713: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$799_EN[23:0]$918 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6716: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$798_EN[23:0]$917 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6719: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$797_EN[31:0]$916 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6725: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$795_EN[7:0]$914 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6728: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$794_EN[23:0]$913 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6731: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$793_EN[23:0]$912 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6734: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$792_EN[31:0]$911 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6740: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$790_EN[7:0]$909 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6743: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$789_EN[23:0]$908 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6746: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$788_EN[23:0]$907 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6749: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$787_EN[31:0]$906 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6755: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$785_EN[7:0]$904 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6758: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$784_EN[23:0]$903 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6761: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$783_EN[23:0]$902 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6764: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$782_EN[31:0]$901 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6770: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$780_EN[7:0]$899 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6773: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$779_EN[23:0]$898 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6776: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$778_EN[23:0]$897 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6779: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$777_EN[31:0]$896 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6785: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$775_EN[7:0]$894 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6788: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$774_EN[23:0]$893 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6791: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$773_EN[23:0]$892 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6794: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$772_EN[31:0]$891 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6800: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$770_EN[7:0]$889 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6803: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$769_EN[23:0]$888 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6806: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$768_EN[23:0]$887 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6809: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:342$767_EN[31:0]$886 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6815: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:340$765_EN[7:0]$884 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6818: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:339$764_EN[23:0]$883 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6821: Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:338$763_EN[23:0]$882 [0] } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$6829: $auto$opt_reduce.cc:137:opt_pmux$11053 New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$6849: { $auto$opt_reduce.cc:137:opt_pmux$11055 $flatten\u_flash_slot_manager.$procmux$6857_CMP } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$6870: { $auto$opt_reduce.cc:137:opt_pmux$11057 $flatten\u_flash_slot_manager.$procmux$6857_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$10061: { $auto$opt_reduce.cc:137:opt_pmux$11059 $flatten\u_psram_ctrl.$procmux$10307_CMP $flatten\u_psram_ctrl.$procmux$10349_CMP $flatten\u_psram_ctrl.$procmux$10327_CMP $flatten\u_psram_ctrl.$procmux$10352_CMP $flatten\u_psram_ctrl.$procmux$10356_CMP $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$255_Y } New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$9344: { $flatten\u_neuron_memory.$procmux$8885_CMP $auto$opt_reduce.cc:137:opt_pmux$11061 $flatten\u_neuron_memory.$procmux$8952_CMP $flatten\u_neuron_memory.$procmux$9119_CMP } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7212: $auto$opt_reduce.cc:137:opt_pmux$11063 New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7245: { $auto$opt_reduce.cc:137:opt_pmux$11065 $flatten\u_flash_slot_manager.$procmux$6857_CMP $flatten\u_flash_slot_manager.$procmux$6858_CMP } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7275: { $auto$opt_reduce.cc:137:opt_pmux$11067 $flatten\u_flash_slot_manager.$procmux$6857_CMP $flatten\u_flash_slot_manager.$procmux$6858_CMP } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7304: { $auto$opt_reduce.cc:137:opt_pmux$11069 $flatten\u_flash_slot_manager.$procmux$6853_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP $flatten\u_flash_slot_manager.$procmux$6858_CMP } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7334: { $flatten\u_flash_slot_manager.$procmux$6850_CMP $auto$opt_reduce.cc:137:opt_pmux$11073 $auto$opt_reduce.cc:137:opt_pmux$11071 $flatten\u_flash_slot_manager.$procmux$6857_CMP } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7387: { $auto$opt_reduce.cc:137:opt_pmux$11075 $flatten\u_flash_slot_manager.$procmux$6857_CMP $flatten\u_flash_slot_manager.$procmux$5477_CMP $flatten\u_flash_slot_manager.$procmux$6858_CMP } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7423: { $auto$opt_reduce.cc:137:opt_pmux$11077 $flatten\u_flash_slot_manager.$procmux$6857_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9963: { $auto$opt_reduce.cc:137:opt_pmux$11079 $flatten\u_psram_ctrl.$procmux$10349_CMP $flatten\u_psram_ctrl.$procmux$10352_CMP $flatten\u_psram_ctrl.$procmux$10356_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9939: { $auto$opt_reduce.cc:137:opt_pmux$11081 $flatten\u_psram_ctrl.$procmux$10349_CMP $flatten\u_psram_ctrl.$procmux$10352_CMP $flatten\u_psram_ctrl.$procmux$10356_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9908: { $auto$opt_reduce.cc:137:opt_pmux$11083 $flatten\u_psram_ctrl.$procmux$10342_CMP $flatten\u_psram_ctrl.$procmux$10349_CMP $flatten\u_psram_ctrl.$procmux$10352_CMP $flatten\u_psram_ctrl.$procmux$10356_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9880: { $auto$opt_reduce.cc:137:opt_pmux$11085 $flatten\u_psram_ctrl.$procmux$10342_CMP $flatten\u_psram_ctrl.$procmux$10349_CMP $flatten\u_psram_ctrl.$procmux$10327_CMP $flatten\u_psram_ctrl.$procmux$10352_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9863: { $auto$opt_reduce.cc:137:opt_pmux$11087 $flatten\u_psram_ctrl.$procmux$10356_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9843: { $auto$opt_reduce.cc:137:opt_pmux$11089 $flatten\u_psram_ctrl.$procmux$10356_CMP $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$255_Y } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2399: { $flatten\u_flash_slot_manager.\u_fce.$procmux$2429_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$2439_CMP $auto$opt_reduce.cc:137:opt_pmux$11091 $flatten\u_flash_slot_manager.\u_fce.$procmux$2447_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$2464_CMP } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2386: { $auto$opt_reduce.cc:137:opt_pmux$11095 $auto$opt_reduce.cc:137:opt_pmux$11093 } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2360: { $auto$opt_reduce.cc:137:opt_pmux$11099 $flatten\u_flash_slot_manager.\u_fce.$procmux$2439_CMP $auto$opt_reduce.cc:137:opt_pmux$11097 } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2347: { $flatten\u_flash_slot_manager.\u_fce.$procmux$2429_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$2439_CMP $auto$opt_reduce.cc:137:opt_pmux$11101 $flatten\u_flash_slot_manager.\u_fce.$procmux$2464_CMP } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8291: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$437_EN[7:0]$507 [0] } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$1982: $auto$opt_reduce.cc:137:opt_pmux$11103 New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$2986: $auto$opt_reduce.cc:137:opt_pmux$11105 New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3178: { $flatten\u_spi_engine.$procmux$3179_CMP $auto$opt_reduce.cc:137:opt_pmux$11107 } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3216: $auto$opt_reduce.cc:137:opt_pmux$11109 New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3444: $auto$opt_reduce.cc:137:opt_pmux$11111 Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8294: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$436_EN[7:0]$506 [0] } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3585: { $auto$opt_reduce.cc:137:opt_pmux$11115 $auto$opt_reduce.cc:137:opt_pmux$11113 $flatten\u_spi_engine.$procmux$3595_CMP $flatten\u_spi_engine.$procmux$3596_CMP $flatten\u_spi_engine.$procmux$3597_CMP $flatten\u_spi_engine.$procmux$3356_CTRL } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8297: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$435_EN[7:0]$505 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8300: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$434_EN[7:0]$504 [0] } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3634: $auto$opt_reduce.cc:137:opt_pmux$11117 Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8100: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$procmux$8100_Y New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$procmux$8100_Y [0] New connections: $flatten\u_graph_engine.$procmux$8100_Y [7:1] = { $flatten\u_graph_engine.$procmux$8100_Y [0] $flatten\u_graph_engine.$procmux$8100_Y [0] $flatten\u_graph_engine.$procmux$8100_Y [0] $flatten\u_graph_engine.$procmux$8100_Y [0] $flatten\u_graph_engine.$procmux$8100_Y [0] $flatten\u_graph_engine.$procmux$8100_Y [0] $flatten\u_graph_engine.$procmux$8100_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8129: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$491_EN[7:0]$561 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8132: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$490_EN[7:0]$560 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8135: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$489_EN[7:0]$559 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8138: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$488_EN[7:0]$558 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8141: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$487_EN[7:0]$557 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8144: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$486_EN[7:0]$556 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8147: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$485_EN[7:0]$555 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8150: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$484_EN[7:0]$554 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8153: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$483_EN[7:0]$553 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8156: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$482_EN[7:0]$552 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8159: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$481_EN[7:0]$551 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8162: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$480_EN[7:0]$550 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8165: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$479_EN[7:0]$549 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8168: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$478_EN[7:0]$548 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8171: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$477_EN[7:0]$547 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8174: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$476_EN[7:0]$546 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8177: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$475_EN[7:0]$545 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8180: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$474_EN[7:0]$544 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8183: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$473_EN[7:0]$543 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8186: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$472_EN[7:0]$542 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8189: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$471_EN[7:0]$541 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8192: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$470_EN[7:0]$540 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8195: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$469_EN[7:0]$539 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8198: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$468_EN[7:0]$538 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8201: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$467_EN[7:0]$537 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8204: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$466_EN[7:0]$536 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8207: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$465_EN[7:0]$535 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8210: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$464_EN[7:0]$534 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8213: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$463_EN[7:0]$533 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8216: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$462_EN[7:0]$532 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8219: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$461_EN[7:0]$531 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8222: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$460_EN[7:0]$530 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8225: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$459_EN[7:0]$529 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8228: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$458_EN[7:0]$528 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8231: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$457_EN[7:0]$527 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8234: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$456_EN[7:0]$526 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8237: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$455_EN[7:0]$525 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8240: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$454_EN[7:0]$524 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8243: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$453_EN[7:0]$523 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8246: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$452_EN[7:0]$522 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8249: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$451_EN[7:0]$521 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8252: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$450_EN[7:0]$520 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8255: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$449_EN[7:0]$519 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8258: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$448_EN[7:0]$518 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8261: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$447_EN[7:0]$517 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8264: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$446_EN[7:0]$516 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8267: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:287$445_EN[7:0]$515 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8270: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:286$444_EN[7:0]$514 [0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$11110: { $flatten\u_spi_engine.$procmux$3417_CMP $flatten\u_spi_engine.$procmux$3418_CMP $flatten\u_spi_engine.$procmux$3419_CMP $flatten\u_spi_engine.$procmux$3420_CMP $flatten\u_spi_engine.$procmux$3421_CMP $flatten\u_spi_engine.$procmux$3422_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$11114: { $flatten\u_spi_engine.$procmux$3417_CMP $flatten\u_spi_engine.$procmux$3418_CMP $flatten\u_spi_engine.$procmux$3419_CMP $flatten\u_spi_engine.$procmux$3420_CMP $flatten\u_spi_engine.$procmux$3421_CMP $flatten\u_spi_engine.$procmux$3422_CMP } Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8385: Old ports: A=$flatten\u_graph_engine.$2$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$643, B=8'00000000, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 New ports: A=$flatten\u_graph_engine.$procmux$8591_Y [0], B=1'0, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [0] New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_EN[7:0]$567 [0] } Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$8394: Old ports: A=$flatten\u_graph_engine.$2$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$640, B=8'00000000, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 New ports: A=$flatten\u_graph_engine.$procmux$8100_Y [0], B=1'0, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [0] New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$rtl/graph_engine.v:520$492_EN[7:0]$564 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$4600: Old ports: A=0, B=$flatten\u_flash_slot_manager.$5$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1300, Y=$flatten\u_flash_slot_manager.$procmux$4600_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$4471_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$4600_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$4600_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] $flatten\u_flash_slot_manager.$procmux$4600_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$4642: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$5$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1297, Y=$flatten\u_flash_slot_manager.$procmux$4642_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$4522_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$4642_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$4642_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] $flatten\u_flash_slot_manager.$procmux$4642_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$8983: Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$356, Y=$flatten\u_neuron_memory.$procmux$8983_Y New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$8882_Y [0], Y=$flatten\u_neuron_memory.$procmux$8983_Y [0] New connections: $flatten\u_neuron_memory.$procmux$8983_Y [7:1] = { $flatten\u_neuron_memory.$procmux$8983_Y [0] $flatten\u_neuron_memory.$procmux$8983_Y [0] $flatten\u_neuron_memory.$procmux$8983_Y [0] $flatten\u_neuron_memory.$procmux$8983_Y [0] $flatten\u_neuron_memory.$procmux$8983_Y [0] $flatten\u_neuron_memory.$procmux$8983_Y [0] $flatten\u_neuron_memory.$procmux$8983_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$9004: Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$346, Y=$flatten\u_neuron_memory.$procmux$9004_Y New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$8912_Y [0], Y=$flatten\u_neuron_memory.$procmux$9004_Y [0] New connections: $flatten\u_neuron_memory.$procmux$9004_Y [7:1] = { $flatten\u_neuron_memory.$procmux$9004_Y [0] $flatten\u_neuron_memory.$procmux$9004_Y [0] $flatten\u_neuron_memory.$procmux$9004_Y [0] $flatten\u_neuron_memory.$procmux$9004_Y [0] $flatten\u_neuron_memory.$procmux$9004_Y [0] $flatten\u_neuron_memory.$procmux$9004_Y [0] $flatten\u_neuron_memory.$procmux$9004_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$9032: Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$335, Y=$flatten\u_neuron_memory.$procmux$9032_Y New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$8949_Y [0], Y=$flatten\u_neuron_memory.$procmux$9032_Y [0] New connections: $flatten\u_neuron_memory.$procmux$9032_Y [7:1] = { $flatten\u_neuron_memory.$procmux$9032_Y [0] $flatten\u_neuron_memory.$procmux$9032_Y [0] $flatten\u_neuron_memory.$procmux$9032_Y [0] $flatten\u_neuron_memory.$procmux$9032_Y [0] $flatten\u_neuron_memory.$procmux$9032_Y [0] $flatten\u_neuron_memory.$procmux$9032_Y [0] $flatten\u_neuron_memory.$procmux$9032_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5242: Old ports: A=0, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$1242, Y=$flatten\u_flash_slot_manager.$procmux$5242_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$4973_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$5242_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5242_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] $flatten\u_flash_slot_manager.$procmux$5242_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5332: Old ports: A=8'00000000, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$1236, Y=$flatten\u_flash_slot_manager.$procmux$5332_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5081_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$5332_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5332_Y [7:1] = { $flatten\u_flash_slot_manager.$procmux$5332_Y [0] $flatten\u_flash_slot_manager.$procmux$5332_Y [0] $flatten\u_flash_slot_manager.$procmux$5332_Y [0] $flatten\u_flash_slot_manager.$procmux$5332_Y [0] $flatten\u_flash_slot_manager.$procmux$5332_Y [0] $flatten\u_flash_slot_manager.$procmux$5332_Y [0] $flatten\u_flash_slot_manager.$procmux$5332_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5377: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$1233, Y=$flatten\u_flash_slot_manager.$procmux$5377_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5135_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$5377_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5377_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] $flatten\u_flash_slot_manager.$procmux$5377_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5422: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$1230, Y=$flatten\u_flash_slot_manager.$procmux$5422_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5189_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$5422_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5422_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] $flatten\u_flash_slot_manager.$procmux$5422_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5808: Old ports: A=0, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$1205, Y=$flatten\u_flash_slot_manager.$procmux$5808_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5476_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$5808_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5808_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] $flatten\u_flash_slot_manager.$procmux$5808_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5880: Old ports: A=8'00000000, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$1201, Y=$flatten\u_flash_slot_manager.$procmux$5880_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5580_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$5880_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5880_Y [7:1] = { $flatten\u_flash_slot_manager.$procmux$5880_Y [0] $flatten\u_flash_slot_manager.$procmux$5880_Y [0] $flatten\u_flash_slot_manager.$procmux$5880_Y [0] $flatten\u_flash_slot_manager.$procmux$5880_Y [0] $flatten\u_flash_slot_manager.$procmux$5880_Y [0] $flatten\u_flash_slot_manager.$procmux$5880_Y [0] $flatten\u_flash_slot_manager.$procmux$5880_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5934: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$1198, Y=$flatten\u_flash_slot_manager.$procmux$5934_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5658_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$5934_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5934_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] $flatten\u_flash_slot_manager.$procmux$5934_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$5988: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$1195, Y=$flatten\u_flash_slot_manager.$procmux$5988_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5736_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$5988_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$5988_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] $flatten\u_flash_slot_manager.$procmux$5988_Y [0] } Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$4705: Old ports: A=0, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1288, Y=$flatten\u_flash_slot_manager.$procmux$4705_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$4600_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$4705_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$4705_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] $flatten\u_flash_slot_manager.$procmux$4705_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$4738: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$4$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1285, Y=$flatten\u_flash_slot_manager.$procmux$4738_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$4642_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$4738_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$4738_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] $flatten\u_flash_slot_manager.$procmux$4738_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$9124: Old ports: A=$flatten\u_neuron_memory.$2$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$332, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 New ports: A=$flatten\u_neuron_memory.$procmux$8983_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [0] New connections: $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$rtl/neuron_memory.v:500$301_EN[7:0]$313 [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$9133: Old ports: A=$flatten\u_neuron_memory.$2$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$329, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 New ports: A=$flatten\u_neuron_memory.$procmux$9004_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [0] New connections: $flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_EN[7:0]$310 [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$9142: Old ports: A=$flatten\u_neuron_memory.$2$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$326, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 New ports: A=$flatten\u_neuron_memory.$procmux$9032_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [0] New connections: $flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_EN[7:0]$307 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6041: Old ports: A=0, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$1192, Y=$flatten\u_flash_slot_manager.$procmux$6041_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5808_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6041_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6041_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] $flatten\u_flash_slot_manager.$procmux$6041_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6101: Old ports: A=8'00000000, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$1188, Y=$flatten\u_flash_slot_manager.$procmux$6101_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5880_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6101_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6101_Y [7:1] = { $flatten\u_flash_slot_manager.$procmux$6101_Y [0] $flatten\u_flash_slot_manager.$procmux$6101_Y [0] $flatten\u_flash_slot_manager.$procmux$6101_Y [0] $flatten\u_flash_slot_manager.$procmux$6101_Y [0] $flatten\u_flash_slot_manager.$procmux$6101_Y [0] $flatten\u_flash_slot_manager.$procmux$6101_Y [0] $flatten\u_flash_slot_manager.$procmux$6101_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6146: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$1185, Y=$flatten\u_flash_slot_manager.$procmux$6146_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5934_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6146_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6146_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] $flatten\u_flash_slot_manager.$procmux$6146_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6191: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$1182, Y=$flatten\u_flash_slot_manager.$procmux$6191_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5988_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6191_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6191_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] $flatten\u_flash_slot_manager.$procmux$6191_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6407: Old ports: A=0, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$1226, Y=$flatten\u_flash_slot_manager.$procmux$6407_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5242_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6407_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6407_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] $flatten\u_flash_slot_manager.$procmux$6407_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6479: Old ports: A=8'00000000, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$1220, Y=$flatten\u_flash_slot_manager.$procmux$6479_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5332_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6479_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6479_Y [7:1] = { $flatten\u_flash_slot_manager.$procmux$6479_Y [0] $flatten\u_flash_slot_manager.$procmux$6479_Y [0] $flatten\u_flash_slot_manager.$procmux$6479_Y [0] $flatten\u_flash_slot_manager.$procmux$6479_Y [0] $flatten\u_flash_slot_manager.$procmux$6479_Y [0] $flatten\u_flash_slot_manager.$procmux$6479_Y [0] $flatten\u_flash_slot_manager.$procmux$6479_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6515: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$1217, Y=$flatten\u_flash_slot_manager.$procmux$6515_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5377_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6515_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6515_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] $flatten\u_flash_slot_manager.$procmux$6515_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6551: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$1214, Y=$flatten\u_flash_slot_manager.$procmux$6551_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$5422_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6551_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6551_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] $flatten\u_flash_slot_manager.$procmux$6551_Y [0] } Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6245: Old ports: A=0, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1280, Y=$flatten\u_flash_slot_manager.$procmux$6245_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$4705_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6245_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6245_Y [31:1] = { $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] $flatten\u_flash_slot_manager.$procmux$6245_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6269: Old ports: A=24'000000000000000000000000, B=$flatten\u_flash_slot_manager.$3$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1277, Y=$flatten\u_flash_slot_manager.$procmux$6269_Y New ports: A=1'0, B=$flatten\u_flash_slot_manager.$procmux$4738_Y [0], Y=$flatten\u_flash_slot_manager.$procmux$6269_Y [0] New connections: $flatten\u_flash_slot_manager.$procmux$6269_Y [23:1] = { $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] $flatten\u_flash_slot_manager.$procmux$6269_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6942: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$1161, B=0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 New ports: A=$flatten\u_flash_slot_manager.$procmux$6407_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_EN[31:0]$989 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6960: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$1155, B=8'00000000, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 New ports: A=$flatten\u_flash_slot_manager.$procmux$6479_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:489$850_EN[7:0]$983 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6969: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$1152, B=24'000000000000000000000000, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 New ports: A=$flatten\u_flash_slot_manager.$procmux$6515_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:488$849_EN[23:0]$980 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6978: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$1149, B=24'000000000000000000000000, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 New ports: A=$flatten\u_flash_slot_manager.$procmux$6551_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:487$848_EN[23:0]$977 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6987: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$1146, B=0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 New ports: A=$flatten\u_flash_slot_manager.$procmux$6041_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$974 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6999: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$1142, B=8'00000000, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 New ports: A=$flatten\u_flash_slot_manager.$procmux$6101_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [7:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_type$rtl/flash_slot_manager.v:376$845_EN[7:0]$970 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$7008: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$1139, B=24'000000000000000000000000, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 New ports: A=$flatten\u_flash_slot_manager.$procmux$6146_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:375$844_EN[23:0]$967 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$7017: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$1136, B=24'000000000000000000000000, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 New ports: A=$flatten\u_flash_slot_manager.$procmux$6191_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_offset$rtl/flash_slot_manager.v:374$843_EN[23:0]$964 [0] } Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6894: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1177, B=0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 New ports: A=$flatten\u_flash_slot_manager.$procmux$6245_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [31:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:609$864_EN[31:0]$1005 [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$6903: Old ports: A=$flatten\u_flash_slot_manager.$2$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1174, B=24'000000000000000000000000, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 New ports: A=$flatten\u_flash_slot_manager.$procmux$6269_Y [0], B=1'0, Y=$flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] New connections: $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [23:1] = { $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] $flatten\u_flash_slot_manager.$0$memwr$\cat_length$rtl/flash_slot_manager.v:608$863_EN[23:0]$1002 [0] } Optimizing cells in module \spi_neuron_top. Performed a total of 222 changes. 20.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 3019 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2800 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2773 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2753 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2733 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2729 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 290 cells. 20.13.6. Executing OPT_DFF pass (perform DFF optimizations). 20.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 1397 unused wires. 20.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.13.9. Rerunning OPT passes. (Maybe there is more to do..) 20.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7123: { $flatten\u_flash_slot_manager.$procmux$4444_CMP $auto$opt_reduce.cc:137:opt_pmux$11119 $flatten\u_flash_slot_manager.$procmux$7140_CMP $flatten\u_flash_slot_manager.$procmux$5481_CMP } New ctrl vector for $pmux cell $flatten\u_arbiter.$procmux$9427: { $auto$opt_reduce.cc:137:opt_pmux$11121 $flatten\u_arbiter.$procmux$9420_CMP } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$2876: { $auto$opt_reduce.cc:137:opt_pmux$11123 $flatten\u_spi_engine.$procmux$2855_CMP } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3002: $auto$opt_reduce.cc:137:opt_pmux$11125 New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3520: { $flatten\u_spi_engine.$procmux$3521_CMP $flatten\u_spi_engine.$eq$rtl/spi_engine.v:364$1309_Y $flatten\u_spi_engine.$procmux$3024_CMP $auto$opt_reduce.cc:137:opt_pmux$11127 $flatten\u_spi_engine.$procmux$3258_CMP $flatten\u_spi_engine.$procmux$3239_CMP $flatten\u_spi_engine.$procmux$2987_CMP $flatten\u_spi_engine.$procmux$3261_CMP $flatten\u_spi_engine.$procmux$2988_CMP $flatten\u_spi_engine.$procmux$3512_CMP $flatten\u_spi_engine.$procmux$2846_CMP $flatten\u_spi_engine.$procmux$2855_CMP $flatten\u_spi_engine.$procmux$2889_CMP $flatten\u_spi_engine.$procmux$2928_CMP } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3715: $auto$opt_reduce.cc:137:opt_pmux$11129 New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3742: { $auto$opt_reduce.cc:137:opt_pmux$11131 $flatten\u_spi_engine.$procmux$3006_CMP $flatten\u_spi_engine.$procmux$3015_CMP } Optimizing cells in module \spi_neuron_top. Performed a total of 7 changes. 20.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2736 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.13.13. Executing OPT_DFF pass (perform DFF optimizations). 20.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.13.16. Rerunning OPT passes. (Maybe there is more to do..) 20.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2736 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.13.20. Executing OPT_DFF pass (perform DFF optimizations). 20.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.13.23. Finished fast OPT passes. (There is nothing left to do.) 20.14. Executing FSM pass (extract and optimize FSM). 20.14.1. Executing FSM_DETECT pass (finding FSMs in design). Found FSM state register spi_neuron_top.u_layer_sequencer.state. Not marking spi_neuron_top.u_neuron_memory.access_wdata as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register spi_neuron_top.u_neuron_memory.state. Found FSM state register spi_neuron_top.u_arbiter.owner. Found FSM state register spi_neuron_top.u_flash_slot_manager.u_fce.u_spi_flash_master.state. Not marking spi_neuron_top.u_flash_slot_manager.u_fce.u_spi_flash_master.hdr_len as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register spi_neuron_top.u_int8_access.state. Found FSM state register spi_neuron_top.u_neuron_memory.u_mem.state. Found FSM state register spi_neuron_top.u_memory_if.state. Not marking spi_neuron_top.u_flash_slot_manager.u_fce.state as FSM state register: Users of register don't seem to benefit from recoding. Not marking spi_neuron_top.u_flash_slot_manager.u_fce.fm_dir as FSM state register: Users of register don't seem to benefit from recoding. Not marking spi_neuron_top.u_flash_slot_manager.u_fce.fm_opcode as FSM state register: Users of register don't seem to benefit from recoding. Not marking spi_neuron_top.u_spi_engine.flash_op_code as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register spi_neuron_top.u_spi_engine.state. Found FSM state register spi_neuron_top.u_spi_engine.flash_payload_len. Found FSM state register spi_neuron_top.u_spi_engine.resp_len. Found FSM state register spi_neuron_top.u_graph_engine.state. Not marking spi_neuron_top.u_flash_slot_manager.state as FSM state register: Users of register don't seem to benefit from recoding. Not marking spi_neuron_top.u_flash_slot_manager.fce_dir as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register spi_neuron_top.u_psram_ctrl.state. 20.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\u_layer_sequencer.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_layer_sequencer.$procdff$10636 root of input selection tree: $flatten\u_layer_sequencer.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \rst found ctrl input: $flatten\u_layer_sequencer.$procmux$7603_CMP found ctrl input: $flatten\u_layer_sequencer.$procmux$7582_CMP found ctrl input: $flatten\u_layer_sequencer.$procmux$7606_CMP found ctrl input: $flatten\u_layer_sequencer.$procmux$7592_CMP found ctrl input: $flatten\u_layer_sequencer.$procmux$7459_CMP found ctrl input: $flatten\u_layer_sequencer.$procmux$7583_CMP found ctrl input: $flatten\u_layer_sequencer.$procmux$7626_CMP found state code: 4'0000 found ctrl input: \u_arbiter.c_ready found ctrl input: $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:321$756_Y found state code: 4'0101 found ctrl input: $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:323$758_Y found state code: 4'0001 found state code: 4'0110 found ctrl input: \u_neuron_memory.done found state code: 4'0100 found ctrl input: $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:255$745_Y found state code: 4'0011 found state code: 4'0010 found ctrl input: \seq_run_start found ctrl input: $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:201$743_Y found ctrl output: $flatten\u_layer_sequencer.$procmux$7626_CMP found ctrl output: $flatten\u_layer_sequencer.$procmux$7606_CMP found ctrl output: $flatten\u_layer_sequencer.$procmux$7603_CMP found ctrl output: $flatten\u_layer_sequencer.$procmux$7592_CMP found ctrl output: $flatten\u_layer_sequencer.$procmux$7583_CMP found ctrl output: $flatten\u_layer_sequencer.$procmux$7582_CMP found ctrl output: $flatten\u_layer_sequencer.$procmux$7459_CMP ctrl inputs: { \u_arbiter.c_ready \u_neuron_memory.done $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:201$743_Y $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:255$745_Y $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:321$756_Y $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:323$758_Y \seq_run_start \rst } ctrl outputs: { $flatten\u_layer_sequencer.$0\state[3:0] $flatten\u_layer_sequencer.$procmux$7459_CMP $flatten\u_layer_sequencer.$procmux$7582_CMP $flatten\u_layer_sequencer.$procmux$7583_CMP $flatten\u_layer_sequencer.$procmux$7592_CMP $flatten\u_layer_sequencer.$procmux$7603_CMP $flatten\u_layer_sequencer.$procmux$7606_CMP $flatten\u_layer_sequencer.$procmux$7626_CMP } transition: 4'0000 8'------00 -> 4'0000 11'00000000001 transition: 4'0000 8'--0---10 -> 4'0001 11'00010000001 transition: 4'0000 8'--1---10 -> 4'0000 11'00000000001 transition: 4'0000 8'-------1 -> 4'0000 11'00000000001 transition: 4'0100 8'-0-----0 -> 4'0100 11'01000000010 transition: 4'0100 8'-1-----0 -> 4'0101 11'01010000010 transition: 4'0100 8'-------1 -> 4'0000 11'00000000010 transition: 4'0010 8'0------0 -> 4'0010 11'00101000000 transition: 4'0010 8'1--0---0 -> 4'0001 11'00011000000 transition: 4'0010 8'1--1---0 -> 4'0011 11'00111000000 transition: 4'0010 8'-------1 -> 4'0000 11'00001000000 transition: 4'0110 8'0------0 -> 4'0110 11'01100000100 transition: 4'0110 8'1---0--0 -> 4'0101 11'01010000100 transition: 4'0110 8'1---10-0 -> 4'0001 11'00010000100 transition: 4'0110 8'1---11-0 -> 4'0000 11'00000000100 transition: 4'0110 8'-------1 -> 4'0000 11'00000000100 transition: 4'0001 8'-------0 -> 4'0010 11'00100010000 transition: 4'0001 8'-------1 -> 4'0000 11'00000010000 transition: 4'0101 8'-------0 -> 4'0110 11'01100100000 transition: 4'0101 8'-------1 -> 4'0000 11'00000100000 transition: 4'0011 8'-------0 -> 4'0100 11'01000001000 transition: 4'0011 8'-------1 -> 4'0000 11'00000001000 Extracting FSM `\u_neuron_memory.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_neuron_memory.$procdff$10748 root of input selection tree: $flatten\u_neuron_memory.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \graph_rst found ctrl input: $flatten\u_neuron_memory.$procmux$8885_CMP found ctrl input: $flatten\u_neuron_memory.$procmux$9088_CMP found ctrl input: $flatten\u_neuron_memory.$procmux$9223_CMP found ctrl input: $flatten\u_neuron_memory.$procmux$8915_CMP found ctrl input: $flatten\u_neuron_memory.$procmux$8952_CMP found ctrl input: $flatten\u_neuron_memory.$procmux$9119_CMP found state code: 4'0000 found ctrl input: \u_neuron_memory.u_neuron.done found ctrl input: $flatten\u_neuron_memory.$eq$rtl/neuron_memory.v:502$358_Y found state code: 4'0010 found state code: 4'0101 found ctrl input: \u_neuron_memory.u_mem.ready found state code: 4'0100 found ctrl input: $flatten\u_neuron_memory.$logic_or$rtl/neuron_memory.v:377$339_Y found state code: 4'0011 found ctrl input: $flatten\u_neuron_memory.$eq$rtl/neuron_memory.v:397$340_Y found ctrl input: \mux_nm_start found state code: 4'0001 found ctrl output: $flatten\u_neuron_memory.$procmux$9223_CMP found ctrl output: $flatten\u_neuron_memory.$procmux$9119_CMP found ctrl output: $flatten\u_neuron_memory.$procmux$9088_CMP found ctrl output: $flatten\u_neuron_memory.$procmux$8952_CMP found ctrl output: $flatten\u_neuron_memory.$procmux$8915_CMP found ctrl output: $flatten\u_neuron_memory.$procmux$8885_CMP ctrl inputs: { $flatten\u_neuron_memory.$logic_or$rtl/neuron_memory.v:377$339_Y $flatten\u_neuron_memory.$eq$rtl/neuron_memory.v:397$340_Y $flatten\u_neuron_memory.$eq$rtl/neuron_memory.v:502$358_Y \u_neuron_memory.u_mem.ready \u_neuron_memory.u_neuron.done \mux_nm_start \graph_rst } ctrl outputs: { $flatten\u_neuron_memory.$0\state[3:0] $flatten\u_neuron_memory.$procmux$8885_CMP $flatten\u_neuron_memory.$procmux$8915_CMP $flatten\u_neuron_memory.$procmux$8952_CMP $flatten\u_neuron_memory.$procmux$9088_CMP $flatten\u_neuron_memory.$procmux$9119_CMP $flatten\u_neuron_memory.$procmux$9223_CMP } transition: 4'0000 7'-----00 -> 4'0000 10'0000000010 transition: 4'0000 7'-----10 -> 4'0001 10'0001000010 transition: 4'0000 7'------1 -> 4'0000 10'0000000010 transition: 4'0100 7'------0 -> 4'0101 10'0101000100 transition: 4'0100 7'------1 -> 4'0000 10'0000000100 transition: 4'0010 7'---0--0 -> 4'0010 10'0010010000 transition: 4'0010 7'0--1--0 -> 4'0010 10'0010010000 transition: 4'0010 7'1--1--0 -> 4'0011 10'0011010000 transition: 4'0010 7'------1 -> 4'0000 10'0000010000 transition: 4'0001 7'---0--0 -> 4'0001 10'0001001000 transition: 4'0001 7'0--1--0 -> 4'0001 10'0001001000 transition: 4'0001 7'10-1--0 -> 4'0010 10'0010001000 transition: 4'0001 7'11-1--0 -> 4'0000 10'0000001000 transition: 4'0001 7'------1 -> 4'0000 10'0000001000 transition: 4'0101 7'----0-0 -> 4'0101 10'0101100000 transition: 4'0101 7'--0-1-0 -> 4'0010 10'0010100000 transition: 4'0101 7'--1-1-0 -> 4'0000 10'0000100000 transition: 4'0101 7'------1 -> 4'0000 10'0000100000 transition: 4'0011 7'---0--0 -> 4'0011 10'0011000001 transition: 4'0011 7'---1--0 -> 4'0100 10'0100000001 transition: 4'0011 7'------1 -> 4'0000 10'0000000001 Extracting FSM `\u_arbiter.owner' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_arbiter.$procdff$10782 root of input selection tree: $flatten\u_arbiter.$0\owner[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \rst found ctrl input: $flatten\u_arbiter.$procmux$9420_CMP found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$11121 found state code: 3'000 found ctrl input: \u_neuron_memory.u_mem.mem_req found ctrl input: \portc_req found ctrl input: \u_spi_engine.ram_req found ctrl input: \flash_d_req found state code: 3'100 found state code: 3'001 found state code: 3'011 found state code: 3'010 found ctrl input: \u_int8_access.ready found ctrl output: $flatten\u_arbiter.$procmux$9420_CMP found ctrl output: $flatten\u_arbiter.$procmux$9399_CMP found ctrl output: $flatten\u_arbiter.$procmux$9388_CMP found ctrl output: $flatten\u_arbiter.$procmux$9378_CMP found ctrl output: $flatten\u_arbiter.$procmux$9369_CMP ctrl inputs: { \u_int8_access.ready \u_neuron_memory.u_mem.mem_req \u_spi_engine.ram_req \portc_req \flash_d_req \rst $auto$opt_reduce.cc:137:opt_pmux$11121 } ctrl outputs: { $flatten\u_arbiter.$0\owner[2:0] $flatten\u_arbiter.$procmux$9369_CMP $flatten\u_arbiter.$procmux$9378_CMP $flatten\u_arbiter.$procmux$9388_CMP $flatten\u_arbiter.$procmux$9399_CMP $flatten\u_arbiter.$procmux$9420_CMP } transition: 3'000 7'-00000- -> 3'000 8'00000001 transition: 3'000 7'-00010- -> 3'100 8'10000001 transition: 3'000 7'-010-0- -> 3'001 8'00100001 transition: 3'000 7'-0-1-0- -> 3'011 8'01100001 transition: 3'000 7'-1---0- -> 3'010 8'01000001 transition: 3'000 7'-----1- -> 3'000 8'00000001 transition: 3'100 7'0----0- -> 3'100 8'10010000 transition: 3'100 7'1----0- -> 3'000 8'00010000 transition: 3'100 7'-----1- -> 3'000 8'00010000 transition: 3'010 7'0----0- -> 3'010 8'01000100 transition: 3'010 7'1----0- -> 3'000 8'00000100 transition: 3'010 7'-----1- -> 3'000 8'00000100 transition: 3'001 7'0----0- -> 3'001 8'00100010 transition: 3'001 7'1----0- -> 3'000 8'00000010 transition: 3'001 7'-----1- -> 3'000 8'00000010 transition: 3'011 7'0----0- -> 3'011 8'01101000 transition: 3'011 7'1----0- -> 3'000 8'00001000 transition: 3'011 7'-----1- -> 3'000 8'00001000 Extracting FSM `\u_flash_slot_manager.u_fce.u_spi_flash_master.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10364 root of input selection tree: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \rst found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1852_CMP found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1757_CMP found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1649_CMP found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1744_CMP found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1681_CMP found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1844_CMP found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1696_CMP found state code: 4'0000 found state code: 4'0111 found ctrl input: \u_flash_slot_manager.u_fce.fm_rdata_ack found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:341$1560_Y found state code: 4'0100 found state code: 4'0110 found ctrl input: \u_flash_slot_manager.u_fce.u_spi_flash_master.sclk_will_rise found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:305$1549_Y found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:302$1548_Y found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:315$1553_Y found state code: 4'0011 found state code: 4'0101 found ctrl input: \u_flash_slot_manager.u_fce.fm_wdata_valid found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:265$1542_Y found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$logic_or$rtl/spi_flash_master.v:269$1545_Y found ctrl input: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:272$1546_Y found state code: 4'0010 found ctrl input: \u_flash_slot_manager.u_fce.fm_start found state code: 4'0001 found ctrl output: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1852_CMP found ctrl output: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1844_CMP found ctrl output: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1757_CMP found ctrl output: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1744_CMP found ctrl output: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1696_CMP found ctrl output: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1681_CMP found ctrl output: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1649_CMP found ctrl output: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1632_CMP ctrl inputs: { \u_flash_slot_manager.u_fce.u_spi_flash_master.sclk_will_rise $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:265$1542_Y $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$logic_or$rtl/spi_flash_master.v:269$1545_Y $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:272$1546_Y $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:302$1548_Y $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:305$1549_Y $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:315$1553_Y $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:341$1560_Y \u_flash_slot_manager.u_fce.fm_rdata_ack \u_flash_slot_manager.u_fce.fm_wdata_valid \u_flash_slot_manager.u_fce.fm_start \rst } ctrl outputs: { $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$0\state[3:0] $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1632_CMP $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1649_CMP $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1681_CMP $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1696_CMP $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1744_CMP $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1757_CMP $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1844_CMP $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1852_CMP } transition: 4'0000 12'----------00 -> 4'0000 12'000000010000 transition: 4'0000 12'----------10 -> 4'0001 12'000100010000 transition: 4'0000 12'-----------1 -> 4'0000 12'000000010000 transition: 4'0100 12'0----------0 -> 4'0100 12'010001000000 transition: 4'0100 12'1----0-----0 -> 4'0100 12'010001000000 transition: 4'0100 12'1---010----0 -> 4'0011 12'001101000000 transition: 4'0100 12'1---011----0 -> 4'0110 12'011001000000 transition: 4'0100 12'1---11-----0 -> 4'0101 12'010101000000 transition: 4'0100 12'-----------1 -> 4'0000 12'000001000000 transition: 4'0010 12'0----------0 -> 4'0010 12'001000100000 transition: 4'0010 12'10---------0 -> 4'0010 12'001000100000 transition: 4'0010 12'1100-------0 -> 4'0100 12'010000100000 transition: 4'0010 12'1101-------0 -> 4'0011 12'001100100000 transition: 4'0010 12'111--------0 -> 4'0110 12'011000100000 transition: 4'0010 12'-----------1 -> 4'0000 12'000000100000 transition: 4'0110 12'-----------0 -> 4'0111 12'011100000001 transition: 4'0110 12'-----------1 -> 4'0000 12'000000000001 transition: 4'0001 12'-----------0 -> 4'0010 12'001000000010 transition: 4'0001 12'-----------1 -> 4'0000 12'000000000010 transition: 4'0101 12'--------0--0 -> 4'0101 12'010100000100 transition: 4'0101 12'-------01--0 -> 4'0100 12'010000000100 transition: 4'0101 12'-------11--0 -> 4'0110 12'011000000100 transition: 4'0101 12'-----------1 -> 4'0000 12'000000000100 transition: 4'0011 12'---------0-0 -> 4'0011 12'001100001000 transition: 4'0011 12'---------1-0 -> 4'0100 12'010000001000 transition: 4'0011 12'-----------1 -> 4'0000 12'000000001000 transition: 4'0111 12'-----------0 -> 4'0000 12'000010000000 transition: 4'0111 12'-----------1 -> 4'0000 12'000010000000 Extracting FSM `\u_int8_access.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_int8_access.$procdff$10791 root of input selection tree: $flatten\u_int8_access.$0\state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \rst found ctrl input: $flatten\u_int8_access.$procmux$9567_CMP found ctrl input: $flatten\u_int8_access.$procmux$9559_CMP found state code: 2'00 found ctrl input: \u_memory_if.ready found ctrl input: \u_arbiter.m_req found state code: 2'01 found ctrl output: $flatten\u_int8_access.$procmux$9567_CMP found ctrl output: $flatten\u_int8_access.$procmux$9559_CMP ctrl inputs: { \u_memory_if.ready \u_arbiter.m_req \rst } ctrl outputs: { $flatten\u_int8_access.$0\state[1:0] $flatten\u_int8_access.$procmux$9559_CMP $flatten\u_int8_access.$procmux$9567_CMP } transition: 2'00 3'-00 -> 2'00 4'0010 transition: 2'00 3'-10 -> 2'01 4'0110 transition: 2'00 3'--1 -> 2'00 4'0010 transition: 2'01 3'0-0 -> 2'01 4'0101 transition: 2'01 3'1-0 -> 2'00 4'0001 transition: 2'01 3'--1 -> 2'00 4'0001 Extracting FSM `\u_neuron_memory.u_mem.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_neuron_memory.\u_mem.$procdff$10791 root of input selection tree: $flatten\u_neuron_memory.\u_mem.$0\state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \graph_rst found ctrl input: $flatten\u_neuron_memory.\u_mem.$procmux$9567_CMP found ctrl input: $flatten\u_neuron_memory.\u_mem.$procmux$9559_CMP found state code: 2'00 found ctrl input: \u_arbiter.b_ready found ctrl input: \u_neuron_memory.access_req found state code: 2'01 found ctrl output: $flatten\u_neuron_memory.\u_mem.$procmux$9567_CMP found ctrl output: $flatten\u_neuron_memory.\u_mem.$procmux$9559_CMP ctrl inputs: { \u_arbiter.b_ready \u_neuron_memory.access_req \graph_rst } ctrl outputs: { $flatten\u_neuron_memory.\u_mem.$procmux$9567_CMP $flatten\u_neuron_memory.\u_mem.$procmux$9559_CMP $flatten\u_neuron_memory.\u_mem.$0\state[1:0] } transition: 2'00 3'-00 -> 2'00 4'0100 transition: 2'00 3'-10 -> 2'01 4'0101 transition: 2'00 3'--1 -> 2'00 4'0100 transition: 2'01 3'0-0 -> 2'01 4'1001 transition: 2'01 3'1-0 -> 2'00 4'1000 transition: 2'01 3'--1 -> 2'00 4'1000 Extracting FSM `\u_memory_if.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_memory_if.$procdff$10801 root of input selection tree: $flatten\u_memory_if.$0\state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \rst found ctrl input: $flatten\u_memory_if.$procmux$9669_CMP found ctrl input: $flatten\u_memory_if.$procmux$9661_CMP found state code: 2'00 found ctrl input: \u_psram_ctrl.mem_ready found ctrl input: \u_int8_access.mem_req found state code: 2'01 found ctrl output: $flatten\u_memory_if.$procmux$9661_CMP found ctrl output: $flatten\u_memory_if.$procmux$9669_CMP ctrl inputs: { \u_psram_ctrl.mem_ready \u_int8_access.mem_req \rst } ctrl outputs: { $flatten\u_memory_if.$0\state[1:0] $flatten\u_memory_if.$procmux$9661_CMP $flatten\u_memory_if.$procmux$9669_CMP } transition: 2'00 3'-00 -> 2'00 4'0010 transition: 2'00 3'-10 -> 2'01 4'0110 transition: 2'00 3'--1 -> 2'00 4'0010 transition: 2'01 3'0-0 -> 2'01 4'0101 transition: 2'01 3'1-0 -> 2'00 4'0001 transition: 2'01 3'--1 -> 2'00 4'0001 Extracting FSM `\u_spi_engine.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_spi_engine.$procdff$10457 root of input selection tree: $flatten\u_spi_engine.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \rst found ctrl input: \u_spi_slave.cs_end found ctrl input: $flatten\u_spi_engine.$procmux$2928_CMP found ctrl input: $flatten\u_spi_engine.$procmux$2889_CMP found ctrl input: $flatten\u_spi_engine.$procmux$2855_CMP found ctrl input: $flatten\u_spi_engine.$procmux$2846_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3512_CMP found ctrl input: $flatten\u_spi_engine.$procmux$2988_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3261_CMP found ctrl input: $flatten\u_spi_engine.$procmux$2987_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3239_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3258_CMP found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$11127 found ctrl input: $flatten\u_spi_engine.$procmux$3024_CMP found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:364$1309_Y found ctrl input: $flatten\u_spi_engine.$procmux$3521_CMP found state code: 4'0000 found ctrl input: \u_spi_slave.rx_valid found ctrl input: $flatten\u_spi_engine.$procmux$3356_CTRL found ctrl input: $flatten\u_spi_engine.$procmux$3597_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3596_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3595_CMP found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$11109 found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$11111 found state code: 4'1011 found state code: 4'0010 found state code: 4'0001 found state code: 4'1100 found state code: 4'1101 found state code: 4'1010 found state code: 4'1110 found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:761$1326_Y found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:765$1327_Y found state code: 4'0011 found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:812$1329_Y found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:817$1330_Y found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:821$1331_Y found state code: 4'0111 found state code: 4'0100 found state code: 4'0101 found state code: 4'0110 found ctrl input: \u_arbiter.a_ready found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:873$1335_Y found state code: 4'1000 found state code: 4'1001 found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1014$1345_Y found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1118$1356_Y found ctrl output: $flatten\u_spi_engine.$procmux$3536_CMP found ctrl output: $flatten\u_spi_engine.$procmux$3521_CMP found ctrl output: $flatten\u_spi_engine.$procmux$3512_CMP found ctrl output: $flatten\u_spi_engine.$procmux$3261_CMP found ctrl output: $flatten\u_spi_engine.$procmux$3258_CMP found ctrl output: $flatten\u_spi_engine.$procmux$3239_CMP found ctrl output: $flatten\u_spi_engine.$procmux$3095_CMP found ctrl output: $flatten\u_spi_engine.$procmux$3024_CMP found ctrl output: $flatten\u_spi_engine.$procmux$2988_CMP found ctrl output: $flatten\u_spi_engine.$procmux$2987_CMP found ctrl output: $flatten\u_spi_engine.$procmux$2928_CMP found ctrl output: $flatten\u_spi_engine.$procmux$2889_CMP found ctrl output: $flatten\u_spi_engine.$procmux$2855_CMP found ctrl output: $flatten\u_spi_engine.$procmux$2846_CMP found ctrl output: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:364$1309_Y ctrl inputs: { \u_arbiter.a_ready $flatten\u_spi_engine.$eq$rtl/spi_engine.v:761$1326_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:765$1327_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:812$1329_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:817$1330_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:821$1331_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:873$1335_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1014$1345_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1118$1356_Y $flatten\u_spi_engine.$procmux$3356_CTRL $flatten\u_spi_engine.$procmux$3595_CMP $flatten\u_spi_engine.$procmux$3596_CMP $flatten\u_spi_engine.$procmux$3597_CMP \u_spi_slave.rx_valid \u_spi_slave.cs_end \rst $auto$opt_reduce.cc:137:opt_pmux$11109 $auto$opt_reduce.cc:137:opt_pmux$11111 $auto$opt_reduce.cc:137:opt_pmux$11127 } ctrl outputs: { $flatten\u_spi_engine.$eq$rtl/spi_engine.v:364$1309_Y $flatten\u_spi_engine.$0\state[3:0] $flatten\u_spi_engine.$procmux$2846_CMP $flatten\u_spi_engine.$procmux$2855_CMP $flatten\u_spi_engine.$procmux$2889_CMP $flatten\u_spi_engine.$procmux$2928_CMP $flatten\u_spi_engine.$procmux$2987_CMP $flatten\u_spi_engine.$procmux$2988_CMP $flatten\u_spi_engine.$procmux$3024_CMP $flatten\u_spi_engine.$procmux$3095_CMP $flatten\u_spi_engine.$procmux$3239_CMP $flatten\u_spi_engine.$procmux$3258_CMP $flatten\u_spi_engine.$procmux$3261_CMP $flatten\u_spi_engine.$procmux$3512_CMP $flatten\u_spi_engine.$procmux$3521_CMP $flatten\u_spi_engine.$procmux$3536_CMP } transition: 4'0000 20'--------------000--- -> 4'0000 19'0000000010000000000 transition: 4'0000 20'----------000010000- -> 4'1011 19'0101100010000000000 transition: 4'0000 20'--------------100-1- -> 4'1110 19'0111000010000000000 transition: 4'0000 20'--------------1001-- -> 4'1010 19'0101000010000000000 transition: 4'0000 20'-----------1--100--- -> 4'1101 19'0110100010000000000 transition: 4'0000 20'------------1-100--- -> 4'1100 19'0110000010000000000 transition: 4'0000 20'-------------1100--- -> 4'0001 19'0000100010000000000 transition: 4'0000 20'----------1---100--- -> 4'0010 19'0001000010000000000 transition: 4'0000 20'---------------10--- -> 4'0000 19'0000000010000000000 transition: 4'0000 20'----------------1--- -> 4'0000 19'0000000010000000000 transition: 4'1000 20'0--------------00--- -> 4'1000 19'0100000000000100000 transition: 4'1000 20'1--------------00--- -> 4'1001 19'0100100000000100000 transition: 4'1000 20'---------------10--- -> 4'0000 19'0000000000000100000 transition: 4'1000 20'----------------1--- -> 4'0000 19'0000000000000100000 transition: 4'0100 20'--------------000--- -> 4'0100 19'0010000000000000100 transition: 4'0100 20'--------------100--- -> 4'0101 19'0010100000000000100 transition: 4'0100 20'---------------10--- -> 4'0000 19'0000000000000000100 transition: 4'0100 20'----------------1--- -> 4'0000 19'0000000000000000100 transition: 4'1100 20'--------------000--- -> 4'1100 19'0110000000001000000 transition: 4'1100 20'--------------100--- -> 4'1011 19'0101100000001000000 transition: 4'1100 20'---------------10--- -> 4'0000 19'0000000000001000000 transition: 4'1100 20'----------------1--- -> 4'0000 19'0000000000001000000 transition: 4'0010 20'--------------000--- -> 4'0010 19'0001001000000000000 transition: 4'0010 20'-0------------100--- -> 4'0010 19'0001001000000000000 transition: 4'0010 20'-10-----------100--- -> 4'0011 19'0001101000000000000 transition: 4'0010 20'-11-----------100--- -> 4'1011 19'0101101000000000000 transition: 4'0010 20'---------------10--- -> 4'0000 19'0000001000000000000 transition: 4'0010 20'----------------1--- -> 4'0000 19'0000001000000000000 transition: 4'1010 20'--------------000--- -> 4'1010 19'1101000000000000000 transition: 4'1010 20'---------0----100--- -> 4'1010 19'1101000000000000000 transition: 4'1010 20'---------1----100--- -> 4'1011 19'1101100000000000000 transition: 4'1010 20'---------------10--- -> 4'0000 19'1000000000000000000 transition: 4'1010 20'----------------1--- -> 4'0000 19'1000000000000000000 transition: 4'0110 20'0--------------00--- -> 4'0110 19'0011000000000001000 transition: 4'0110 20'1-----0--------00--- -> 4'0100 19'0010000000000001000 transition: 4'0110 20'1-----1--------00--- -> 4'1011 19'0101100000000001000 transition: 4'0110 20'---------------10--- -> 4'0000 19'0000000000000001000 transition: 4'0110 20'----------------1--- -> 4'0000 19'0000000000000001000 transition: 4'1110 20'--------------000--- -> 4'1110 19'0111000000010000000 transition: 4'1110 20'-------0------100--- -> 4'1110 19'0111000000010000000 transition: 4'1110 20'-------10-----100--- -> 4'1011 19'0101100000010000000 transition: 4'1110 20'-------11-----100--- -> 4'1010 19'0101000000010000000 transition: 4'1110 20'---------------10--- -> 4'0000 19'0000000000010000000 transition: 4'1110 20'----------------1--- -> 4'0000 19'0000000000010000000 transition: 4'0001 20'--------------000--- -> 4'0001 19'0000100100000000000 transition: 4'0001 20'--------------100--- -> 4'0010 19'0001000100000000000 transition: 4'0001 20'---------------10--- -> 4'0000 19'0000000100000000000 transition: 4'0001 20'----------------1--- -> 4'0000 19'0000000100000000000 transition: 4'1001 20'--------------000--- -> 4'1001 19'0100100000000010000 transition: 4'1001 20'------0-------100--- -> 4'0111 19'0011100000000010000 transition: 4'1001 20'------1-------100--- -> 4'1011 19'0101100000000010000 transition: 4'1001 20'---------------10--- -> 4'0000 19'0000000000000010000 transition: 4'1001 20'----------------1--- -> 4'0000 19'0000000000000010000 transition: 4'0101 20'---------------00--- -> 4'0110 19'0011000000100000000 transition: 4'0101 20'---------------10--- -> 4'0000 19'0000000000100000000 transition: 4'0101 20'----------------1--- -> 4'0000 19'0000000000100000000 transition: 4'1101 20'--------------000--- -> 4'1101 19'0110100000000000001 transition: 4'1101 20'--------------100--- -> 4'1011 19'0101100000000000001 transition: 4'1101 20'---------------10--- -> 4'0000 19'0000000000000000001 transition: 4'1101 20'----------------1--- -> 4'0000 19'0000000000000000001 transition: 4'0011 20'--------------000--- -> 4'0011 19'0001110000000000000 transition: 4'0011 20'---0----------100--- -> 4'0011 19'0001110000000000000 transition: 4'0011 20'---100--------100--- -> 4'0111 19'0011110000000000000 transition: 4'0011 20'---101--------100--- -> 4'0100 19'0010010000000000000 transition: 4'0011 20'---11---------100--- -> 4'1011 19'0101110000000000000 transition: 4'0011 20'---------------10--- -> 4'0000 19'0000010000000000000 transition: 4'0011 20'----------------1--- -> 4'0000 19'0000010000000000000 transition: 4'1011 20'---------------00--- -> 4'1011 19'0101100000000000010 transition: 4'1011 20'---------------10--- -> 4'0000 19'0000000000000000010 transition: 4'1011 20'----------------1--- -> 4'0000 19'0000000000000000010 transition: 4'0111 20'---------------00--- -> 4'1000 19'0100000001000000000 transition: 4'0111 20'---------------10--- -> 4'0000 19'0000000001000000000 transition: 4'0111 20'----------------1--- -> 4'0000 19'0000000001000000000 Extracting FSM `\u_spi_engine.flash_payload_len' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_spi_engine.$procdff$10462 root of input selection tree: $flatten\u_spi_engine.$0\flash_payload_len[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \rst found ctrl input: \u_spi_slave.cs_end found ctrl input: $flatten\u_spi_engine.$procmux$2928_CMP found ctrl input: \u_spi_slave.rx_valid found ctrl input: $flatten\u_spi_engine.$procmux$3417_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3418_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3419_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3420_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3421_CMP found ctrl input: $flatten\u_spi_engine.$procmux$3422_CTRL found state code: 4'0001 found state code: 4'0111 found state code: 4'0100 found state code: 4'1000 found state code: 4'0011 found state code: 4'1001 found state code: 4'0000 ctrl inputs: { $flatten\u_spi_engine.$procmux$2928_CMP $flatten\u_spi_engine.$procmux$3417_CMP $flatten\u_spi_engine.$procmux$3418_CMP $flatten\u_spi_engine.$procmux$3419_CMP $flatten\u_spi_engine.$procmux$3420_CMP $flatten\u_spi_engine.$procmux$3421_CMP $flatten\u_spi_engine.$procmux$3422_CTRL \u_spi_slave.rx_valid \u_spi_slave.cs_end \rst } ctrl outputs: $flatten\u_spi_engine.$0\flash_payload_len[3:0] transition: 4'0000 10'0-------00 -> 4'0000 4'0000 transition: 4'0000 10'1------000 -> 4'0000 4'0000 transition: 4'0000 10'1000000100 -> 4'0000 4'0000 transition: 4'0000 10'1-----1100 -> 4'1001 4'1001 transition: 4'0000 10'1----1-100 -> 4'0011 4'0011 transition: 4'0000 10'1---1--100 -> 4'1000 4'1000 transition: 4'0000 10'1--1---100 -> 4'0100 4'0100 transition: 4'0000 10'1-1----100 -> 4'0111 4'0111 transition: 4'0000 10'11-----100 -> 4'0001 4'0001 transition: 4'0000 10'--------10 -> 4'0000 4'0000 transition: 4'0000 10'---------1 -> 4'0000 4'0000 transition: 4'1000 10'0-------00 -> 4'1000 4'1000 transition: 4'1000 10'1------000 -> 4'1000 4'1000 transition: 4'1000 10'1000000100 -> 4'1000 4'1000 transition: 4'1000 10'1-----1100 -> 4'1001 4'1001 transition: 4'1000 10'1----1-100 -> 4'0011 4'0011 transition: 4'1000 10'1---1--100 -> 4'1000 4'1000 transition: 4'1000 10'1--1---100 -> 4'0100 4'0100 transition: 4'1000 10'1-1----100 -> 4'0111 4'0111 transition: 4'1000 10'11-----100 -> 4'0001 4'0001 transition: 4'1000 10'--------10 -> 4'1000 4'1000 transition: 4'1000 10'---------1 -> 4'0000 4'0000 transition: 4'0100 10'0-------00 -> 4'0100 4'0100 transition: 4'0100 10'1------000 -> 4'0100 4'0100 transition: 4'0100 10'1000000100 -> 4'0100 4'0100 transition: 4'0100 10'1-----1100 -> 4'1001 4'1001 transition: 4'0100 10'1----1-100 -> 4'0011 4'0011 transition: 4'0100 10'1---1--100 -> 4'1000 4'1000 transition: 4'0100 10'1--1---100 -> 4'0100 4'0100 transition: 4'0100 10'1-1----100 -> 4'0111 4'0111 transition: 4'0100 10'11-----100 -> 4'0001 4'0001 transition: 4'0100 10'--------10 -> 4'0100 4'0100 transition: 4'0100 10'---------1 -> 4'0000 4'0000 transition: 4'0001 10'0-------00 -> 4'0001 4'0001 transition: 4'0001 10'1------000 -> 4'0001 4'0001 transition: 4'0001 10'1000000100 -> 4'0001 4'0001 transition: 4'0001 10'1-----1100 -> 4'1001 4'1001 transition: 4'0001 10'1----1-100 -> 4'0011 4'0011 transition: 4'0001 10'1---1--100 -> 4'1000 4'1000 transition: 4'0001 10'1--1---100 -> 4'0100 4'0100 transition: 4'0001 10'1-1----100 -> 4'0111 4'0111 transition: 4'0001 10'11-----100 -> 4'0001 4'0001 transition: 4'0001 10'--------10 -> 4'0001 4'0001 transition: 4'0001 10'---------1 -> 4'0000 4'0000 transition: 4'1001 10'0-------00 -> 4'1001 4'1001 transition: 4'1001 10'1------000 -> 4'1001 4'1001 transition: 4'1001 10'1000000100 -> 4'1001 4'1001 transition: 4'1001 10'1-----1100 -> 4'1001 4'1001 transition: 4'1001 10'1----1-100 -> 4'0011 4'0011 transition: 4'1001 10'1---1--100 -> 4'1000 4'1000 transition: 4'1001 10'1--1---100 -> 4'0100 4'0100 transition: 4'1001 10'1-1----100 -> 4'0111 4'0111 transition: 4'1001 10'11-----100 -> 4'0001 4'0001 transition: 4'1001 10'--------10 -> 4'1001 4'1001 transition: 4'1001 10'---------1 -> 4'0000 4'0000 transition: 4'0011 10'0-------00 -> 4'0011 4'0011 transition: 4'0011 10'1------000 -> 4'0011 4'0011 transition: 4'0011 10'1000000100 -> 4'0011 4'0011 transition: 4'0011 10'1-----1100 -> 4'1001 4'1001 transition: 4'0011 10'1----1-100 -> 4'0011 4'0011 transition: 4'0011 10'1---1--100 -> 4'1000 4'1000 transition: 4'0011 10'1--1---100 -> 4'0100 4'0100 transition: 4'0011 10'1-1----100 -> 4'0111 4'0111 transition: 4'0011 10'11-----100 -> 4'0001 4'0001 transition: 4'0011 10'--------10 -> 4'0011 4'0011 transition: 4'0011 10'---------1 -> 4'0000 4'0000 transition: 4'0111 10'0-------00 -> 4'0111 4'0111 transition: 4'0111 10'1------000 -> 4'0111 4'0111 transition: 4'0111 10'1000000100 -> 4'0111 4'0111 transition: 4'0111 10'1-----1100 -> 4'1001 4'1001 transition: 4'0111 10'1----1-100 -> 4'0011 4'0011 transition: 4'0111 10'1---1--100 -> 4'1000 4'1000 transition: 4'0111 10'1--1---100 -> 4'0100 4'0100 transition: 4'0111 10'1-1----100 -> 4'0111 4'0111 transition: 4'0111 10'11-----100 -> 4'0001 4'0001 transition: 4'0111 10'--------10 -> 4'0111 4'0111 transition: 4'0111 10'---------1 -> 4'0000 4'0000 Extracting FSM `\u_spi_engine.resp_len' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_spi_engine.$procdff$10471 root of input selection tree: $flatten\u_spi_engine.$0\resp_len[4:0] found reset state: 5'00000 (guessed from mux tree) found ctrl input: \rst found ctrl input: \u_spi_slave.cs_end found ctrl input: $flatten\u_spi_engine.$procmux$3024_CMP found ctrl input: $flatten\u_spi_engine.$procmux$2928_CMP found ctrl input: \u_spi_slave.rx_valid found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1014$1345_Y found ctrl input: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y found state code: 5'10000 found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$11107 found ctrl input: $flatten\u_spi_engine.$procmux$3179_CMP found state code: 5'00001 found state code: 5'01011 found state code: 5'00000 ctrl inputs: { $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1014$1345_Y $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$2928_CMP $flatten\u_spi_engine.$procmux$3024_CMP $flatten\u_spi_engine.$procmux$3179_CMP \u_spi_slave.rx_valid \u_spi_slave.cs_end \rst $auto$opt_reduce.cc:137:opt_pmux$11107 } ctrl outputs: $flatten\u_spi_engine.$0\resp_len[4:0] transition: 5'00000 9'--00--00- -> 5'00000 5'00000 transition: 5'00000 9'--1--000- -> 5'00000 5'00000 transition: 5'00000 9'--1-01000 -> 5'00000 5'00000 transition: 5'00000 9'--1-1100- -> 5'01011 5'01011 transition: 5'00000 9'--1--1001 -> 5'00001 5'00001 transition: 5'00000 9'---1-000- -> 5'00000 5'00000 transition: 5'00000 9'0--1-100- -> 5'00000 5'00000 transition: 5'00000 9'10-1-100- -> 5'00000 5'00000 transition: 5'00000 9'11-1-100- -> 5'10000 5'10000 transition: 5'00000 9'------10- -> 5'00000 5'00000 transition: 5'00000 9'-------1- -> 5'00000 5'00000 transition: 5'10000 9'--00--00- -> 5'10000 5'10000 transition: 5'10000 9'--1--000- -> 5'10000 5'10000 transition: 5'10000 9'--1-01000 -> 5'10000 5'10000 transition: 5'10000 9'--1-1100- -> 5'01011 5'01011 transition: 5'10000 9'--1--1001 -> 5'00001 5'00001 transition: 5'10000 9'---1-000- -> 5'10000 5'10000 transition: 5'10000 9'0--1-100- -> 5'10000 5'10000 transition: 5'10000 9'10-1-100- -> 5'10000 5'10000 transition: 5'10000 9'11-1-100- -> 5'10000 5'10000 transition: 5'10000 9'------10- -> 5'10000 5'10000 transition: 5'10000 9'-------1- -> 5'00000 5'00000 transition: 5'00001 9'--00--00- -> 5'00001 5'00001 transition: 5'00001 9'--1--000- -> 5'00001 5'00001 transition: 5'00001 9'--1-01000 -> 5'00001 5'00001 transition: 5'00001 9'--1-1100- -> 5'01011 5'01011 transition: 5'00001 9'--1--1001 -> 5'00001 5'00001 transition: 5'00001 9'---1-000- -> 5'00001 5'00001 transition: 5'00001 9'0--1-100- -> 5'00001 5'00001 transition: 5'00001 9'10-1-100- -> 5'00001 5'00001 transition: 5'00001 9'11-1-100- -> 5'10000 5'10000 transition: 5'00001 9'------10- -> 5'00001 5'00001 transition: 5'00001 9'-------1- -> 5'00000 5'00000 transition: 5'01011 9'--00--00- -> 5'01011 5'01011 transition: 5'01011 9'--1--000- -> 5'01011 5'01011 transition: 5'01011 9'--1-01000 -> 5'01011 5'01011 transition: 5'01011 9'--1-1100- -> 5'01011 5'01011 transition: 5'01011 9'--1--1001 -> 5'00001 5'00001 transition: 5'01011 9'---1-000- -> 5'01011 5'01011 transition: 5'01011 9'0--1-100- -> 5'01011 5'01011 transition: 5'01011 9'10-1-100- -> 5'01011 5'01011 transition: 5'01011 9'11-1-100- -> 5'10000 5'10000 transition: 5'01011 9'------10- -> 5'01011 5'01011 transition: 5'01011 9'-------1- -> 5'00000 5'00000 Extracting FSM `\u_graph_engine.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_graph_engine.$procdff$10656 root of input selection tree: $flatten\u_graph_engine.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \graph_rst found ctrl input: $flatten\u_graph_engine.$procmux$8362_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8323_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8348_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8338_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8081_CMP found ctrl input: $flatten\u_graph_engine.$procmux$7967_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8327_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8002_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8328_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8351_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8329_CMP found ctrl input: $flatten\u_graph_engine.$procmux$8650_CTRL found state code: 4'0000 found ctrl input: \u_arbiter.c_ready found ctrl input: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:552$670_Y found state code: 4'0011 found state code: 4'1011 found ctrl input: \u_graph_engine.u_neuron.done found ctrl input: \u_graph_engine.is_output_sink found state code: 4'1010 found state code: 4'1001 found ctrl input: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:523$667_Y found state code: 4'0101 found state code: 4'1000 found ctrl input: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:474$659_Y found ctrl input: $flatten\u_graph_engine.$logic_or$rtl/graph_engine.v:481$664_Y found state code: 4'0111 found state code: 4'1100 found ctrl input: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:445$655_Y found state code: 4'0110 found ctrl input: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:414$650_Y found state code: 4'0100 found ctrl input: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:346$646_Y found state code: 4'0001 found ctrl input: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:365$647_Y found state code: 4'0010 found ctrl input: \graph_run_start found ctrl output: $flatten\u_graph_engine.$procmux$8650_CMP [1] found ctrl output: $flatten\u_graph_engine.$procmux$8650_CMP [0] found ctrl output: $flatten\u_graph_engine.$procmux$8362_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8351_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8348_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8338_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8329_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8328_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8327_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8323_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8081_CMP found ctrl output: $flatten\u_graph_engine.$procmux$8002_CMP found ctrl output: $flatten\u_graph_engine.$procmux$7967_CMP ctrl inputs: { \u_arbiter.c_ready \u_graph_engine.is_output_sink $flatten\u_graph_engine.$eq$rtl/graph_engine.v:346$646_Y $flatten\u_graph_engine.$eq$rtl/graph_engine.v:365$647_Y $flatten\u_graph_engine.$eq$rtl/graph_engine.v:414$650_Y $flatten\u_graph_engine.$eq$rtl/graph_engine.v:445$655_Y $flatten\u_graph_engine.$eq$rtl/graph_engine.v:474$659_Y $flatten\u_graph_engine.$logic_or$rtl/graph_engine.v:481$664_Y $flatten\u_graph_engine.$eq$rtl/graph_engine.v:523$667_Y $flatten\u_graph_engine.$eq$rtl/graph_engine.v:552$670_Y $flatten\u_graph_engine.$procmux$8650_CTRL \u_graph_engine.u_neuron.done \graph_rst \graph_run_start } ctrl outputs: { $flatten\u_graph_engine.$0\state[3:0] $flatten\u_graph_engine.$procmux$7967_CMP $flatten\u_graph_engine.$procmux$8002_CMP $flatten\u_graph_engine.$procmux$8081_CMP $flatten\u_graph_engine.$procmux$8323_CMP $flatten\u_graph_engine.$procmux$8327_CMP $flatten\u_graph_engine.$procmux$8328_CMP $flatten\u_graph_engine.$procmux$8329_CMP $flatten\u_graph_engine.$procmux$8338_CMP $flatten\u_graph_engine.$procmux$8348_CMP $flatten\u_graph_engine.$procmux$8351_CMP $flatten\u_graph_engine.$procmux$8362_CMP $flatten\u_graph_engine.$procmux$8650_CMP } transition: 4'0000 14'------------00 -> 4'0000 17'00000000000000001 transition: 4'0000 14'------------01 -> 4'0001 17'00010000000000001 transition: 4'0000 14'------------1- -> 4'0000 17'00000000000000001 transition: 4'1000 14'------------0- -> 4'1001 17'10010000000100000 transition: 4'1000 14'------------1- -> 4'0000 17'00000000000100000 transition: 4'0100 14'0-----------0- -> 4'0100 17'01000100000000000 transition: 4'0100 14'1---0-------0- -> 4'0011 17'00110100000000000 transition: 4'0100 14'1---1-------0- -> 4'0101 17'01010100000000000 transition: 4'0100 14'------------1- -> 4'0000 17'00000100000000000 transition: 4'1100 14'------------00 -> 4'1100 17'11000000000000010 transition: 4'1100 14'------------01 -> 4'0001 17'00010000000000010 transition: 4'1100 14'------------1- -> 4'0000 17'00000000000000010 transition: 4'0010 14'0-----------0- -> 4'0010 17'00100000000001000 transition: 4'0010 14'1-0---------0- -> 4'0001 17'00010000000001000 transition: 4'0010 14'1-10--------0- -> 4'0011 17'00110000000001000 transition: 4'0010 14'1-11--------0- -> 4'0000 17'00000000000001000 transition: 4'0010 14'------------1- -> 4'0000 17'00000000000001000 transition: 4'1010 14'------------0- -> 4'1011 17'10110001000000000 transition: 4'1010 14'------------1- -> 4'0000 17'00000001000000000 transition: 4'0110 14'0-----------0- -> 4'0110 17'01101000000000000 transition: 4'0110 14'1-----0-----0- -> 4'0101 17'01011000000000000 transition: 4'0110 14'1-----10----0- -> 4'0111 17'01111000000000000 transition: 4'0110 14'1-----11----0- -> 4'1100 17'11001000000000000 transition: 4'0110 14'------------1- -> 4'0000 17'00001000000000000 transition: 4'0001 14'------------0- -> 4'0010 17'00100000001000000 transition: 4'0001 14'------------1- -> 4'0000 17'00000000001000000 transition: 4'1001 14'-----------00- -> 4'1001 17'10010000000010000 transition: 4'1001 14'-0-------0-10- -> 4'0011 17'00110000000010000 transition: 4'1001 14'-0-------1-10- -> 4'0000 17'00000000000010000 transition: 4'1001 14'-1---------10- -> 4'1010 17'10100000000010000 transition: 4'1001 14'------------1- -> 4'0000 17'00000000000010000 transition: 4'0101 14'-----0------0- -> 4'0110 17'01100000100000000 transition: 4'0101 14'-----1------0- -> 4'1100 17'11000000100000000 transition: 4'0101 14'------------1- -> 4'0000 17'00000000100000000 transition: 4'0011 14'------------0- -> 4'0100 17'01000000010000000 transition: 4'0011 14'------------1- -> 4'0000 17'00000000010000000 transition: 4'1011 14'0-----------0- -> 4'1011 17'10110000000000100 transition: 4'1011 14'1--------0--0- -> 4'0011 17'00110000000000100 transition: 4'1011 14'1--------1--0- -> 4'0000 17'00000000000000100 transition: 4'1011 14'------------1- -> 4'0000 17'00000000000000100 transition: 4'0111 14'--------0---0- -> 4'0101 17'01010010000000000 transition: 4'0111 14'--------1---0- -> 4'1000 17'10000010000000000 transition: 4'0111 14'------------1- -> 4'0000 17'00000010000000000 Extracting FSM `\u_psram_ctrl.state' from module `\spi_neuron_top'. found $dff cell for state register: $flatten\u_psram_ctrl.$procdff$10811 root of input selection tree: $flatten\u_psram_ctrl.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \rst found ctrl input: $flatten\u_psram_ctrl.$procmux$10062_CMP found ctrl input: $flatten\u_psram_ctrl.$procmux$10066_CMP found ctrl input: $flatten\u_psram_ctrl.$procmux$10103_CMP found ctrl input: $flatten\u_psram_ctrl.$procmux$10067_CMP found ctrl input: $flatten\u_psram_ctrl.$procmux$10024_CMP found ctrl input: $flatten\u_psram_ctrl.$procmux$10078_CMP found ctrl input: $flatten\u_psram_ctrl.$procmux$10001_CMP found ctrl input: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$256_Y found ctrl input: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$255_Y found state code: 4'0000 found ctrl input: \u_psram_ctrl.cr_init_active found state code: 4'0001 found state code: 4'0101 found ctrl input: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:765$287_Y found state code: 4'0100 found ctrl input: \u_psram_ctrl.wr_reg found state code: 4'0010 found state code: 4'0011 found state code: 4'1000 found ctrl input: \u_memory_if.mem_req found ctrl input: $flatten\u_psram_ctrl.$ge$rtl/psram_controller.v:605$282_Y found ctrl input: $flatten\u_psram_ctrl.$logic_or$rtl/psram_controller.v:604$283_Y found state code: 4'0111 found ctrl input: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:515$279_Y found state code: 4'0110 found ctrl input: $flatten\u_psram_ctrl.$logic_or$rtl/psram_controller.v:412$270_Y found ctrl input: \u_memory_if.mem_wr found ctrl input: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:340$263_Y found ctrl input: $flatten\u_psram_ctrl.$lt$rtl/psram_controller.v:362$264_Y found ctrl input: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:312$261_Y found ctrl output: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$256_Y found ctrl output: $flatten\u_psram_ctrl.$procmux$10001_CMP found ctrl output: $flatten\u_psram_ctrl.$procmux$10024_CMP found ctrl output: $flatten\u_psram_ctrl.$procmux$10103_CMP found ctrl output: $flatten\u_psram_ctrl.$procmux$10078_CMP found ctrl output: $flatten\u_psram_ctrl.$procmux$10066_CMP found ctrl output: $flatten\u_psram_ctrl.$procmux$10067_CMP found ctrl output: $flatten\u_psram_ctrl.$procmux$10062_CMP found ctrl output: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$255_Y ctrl inputs: { \u_psram_ctrl.wr_reg \u_psram_ctrl.cr_init_active $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:312$261_Y $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:340$263_Y $flatten\u_psram_ctrl.$lt$rtl/psram_controller.v:362$264_Y $flatten\u_psram_ctrl.$logic_or$rtl/psram_controller.v:412$270_Y $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:515$279_Y $flatten\u_psram_ctrl.$ge$rtl/psram_controller.v:605$282_Y $flatten\u_psram_ctrl.$logic_or$rtl/psram_controller.v:604$283_Y $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:765$287_Y \u_memory_if.mem_req \u_memory_if.mem_wr \rst } ctrl outputs: { $flatten\u_psram_ctrl.$0\state[3:0] $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$255_Y $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$256_Y $flatten\u_psram_ctrl.$procmux$10001_CMP $flatten\u_psram_ctrl.$procmux$10024_CMP $flatten\u_psram_ctrl.$procmux$10062_CMP $flatten\u_psram_ctrl.$procmux$10066_CMP $flatten\u_psram_ctrl.$procmux$10067_CMP $flatten\u_psram_ctrl.$procmux$10078_CMP $flatten\u_psram_ctrl.$procmux$10103_CMP } transition: 4'0000 13'--0---------0 -> 4'0000 13'0000100000000 transition: 4'0000 13'--1---------0 -> 4'0101 13'0101100000000 transition: 4'0000 13'------------1 -> 4'0000 13'0000100000000 transition: 4'1000 13'0-----------0 -> 4'0010 13'0010000000001 transition: 4'1000 13'1-----------0 -> 4'0011 13'0011000000001 transition: 4'1000 13'------------1 -> 4'0000 13'0000000000001 transition: 4'0100 13'-0----------0 -> 4'0001 13'0001000010000 transition: 4'0100 13'-1----------0 -> 4'0101 13'0101000010000 transition: 4'0100 13'------------1 -> 4'0000 13'0000000010000 transition: 4'0010 13'------0-----0 -> 4'0010 13'0010000000010 transition: 4'0010 13'-0----1-----0 -> 4'0110 13'0110000000010 transition: 4'0010 13'-1----1-----0 -> 4'0101 13'0101000000010 transition: 4'0010 13'------------1 -> 4'0000 13'0000000000010 transition: 4'0110 13'-------0--0-0 -> 4'0110 13'0110000100000 transition: 4'0110 13'-------1--0-0 -> 4'0001 13'0001000100000 transition: 4'0110 13'--------0-1-0 -> 4'0010 13'0010000100000 transition: 4'0110 13'--------1-1-0 -> 4'0111 13'0111000100000 transition: 4'0110 13'------------1 -> 4'0000 13'0000000100000 transition: 4'0001 13'-----0------0 -> 4'0001 13'0001001000000 transition: 4'0001 13'-----1-----00 -> 4'0010 13'0010001000000 transition: 4'0001 13'-----1-----10 -> 4'0011 13'0011001000000 transition: 4'0001 13'------------1 -> 4'0000 13'0000001000000 transition: 4'0101 13'---00-------0 -> 4'0011 13'0011010000000 transition: 4'0101 13'---01-------0 -> 4'0010 13'0010010000000 transition: 4'0101 13'---1--------0 -> 4'0001 13'0001010000000 transition: 4'0101 13'------------1 -> 4'0000 13'0000010000000 transition: 4'0011 13'---------0--0 -> 4'0011 13'0011000001000 transition: 4'0011 13'---------1--0 -> 4'0100 13'0100000001000 transition: 4'0011 13'------------1 -> 4'0000 13'0000000001000 transition: 4'0111 13'------------0 -> 4'1000 13'1000000000100 transition: 4'0111 13'------------1 -> 4'0000 13'0000000000100 20.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\u_psram_ctrl.state$11214' from module `\spi_neuron_top'. Optimizing FSM `$fsm$\u_graph_engine.state$11199' from module `\spi_neuron_top'. Removing unused input signal $flatten\u_graph_engine.$procmux$8650_CTRL. Optimizing FSM `$fsm$\u_spi_engine.resp_len$11197' from module `\spi_neuron_top'. Merging pattern 9'10-1-100- and 9'11-1-100- from group (1 1 5'10000). Merging pattern 9'11-1-100- and 9'10-1-100- from group (1 1 5'10000). Merging pattern 9'0--1-100- and 9'1--1-100- from group (1 1 5'10000). Merging pattern 9'1--1-100- and 9'0--1-100- from group (1 1 5'10000). Merging pattern 9'---1-000- and 9'---1-100- from group (1 1 5'10000). Merging pattern 9'---1-100- and 9'---1-000- from group (1 1 5'10000). Optimizing FSM `$fsm$\u_spi_engine.flash_payload_len$11195' from module `\spi_neuron_top'. Optimizing FSM `$fsm$\u_spi_engine.state$11178' from module `\spi_neuron_top'. Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$11127. Optimizing FSM `$fsm$\u_memory_if.state$11174' from module `\spi_neuron_top'. Optimizing FSM `$fsm$\u_neuron_memory.u_mem.state$11170' from module `\spi_neuron_top'. Optimizing FSM `$fsm$\u_int8_access.state$11166' from module `\spi_neuron_top'. Optimizing FSM `$fsm$\u_flash_slot_manager.u_fce.u_spi_flash_master.state$11156' from module `\spi_neuron_top'. Merging pattern 12'-----------0 and 12'-----------1 from group (7 0 12'000010000000). Merging pattern 12'-----------1 and 12'-----------0 from group (7 0 12'000010000000). Optimizing FSM `$fsm$\u_arbiter.owner$11149' from module `\spi_neuron_top'. Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$11121. Optimizing FSM `$fsm$\u_neuron_memory.state$11141' from module `\spi_neuron_top'. Optimizing FSM `$fsm$\u_layer_sequencer.state$11132' from module `\spi_neuron_top'. 20.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 205 unused cells and 205 unused wires. 20.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\u_graph_engine.state$11199' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [0]. Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [1]. Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [2]. Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [3]. Optimizing FSM `$fsm$\u_psram_ctrl.state$11214' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_psram_ctrl.$0\state[3:0] [0]. Removing unused output signal $flatten\u_psram_ctrl.$0\state[3:0] [1]. Removing unused output signal $flatten\u_psram_ctrl.$0\state[3:0] [2]. Removing unused output signal $flatten\u_psram_ctrl.$0\state[3:0] [3]. Optimizing FSM `$fsm$\u_layer_sequencer.state$11132' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [0]. Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [1]. Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [2]. Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [3]. Optimizing FSM `$fsm$\u_neuron_memory.state$11141' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [0]. Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [1]. Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [2]. Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [3]. Optimizing FSM `$fsm$\u_arbiter.owner$11149' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_arbiter.$0\owner[2:0] [0]. Removing unused output signal $flatten\u_arbiter.$0\owner[2:0] [1]. Removing unused output signal $flatten\u_arbiter.$0\owner[2:0] [2]. Optimizing FSM `$fsm$\u_flash_slot_manager.u_fce.u_spi_flash_master.state$11156' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$0\state[3:0] [0]. Removing unused output signal $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$0\state[3:0] [1]. Removing unused output signal $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$0\state[3:0] [2]. Removing unused output signal $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$0\state[3:0] [3]. Optimizing FSM `$fsm$\u_int8_access.state$11166' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_int8_access.$0\state[1:0] [0]. Removing unused output signal $flatten\u_int8_access.$0\state[1:0] [1]. Optimizing FSM `$fsm$\u_neuron_memory.u_mem.state$11170' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_neuron_memory.\u_mem.$0\state[1:0] [0]. Removing unused output signal $flatten\u_neuron_memory.\u_mem.$0\state[1:0] [1]. Optimizing FSM `$fsm$\u_memory_if.state$11174' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_memory_if.$0\state[1:0] [0]. Removing unused output signal $flatten\u_memory_if.$0\state[1:0] [1]. Optimizing FSM `$fsm$\u_spi_engine.state$11178' from module `\spi_neuron_top'. Removing unused output signal $flatten\u_spi_engine.$procmux$3521_CMP. Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [0]. Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [1]. Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [2]. Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [3]. Optimizing FSM `$fsm$\u_spi_engine.flash_payload_len$11195' from module `\spi_neuron_top'. Optimizing FSM `$fsm$\u_spi_engine.resp_len$11197' from module `\spi_neuron_top'. 20.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\u_graph_engine.state$11199' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ------------1 1000 -> -----------1- 0100 -> ----------1-- 1100 -> ---------1--- 0010 -> --------1---- 1010 -> -------1----- 0110 -> ------1------ 0001 -> -----1------- 1001 -> ----1-------- 0101 -> ---1--------- 0011 -> --1---------- 1011 -> -1----------- 0111 -> 1------------ Recoding FSM `$fsm$\u_psram_ctrl.state$11214' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> --------1 1000 -> -------1- 0100 -> ------1-- 0010 -> -----1--- 0110 -> ----1---- 0001 -> ---1----- 0101 -> --1------ 0011 -> -1------- 0111 -> 1-------- Recoding FSM `$fsm$\u_layer_sequencer.state$11132' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ------1 0100 -> -----1- 0010 -> ----1-- 0110 -> ---1--- 0001 -> --1---- 0101 -> -1----- 0011 -> 1------ Recoding FSM `$fsm$\u_neuron_memory.state$11141' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -----1 0100 -> ----1- 0010 -> ---1-- 0001 -> --1--- 0101 -> -1---- 0011 -> 1----- Recoding FSM `$fsm$\u_arbiter.owner$11149' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\u_flash_slot_manager.u_fce.u_spi_flash_master.state$11156' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -------1 0100 -> ------1- 0010 -> -----1-- 0110 -> ----1--- 0001 -> ---1---- 0101 -> --1----- 0011 -> -1------ 0111 -> 1------- Recoding FSM `$fsm$\u_int8_access.state$11166' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> -1 01 -> 1- Recoding FSM `$fsm$\u_neuron_memory.u_mem.state$11170' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> -1 01 -> 1- Recoding FSM `$fsm$\u_memory_if.state$11174' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> -1 01 -> 1- Recoding FSM `$fsm$\u_spi_engine.state$11178' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> --------------1 1000 -> -------------1- 0100 -> ------------1-- 1100 -> -----------1--- 0010 -> ----------1---- 1010 -> ---------1----- 0110 -> --------1------ 1110 -> -------1------- 0001 -> ------1-------- 1001 -> -----1--------- 0101 -> ----1---------- 1101 -> ---1----------- 0011 -> --1------------ 1011 -> -1------------- 0111 -> 1-------------- Recoding FSM `$fsm$\u_spi_engine.flash_payload_len$11195' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ------1 1000 -> -----1- 0100 -> ----1-- 0001 -> ---1--- 1001 -> --1---- 0011 -> -1----- 0111 -> 1------ Recoding FSM `$fsm$\u_spi_engine.resp_len$11197' from module `\spi_neuron_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00000 -> ---1 10000 -> --1- 00001 -> -1-- 01011 -> 1--- 20.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\u_graph_engine.state$11199' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_graph_engine.state$11199 (\u_graph_engine.state): Number of input signals: 13 Number of output signals: 13 Number of state bits: 13 Input signals: 0: \graph_run_start 1: \graph_rst 2: \u_graph_engine.u_neuron.done 3: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:552$670_Y 4: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:523$667_Y 5: $flatten\u_graph_engine.$logic_or$rtl/graph_engine.v:481$664_Y 6: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:474$659_Y 7: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:445$655_Y 8: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:414$650_Y 9: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:365$647_Y 10: $flatten\u_graph_engine.$eq$rtl/graph_engine.v:346$646_Y 11: \u_graph_engine.is_output_sink 12: \u_arbiter.c_ready Output signals: 0: $flatten\u_graph_engine.$procmux$8650_CMP [0] 1: $flatten\u_graph_engine.$procmux$8650_CMP [1] 2: $flatten\u_graph_engine.$procmux$8362_CMP 3: $flatten\u_graph_engine.$procmux$8351_CMP 4: $flatten\u_graph_engine.$procmux$8348_CMP 5: $flatten\u_graph_engine.$procmux$8338_CMP 6: $flatten\u_graph_engine.$procmux$8329_CMP 7: $flatten\u_graph_engine.$procmux$8328_CMP 8: $flatten\u_graph_engine.$procmux$8327_CMP 9: $flatten\u_graph_engine.$procmux$8323_CMP 10: $flatten\u_graph_engine.$procmux$8081_CMP 11: $flatten\u_graph_engine.$procmux$8002_CMP 12: $flatten\u_graph_engine.$procmux$7967_CMP State encoding: 0: 13'------------1 1: 13'-----------1- 2: 13'----------1-- 3: 13'---------1--- 4: 13'--------1---- 5: 13'-------1----- 6: 13'------1------ 7: 13'-----1------- 8: 13'----1-------- 9: 13'---1--------- 10: 13'--1---------- 11: 13'-1----------- 12: 13'1------------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'-----------00 -> 0 13'0000000000001 1: 0 13'-----------1- -> 0 13'0000000000001 2: 0 13'-----------01 -> 7 13'0000000000001 3: 1 13'-----------1- -> 0 13'0000000100000 4: 1 13'-----------0- -> 8 13'0000000100000 5: 2 13'-----------1- -> 0 13'0100000000000 6: 2 13'0----------0- -> 2 13'0100000000000 7: 2 13'1---1------0- -> 9 13'0100000000000 8: 2 13'1---0------0- -> 10 13'0100000000000 9: 3 13'-----------1- -> 0 13'0000000000010 10: 3 13'-----------00 -> 3 13'0000000000010 11: 3 13'-----------01 -> 7 13'0000000000010 12: 4 13'1-11-------0- -> 0 13'0000000001000 13: 4 13'-----------1- -> 0 13'0000000001000 14: 4 13'0----------0- -> 4 13'0000000001000 15: 4 13'1-0--------0- -> 7 13'0000000001000 16: 4 13'1-10-------0- -> 10 13'0000000001000 17: 5 13'-----------1- -> 0 13'0001000000000 18: 5 13'-----------0- -> 11 13'0001000000000 19: 6 13'-----------1- -> 0 13'1000000000000 20: 6 13'1-----11---0- -> 3 13'1000000000000 21: 6 13'0----------0- -> 6 13'1000000000000 22: 6 13'1-----0----0- -> 9 13'1000000000000 23: 6 13'1-----10---0- -> 12 13'1000000000000 24: 7 13'-----------1- -> 0 13'0000001000000 25: 7 13'-----------0- -> 4 13'0000001000000 26: 8 13'-0-------110- -> 0 13'0000000010000 27: 8 13'-----------1- -> 0 13'0000000010000 28: 8 13'-1--------10- -> 5 13'0000000010000 29: 8 13'----------00- -> 8 13'0000000010000 30: 8 13'-0-------010- -> 10 13'0000000010000 31: 9 13'-----------1- -> 0 13'0000100000000 32: 9 13'-----1-----0- -> 3 13'0000100000000 33: 9 13'-----0-----0- -> 6 13'0000100000000 34: 10 13'-----------1- -> 0 13'0000010000000 35: 10 13'-----------0- -> 2 13'0000010000000 36: 11 13'1--------1-0- -> 0 13'0000000000100 37: 11 13'-----------1- -> 0 13'0000000000100 38: 11 13'1--------0-0- -> 10 13'0000000000100 39: 11 13'0----------0- -> 11 13'0000000000100 40: 12 13'-----------1- -> 0 13'0010000000000 41: 12 13'--------1--0- -> 1 13'0010000000000 42: 12 13'--------0--0- -> 9 13'0010000000000 ------------------------------------- FSM `$fsm$\u_psram_ctrl.state$11214' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_psram_ctrl.state$11214 (\u_psram_ctrl.state): Number of input signals: 13 Number of output signals: 9 Number of state bits: 9 Input signals: 0: \rst 1: \u_memory_if.mem_wr 2: \u_memory_if.mem_req 3: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:765$287_Y 4: $flatten\u_psram_ctrl.$logic_or$rtl/psram_controller.v:604$283_Y 5: $flatten\u_psram_ctrl.$ge$rtl/psram_controller.v:605$282_Y 6: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:515$279_Y 7: $flatten\u_psram_ctrl.$logic_or$rtl/psram_controller.v:412$270_Y 8: $flatten\u_psram_ctrl.$lt$rtl/psram_controller.v:362$264_Y 9: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:340$263_Y 10: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:312$261_Y 11: \u_psram_ctrl.cr_init_active 12: \u_psram_ctrl.wr_reg Output signals: 0: $flatten\u_psram_ctrl.$procmux$10103_CMP 1: $flatten\u_psram_ctrl.$procmux$10078_CMP 2: $flatten\u_psram_ctrl.$procmux$10067_CMP 3: $flatten\u_psram_ctrl.$procmux$10066_CMP 4: $flatten\u_psram_ctrl.$procmux$10062_CMP 5: $flatten\u_psram_ctrl.$procmux$10024_CMP 6: $flatten\u_psram_ctrl.$procmux$10001_CMP 7: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$256_Y 8: $flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:283$255_Y State encoding: 0: 9'--------1 1: 9'-------1- 2: 9'------1-- 3: 9'-----1--- 4: 9'----1---- 5: 9'---1----- 6: 9'--1------ 7: 9'-1------- 8: 9'1-------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'--0---------0 -> 0 9'100000000 1: 0 13'------------1 -> 0 9'100000000 2: 0 13'--1---------0 -> 6 9'100000000 3: 1 13'------------1 -> 0 9'000000001 4: 1 13'0-----------0 -> 3 9'000000001 5: 1 13'1-----------0 -> 7 9'000000001 6: 2 13'------------1 -> 0 9'000010000 7: 2 13'-0----------0 -> 5 9'000010000 8: 2 13'-1----------0 -> 6 9'000010000 9: 3 13'------------1 -> 0 9'000000010 10: 3 13'------0-----0 -> 3 9'000000010 11: 3 13'-0----1-----0 -> 4 9'000000010 12: 3 13'-1----1-----0 -> 6 9'000000010 13: 4 13'------------1 -> 0 9'000100000 14: 4 13'--------0-1-0 -> 3 9'000100000 15: 4 13'-------0--0-0 -> 4 9'000100000 16: 4 13'-------1--0-0 -> 5 9'000100000 17: 4 13'--------1-1-0 -> 8 9'000100000 18: 5 13'------------1 -> 0 9'001000000 19: 5 13'-----1-----00 -> 3 9'001000000 20: 5 13'-----0------0 -> 5 9'001000000 21: 5 13'-----1-----10 -> 7 9'001000000 22: 6 13'------------1 -> 0 9'010000000 23: 6 13'---01-------0 -> 3 9'010000000 24: 6 13'---1--------0 -> 5 9'010000000 25: 6 13'---00-------0 -> 7 9'010000000 26: 7 13'------------1 -> 0 9'000001000 27: 7 13'---------1--0 -> 2 9'000001000 28: 7 13'---------0--0 -> 7 9'000001000 29: 8 13'------------1 -> 0 9'000000100 30: 8 13'------------0 -> 1 9'000000100 ------------------------------------- FSM `$fsm$\u_layer_sequencer.state$11132' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_layer_sequencer.state$11132 (\u_layer_sequencer.state): Number of input signals: 8 Number of output signals: 7 Number of state bits: 7 Input signals: 0: \rst 1: \seq_run_start 2: $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:323$758_Y 3: $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:321$756_Y 4: $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:255$745_Y 5: $flatten\u_layer_sequencer.$eq$rtl/layer_sequencer.v:201$743_Y 6: \u_neuron_memory.done 7: \u_arbiter.c_ready Output signals: 0: $flatten\u_layer_sequencer.$procmux$7626_CMP 1: $flatten\u_layer_sequencer.$procmux$7606_CMP 2: $flatten\u_layer_sequencer.$procmux$7603_CMP 3: $flatten\u_layer_sequencer.$procmux$7592_CMP 4: $flatten\u_layer_sequencer.$procmux$7583_CMP 5: $flatten\u_layer_sequencer.$procmux$7582_CMP 6: $flatten\u_layer_sequencer.$procmux$7459_CMP State encoding: 0: 7'------1 1: 7'-----1- 2: 7'----1-- 3: 7'---1--- 4: 7'--1---- 5: 7'-1----- 6: 7'1------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 8'------00 -> 0 7'0000001 1: 0 8'--1---10 -> 0 7'0000001 2: 0 8'-------1 -> 0 7'0000001 3: 0 8'--0---10 -> 4 7'0000001 4: 1 8'-------1 -> 0 7'0000010 5: 1 8'-0-----0 -> 1 7'0000010 6: 1 8'-1-----0 -> 5 7'0000010 7: 2 8'-------1 -> 0 7'1000000 8: 2 8'0------0 -> 2 7'1000000 9: 2 8'1--0---0 -> 4 7'1000000 10: 2 8'1--1---0 -> 6 7'1000000 11: 3 8'1---11-0 -> 0 7'0000100 12: 3 8'-------1 -> 0 7'0000100 13: 3 8'0------0 -> 3 7'0000100 14: 3 8'1---10-0 -> 4 7'0000100 15: 3 8'1---0--0 -> 5 7'0000100 16: 4 8'-------1 -> 0 7'0010000 17: 4 8'-------0 -> 2 7'0010000 18: 5 8'-------1 -> 0 7'0100000 19: 5 8'-------0 -> 3 7'0100000 20: 6 8'-------1 -> 0 7'0001000 21: 6 8'-------0 -> 1 7'0001000 ------------------------------------- FSM `$fsm$\u_neuron_memory.state$11141' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_neuron_memory.state$11141 (\u_neuron_memory.state): Number of input signals: 7 Number of output signals: 6 Number of state bits: 6 Input signals: 0: \graph_rst 1: \mux_nm_start 2: \u_neuron_memory.u_neuron.done 3: \u_neuron_memory.u_mem.ready 4: $flatten\u_neuron_memory.$eq$rtl/neuron_memory.v:502$358_Y 5: $flatten\u_neuron_memory.$eq$rtl/neuron_memory.v:397$340_Y 6: $flatten\u_neuron_memory.$logic_or$rtl/neuron_memory.v:377$339_Y Output signals: 0: $flatten\u_neuron_memory.$procmux$9223_CMP 1: $flatten\u_neuron_memory.$procmux$9119_CMP 2: $flatten\u_neuron_memory.$procmux$9088_CMP 3: $flatten\u_neuron_memory.$procmux$8952_CMP 4: $flatten\u_neuron_memory.$procmux$8915_CMP 5: $flatten\u_neuron_memory.$procmux$8885_CMP State encoding: 0: 6'-----1 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 7'-----00 -> 0 6'000010 1: 0 7'------1 -> 0 6'000010 2: 0 7'-----10 -> 3 6'000010 3: 1 7'------1 -> 0 6'000100 4: 1 7'------0 -> 4 6'000100 5: 2 7'------1 -> 0 6'010000 6: 2 7'---0--0 -> 2 6'010000 7: 2 7'0--1--0 -> 2 6'010000 8: 2 7'1--1--0 -> 5 6'010000 9: 3 7'11-1--0 -> 0 6'001000 10: 3 7'------1 -> 0 6'001000 11: 3 7'10-1--0 -> 2 6'001000 12: 3 7'---0--0 -> 3 6'001000 13: 3 7'0--1--0 -> 3 6'001000 14: 4 7'--1-1-0 -> 0 6'100000 15: 4 7'------1 -> 0 6'100000 16: 4 7'--0-1-0 -> 2 6'100000 17: 4 7'----0-0 -> 4 6'100000 18: 5 7'------1 -> 0 6'000001 19: 5 7'---1--0 -> 1 6'000001 20: 5 7'---0--0 -> 5 6'000001 ------------------------------------- FSM `$fsm$\u_arbiter.owner$11149' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_arbiter.owner$11149 (\u_arbiter.owner): Number of input signals: 6 Number of output signals: 5 Number of state bits: 5 Input signals: 0: \rst 1: \flash_d_req 2: \portc_req 3: \u_spi_engine.ram_req 4: \u_neuron_memory.u_mem.mem_req 5: \u_int8_access.ready Output signals: 0: $flatten\u_arbiter.$procmux$9420_CMP 1: $flatten\u_arbiter.$procmux$9399_CMP 2: $flatten\u_arbiter.$procmux$9388_CMP 3: $flatten\u_arbiter.$procmux$9378_CMP 4: $flatten\u_arbiter.$procmux$9369_CMP State encoding: 0: 5'----1 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 6'-00000 -> 0 5'00001 1: 0 6'-----1 -> 0 5'00001 2: 0 6'-00010 -> 1 5'00001 3: 0 6'-1---0 -> 2 5'00001 4: 0 6'-010-0 -> 3 5'00001 5: 0 6'-0-1-0 -> 4 5'00001 6: 1 6'1----0 -> 0 5'10000 7: 1 6'-----1 -> 0 5'10000 8: 1 6'0----0 -> 1 5'10000 9: 2 6'1----0 -> 0 5'00100 10: 2 6'-----1 -> 0 5'00100 11: 2 6'0----0 -> 2 5'00100 12: 3 6'1----0 -> 0 5'00010 13: 3 6'-----1 -> 0 5'00010 14: 3 6'0----0 -> 3 5'00010 15: 4 6'1----0 -> 0 5'01000 16: 4 6'-----1 -> 0 5'01000 17: 4 6'0----0 -> 4 5'01000 ------------------------------------- FSM `$fsm$\u_flash_slot_manager.u_fce.u_spi_flash_master.state$11156' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_flash_slot_manager.u_fce.u_spi_flash_master.state$11156 (\u_flash_slot_manager.u_fce.u_spi_flash_master.state): Number of input signals: 12 Number of output signals: 8 Number of state bits: 8 Input signals: 0: \rst 1: \u_flash_slot_manager.u_fce.fm_start 2: \u_flash_slot_manager.u_fce.fm_wdata_valid 3: \u_flash_slot_manager.u_fce.fm_rdata_ack 4: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:341$1560_Y 5: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:315$1553_Y 6: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:305$1549_Y 7: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:302$1548_Y 8: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:272$1546_Y 9: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$logic_or$rtl/spi_flash_master.v:269$1545_Y 10: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:265$1542_Y 11: \u_flash_slot_manager.u_fce.u_spi_flash_master.sclk_will_rise Output signals: 0: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1852_CMP 1: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1844_CMP 2: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1757_CMP 3: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1744_CMP 4: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1696_CMP 5: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1681_CMP 6: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1649_CMP 7: $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1632_CMP State encoding: 0: 8'-------1 1: 8'------1- 2: 8'-----1-- 3: 8'----1--- 4: 8'---1---- 5: 8'--1----- 6: 8'-1------ 7: 8'1------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 12'----------00 -> 0 8'00010000 1: 0 12'-----------1 -> 0 8'00010000 2: 0 12'----------10 -> 4 8'00010000 3: 1 12'-----------1 -> 0 8'01000000 4: 1 12'1----0-----0 -> 1 8'01000000 5: 1 12'0----------0 -> 1 8'01000000 6: 1 12'1---011----0 -> 3 8'01000000 7: 1 12'1---11-----0 -> 5 8'01000000 8: 1 12'1---010----0 -> 6 8'01000000 9: 2 12'-----------1 -> 0 8'00100000 10: 2 12'1100-------0 -> 1 8'00100000 11: 2 12'10---------0 -> 2 8'00100000 12: 2 12'0----------0 -> 2 8'00100000 13: 2 12'111--------0 -> 3 8'00100000 14: 2 12'1101-------0 -> 6 8'00100000 15: 3 12'-----------1 -> 0 8'00000001 16: 3 12'-----------0 -> 7 8'00000001 17: 4 12'-----------1 -> 0 8'00000010 18: 4 12'-----------0 -> 2 8'00000010 19: 5 12'-----------1 -> 0 8'00000100 20: 5 12'-------01--0 -> 1 8'00000100 21: 5 12'-------11--0 -> 3 8'00000100 22: 5 12'--------0--0 -> 5 8'00000100 23: 6 12'-----------1 -> 0 8'00001000 24: 6 12'---------1-0 -> 1 8'00001000 25: 6 12'---------0-0 -> 6 8'00001000 26: 7 12'------------ -> 0 8'10000000 ------------------------------------- FSM `$fsm$\u_int8_access.state$11166' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_int8_access.state$11166 (\u_int8_access.state): Number of input signals: 3 Number of output signals: 2 Number of state bits: 2 Input signals: 0: \rst 1: \u_arbiter.m_req 2: \u_memory_if.ready Output signals: 0: $flatten\u_int8_access.$procmux$9567_CMP 1: $flatten\u_int8_access.$procmux$9559_CMP State encoding: 0: 2'-1 1: 2'1- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'-00 -> 0 2'10 1: 0 3'--1 -> 0 2'10 2: 0 3'-10 -> 1 2'10 3: 1 3'1-0 -> 0 2'01 4: 1 3'--1 -> 0 2'01 5: 1 3'0-0 -> 1 2'01 ------------------------------------- FSM `$fsm$\u_neuron_memory.u_mem.state$11170' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_neuron_memory.u_mem.state$11170 (\u_neuron_memory.u_mem.state): Number of input signals: 3 Number of output signals: 2 Number of state bits: 2 Input signals: 0: \graph_rst 1: \u_neuron_memory.access_req 2: \u_arbiter.b_ready Output signals: 0: $flatten\u_neuron_memory.\u_mem.$procmux$9559_CMP 1: $flatten\u_neuron_memory.\u_mem.$procmux$9567_CMP State encoding: 0: 2'-1 1: 2'1- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'-00 -> 0 2'01 1: 0 3'--1 -> 0 2'01 2: 0 3'-10 -> 1 2'01 3: 1 3'1-0 -> 0 2'10 4: 1 3'--1 -> 0 2'10 5: 1 3'0-0 -> 1 2'10 ------------------------------------- FSM `$fsm$\u_memory_if.state$11174' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_memory_if.state$11174 (\u_memory_if.state): Number of input signals: 3 Number of output signals: 2 Number of state bits: 2 Input signals: 0: \rst 1: \u_int8_access.mem_req 2: \u_psram_ctrl.mem_ready Output signals: 0: $flatten\u_memory_if.$procmux$9669_CMP 1: $flatten\u_memory_if.$procmux$9661_CMP State encoding: 0: 2'-1 1: 2'1- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'-00 -> 0 2'10 1: 0 3'--1 -> 0 2'10 2: 0 3'-10 -> 1 2'10 3: 1 3'1-0 -> 0 2'01 4: 1 3'--1 -> 0 2'01 5: 1 3'0-0 -> 1 2'01 ------------------------------------- FSM `$fsm$\u_spi_engine.state$11178' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_spi_engine.state$11178 (\u_spi_engine.state): Number of input signals: 19 Number of output signals: 14 Number of state bits: 15 Input signals: 0: $auto$opt_reduce.cc:137:opt_pmux$11111 1: $auto$opt_reduce.cc:137:opt_pmux$11109 2: \rst 3: \u_spi_slave.cs_end 4: \u_spi_slave.rx_valid 5: $flatten\u_spi_engine.$procmux$3597_CMP 6: $flatten\u_spi_engine.$procmux$3596_CMP 7: $flatten\u_spi_engine.$procmux$3595_CMP 8: $flatten\u_spi_engine.$procmux$3356_CTRL 9: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1118$1356_Y 10: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y 11: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1014$1345_Y 12: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:873$1335_Y 13: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:821$1331_Y 14: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:817$1330_Y 15: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:812$1329_Y 16: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:765$1327_Y 17: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:761$1326_Y 18: \u_arbiter.a_ready Output signals: 0: $flatten\u_spi_engine.$procmux$3536_CMP 1: $flatten\u_spi_engine.$procmux$3512_CMP 2: $flatten\u_spi_engine.$procmux$3261_CMP 3: $flatten\u_spi_engine.$procmux$3258_CMP 4: $flatten\u_spi_engine.$procmux$3239_CMP 5: $flatten\u_spi_engine.$procmux$3095_CMP 6: $flatten\u_spi_engine.$procmux$3024_CMP 7: $flatten\u_spi_engine.$procmux$2988_CMP 8: $flatten\u_spi_engine.$procmux$2987_CMP 9: $flatten\u_spi_engine.$procmux$2928_CMP 10: $flatten\u_spi_engine.$procmux$2889_CMP 11: $flatten\u_spi_engine.$procmux$2855_CMP 12: $flatten\u_spi_engine.$procmux$2846_CMP 13: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:364$1309_Y State encoding: 0: 15'--------------1 1: 15'-------------1- 2: 15'------------1-- 3: 15'-----------1--- 4: 15'----------1---- 5: 15'---------1----- 6: 15'--------1------ 7: 15'-------1------- 8: 15'------1-------- 9: 15'-----1--------- 10: 15'----1---------- 11: 15'---1----------- 12: 15'--1------------ 13: 15'-1------------- 14: 15'1-------------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 19'--------------000-- -> 0 14'00001000000000 1: 0 19'---------------10-- -> 0 14'00001000000000 2: 0 19'----------------1-- -> 0 14'00001000000000 3: 0 19'------------1-100-- -> 3 14'00001000000000 4: 0 19'----------1---100-- -> 4 14'00001000000000 5: 0 19'--------------1001- -> 5 14'00001000000000 6: 0 19'--------------100-1 -> 7 14'00001000000000 7: 0 19'-------------1100-- -> 8 14'00001000000000 8: 0 19'-----------1--100-- -> 11 14'00001000000000 9: 0 19'----------000010000 -> 13 14'00001000000000 10: 1 19'---------------10-- -> 0 14'00000000010000 11: 1 19'----------------1-- -> 0 14'00000000010000 12: 1 19'0--------------00-- -> 1 14'00000000010000 13: 1 19'1--------------00-- -> 9 14'00000000010000 14: 2 19'---------------10-- -> 0 14'00000000000010 15: 2 19'----------------1-- -> 0 14'00000000000010 16: 2 19'--------------000-- -> 2 14'00000000000010 17: 2 19'--------------100-- -> 10 14'00000000000010 18: 3 19'---------------10-- -> 0 14'00000000100000 19: 3 19'----------------1-- -> 0 14'00000000100000 20: 3 19'--------------000-- -> 3 14'00000000100000 21: 3 19'--------------100-- -> 13 14'00000000100000 22: 4 19'---------------10-- -> 0 14'00100000000000 23: 4 19'----------------1-- -> 0 14'00100000000000 24: 4 19'--------------000-- -> 4 14'00100000000000 25: 4 19'-0------------100-- -> 4 14'00100000000000 26: 4 19'-10-----------100-- -> 12 14'00100000000000 27: 4 19'-11-----------100-- -> 13 14'00100000000000 28: 5 19'---------------10-- -> 0 14'10000000000000 29: 5 19'----------------1-- -> 0 14'10000000000000 30: 5 19'--------------000-- -> 5 14'10000000000000 31: 5 19'---------0----100-- -> 5 14'10000000000000 32: 5 19'---------1----100-- -> 13 14'10000000000000 33: 6 19'---------------10-- -> 0 14'00000000000100 34: 6 19'----------------1-- -> 0 14'00000000000100 35: 6 19'1-----0--------00-- -> 2 14'00000000000100 36: 6 19'0--------------00-- -> 6 14'00000000000100 37: 6 19'1-----1--------00-- -> 13 14'00000000000100 38: 7 19'---------------10-- -> 0 14'00000001000000 39: 7 19'----------------1-- -> 0 14'00000001000000 40: 7 19'-------11-----100-- -> 5 14'00000001000000 41: 7 19'--------------000-- -> 7 14'00000001000000 42: 7 19'-------0------100-- -> 7 14'00000001000000 43: 7 19'-------10-----100-- -> 13 14'00000001000000 44: 8 19'---------------10-- -> 0 14'00010000000000 45: 8 19'----------------1-- -> 0 14'00010000000000 46: 8 19'--------------100-- -> 4 14'00010000000000 47: 8 19'--------------000-- -> 8 14'00010000000000 48: 9 19'---------------10-- -> 0 14'00000000001000 49: 9 19'----------------1-- -> 0 14'00000000001000 50: 9 19'--------------000-- -> 9 14'00000000001000 51: 9 19'------1-------100-- -> 13 14'00000000001000 52: 9 19'------0-------100-- -> 14 14'00000000001000 53: 10 19'---------------10-- -> 0 14'00000010000000 54: 10 19'----------------1-- -> 0 14'00000010000000 55: 10 19'---------------00-- -> 6 14'00000010000000 56: 11 19'---------------10-- -> 0 14'00000000000001 57: 11 19'----------------1-- -> 0 14'00000000000001 58: 11 19'--------------000-- -> 11 14'00000000000001 59: 11 19'--------------100-- -> 13 14'00000000000001 60: 12 19'---------------10-- -> 0 14'01000000000000 61: 12 19'----------------1-- -> 0 14'01000000000000 62: 12 19'---101--------100-- -> 2 14'01000000000000 63: 12 19'--------------000-- -> 12 14'01000000000000 64: 12 19'---0----------100-- -> 12 14'01000000000000 65: 12 19'---11---------100-- -> 13 14'01000000000000 66: 12 19'---100--------100-- -> 14 14'01000000000000 67: 13 19'---------------10-- -> 0 14'00000000000000 68: 13 19'----------------1-- -> 0 14'00000000000000 69: 13 19'---------------00-- -> 13 14'00000000000000 70: 14 19'---------------10-- -> 0 14'00000100000000 71: 14 19'----------------1-- -> 0 14'00000100000000 72: 14 19'---------------00-- -> 1 14'00000100000000 ------------------------------------- FSM `$fsm$\u_spi_engine.flash_payload_len$11195' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_spi_engine.flash_payload_len$11195 (\u_spi_engine.flash_payload_len): Number of input signals: 10 Number of output signals: 4 Number of state bits: 7 Input signals: 0: \rst 1: \u_spi_slave.cs_end 2: \u_spi_slave.rx_valid 3: $flatten\u_spi_engine.$procmux$3422_CTRL 4: $flatten\u_spi_engine.$procmux$3421_CMP 5: $flatten\u_spi_engine.$procmux$3420_CMP 6: $flatten\u_spi_engine.$procmux$3419_CMP 7: $flatten\u_spi_engine.$procmux$3418_CMP 8: $flatten\u_spi_engine.$procmux$3417_CMP 9: $flatten\u_spi_engine.$procmux$2928_CMP Output signals: 0: $flatten\u_spi_engine.$0\flash_payload_len[3:0] [0] 1: $flatten\u_spi_engine.$0\flash_payload_len[3:0] [1] 2: $flatten\u_spi_engine.$0\flash_payload_len[3:0] [2] 3: $flatten\u_spi_engine.$0\flash_payload_len[3:0] [3] State encoding: 0: 7'------1 1: 7'-----1- 2: 7'----1-- 3: 7'---1--- 4: 7'--1---- 5: 7'-1----- 6: 7'1------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 10'1------000 -> 0 4'0000 1: 0 10'1000000100 -> 0 4'0000 2: 0 10'0-------00 -> 0 4'0000 3: 0 10'--------10 -> 0 4'0000 4: 0 10'---------1 -> 0 4'0000 5: 0 10'1---1--100 -> 1 4'1000 6: 0 10'1--1---100 -> 2 4'0100 7: 0 10'11-----100 -> 3 4'0001 8: 0 10'1-----1100 -> 4 4'1001 9: 0 10'1----1-100 -> 5 4'0011 10: 0 10'1-1----100 -> 6 4'0111 11: 1 10'---------1 -> 0 4'0000 12: 1 10'1------000 -> 1 4'1000 13: 1 10'1000000100 -> 1 4'1000 14: 1 10'1---1--100 -> 1 4'1000 15: 1 10'0-------00 -> 1 4'1000 16: 1 10'--------10 -> 1 4'1000 17: 1 10'1--1---100 -> 2 4'0100 18: 1 10'11-----100 -> 3 4'0001 19: 1 10'1-----1100 -> 4 4'1001 20: 1 10'1----1-100 -> 5 4'0011 21: 1 10'1-1----100 -> 6 4'0111 22: 2 10'---------1 -> 0 4'0000 23: 2 10'1---1--100 -> 1 4'1000 24: 2 10'1------000 -> 2 4'0100 25: 2 10'1000000100 -> 2 4'0100 26: 2 10'1--1---100 -> 2 4'0100 27: 2 10'0-------00 -> 2 4'0100 28: 2 10'--------10 -> 2 4'0100 29: 2 10'11-----100 -> 3 4'0001 30: 2 10'1-----1100 -> 4 4'1001 31: 2 10'1----1-100 -> 5 4'0011 32: 2 10'1-1----100 -> 6 4'0111 33: 3 10'---------1 -> 0 4'0000 34: 3 10'1---1--100 -> 1 4'1000 35: 3 10'1--1---100 -> 2 4'0100 36: 3 10'1------000 -> 3 4'0001 37: 3 10'1000000100 -> 3 4'0001 38: 3 10'11-----100 -> 3 4'0001 39: 3 10'0-------00 -> 3 4'0001 40: 3 10'--------10 -> 3 4'0001 41: 3 10'1-----1100 -> 4 4'1001 42: 3 10'1----1-100 -> 5 4'0011 43: 3 10'1-1----100 -> 6 4'0111 44: 4 10'---------1 -> 0 4'0000 45: 4 10'1---1--100 -> 1 4'1000 46: 4 10'1--1---100 -> 2 4'0100 47: 4 10'11-----100 -> 3 4'0001 48: 4 10'1------000 -> 4 4'1001 49: 4 10'1000000100 -> 4 4'1001 50: 4 10'1-----1100 -> 4 4'1001 51: 4 10'0-------00 -> 4 4'1001 52: 4 10'--------10 -> 4 4'1001 53: 4 10'1----1-100 -> 5 4'0011 54: 4 10'1-1----100 -> 6 4'0111 55: 5 10'---------1 -> 0 4'0000 56: 5 10'1---1--100 -> 1 4'1000 57: 5 10'1--1---100 -> 2 4'0100 58: 5 10'11-----100 -> 3 4'0001 59: 5 10'1-----1100 -> 4 4'1001 60: 5 10'1------000 -> 5 4'0011 61: 5 10'1000000100 -> 5 4'0011 62: 5 10'1----1-100 -> 5 4'0011 63: 5 10'0-------00 -> 5 4'0011 64: 5 10'--------10 -> 5 4'0011 65: 5 10'1-1----100 -> 6 4'0111 66: 6 10'---------1 -> 0 4'0000 67: 6 10'1---1--100 -> 1 4'1000 68: 6 10'1--1---100 -> 2 4'0100 69: 6 10'11-----100 -> 3 4'0001 70: 6 10'1-----1100 -> 4 4'1001 71: 6 10'1----1-100 -> 5 4'0011 72: 6 10'1------000 -> 6 4'0111 73: 6 10'1000000100 -> 6 4'0111 74: 6 10'1-1----100 -> 6 4'0111 75: 6 10'0-------00 -> 6 4'0111 76: 6 10'--------10 -> 6 4'0111 ------------------------------------- FSM `$fsm$\u_spi_engine.resp_len$11197' from module `spi_neuron_top': ------------------------------------- Information on FSM $fsm$\u_spi_engine.resp_len$11197 (\u_spi_engine.resp_len): Number of input signals: 9 Number of output signals: 5 Number of state bits: 4 Input signals: 0: $auto$opt_reduce.cc:137:opt_pmux$11107 1: \rst 2: \u_spi_slave.cs_end 3: \u_spi_slave.rx_valid 4: $flatten\u_spi_engine.$procmux$3179_CMP 5: $flatten\u_spi_engine.$procmux$3024_CMP 6: $flatten\u_spi_engine.$procmux$2928_CMP 7: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y 8: $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1014$1345_Y Output signals: 0: $flatten\u_spi_engine.$0\resp_len[4:0] [0] 1: $flatten\u_spi_engine.$0\resp_len[4:0] [1] 2: $flatten\u_spi_engine.$0\resp_len[4:0] [2] 3: $flatten\u_spi_engine.$0\resp_len[4:0] [3] 4: $flatten\u_spi_engine.$0\resp_len[4:0] [4] State encoding: 0: 4'---1 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 9'--1-01000 -> 0 5'00000 1: 0 9'---1-000- -> 0 5'00000 2: 0 9'--1--000- -> 0 5'00000 3: 0 9'10-1-100- -> 0 5'00000 4: 0 9'0--1-100- -> 0 5'00000 5: 0 9'--00--00- -> 0 5'00000 6: 0 9'------10- -> 0 5'00000 7: 0 9'-------1- -> 0 5'00000 8: 0 9'11-1-100- -> 1 5'10000 9: 0 9'--1--1001 -> 2 5'00001 10: 0 9'--1-1100- -> 3 5'01011 11: 1 9'-------1- -> 0 5'00000 12: 1 9'--1-01000 -> 1 5'10000 13: 1 9'--1--000- -> 1 5'10000 14: 1 9'--00--00- -> 1 5'10000 15: 1 9'---1--00- -> 1 5'10000 16: 1 9'------10- -> 1 5'10000 17: 1 9'--1--1001 -> 2 5'00001 18: 1 9'--1-1100- -> 3 5'01011 19: 2 9'-------1- -> 0 5'00000 20: 2 9'11-1-100- -> 1 5'10000 21: 2 9'--1-01000 -> 2 5'00001 22: 2 9'--1--1001 -> 2 5'00001 23: 2 9'---1-000- -> 2 5'00001 24: 2 9'--1--000- -> 2 5'00001 25: 2 9'10-1-100- -> 2 5'00001 26: 2 9'0--1-100- -> 2 5'00001 27: 2 9'--00--00- -> 2 5'00001 28: 2 9'------10- -> 2 5'00001 29: 2 9'--1-1100- -> 3 5'01011 30: 3 9'-------1- -> 0 5'00000 31: 3 9'11-1-100- -> 1 5'10000 32: 3 9'--1--1001 -> 2 5'00001 33: 3 9'--1-01000 -> 3 5'01011 34: 3 9'---1-000- -> 3 5'01011 35: 3 9'--1--000- -> 3 5'01011 36: 3 9'--1-1100- -> 3 5'01011 37: 3 9'10-1-100- -> 3 5'01011 38: 3 9'0--1-100- -> 3 5'01011 39: 3 9'--00--00- -> 3 5'01011 40: 3 9'------10- -> 3 5'01011 ------------------------------------- 20.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\u_graph_engine.state$11199' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_psram_ctrl.state$11214' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_layer_sequencer.state$11132' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_neuron_memory.state$11141' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_arbiter.owner$11149' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_flash_slot_manager.u_fce.u_spi_flash_master.state$11156' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_int8_access.state$11166' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_neuron_memory.u_mem.state$11170' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_memory_if.state$11174' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_spi_engine.state$11178' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_spi_engine.flash_payload_len$11195' from module `\spi_neuron_top'. Mapping FSM `$fsm$\u_spi_engine.resp_len$11197' from module `\spi_neuron_top'. 20.15. Executing OPT pass (performing simple optimizations). 20.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 3191 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3035 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3016 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3013 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 178 cells. 20.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 3013 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.15.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\u_int8_access.$procdff$10792 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9575_Y, Q = \u_int8_access.addr_reg, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12516 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_addr, Q = \u_int8_access.addr_reg). Adding SRST signal on $flatten\u_memory_if.$procdff$10798 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$9666_Y, Q = \u_memory_if.ready, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$10426 ($dff) from module spi_neuron_top (D = { \u_spi_slave.cs_n_sync [1:0] \cs_n }, Q = \u_spi_slave.cs_n_sync, rval = 3'111). Adding SRST signal on $flatten\u_spi_slave.$procdff$10425 ($dff) from module spi_neuron_top (D = { \u_spi_slave.mosi_sync [1:0] \mosi }, Q = \u_spi_slave.mosi_sync, rval = 3'000). Adding SRST signal on $flatten\u_spi_slave.$procdff$10424 ($dff) from module spi_neuron_top (D = { \u_spi_slave.sclk_sync [1:0] \sclk }, Q = \u_spi_slave.sclk_sync, rval = 3'000). Adding SRST signal on $flatten\u_spi_slave.$procdff$10423 ($dff) from module spi_neuron_top (D = \u_spi_slave.cs_n_sync [2], Q = \u_spi_slave.cs_n_prev, rval = 1'1). Adding SRST signal on $flatten\u_spi_slave.$procdff$10422 ($dff) from module spi_neuron_top (D = \u_spi_slave.sclk_sync [2], Q = \u_spi_slave.sclk_prev, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$10421 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2744_Y, Q = \u_spi_slave.tx_shift, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12530 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2744_Y, Q = \u_spi_slave.tx_shift). Adding SRST signal on $flatten\u_spi_slave.$procdff$10420 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2758_Y, Q = \u_spi_slave.rx_shift, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12542 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_shift). Adding SRST signal on $flatten\u_spi_slave.$procdff$10419 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2772_Y, Q = \u_spi_slave.bit_count, rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$12552 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2765_Y, Q = \u_spi_slave.bit_count). Adding SRST signal on $flatten\u_spi_slave.$procdff$10417 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2680_Y, Q = \u_spi_slave.cs_end, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$10415 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2715_Y, Q = \u_spi_slave.rx_valid, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$10414 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2792_Y, Q = \u_spi_slave.rx_byte, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12570 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_byte). Adding SRST signal on $flatten\u_spi_slave.$procdff$10413 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2811_Y, Q = \u_spi_slave.miso, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$12580 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2811_Y, Q = \u_spi_slave.miso). Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$10407 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$2674_Y, Q = \u_graph_engine.u_neuron.y, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12592 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$2669_Y, Q = \u_graph_engine.u_neuron.y). Adding SRST signal on $flatten\u_spi_engine.$procdff$10476 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4412_Y, Q = \u_spi_engine.flash_err_sticky, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$12598 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4412_Y, Q = \u_spi_engine.flash_err_sticky). Adding SRST signal on $flatten\u_spi_engine.$procdff$10475 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4423_Y, Q = \u_spi_engine.status_done_sticky, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$12604 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4423_Y, Q = \u_spi_engine.status_done_sticky). Adding SRST signal on $flatten\u_spi_engine.$procdff$10474 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3075_Y, Q = \u_spi_engine.status_snapshot, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12610 ($sdff) from module spi_neuron_top (D = { 3'000 \u_spi_engine.flash_busy \u_spi_engine.flash_err_sticky \u_graph_engine.err \u_spi_engine.status_done_sticky \u_spi_engine.busy_all }, Q = \u_spi_engine.status_snapshot). Adding SRST signal on $flatten\u_spi_engine.$procdff$10473 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3114_Y, Q = \u_spi_engine.graph_mode, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$10472 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3153_Y, Q = \u_spi_engine.net_mode, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$10470 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3224_Y, Q = \u_spi_engine.resp_index, rval = 5'00000). Adding EN signal on $auto$ff.cc:337:slice$12618 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3198_Y, Q = \u_spi_engine.resp_index). Adding SRST signal on $flatten\u_spi_engine.$procdff$10469 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3241_Y, Q = \u_spi_engine.cur_read_byte, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12640 ($sdff) from module spi_neuron_top (D = \u_arbiter.a_rdata, Q = \u_spi_engine.cur_read_byte). Adding SRST signal on $flatten\u_spi_engine.$procdff$10467 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3272_Y, Q = \u_spi_engine.cur_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12646 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3257_Y, Q = \u_spi_engine.cur_addr). Adding SRST signal on $flatten\u_spi_engine.$procdff$10466 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3297_Y, Q = \u_spi_engine.len_remaining, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12664 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3285_Y, Q = \u_spi_engine.len_remaining). Adding SRST signal on $flatten\u_spi_engine.$procdff$10465 ($dff) from module spi_neuron_top (D = { $flatten\u_spi_engine.$procmux$2857_Y $flatten\u_spi_engine.$procmux$2891_Y }, Q = \u_spi_engine.len_acc, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12680 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2876_Y, Q = \u_spi_engine.len_acc [7:0]). Adding EN signal on $auto$ff.cc:337:slice$12680 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2845_Y, Q = \u_spi_engine.len_acc [15:8]). Adding SRST signal on $flatten\u_spi_engine.$procdff$10464 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3361_Y, Q = \u_spi_engine.addr_acc, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12711 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3334_Y, Q = \u_spi_engine.addr_acc). Adding SRST signal on $flatten\u_spi_engine.$procdff$10463 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3395_Y, Q = \u_spi_engine.byte_pos, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$12727 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3383_Y, Q = \u_spi_engine.byte_pos). Adding SRST signal on $flatten\u_spi_engine.$procdff$10461 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3455_Y, Q = \u_spi_engine.flash_byte_pos, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$12741 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3441_Y, Q = \u_spi_engine.flash_byte_pos). Adding SRST signal on $flatten\u_spi_engine.$procdff$10460 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3468_Y, Q = \u_spi_engine.flash_payload, rval = 72'000000000000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12757 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.flash_payload [63:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.flash_payload). Adding SRST signal on $flatten\u_spi_engine.$procdff$10459 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3493_Y, Q = \u_spi_engine.opcode, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12763 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.opcode). Adding SRST signal on $flatten\u_spi_engine.$procdff$10458 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3514_Y, Q = \u_spi_engine.pending_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12769 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.pending_wdata). Adding SRST signal on $flatten\u_spi_engine.$procdff$10456 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3621_Y, Q = \u_spi_engine.ram_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12775 ($sdff) from module spi_neuron_top (D = \u_spi_engine.pending_wdata, Q = \u_spi_engine.ram_wdata). Adding SRST signal on $flatten\u_spi_engine.$procdff$10455 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3638_Y, Q = \u_spi_engine.ram_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12781 ($sdff) from module spi_neuron_top (D = \u_spi_engine.cur_addr, Q = \u_spi_engine.ram_addr). Adding SRST signal on $flatten\u_spi_engine.$procdff$10454 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3655_Y, Q = \u_spi_engine.ram_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$12787 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3651_Y, Q = \u_spi_engine.ram_wr). Adding SRST signal on $flatten\u_spi_engine.$procdff$10453 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2986_Y, Q = \u_spi_engine.ram_req, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$10452 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3673_Y, Q = \u_spi_engine.flash_cat_read_sel, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$12798 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte [3:0], Q = \u_spi_engine.flash_cat_read_sel). Adding SRST signal on $flatten\u_spi_engine.$procdff$10451 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3703_Y, Q = \u_spi_engine.flash_raw_flash_addr, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12804 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3688_Y, Q = \u_spi_engine.flash_raw_flash_addr). Adding SRST signal on $flatten\u_spi_engine.$procdff$10450 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3730_Y, Q = \u_spi_engine.flash_ext_length, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12818 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.flash_payload [15:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.flash_ext_length). Adding SRST signal on $flatten\u_spi_engine.$procdff$10449 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3760_Y, Q = \u_spi_engine.flash_ext_psram_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12826 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3742_Y, Q = \u_spi_engine.flash_ext_psram_addr). Adding SRST signal on $flatten\u_spi_engine.$procdff$10448 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3783_Y, Q = \u_spi_engine.flash_new_type, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12840 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.flash_new_type). Adding SRST signal on $flatten\u_spi_engine.$procdff$10447 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3806_Y, Q = \u_spi_engine.flash_new_length, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12848 ($sdff) from module spi_neuron_top (D = \u_spi_engine.flash_payload [23:0], Q = \u_spi_engine.flash_new_length). Adding SRST signal on $flatten\u_spi_engine.$procdff$10446 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3829_Y, Q = \u_spi_engine.flash_new_offset, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12856 ($sdff) from module spi_neuron_top (D = \u_spi_engine.flash_payload [47:24], Q = \u_spi_engine.flash_new_offset). Adding SRST signal on $flatten\u_spi_engine.$procdff$10445 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3856_Y, Q = \u_spi_engine.flash_slot_id, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$12864 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3841_Y, Q = \u_spi_engine.flash_slot_id). Adding SRST signal on $flatten\u_spi_engine.$procdff$10444 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3904_Y, Q = \u_spi_engine.flash_op_code, rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$12878 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3889_Y, Q = \u_spi_engine.flash_op_code). Adding SRST signal on $flatten\u_spi_engine.$procdff$10443 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3023_Y, Q = \u_spi_engine.flash_op_start, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$10442 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3935_Y, Q = \u_spi_engine.n_out, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12913 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_out). Adding SRST signal on $flatten\u_spi_engine.$procdff$10441 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3967_Y, Q = \u_spi_engine.num_neurons_graph, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12919 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.num_neurons_graph). Adding SRST signal on $flatten\u_spi_engine.$procdff$10440 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4000_Y, Q = \u_spi_engine.net_type, rval = 8'00000001). Adding EN signal on $auto$ff.cc:337:slice$12925 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3980_Y, Q = \u_spi_engine.net_type). Adding SRST signal on $flatten\u_spi_engine.$procdff$10439 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4017_Y, Q = \u_spi_engine.run_num_layers, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$12941 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.run_num_layers). Adding SRST signal on $flatten\u_spi_engine.$procdff$10438 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2964_Y, Q = \u_spi_engine.run_start, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$10437 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4053_Y, Q = \u_spi_engine.buf_b_base, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12956 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.buf_b_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$10436 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4090_Y, Q = \u_spi_engine.buf_a_base, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12962 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.buf_a_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$10435 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4128_Y, Q = \u_spi_engine.table_base, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$12968 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.table_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$10434 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2923_Y, Q = \u_spi_engine.nm_soft_rst, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$10433 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2964_Y, Q = \u_spi_engine.nm_start, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$10432 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4161_Y, Q = \u_spi_engine.n_neurons_real, rval = 16'0000000000000001). Adding EN signal on $auto$ff.cc:337:slice$12990 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_neurons_real). Adding SRST signal on $flatten\u_spi_engine.$procdff$10431 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4195_Y, Q = \u_spi_engine.n_inputs_real, rval = 16'0000000000100000). Adding EN signal on $auto$ff.cc:337:slice$12996 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_inputs_real). Adding SRST signal on $flatten\u_spi_engine.$procdff$10430 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4230_Y, Q = \u_spi_engine.activation, rval = 2'01). Adding EN signal on $auto$ff.cc:337:slice$13002 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte [1:0], Q = \u_spi_engine.activation). Adding SRST signal on $flatten\u_spi_engine.$procdff$10429 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4269_Y, Q = \u_spi_engine.bias_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13008 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.bias_addr). Adding SRST signal on $flatten\u_spi_engine.$procdff$10428 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4309_Y, Q = \u_spi_engine.w_base, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13014 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.w_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$10427 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4350_Y, Q = \u_spi_engine.x_base, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13020 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.x_base). Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$10408 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$2662_Y, Q = \u_graph_engine.u_neuron.busy, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13026 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$2662_Y, Q = \u_graph_engine.u_neuron.busy). Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$10409 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$2609_Y, Q = \u_graph_engine.u_neuron.done, rval = 1'0). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10817 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9939_Y, Q = \u_psram_ctrl.ub_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$13033 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9939_Y, Q = \u_psram_ctrl.ub_reg). Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$10410 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$2650_Y, Q = \u_graph_engine.u_neuron.group_index, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$13045 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$add$rtl/neuron_parallel.v:265$1400_Y, Q = \u_graph_engine.u_neuron.group_index). Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$10411 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$2636_Y, Q = \u_graph_engine.u_neuron.acc, rval = 0). Adding EN signal on $auto$ff.cc:337:slice$13055 ($sdff) from module spi_neuron_top (D = \u_graph_engine.u_neuron.acc_next, Q = \u_graph_engine.u_neuron.acc). Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$10412 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$2626_Y, Q = \u_graph_engine.u_neuron.finishing, rval = 1'0). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10818 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9908_Y, Q = \u_psram_ctrl.page_hit_reg, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13064 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9908_Y, Q = \u_psram_ctrl.page_hit_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10819 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9880_Y, Q = \u_psram_ctrl.hold_cycles, rval = 9'000000000). Adding EN signal on $auto$ff.cc:337:slice$13082 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9880_Y, Q = \u_psram_ctrl.hold_cycles). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10820 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9863_Y, Q = \u_psram_ctrl.cr_init_active, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13098 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9863_Y, Q = \u_psram_ctrl.cr_init_active). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10821 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9843_Y, Q = \u_psram_ctrl.cr_step, rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$13102 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9843_Y, Q = \u_psram_ctrl.cr_step). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10822 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9837_Y, Q = \u_psram_ctrl.req_pending, rval = 1'0). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10823 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9821_Y, Q = \u_psram_ctrl.pending_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13113 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_addr, Q = \u_psram_ctrl.pending_addr). Adding SRST signal on $flatten\u_memory_if.$procdff$10800 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$9688_Y, Q = \u_memory_if.mem_ub_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$13115 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_ub_n, Q = \u_memory_if.mem_ub_n). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10824 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9816_Y, Q = \u_psram_ctrl.pending_wdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13119 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_wdata, Q = \u_psram_ctrl.pending_wdata). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10825 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9811_Y, Q = \u_psram_ctrl.pending_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13121 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_wr, Q = \u_psram_ctrl.pending_wr). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10826 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9806_Y, Q = \u_psram_ctrl.pending_lb_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$13123 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_lb_n, Q = \u_psram_ctrl.pending_lb_n). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10827 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9801_Y, Q = \u_psram_ctrl.pending_ub_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$13125 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_ub_n, Q = \u_psram_ctrl.pending_ub_n). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10828 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9783_Y, Q = \u_psram_ctrl.dq_out, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13127 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9783_Y, Q = \u_psram_ctrl.dq_out). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10625 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7731_Y, Q = \u_layer_sequencer.seq_done, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10377 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2005_Y, Q = \u_flash_slot_manager.u_fce.done, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10378 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2570_Y, Q = \u_flash_slot_manager.u_fce.err, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13145 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2014_Y, Q = \u_flash_slot_manager.u_fce.err). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10379 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2531_Y, Q = \u_flash_slot_manager.u_fce.d_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13149 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2531_Y, Q = \u_flash_slot_manager.u_fce.d_wr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10380 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2514_Y, Q = \u_flash_slot_manager.u_fce.d_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13159 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2514_Y, Q = \u_flash_slot_manager.u_fce.d_addr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10381 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2501_Y, Q = \u_flash_slot_manager.u_fce.d_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13169 ($sdff) from module spi_neuron_top (D = \u_flash_slot_manager.u_fce.u_spi_flash_master.rdata, Q = \u_flash_slot_manager.u_fce.d_wdata). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10382 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2424_Y, Q = \u_flash_slot_manager.u_fce.state, rval = 5'00000). Adding EN signal on $auto$ff.cc:337:slice$13173 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2424_Y, Q = \u_flash_slot_manager.u_fce.state). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10383 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$1982_Y, Q = \u_flash_slot_manager.u_fce.fm_start, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10384 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2399_Y, Q = \u_flash_slot_manager.u_fce.fm_opcode, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13198 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2399_Y, Q = \u_flash_slot_manager.u_fce.fm_opcode). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10385 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2386_Y, Q = \u_flash_slot_manager.u_fce.fm_has_addr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13202 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2386_Y, Q = \u_flash_slot_manager.u_fce.fm_has_addr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10386 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2376_Y, Q = \u_flash_slot_manager.u_fce.fm_addr, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13206 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2376_Y, Q = \u_flash_slot_manager.u_fce.fm_addr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10387 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2360_Y, Q = \u_flash_slot_manager.u_fce.fm_dir, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$13210 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2360_Y, Q = \u_flash_slot_manager.u_fce.fm_dir). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10388 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2347_Y, Q = \u_flash_slot_manager.u_fce.fm_n_data, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13214 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2347_Y, Q = \u_flash_slot_manager.u_fce.fm_n_data). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10389 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2339_Y, Q = \u_flash_slot_manager.u_fce.fm_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13218 ($sdff) from module spi_neuron_top (D = \u_arbiter.d_rdata, Q = \u_flash_slot_manager.u_fce.fm_wdata). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10390 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$1960_Y, Q = \u_flash_slot_manager.u_fce.fm_wdata_valid, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10391 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$1971_Y, Q = \u_flash_slot_manager.u_fce.fm_rdata_ack, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10392 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2316_Y, Q = \u_flash_slot_manager.u_fce.remaining, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13228 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2316_Y, Q = \u_flash_slot_manager.u_fce.remaining). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10393 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2283_Y, Q = \u_flash_slot_manager.u_fce.cur_flash_addr, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13244 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2283_Y, Q = \u_flash_slot_manager.u_fce.cur_flash_addr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10394 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2250_Y, Q = \u_flash_slot_manager.u_fce.cur_psram_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13260 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2250_Y, Q = \u_flash_slot_manager.u_fce.cur_psram_addr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10395 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2211_Y, Q = \u_flash_slot_manager.u_fce.save_phase, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13276 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2211_Y, Q = \u_flash_slot_manager.u_fce.save_phase). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10396 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2196_Y, Q = \u_flash_slot_manager.u_fce.save_end, rval = 25'0000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13296 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2192_Y, Q = \u_flash_slot_manager.u_fce.save_end). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10397 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2145_Y, Q = \u_flash_slot_manager.u_fce.erase_addr, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13306 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2145_Y, Q = \u_flash_slot_manager.u_fce.erase_addr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10398 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2119_Y, Q = \u_flash_slot_manager.u_fce.prog_addr, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13326 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2119_Y, Q = \u_flash_slot_manager.u_fce.prog_addr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10399 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2096_Y, Q = \u_flash_slot_manager.u_fce.prog_psram_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13342 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2096_Y, Q = \u_flash_slot_manager.u_fce.prog_psram_addr). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10400 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2073_Y, Q = \u_flash_slot_manager.u_fce.prog_remaining, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13358 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2073_Y, Q = \u_flash_slot_manager.u_fce.prog_remaining). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10401 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2062_Y, Q = \u_flash_slot_manager.u_fce.wip_busy, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13374 ($sdff) from module spi_neuron_top (D = \u_flash_slot_manager.u_fce.u_spi_flash_master.rdata [0], Q = \u_flash_slot_manager.u_fce.wip_busy). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.$procdff$10402 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2053_Y, Q = \u_flash_slot_manager.u_fce.erase_only, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13378 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2049_Y, Q = \u_flash_slot_manager.u_fce.erase_only). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10376 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1951_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.sclk_reg, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13388 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$not$rtl/spi_flash_master.v:158$1527_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.sclk_reg). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10375 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:160$1528_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.div_cnt, rval = 16'0000000000000000). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10374 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1695_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.cur_dir, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$13393 ($sdff) from module spi_neuron_top (D = \u_flash_slot_manager.u_fce.fm_dir, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.cur_dir). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10373 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1710_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.data_total, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13397 ($sdff) from module spi_neuron_top (D = \u_flash_slot_manager.u_fce.fm_n_data, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.data_total). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10372 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1724_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.data_idx, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13401 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1724_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.data_idx). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10371 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1740_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.byte_shift, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13413 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1740_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.byte_shift). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10370 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1756_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.bit_idx, rval = 6'000000). Adding EN signal on $auto$ff.cc:337:slice$13425 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1756_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.bit_idx). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10369 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1789_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.hdr_len, rval = 6'000000). Adding EN signal on $auto$ff.cc:337:slice$13445 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:227$1537_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.hdr_len). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10368 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1804_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.hdr_shift, rval = 0). Adding EN signal on $auto$ff.cc:337:slice$13449 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:226$1536_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.hdr_shift). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10367 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1817_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.shifting, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13453 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1817_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.shifting). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10366 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1642_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.rdata_valid, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10365 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1668_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.wdata_req, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10363 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1905_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13485 ($sdff) from module spi_neuron_top (D = { \u_flash_slot_manager.u_fce.u_spi_flash_master.byte_shift [6:0] \flash_miso }, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.rdata). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10362 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1631_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.done, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10361 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1912_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.cs_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$13490 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1912_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.cs_n). Adding SRST signal on $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procdff$10360 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1928_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.mosi, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13498 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1928_Y, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.mosi). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10622 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7443_Y, Q = \u_flash_slot_manager.crc_acc, rval = 32'11111111111111111111111111111111). Adding EN signal on $auto$ff.cc:337:slice$13516 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7443_Y, Q = \u_flash_slot_manager.crc_acc). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$10407 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2674_Y, Q = \u_neuron_memory.u_neuron.y, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13520 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2669_Y, Q = \u_neuron_memory.u_neuron.y). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$10408 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2662_Y, Q = \u_neuron_memory.u_neuron.busy, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13526 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2662_Y, Q = \u_neuron_memory.u_neuron.busy). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$10409 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2609_Y, Q = \u_neuron_memory.u_neuron.done, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$10410 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2650_Y, Q = \u_neuron_memory.u_neuron.group_index, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$13533 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$add$rtl/neuron_parallel.v:265$1400_Y, Q = \u_neuron_memory.u_neuron.group_index). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$10411 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2636_Y, Q = \u_neuron_memory.u_neuron.acc, rval = 0). Adding EN signal on $auto$ff.cc:337:slice$13543 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_neuron.acc_next, Q = \u_neuron_memory.u_neuron.acc). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$10412 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2626_Y, Q = \u_neuron_memory.u_neuron.finishing, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10495 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7038_Y, Q = \u_flash_slot_manager.active_slot, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$13552 ($sdff) from module spi_neuron_top (D = \u_spi_engine.flash_slot_id, Q = \u_flash_slot_manager.active_slot). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10494 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7056_Y, Q = \u_flash_slot_manager.active_op, rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$13556 ($sdff) from module spi_neuron_top (D = \u_spi_engine.flash_op_code, Q = \u_flash_slot_manager.active_op). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10493 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7071_Y, Q = \u_flash_slot_manager.entry_shift, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13560 ($sdff) from module spi_neuron_top (D = { \u_flash_slot_manager.entry_shift [119:0] \u_arbiter.d_rdata }, Q = \u_flash_slot_manager.entry_shift). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10492 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7088_Y, Q = \u_flash_slot_manager.cur_slot, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$13564 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7088_Y, Q = \u_flash_slot_manager.cur_slot). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10491 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7123_Y, Q = \u_flash_slot_manager.byte_idx, rval = 9'000000000). Adding EN signal on $auto$ff.cc:337:slice$13584 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7123_Y, Q = \u_flash_slot_manager.byte_idx). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10490 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7162_Y, Q = \u_flash_slot_manager.crc_active, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13606 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7162_Y, Q = \u_flash_slot_manager.crc_active). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10489 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7201_Y, Q = \u_flash_slot_manager.fsm_d_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13620 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7188_Y, Q = \u_flash_slot_manager.fsm_d_wdata). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10488 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7212_Y, Q = \u_flash_slot_manager.fsm_d_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13622 ($sdff) from module spi_neuron_top (D = { 14'00000000000000 \u_flash_slot_manager.byte_idx }, Q = \u_flash_slot_manager.fsm_d_addr). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10487 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7224_Y, Q = \u_flash_slot_manager.fsm_d_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13624 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7224_Y, Q = \u_flash_slot_manager.fsm_d_wr). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10486 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$6829_Y, Q = \u_flash_slot_manager.fsm_d_req, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10485 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7240_Y, Q = \u_flash_slot_manager.fce_len, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13629 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7240_Y, Q = \u_flash_slot_manager.fce_len). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10484 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7270_Y, Q = \u_flash_slot_manager.fce_psram_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13645 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7270_Y, Q = \u_flash_slot_manager.fce_psram_addr). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10483 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7300_Y, Q = \u_flash_slot_manager.fce_flash_addr, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13661 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7300_Y, Q = \u_flash_slot_manager.fce_flash_addr). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10482 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7330_Y, Q = \u_flash_slot_manager.fce_dir, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$13677 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7330_Y, Q = \u_flash_slot_manager.fce_dir). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10481 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$6845_Y, Q = \u_flash_slot_manager.fce_start, rval = 1'0). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10479 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7352_Y, Q = \u_flash_slot_manager.state, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$13694 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7352_Y, Q = \u_flash_slot_manager.state). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10478 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7419_Y, Q = \u_flash_slot_manager.err, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13714 ($sdff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$7419_Y, Q = \u_flash_slot_manager.err). Adding SRST signal on $flatten\u_flash_slot_manager.$procdff$10477 ($dff) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.$procmux$6866_Y, Q = \u_flash_slot_manager.done, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$10783 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$9556_Y, Q = \u_neuron_memory.u_mem.mem_req, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$10784 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$9651_Y, Q = \u_neuron_memory.u_mem.mem_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13734 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_wr, Q = \u_neuron_memory.u_mem.mem_wr). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$10787 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$9621_Y, Q = \u_neuron_memory.u_mem.rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13738 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$9617_Y, Q = \u_neuron_memory.u_mem.rdata). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$10788 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$9564_Y, Q = \u_neuron_memory.u_mem.ready, rval = 1'0). Adding SRST signal on $flatten\u_memory_if.$procdff$10793 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$9658_Y, Q = \u_memory_if.mem_req, rval = 1'0). Adding SRST signal on $flatten\u_memory_if.$procdff$10794 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$9734_Y, Q = \u_memory_if.mem_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13752 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_wr, Q = \u_memory_if.mem_wr). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10758 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9087_Y, Q = \u_neuron_memory.neuron_start, rval = 1'0). Adding EN signal on $flatten\u_neuron_memory.$procdff$10757 ($dff) from module spi_neuron_top (D = 8'00000000, Q = \u_neuron_memory.access_wdata). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10756 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9160_Y, Q = \u_neuron_memory.access_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13758 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9160_Y, Q = \u_neuron_memory.access_addr). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10755 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9192_Y, Q = \u_neuron_memory.access_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13776 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9192_Y, Q = \u_neuron_memory.access_wr). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10754 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9099_Y, Q = \u_neuron_memory.access_req, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10753 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9222_Y, Q = \u_neuron_memory.bias_reg, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13799 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.bias_reg). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10752 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9234_Y, Q = \u_neuron_memory.bias_group_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13803 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9234_Y, Q = \u_neuron_memory.bias_group_addr). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10751 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9249_Y, Q = \u_neuron_memory.w_group_base, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13815 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9249_Y, Q = \u_neuron_memory.w_group_base). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10750 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9264_Y, Q = \u_neuron_memory.neuron_index, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13827 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9264_Y, Q = \u_neuron_memory.neuron_index). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10749 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9279_Y, Q = \u_neuron_memory.index, rval = 6'000000). Adding EN signal on $auto$ff.cc:337:slice$13839 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9279_Y, Q = \u_neuron_memory.index). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10747 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9064_Y, Q = \u_neuron_memory.done, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.$procdff$10746 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9344_Y, Q = \u_neuron_memory.busy, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13858 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$9344_Y, Q = \u_neuron_memory.busy). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10829 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9755_Y, Q = \u_psram_ctrl.dq_oe, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13874 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9755_Y, Q = \u_psram_ctrl.dq_oe). Adding SRST signal on $flatten\u_graph_engine.$procdff$10674 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8415_Y, Q = \u_graph_engine.n_conn_padded_reg, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13878 ($sdff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$add$rtl/graph_engine.v:419$651_Y [15:3] 3'000 }, Q = \u_graph_engine.n_conn_padded_reg). Adding SRST signal on $flatten\u_graph_engine.$procdff$10673 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8433_Y, Q = \u_graph_engine.activation_reg, rval = 2'01). Adding EN signal on $auto$ff.cc:337:slice$13882 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata [1:0], Q = \u_graph_engine.activation_reg). Adding SRST signal on $flatten\u_graph_engine.$procdff$10672 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8443_Y, Q = \u_graph_engine.act_wr_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13886 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8443_Y, Q = \u_graph_engine.act_wr_data). Adding SRST signal on $flatten\u_graph_engine.$procdff$10671 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8456_Y, Q = \u_graph_engine.act_wr_addr, rval = 12'000000000000). Adding EN signal on $auto$ff.cc:337:slice$13896 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8456_Y, Q = \u_graph_engine.act_wr_addr). Adding SRST signal on $flatten\u_graph_engine.$procdff$10670 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8347_Y, Q = \u_graph_engine.act_wr_en, rval = 1'0). Adding SRST signal on $flatten\u_graph_engine.$procdff$10669 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8474_Y, Q = \u_graph_engine.weight_acc, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$13907 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.weight_acc). Adding SRST signal on $flatten\u_graph_engine.$procdff$10668 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$7966_Y $flatten\u_graph_engine.$procmux$7982_Y }, Q = \u_graph_engine.src_id_acc, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13911 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.src_id_acc [7:0]). Adding EN signal on $auto$ff.cc:337:slice$13911 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.src_id_acc [15:8]). Adding SRST signal on $flatten\u_graph_engine.$procdff$10667 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8510_Y, Q = \u_graph_engine.edge_byte_idx, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$13918 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8510_Y, Q = \u_graph_engine.edge_byte_idx). Adding SRST signal on $flatten\u_graph_engine.$procdff$10666 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8529_Y, Q = \u_graph_engine.conn_i, rval = 6'000000). Adding EN signal on $auto$ff.cc:337:slice$13930 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8529_Y, Q = \u_graph_engine.conn_i). Adding SRST signal on $flatten\u_graph_engine.$procdff$10665 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$8494_Y $flatten\u_graph_engine.$procmux$8001_Y }, Q = \u_graph_engine.out_id_acc, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13940 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.out_id_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$13940 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.out_id_acc [7:0]). Adding SRST signal on $flatten\u_graph_engine.$procdff$10664 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$8557_Y $flatten\u_graph_engine.$procmux$8022_Y }, Q = \u_graph_engine.n_conn_acc, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13947 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.n_conn_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$13947 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.n_conn_acc [7:0]). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10624 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7943_Y, Q = \u_layer_sequencer.seq_busy, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$13954 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7943_Y, Q = \u_layer_sequencer.seq_busy). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10623 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7591_Y, Q = \u_layer_sequencer.nm_start, rval = 1'0). Adding SRST signal on $flatten\u_int8_access.$procdff$10790 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9592_Y, Q = \u_int8_access.mem_ub_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$13971 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9592_Y, Q = \u_int8_access.mem_ub_n). Adding SRST signal on $flatten\u_int8_access.$procdff$10789 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9604_Y, Q = \u_int8_access.mem_lb_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$13979 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9604_Y, Q = \u_int8_access.mem_lb_n). Adding SRST signal on $flatten\u_graph_engine.$procdff$10663 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$8070_Y $flatten\u_graph_engine.$procmux$8581_Y $flatten\u_graph_engine.$procmux$8045_Y }, Q = \u_graph_engine.conn_ptr_acc, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$13987 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$13987 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [23:16]). Adding EN signal on $auto$ff.cc:337:slice$13987 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [7:0]). Adding SRST signal on $flatten\u_graph_engine.$procdff$10662 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8602_Y, Q = \u_graph_engine.desc_byte_idx, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$13997 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8602_Y, Q = \u_graph_engine.desc_byte_idx). Adding SRST signal on $flatten\u_int8_access.$procdff$10788 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9564_Y, Q = \u_int8_access.ready, rval = 1'0). Adding SRST signal on $flatten\u_graph_engine.$procdff$10661 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8637_Y, Q = \u_graph_engine.desc_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14024 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8637_Y, Q = \u_graph_engine.desc_addr). Adding SRST signal on $flatten\u_graph_engine.$procdff$10660 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8660_Y, Q = \u_graph_engine.neuron_idx, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14038 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8660_Y, Q = \u_graph_engine.neuron_idx). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10626 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7581_Y, Q = \u_layer_sequencer.ram_req, rval = 1'0). Adding SRST signal on $flatten\u_graph_engine.$procdff$10659 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8692_Y, Q = \u_graph_engine.in_idx, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14053 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8692_Y, Q = \u_graph_engine.in_idx). Adding SRST signal on $flatten\u_graph_engine.$procdff$10658 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8337_Y, Q = \u_graph_engine.neuron_start, rval = 1'0). Adding SRST signal on $flatten\u_int8_access.$procdff$10787 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9621_Y, Q = \u_int8_access.rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14066 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9617_Y, Q = \u_int8_access.rdata). Adding SRST signal on $flatten\u_graph_engine.$procdff$10657 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8712_Y, Q = \u_graph_engine.bias_reg, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14070 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.bias_reg). Adding SRST signal on $flatten\u_graph_engine.$procdff$10655 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8790_Y, Q = \u_graph_engine.err, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14074 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8790_Y, Q = \u_graph_engine.err). Adding SRST signal on $flatten\u_int8_access.$procdff$10786 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9633_Y, Q = \u_int8_access.mem_wdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14090 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9629_Y, Q = \u_int8_access.mem_wdata). Adding SRST signal on $flatten\u_graph_engine.$procdff$10654 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8361_Y, Q = \u_graph_engine.done, rval = 1'0). Adding SRST signal on $flatten\u_graph_engine.$procdff$10653 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8808_Y, Q = \u_graph_engine.busy, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14095 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8808_Y, Q = \u_graph_engine.busy). Adding SRST signal on $flatten\u_graph_engine.$procdff$10652 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8849_Y, Q = \u_graph_engine.ram_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14123 ($sdff) from module spi_neuron_top (D = \u_graph_engine.u_neuron.y, Q = \u_graph_engine.ram_wdata). Adding SRST signal on $flatten\u_graph_engine.$procdff$10651 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8856_Y, Q = \u_graph_engine.ram_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14125 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8856_Y, Q = \u_graph_engine.ram_addr). Adding SRST signal on $flatten\u_graph_engine.$procdff$10650 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8869_Y, Q = \u_graph_engine.ram_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14133 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8869_Y, Q = \u_graph_engine.ram_wr). Adding SRST signal on $flatten\u_graph_engine.$procdff$10649 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8322_Y, Q = \u_graph_engine.ram_req, rval = 1'0). Adding SRST signal on $flatten\u_int8_access.$procdff$10785 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9642_Y, Q = \u_int8_access.mem_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14142 ($sdff) from module spi_neuron_top (D = { 1'0 \u_arbiter.m_addr [22:1] }, Q = \u_int8_access.mem_addr). Adding SRST signal on $flatten\u_int8_access.$procdff$10784 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9651_Y, Q = \u_int8_access.mem_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14146 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_wr, Q = \u_int8_access.mem_wr). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10802 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10341_Y, Q = \u_psram_ctrl.psram_a, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14150 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10341_Y, Q = \u_psram_ctrl.psram_a). Adding SRST signal on $flatten\u_int8_access.$procdff$10783 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$9556_Y, Q = \u_int8_access.mem_req, rval = 1'0). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10803 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10306_Y, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$14169 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10306_Y, Q = \u_psram_ctrl.psram_ce_n). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10804 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10269_Y, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$14173 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10269_Y, Q = \u_psram_ctrl.psram_oe_n). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10805 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10241_Y, Q = \u_psram_ctrl.psram_we_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$14177 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10241_Y, Q = \u_psram_ctrl.psram_we_n). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$10792 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$9575_Y, Q = \u_neuron_memory.u_mem.addr_reg, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14181 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_addr, Q = \u_neuron_memory.u_mem.addr_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10806 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10206_Y, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$14185 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10206_Y, Q = \u_psram_ctrl.psram_lb_n). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10807 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10174_Y, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$14189 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10174_Y, Q = \u_psram_ctrl.psram_ub_n). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10808 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10165_Y, Q = \u_psram_ctrl.psram_zz_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$14193 ($sdff) from module spi_neuron_top (D = 1'1, Q = \u_psram_ctrl.psram_zz_n). Adding SRST signal on $flatten\u_arbiter.$procdff$10781 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9469_Y, Q = \u_arbiter.m_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14199 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9467_Y, Q = \u_arbiter.m_wdata). Adding SRST signal on $flatten\u_arbiter.$procdff$10780 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9490_Y, Q = \u_arbiter.m_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14205 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9488_Y, Q = \u_arbiter.m_addr). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10809 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10151_Y, Q = \u_psram_ctrl.mem_rdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14211 ($sdff) from module spi_neuron_top (D = \psram_dq, Q = \u_psram_ctrl.mem_rdata). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10810 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9742_Y, Q = \u_psram_ctrl.mem_ready, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$10779 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9511_Y, Q = \u_arbiter.m_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14216 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9509_Y, Q = \u_arbiter.m_wr). Adding SRST signal on $flatten\u_arbiter.$procdff$10778 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9417_Y, Q = \u_arbiter.m_req, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$10777 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9366_Y, Q = \u_arbiter.c_ready, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$10776 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9520_Y, Q = \u_arbiter.c_rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14232 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.c_rdata). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10812 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10061_Y, Q = \u_psram_ctrl.counter, rval = 14'00000000000000). Adding EN signal on $auto$ff.cc:337:slice$14236 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10061_Y, Q = \u_psram_ctrl.counter). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10813 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10048_Y, Q = \u_psram_ctrl.address_reg, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14250 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10048_Y, Q = \u_psram_ctrl.address_reg). Adding SRST signal on $flatten\u_arbiter.$procdff$10775 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9366_Y, Q = \u_arbiter.b_ready, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$10774 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9530_Y, Q = \u_arbiter.b_rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14267 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.b_rdata). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10814 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10023_Y, Q = \u_psram_ctrl.wdata_reg, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14271 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$10023_Y, Q = \u_psram_ctrl.wdata_reg). Adding SRST signal on $flatten\u_arbiter.$procdff$10773 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9366_Y, Q = \u_arbiter.a_ready, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$10772 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9541_Y, Q = \u_arbiter.a_rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14292 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.a_rdata). Adding SRST signal on $flatten\u_arbiter.$procdff$10771 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9366_Y, Q = \u_arbiter.d_ready, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$10770 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$9549_Y, Q = \u_arbiter.d_rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14301 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.d_rdata). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10815 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9997_Y, Q = \u_psram_ctrl.wr_reg, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14305 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9997_Y, Q = \u_psram_ctrl.wr_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$10816 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9963_Y, Q = \u_psram_ctrl.lb_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$14319 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$9963_Y, Q = \u_psram_ctrl.lb_reg). Adding SRST signal on $flatten\u_memory_if.$procdff$10796 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$9716_Y, Q = \u_memory_if.mem_wdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14331 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_wdata, Q = \u_memory_if.mem_wdata). Adding SRST signal on $flatten\u_memory_if.$procdff$10795 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$9725_Y, Q = \u_memory_if.mem_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14335 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_addr, Q = \u_memory_if.mem_addr). Adding SRST signal on $flatten\u_memory_if.$procdff$10797 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$9707_Y, Q = \u_memory_if.rdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14339 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_rdata, Q = \u_memory_if.rdata). Adding SRST signal on $flatten\u_memory_if.$procdff$10799 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$9697_Y, Q = \u_memory_if.mem_lb_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$14345 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_lb_n, Q = \u_memory_if.mem_lb_n). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10648 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7602_Y, Q = \u_layer_sequencer.copy_idx, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14349 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7602_Y, Q = \u_layer_sequencer.copy_idx). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10647 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7619_Y, Q = \u_layer_sequencer.write_sel, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14361 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7619_Y, Q = \u_layer_sequencer.write_sel). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10646 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7639_Y, Q = \u_layer_sequencer.cur_sel, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14377 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.write_sel, Q = \u_layer_sequencer.cur_sel). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10645 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$7458_Y $flatten\u_layer_sequencer.$procmux$7472_Y }, Q = \u_layer_sequencer.n_neurons_acc, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14383 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_neurons_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$14383 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_neurons_acc [7:0]). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10644 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$7656_Y $flatten\u_layer_sequencer.$procmux$7488_Y }, Q = \u_layer_sequencer.n_inputs_acc, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14390 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_inputs_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$14390 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_inputs_acc [7:0]). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10643 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7694_Y, Q = \u_layer_sequencer.activation_acc, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14397 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.activation_acc). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10642 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$7528_Y $flatten\u_layer_sequencer.$procmux$7676_Y $flatten\u_layer_sequencer.$procmux$7507_Y }, Q = \u_layer_sequencer.bias_addr_acc, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14401 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$14401 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [23:16]). Adding EN signal on $auto$ff.cc:337:slice$14401 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [7:0]). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10641 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$7574_Y $flatten\u_layer_sequencer.$procmux$7717_Y $flatten\u_layer_sequencer.$procmux$7550_Y }, Q = \u_layer_sequencer.w_base_acc, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14411 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$14411 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [23:16]). Adding EN signal on $auto$ff.cc:337:slice$14411 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [7:0]). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10640 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7751_Y, Q = \u_layer_sequencer.desc_table_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14421 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7751_Y, Q = \u_layer_sequencer.desc_table_addr). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10639 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7774_Y, Q = \u_layer_sequencer.num_layers_reg, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14437 ($sdff) from module spi_neuron_top (D = \u_spi_engine.run_num_layers, Q = \u_layer_sequencer.num_layers_reg). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10638 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7788_Y, Q = \u_layer_sequencer.layer_idx, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14443 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7788_Y, Q = \u_layer_sequencer.layer_idx). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10637 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7808_Y, Q = \u_layer_sequencer.desc_byte_idx, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$14459 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7808_Y, Q = \u_layer_sequencer.desc_byte_idx). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10635 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7861_Y, Q = \u_layer_sequencer.nm_n_neurons, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14477 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.n_neurons_acc, Q = \u_layer_sequencer.nm_n_neurons). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10634 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7870_Y, Q = \u_layer_sequencer.nm_n_inputs, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14479 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.n_inputs_acc, Q = \u_layer_sequencer.nm_n_inputs). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10633 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7879_Y, Q = \u_layer_sequencer.nm_activation, rval = 2'01). Adding EN signal on $auto$ff.cc:337:slice$14481 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.activation_acc [1:0], Q = \u_layer_sequencer.nm_activation). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10632 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7888_Y, Q = \u_layer_sequencer.nm_bias_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14483 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.bias_addr_acc [22:0], Q = \u_layer_sequencer.nm_bias_addr). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10631 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7897_Y, Q = \u_layer_sequencer.nm_w_base, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14485 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.w_base_acc [22:0], Q = \u_layer_sequencer.nm_w_base). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10630 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7906_Y, Q = \u_layer_sequencer.nm_x_base, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14487 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$ternary$rtl/layer_sequencer.v:279$749_Y, Q = \u_layer_sequencer.nm_x_base). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10629 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7913_Y, Q = \u_layer_sequencer.ram_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$14489 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$shiftx$rtl/layer_sequencer.v:311$754_Y, Q = \u_layer_sequencer.ram_wdata). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10628 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7920_Y, Q = \u_layer_sequencer.ram_addr, rval = 23'00000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$14491 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7920_Y, Q = \u_layer_sequencer.ram_addr). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$10627 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7928_Y, Q = \u_layer_sequencer.ram_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$14495 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$7928_Y, Q = \u_layer_sequencer.ram_wr). Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$14198 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$14143 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$13879 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$13879 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$13879 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$13757 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$13757 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$13757 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$13757 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$13757 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$13757 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$13757 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$13757 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 9 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 10 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 11 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 12 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 13 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 14 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 15 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 16 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 17 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 18 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 19 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 20 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$13623 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$12611 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$12611 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$12611 ($sdffe) from module spi_neuron_top. 20.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 662 unused cells and 938 unused wires. 20.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.15.9. Rerunning OPT passes. (Maybe there is more to do..) 20.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 3119 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2796 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2772 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 347 cells. 20.15.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$14336 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 2 on $flatten\u_spi_engine.$procdff$10471 ($dff) from module spi_neuron_top. 20.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 1 unused cells and 348 unused wires. 20.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.15.16. Rerunning OPT passes. (Maybe there is more to do..) 20.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.15.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2771 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.15.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$13114 ($sdffe) from module spi_neuron_top. 20.15.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.15.22. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.15.23. Rerunning OPT passes. (Maybe there is more to do..) 20.15.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.15.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.15.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2771 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.15.27. Executing OPT_DFF pass (perform DFF optimizations). 20.15.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.15.29. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.15.30. Finished fast OPT passes. (There is nothing left to do.) 20.16. Executing WREDUCE pass (reducing word size of cells). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$414 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$415 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$416 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$417 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$418 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$419 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$420 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$421 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$422 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$423 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$424 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$425 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$426 (u_neuron_memory.w_mem). Removed top 32 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\y_reg$rtl/neuron_memory.v:140$427 (u_neuron_memory.y_reg). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$388 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$387 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$404 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$395 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$410 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$403 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$394 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$386 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$385 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$384 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$381 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$383 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$396 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$367 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$368 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$369 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$370 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$411 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$412 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$413 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$402 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$407 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$408 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$409 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$363 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$364 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10924 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10925 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10926 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10927 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10928 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10929 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10930 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10931 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10932 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10933 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10934 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10935 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10936 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10937 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10938 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10939 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10940 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10941 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10942 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10943 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10944 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10945 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10946 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10947 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10948 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10949 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10950 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10951 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10952 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10953 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10954 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10955 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10956 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10957 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10958 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10959 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10960 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10961 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10962 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10963 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$393 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$392 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$372 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10964 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$391 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$401 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$371 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10965 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10966 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10967 (u_graph_engine.w_mem). Removed top 32 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$10990 (u_neuron_memory.y_reg). Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$10991 (u_neuron_memory.x_mem). Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$10992 (u_neuron_memory.w_mem). Removed top 1 address bits (of 1) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$10993 (u_neuron_memory.y_reg). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$405 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$390 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$400 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10968 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$406 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$380 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10969 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$389 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10970 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10971 (u_graph_engine.w_mem). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10831 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10832 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10833 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10834 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10835 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10836 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10837 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10838 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10839 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10840 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10841 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10842 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10843 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10844 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10845 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10846 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10847 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10848 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10849 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10850 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10851 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10852 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10853 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10854 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10855 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10856 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10857 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10858 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10859 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10860 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10861 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10862 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10863 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10864 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10865 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10866 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10867 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10868 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10869 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10870 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10871 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10872 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10873 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10874 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10875 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10876 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10877 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10878 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10879 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10880 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10881 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10882 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10883 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10884 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10885 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10886 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10887 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10888 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10889 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10890 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10891 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10892 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10893 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10894 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10895 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10896 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10897 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10898 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10899 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10900 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10901 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10902 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10903 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10904 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10905 (u_flash_slot_manager.cat_crc). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10906 (u_flash_slot_manager.cat_offset). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10907 (u_flash_slot_manager.cat_length). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10908 (u_flash_slot_manager.cat_type). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10909 (u_flash_slot_manager.cat_valid). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10910 (u_flash_slot_manager.cat_crc). Removed top 1 address bits (of 5) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10916 (u_flash_slot_manager.cat_offset). Removed top 1 address bits (of 5) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10917 (u_flash_slot_manager.cat_length). Removed top 1 address bits (of 5) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10918 (u_flash_slot_manager.cat_type). Removed top 1 address bits (of 5) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10919 (u_flash_slot_manager.cat_valid). Removed top 1 address bits (of 5) from memory init port spi_neuron_top.$flatten\u_flash_slot_manager.$auto$proc_memwr.cc:45:proc_memwr$10920 (u_flash_slot_manager.cat_crc). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$379 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$378 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10972 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10973 (u_graph_engine.w_mem). Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10989 (u_graph_engine.w_mem). Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10988 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10974 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10975 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10976 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10977 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$399 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$678 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$679 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$680 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$681 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$682 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$683 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$684 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$685 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10978 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$686 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$687 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$688 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$689 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$690 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$691 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$692 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$693 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$694 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$695 (u_graph_engine.w_mem). Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_spi_engine.$auto$mem.cc:351:emit$1629 ($flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$382 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$696 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$697 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10979 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$698 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10980 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10981 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10982 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10983 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10984 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10985 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$699 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$700 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$377 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$701 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$702 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$703 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$704 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$705 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$706 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$707 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$708 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$376 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$709 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$710 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$711 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$712 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$713 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$714 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$715 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$716 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10986 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$717 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$718 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$719 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$720 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$10987 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$721 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$722 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$723 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$724 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$725 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$726 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$727 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$375 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$728 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$729 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$730 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$731 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$732 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$733 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$734 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$735 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$736 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$737 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$738 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$739 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$374 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$rtl/graph_engine.v:214$740 (u_graph_engine.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$rtl/graph_engine.v:215$741 (u_graph_engine.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$373 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$365 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$398 (u_neuron_memory.w_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$rtl/neuron_memory.v:129$397 (u_neuron_memory.x_mem). Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$rtl/neuron_memory.v:130$366 (u_neuron_memory.w_mem). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$14472 ($ne). Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$14415 ($sdffe). Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$14405 ($sdffe). Removed top 6 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$14398 ($sdffe). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$14356 ($ne). Removed top 22 bits (of 23) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$14182 ($sdffe). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$14029 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$14016 ($ne). Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$13991 ($sdffe). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13967 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13927 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13925 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13893 ($ne). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13723 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13711 ($ne). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13697 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13642 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13640 ($ne). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13615 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13603 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13601 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13591 ($ne). Removed top 8 bits (of 128) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$13561 ($sdffe). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13513 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13472 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13410 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13331 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13323 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13293 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13289 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13257 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13249 ($ne). Removed top 2 bits (of 3) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13194 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13192 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13190 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13184 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13156 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$13154 ($ne). Removed top 8 bits (of 72) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$12758 ($sdffe). Removed top 8 bits (of 24) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$12712 ($sdffe). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$12685 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$12675 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$12583 ($ne). Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$12543 ($sdffe). Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$12531 ($sdffe). Removed top 22 bits (of 23) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$12517 ($sdffe). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$12481 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11999 ($eq). Removed top 4 bits (of 9) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11960 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11951 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11911 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11885 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11868 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11671 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11647 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11638 ($eq). Removed top 3 bits (of 5) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11620 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11580 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11555 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11506 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11404 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11391 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11383 ($eq). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11330 ($eq). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11297 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$11234 ($eq). Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$2744 ($mux). Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$2741 ($mux). Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$2738 ($mux). Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$2736 ($mux). Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$2733 ($mux). Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$2731 ($mux). Removed top 2 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_spi_slave.$add$rtl/spi_slave.v:173$1371 ($add). Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4393_CMP0 ($eq). Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4382_CMP0 ($eq). Removed top 4 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4369_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4368_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4367_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4366_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4365_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4364_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4363_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4362_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4361_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4360_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4359_CMP0 ($eq). Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4299_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4259_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4220_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4185_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4151_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4118_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4080_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4043_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3957_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3925_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3597_CMP0 ($eq). Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3596_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3595_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3422_CMP1 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3422_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3421_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3420_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3419_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3418_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3417_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3356_CMP1 ($eq). Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3356_CMP0 ($eq). Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3334 ($pmux). Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3332 ($mux). Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3180_CMP0 ($eq). Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3179_CMP0 ($eq). Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3069_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3033_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3018_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3015_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3012_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3009_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3006_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3003_CMP0 ($eq). Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$2967_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$2924_CMP0 ($eq). Removed top 4 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$rtl/spi_engine.v:1121$1357 ($add). Removed top 4 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$rtl/spi_engine.v:1118$1355 ($sub). Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$rtl/spi_engine.v:1102$1354 ($add). Removed top 1 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352 ($eq). Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$rtl/spi_engine.v:1014$1344 ($sub). Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$rtl/spi_engine.v:946$1340 ($eq). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$rtl/spi_engine.v:873$1335 ($eq). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$rtl/spi_engine.v:871$1334 ($sub). Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$rtl/spi_engine.v:821$1331 ($eq). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$rtl/spi_engine.v:812$1329 ($eq). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$rtl/spi_engine.v:794$1328 ($add). Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$rtl/spi_engine.v:765$1327 ($eq). Removed top 7 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_engine.$ternary$rtl/spi_engine.v:486$1322 ($mux). Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$shiftx$rtl/spi_engine.v:448$1321 ($shiftx). Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$lt$rtl/spi_engine.v:447$1318 ($lt). Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$rtl/spi_engine.v:364$1310 ($eq). Removed top 1 bits (of 14) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$auto$opt_expr.cc:702:replace_const_cells$10994 ($not). Removed top 1 bits (of 14) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$auto$opt_expr.cc:702:replace_const_cells$10996 ($not). Removed top 1 bits (of 14) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$auto$opt_expr.cc:702:replace_const_cells$10998 ($not). Removed top 1 bits (of 14) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$auto$opt_expr.cc:702:replace_const_cells$11000 ($not). Removed top 1 bits (of 14) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$auto$opt_expr.cc:702:replace_const_cells$11004 ($not). Removed top 1 bits (of 14) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$auto$opt_expr.cc:702:replace_const_cells$11002 ($not). Removed top 1 bits (of 14) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$auto$opt_expr.cc:702:replace_const_cells$11008 ($not). Removed top 1 bits (of 14) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$auto$opt_expr.cc:702:replace_const_cells$11006 ($not). Removed top 8 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:323$1461 ($add). Removed top 19 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:323$1461 ($add). Removed top 7 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:323$1461 ($add). Removed top 7 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:323$1462 ($gt). Removed top 7 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:323$1462 ($gt). Removed top 1 bits (of 25) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:332$1465 ($add). Removed top 12 bits (of 25) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:332$1465 ($add). Removed top 8 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:346$1466 ($add). Removed top 8 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:346$1466 ($add). Removed top 7 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:346$1466 ($add). Removed top 7 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:346$1467 ($gt). Removed top 7 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:346$1467 ($gt). Removed top 9 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:347$1468 ($add). Removed top 8 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:347$1468 ($add). Removed top 7 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:347$1468 ($add). Removed top 7 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:347$1469 ($gt). Removed top 8 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:347$1469 ($gt). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$ne$rtl/flash_copy_engine.v:350$1474 ($ne). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$eq$rtl/flash_copy_engine.v:351$1477 ($eq). Removed top 1 bits (of 25) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:365$1482 ($add). Removed top 1 bits (of 25) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:365$1482 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:385$1483 ($gt). Removed top 23 bits (of 24) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:428$1486 ($add). Removed top 23 bits (of 24) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$sub$rtl/flash_copy_engine.v:430$1488 ($sub). Removed top 15 bits (of 24) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:513$1489 ($gt). Removed top 23 bits (of 24) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:543$1492 ($add). Removed top 23 bits (of 24) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$sub$rtl/flash_copy_engine.v:544$1493 ($sub). Removed top 11 bits (of 24) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:580$1495 ($add). Removed top 1 bits (of 25) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:581$1496 ($add). Removed top 12 bits (of 25) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:581$1496 ($add). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$ternary$rtl/flash_copy_engine.v:586$1498 ($mux). Removed top 2 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2006_CMP0 ($eq). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2411 ($mux). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2415 ($mux). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2417 ($mux). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2420 ($mux). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2429_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2432_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2439_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2442_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2443_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2446_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2447_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2450_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2451_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2454_CMP0 ($eq). Removed top 2 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2456 ($mux). Removed top 4 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2464_CMP0 ($eq). Removed top 2 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2466 ($mux). Removed top 1 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2532_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2536_CMP0 ($eq). Removed top 29 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:333$1558 ($sub). Removed top 25 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:333$1558 ($sub). Removed top 2 bits (of 6) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$lt$rtl/spi_flash_master.v:332$1557 ($lt). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:307$1550 ($add). Removed top 3 bits (of 6) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:305$1549 ($eq). Removed top 5 bits (of 6) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:280$1547 ($add). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:272$1546 ($eq). Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:265$1541 ($sub). Removed top 25 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:265$1541 ($sub). Removed top 27 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:262$1539 ($sub). Removed top 25 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:262$1539 ($sub). Removed top 8 bits (of 32) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:226$1536 ($mux). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:160$1528 ($add). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7416_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7357 ($mux). Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7199_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7198_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7197_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7196_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7195_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7194_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7193_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7140_CMP0 ($eq). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$6948 ($mux). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$6857_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$6853_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$6846_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$6831_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$6830_CMP0 ($eq). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$6431 ($mux). Removed top 2 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$5477_CMP0 ($eq). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$5272 ($mux). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$5009 ($mux). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$4978_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$4440_CMP0 ($eq). Removed top 1 bits (of 5) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.$ternary$rtl/flash_slot_manager.v:549$1274 ($mux). Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:549$1273 ($add). Removed top 1 bits (of 5) from port Y of cell spi_neuron_top.$flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:549$1273 ($add). Removed top 1 bits (of 5) from port A of cell spi_neuron_top.$flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:549$1273 ($add). Removed top 7 bits (of 8) from mux cell spi_neuron_top.$flatten\u_flash_slot_manager.$ternary$rtl/flash_slot_manager.v:528$1265 ($mux). Removed top 8 bits (of 9) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:499$1245 ($add). Removed top 1 bits (of 9) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$eq$rtl/flash_slot_manager.v:496$1244 ($eq). Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.$eq$rtl/flash_slot_manager.v:490$1243 ($eq). Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$xor$rtl/crc32.v:37$1420 ($xor). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:150$1523 ($eq). Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$7714_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$7691_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$7673_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$7653_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$7547_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$7525_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$7504_CMP0 ($eq). Removed top 28 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:337$761 ($add). Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:337$761 ($add). Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:336$760 ($add). Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$sub$rtl/layer_sequencer.v:323$757 ($sub). Removed top 27 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$shiftx$rtl/layer_sequencer.v:311$754 ($shiftx). Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:259$746 ($add). Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$shiftx$rtl/neuron_parallel.v:112$1377 ($shiftx). Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$shiftx$rtl/neuron_parallel.v:118$1381 ($shiftx). Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$add$rtl/neuron_parallel.v:158$1382 ($add). Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add). Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add). Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add). Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add). Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add). Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add). Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add). Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add). Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$8578_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$8554_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$8491_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$8430_CMP0 ($eq). Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_graph_engine.$procmux$8391 ($mux). Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_graph_engine.$procmux$8090 ($mux). Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$8042_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$8019_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$7998_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$7979_CMP0 ($eq). Removed top 28 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:558$672 ($add). Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:558$672 ($add). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:557$671 ($add). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$sub$rtl/graph_engine.v:552$669 ($sub). Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:503$665 ($add). Removed top 3 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$ge$rtl/graph_engine.v:483$663 ($ge). Removed top 3 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$ge$rtl/graph_engine.v:482$661 ($ge). Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:455$658 ($add). Removed top 9 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:455$658 ($add). Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:455$657 ($add). Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:455$657 ($add). Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:426$654 ($add). Removed top 29 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:419$651 ($add). Removed top 16 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:419$651 ($add). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:375$648 ($add). Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$sub$rtl/graph_engine.v:346$645 ($sub). Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$shiftx$rtl/neuron_parallel.v:112$1377 ($shiftx). Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$shiftx$rtl/neuron_parallel.v:118$1381 ($shiftx). Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$add$rtl/neuron_parallel.v:158$1382 ($add). Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add). Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add). Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add). Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add). Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add). Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add). Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add). Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add). Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add). Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$9148 ($mux). Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$9139 ($mux). Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$9130 ($mux). Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$9052 ($mux). Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$9022 ($mux). Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$8995 ($mux). Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$8936 ($mux). Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$8900 ($mux). Removed top 11 bits (of 14) from port B of cell spi_neuron_top.$flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:765$287 ($eq). Removed top 1 bits (of 19) from port A of cell spi_neuron_top.$flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:638$284 ($eq). Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_psram_ctrl.$ge$rtl/psram_controller.v:605$282 ($ge). Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_psram_ctrl.$sub$rtl/psram_controller.v:516$278 ($sub). Removed top 29 bits (of 32) from mux cell spi_neuron_top.$flatten\u_psram_ctrl.$ternary$rtl/psram_controller.v:516$277 ($mux). Removed top 1 bits (of 23) from mux cell spi_neuron_top.$flatten\u_psram_ctrl.$ternary$rtl/psram_controller.v:426$271 ($mux). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_psram_ctrl.$eq$rtl/psram_controller.v:379$267 ($eq). Removed top 8 bits (of 16) from mux cell spi_neuron_top.$flatten\u_psram_ctrl.$ternary$rtl/psram_controller.v:377$266 ($mux). Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_psram_ctrl.$lt$rtl/psram_controller.v:362$264 ($lt). Removed top 1 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$12712 ($sdffe). Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3357 ($mux). Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3336 ($mux). Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3334 ($pmux). Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3332 ($mux). Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3357 ($mux). Removed top 9 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3355 ($mux). Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3336 ($mux). Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.$ternary$rtl/flash_slot_manager.v:549$1274_Y. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:549$1273_Y. Removed top 7 bits (of 8) from wire spi_neuron_top.$flatten\u_flash_slot_manager.$ternary$rtl/flash_slot_manager.v:528$1265_Y. Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$3$memwr$\w_mem$rtl/neuron_memory.v:434$300_ADDR[5:0]$344. Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$2$memwr$\w_mem$rtl/neuron_memory.v:434$300_ADDR[5:0]$327. Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$2$memwr$\x_mem$rtl/neuron_memory.v:367$299_ADDR[5:0]$324. Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$0$memwr$\w_mem$rtl/neuron_memory.v:434$300_ADDR[5:0]$308. Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$0$memwr$\x_mem$rtl/neuron_memory.v:367$299_ADDR[5:0]$305. Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:337$761_Y. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.$4$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR[4:0]$1240. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.$3$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR[4:0]$1224. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.$2$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR[4:0]$1159. Removed top 1 bits (of 4) from wire spi_neuron_top.$flatten\u_flash_slot_manager.$procmux$7357_Y. Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:455$658_Y. Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:455$657_Y. Removed top 2 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2466_Y. Removed top 2 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2456_Y. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2420_Y. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2417_Y. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2415_Y. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$procmux$2411_Y. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.$0$memwr$\cat_crc$rtl/flash_slot_manager.v:491$852_ADDR[4:0]$987. Removed top 1 bits (of 5) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$ternary$rtl/flash_copy_engine.v:586$1498_Y. Removed top 7 bits (of 32) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:347$1468_Y. Removed top 7 bits (of 32) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:346$1466_Y. Removed top 7 bits (of 32) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:323$1461_Y. Removed top 1 bits (of 32) from wire spi_neuron_top.$flatten\u_flash_slot_manager.\u_crc32.$shr$rtl/crc32.v:40$1422_Y. Removed top 7 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_engine.$ternary$rtl/spi_engine.v:486$1322_Y. Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:558$672_Y. Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$3332_Y. Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$3334_Y. Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$3336_Y. Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$3355_Y. Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$3357_Y. Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_graph_engine.$2$memwr$\w_mem$rtl/graph_engine.v:521$493_ADDR[5:0]$641. Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_graph_engine.$0$memwr$\w_mem$rtl/graph_engine.v:521$493_ADDR[5:0]$565. Removed top 16 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$rtl/graph_engine.v:419$651_Y. Removed top 29 bits (of 32) from wire spi_neuron_top.$flatten\u_psram_ctrl.$ternary$rtl/psram_controller.v:516$277_Y. Removed top 1 bits (of 23) from wire spi_neuron_top.$flatten\u_psram_ctrl.$ternary$rtl/psram_controller.v:426$271_Y. Removed top 8 bits (of 16) from wire spi_neuron_top.$flatten\u_psram_ctrl.$ternary$rtl/psram_controller.v:377$266_Y. Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$2731_Y. Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$2733_Y. Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$2736_Y. Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$2738_Y. Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$2741_Y. Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$2744_Y. Removed top 1 bits (of 23) from wire spi_neuron_top.psram_mem_addr. Removed top 1 bits (of 23) from wire spi_neuron_top.i8_mem_addr. 20.17. Executing PEEPOPT pass (run peephole optimizers). shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_graph_engine.\u_neuron.$shiftx$rtl/neuron_parallel.v:118$1381, index=\u_graph_engine.u_neuron.group_index, stride=64, width=64, ways=4 shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_graph_engine.\u_neuron.$shiftx$rtl/neuron_parallel.v:112$1377, index=\u_graph_engine.u_neuron.group_index, stride=64, width=64, ways=4 shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_layer_sequencer.$shiftx$rtl/layer_sequencer.v:311$754, index=\u_layer_sequencer.copy_idx, stride=8, width=8, ways=2 shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_neuron_memory.\u_neuron.$shiftx$rtl/neuron_parallel.v:118$1381, index=\u_neuron_memory.u_neuron.group_index, stride=64, width=64, ways=4 shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_neuron_memory.\u_neuron.$shiftx$rtl/neuron_parallel.v:112$1377, index=\u_neuron_memory.u_neuron.group_index, stride=64, width=64, ways=4 20.18. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 51 unused wires. 20.19. Executing SHARE pass (SAT-based resource sharing). Found 13 cells in module spi_neuron_top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866 ($memrd): Found 6 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4368_CMP $flatten\u_spi_engine.$procmux$4369_CMP $flatten\u_spi_engine.$procmux$4370_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. Found 2 candidates: $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257 $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257 ($memrd): Found 3 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$procmux$7198_CMP $flatten\u_flash_slot_manager.$procmux$7199_CMP $flatten\u_flash_slot_manager.$procmux$7200_CMP }. Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4368_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4368_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4369_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4369_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4370_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4370_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257: $flatten\u_flash_slot_manager.$procmux$7198_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257: $flatten\u_flash_slot_manager.$procmux$7199_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257: $flatten\u_flash_slot_manager.$procmux$7200_CMP = 1'1 Size of SAT problem: 16 cells, 203 variables, 722 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$procmux$7198_CMP $flatten\u_flash_slot_manager.$procmux$7199_CMP $flatten\u_flash_slot_manager.$procmux$7200_CMP \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4368_CMP $flatten\u_spi_engine.$procmux$4369_CMP $flatten\u_spi_engine.$procmux$4370_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 14'10011001001001 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208 ($memrd): Found 2 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6853_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start }. Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4368_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4368_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4369_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4369_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4370_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:184$866: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4370_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208: { $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6853_CMP \u_spi_engine.flash_op_start } = 3'111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start } = 4'1111 Size of SAT problem: 16 cells, 214 variables, 742 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6853_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4368_CMP $flatten\u_spi_engine.$procmux$4369_CMP $flatten\u_spi_engine.$procmux$4370_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 16'0110111001001001 Analyzing resource sharing options for $flatten\u_spi_engine.$auto$mem.cc:305:emit$1628 ($memrd_v2): Found 2 activation_patterns using ctrl signal { \u_spi_engine.state [5] \u_spi_engine.resp_index [4] $flatten\u_spi_engine.$procmux$4382_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. No candidates found. Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:529$1266 ($memrd): Found 4 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$procmux$7189_CMP $flatten\u_flash_slot_manager.$procmux$7190_CMP $flatten\u_flash_slot_manager.$procmux$7191_CMP $flatten\u_flash_slot_manager.$procmux$7192_CMP }. Found 1 candidates: $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870 ($memrd): Found 8 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4359_CMP $flatten\u_spi_engine.$procmux$4360_CMP $flatten\u_spi_engine.$procmux$4361_CMP $flatten\u_spi_engine.$procmux$4362_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:529$1266: $flatten\u_flash_slot_manager.$procmux$7189_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:529$1266: $flatten\u_flash_slot_manager.$procmux$7190_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:529$1266: $flatten\u_flash_slot_manager.$procmux$7191_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:529$1266: $flatten\u_flash_slot_manager.$procmux$7192_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4359_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4359_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4360_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4360_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4361_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4361_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4362_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4362_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Size of SAT problem: 18 cells, 220 variables, 787 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$procmux$7189_CMP $flatten\u_flash_slot_manager.$procmux$7190_CMP $flatten\u_flash_slot_manager.$procmux$7191_CMP $flatten\u_flash_slot_manager.$procmux$7192_CMP \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4359_CMP $flatten\u_spi_engine.$procmux$4360_CMP $flatten\u_spi_engine.$procmux$4361_CMP $flatten\u_spi_engine.$procmux$4362_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 16'0100111000001001 Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:528$1264 ($memrd): Found 1 activation_patterns using ctrl signal $flatten\u_flash_slot_manager.$procmux$7193_CMP. Found 1 candidates: $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:187$869 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:187$869 ($memrd): Found 2 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4363_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. Forbidden control signals for this pair of cells: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:528$1264_DATA \u_spi_engine.flash_cat_out_valid } Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:528$1264: $flatten\u_flash_slot_manager.$procmux$7193_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:187$869: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4363_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:187$869: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4363_CMP \u_spi_slave.cs_fell } = 4'1111 Size of SAT problem: 12 cells, 172 variables, 612 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$procmux$7193_CMP \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4363_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 10'1111001100 Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_type$rtl/flash_slot_manager.v:527$1263 ($memrd): Found 1 activation_patterns using ctrl signal $flatten\u_flash_slot_manager.$procmux$7194_CMP. Found 1 candidates: $flatten\u_flash_slot_manager.$memrd$\cat_type$rtl/flash_slot_manager.v:186$868 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_type$rtl/flash_slot_manager.v:186$868 ($memrd): Found 2 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4364_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_type$rtl/flash_slot_manager.v:527$1263: $flatten\u_flash_slot_manager.$procmux$7194_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_type$rtl/flash_slot_manager.v:186$868: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4364_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_type$rtl/flash_slot_manager.v:186$868: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4364_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Size of SAT problem: 12 cells, 172 variables, 612 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$procmux$7194_CMP \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4364_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 10'1111001100 Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:524$1260 ($memrd): Found 3 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$procmux$7195_CMP $flatten\u_flash_slot_manager.$procmux$7196_CMP $flatten\u_flash_slot_manager.$procmux$7197_CMP }. Found 2 candidates: $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:395$1209 $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:395$1209 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start }. Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:524$1260: $flatten\u_flash_slot_manager.$procmux$7195_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:524$1260: $flatten\u_flash_slot_manager.$procmux$7196_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:524$1260: $flatten\u_flash_slot_manager.$procmux$7197_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:395$1209: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start } = 4'1111 Size of SAT problem: 5 cells, 87 variables, 224 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP $flatten\u_flash_slot_manager.$procmux$7195_CMP $flatten\u_flash_slot_manager.$procmux$7196_CMP $flatten\u_flash_slot_manager.$procmux$7197_CMP \u_spi_engine.flash_op_start } = 7'1110101 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867 ($memrd): Found 6 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP $flatten\u_spi_engine.$procmux$4366_CMP $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:524$1260: $flatten\u_flash_slot_manager.$procmux$7195_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:524$1260: $flatten\u_flash_slot_manager.$procmux$7196_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:524$1260: $flatten\u_flash_slot_manager.$procmux$7197_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4366_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4366_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Size of SAT problem: 16 cells, 207 variables, 734 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$procmux$7195_CMP $flatten\u_flash_slot_manager.$procmux$7196_CMP $flatten\u_flash_slot_manager.$procmux$7197_CMP \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP $flatten\u_spi_engine.$procmux$4366_CMP $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 14'01011010001001 Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257 ($memrd): Found 3 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$procmux$7198_CMP $flatten\u_flash_slot_manager.$procmux$7199_CMP $flatten\u_flash_slot_manager.$procmux$7200_CMP }. Found 1 candidates: $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208 ($memrd): Found 2 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6853_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start }. Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257: $flatten\u_flash_slot_manager.$procmux$7198_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257: $flatten\u_flash_slot_manager.$procmux$7199_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:521$1257: $flatten\u_flash_slot_manager.$procmux$7200_CMP = 1'1 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208: { $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6853_CMP \u_spi_engine.flash_op_start } = 3'111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start } = 4'1111 Size of SAT problem: 6 cells, 99 variables, 261 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6853_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP $flatten\u_flash_slot_manager.$procmux$7198_CMP $flatten\u_flash_slot_manager.$procmux$7199_CMP $flatten\u_flash_slot_manager.$procmux$7200_CMP \u_spi_engine.flash_op_start } = 8'01100101 Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:395$1209 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start }. Found 1 candidates: $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867 Analyzing resource sharing with $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867 ($memrd): Found 6 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP $flatten\u_spi_engine.$procmux$4366_CMP $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:395$1209: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4366_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4366_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_fell } = 4'1111 Activation pattern for cell $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867: { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 9'111001001 Size of SAT problem: 15 cells, 205 variables, 727 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP $flatten\u_spi_engine.$procmux$4366_CMP $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y } = 15'111111100001101 Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_offset$rtl/flash_slot_manager.v:393$1208 ($memrd): Found 2 activation_patterns using ctrl signal { $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:385$1206_DATA $flatten\u_flash_slot_manager.$procmux$5481_CMP $flatten\u_flash_slot_manager.$procmux$6853_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP \u_spi_engine.flash_op_start }. No candidates found. Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_crc$rtl/flash_slot_manager.v:188$870 ($memrd): Found 8 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4359_CMP $flatten\u_spi_engine.$procmux$4360_CMP $flatten\u_spi_engine.$procmux$4361_CMP $flatten\u_spi_engine.$procmux$4362_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. No candidates found. Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_valid$rtl/flash_slot_manager.v:187$869 ($memrd): Found 2 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4363_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. No candidates found. Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_type$rtl/flash_slot_manager.v:186$868 ($memrd): Found 2 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4364_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. No candidates found. Analyzing resource sharing options for $flatten\u_flash_slot_manager.$memrd$\cat_length$rtl/flash_slot_manager.v:185$867 ($memrd): Found 6 activation_patterns using ctrl signal { \u_spi_engine.state [5] $flatten\u_spi_engine.$eq$rtl/spi_engine.v:1098$1352_Y $flatten\u_spi_engine.$procmux$4365_CMP $flatten\u_spi_engine.$procmux$4366_CMP $flatten\u_spi_engine.$procmux$4367_CMP \u_spi_slave.cs_n_sync [2] \u_spi_slave.sclk_rise \u_spi_slave.sclk_fall \u_spi_slave.cs_fell \u_spi_slave.cs_rose $flatten\u_spi_slave.$eq$rtl/spi_slave.v:182$1372_Y }. No candidates found. 20.20. Executing TECHMAP pass (map to technology primitives). 20.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 20.20.2. Continuing TECHMAP pass. Using template $paramod$cfdad2d5c6ed189d9565d7e849f44dc84ae90046\_90_lut_cmp_ for cells of type $lt. No more expansions possible. 20.21. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.22. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 3 unused wires. 20.23. Executing TECHMAP pass (map to technology primitives). 20.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 20.23.2. Continuing TECHMAP pass. Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul. No more expansions possible. 20.24. Executing TECHMAP pass (map to technology primitives). 20.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 20.24.2. Continuing TECHMAP pass. Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. 20.25. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module spi_neuron_top: creating $macc model for $flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:499$1245 ($add). creating $macc model for $flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:549$1273 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.$add$rtl/neuron_parallel.v:158$1382 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:115$1595 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.$add$rtl/neuron_parallel.v:265$1400 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.$sub$rtl/neuron_parallel.v:257$1398 ($sub). creating $macc model for $flatten\u_neuron_memory.$sub$rtl/neuron_memory.v:378$337 ($sub). creating $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:415$341 ($add). creating $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:417$342 ($add). creating $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:417$343 ($add). creating $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:455$352 ($add). creating $macc model for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:310$751 ($add). creating $macc model for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:231$744 ($add). creating $macc model for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:259$746 ($add). creating $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:455$353 ($add). creating $macc model for $flatten\u_neuron_memory.$sub$rtl/neuron_memory.v:502$357 ($sub). creating $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:515$359 ($add). creating $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:516$360 ($add). creating $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:517$361 ($add). creating $macc model for $flatten\u_layer_sequencer.$sub$rtl/layer_sequencer.v:321$755 ($sub). creating $macc model for $flatten\u_layer_sequencer.$sub$rtl/layer_sequencer.v:323$757 ($sub). creating $macc model for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:336$760 ($add). creating $macc model for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:337$761 ($add). creating $macc model for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:346$762 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1621 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1623 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1625 ($add). creating $macc model for $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:390$269 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:160$1528 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:262$1539 ($sub). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:265$1541 ($sub). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:280$1547 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:307$1550 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:333$1558 ($sub). creating $macc model for $flatten\u_neuron_memory.\u_neuron.$add$rtl/neuron_parallel.v:265$1400 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.$sub$rtl/neuron_parallel.v:257$1398 ($sub). creating $macc model for $flatten\u_neuron_memory.\u_neuron.$add$rtl/neuron_parallel.v:158$1382 ($add). creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:115$1595 ($add). creating $macc model for $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:513$276 ($add). creating $macc model for $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:320$262 ($add). creating $macc model for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:177$496 ($sub). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:332$644 ($add). creating $macc model for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:346$645 ($sub). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:375$648 ($add). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:391$649 ($add). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:419$651 ($add). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:426$654 ($add). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:455$657 ($add). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:455$658 ($add). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:503$665 ($add). creating $macc model for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:523$666 ($sub). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:527$668 ($add). creating $macc model for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:552$669 ($sub). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:557$671 ($add). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:558$672 ($add). creating $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:575$673 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:581$1496 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:580$1495 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$sub$rtl/flash_copy_engine.v:544$1493 ($sub). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:543$1492 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:542$1491 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$sub$rtl/flash_copy_engine.v:430$1488 ($sub). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:429$1487 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:428$1486 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:365$1482 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:347$1468 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:346$1466 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:332$1465 ($add). creating $macc model for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:323$1461 ($add). creating $macc model for $flatten\u_spi_engine.$add$rtl/spi_engine.v:794$1328 ($add). creating $macc model for $flatten\u_spi_engine.$add$rtl/spi_engine.v:870$1333 ($add). creating $macc model for $flatten\u_spi_engine.$sub$rtl/spi_engine.v:871$1334 ($sub). creating $macc model for $flatten\u_spi_engine.$sub$rtl/spi_engine.v:1014$1344 ($sub). creating $macc model for $flatten\u_spi_engine.$add$rtl/spi_engine.v:1102$1354 ($add). creating $macc model for $flatten\u_spi_engine.$sub$rtl/spi_engine.v:1118$1355 ($sub). creating $macc model for $flatten\u_spi_engine.$add$rtl/spi_engine.v:1121$1357 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1621 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1623 ($add). creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1625 ($add). creating $macc model for $flatten\u_psram_ctrl.$sub$rtl/psram_controller.v:516$278 ($sub). creating $macc model for $flatten\u_spi_slave.$add$rtl/spi_slave.v:173$1371 ($add). creating $macc model for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:175$494 ($sub). merging $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1621 into $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1625. merging $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1623 into $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1625. merging $macc model for $flatten\u_graph_engine.$add$rtl/graph_engine.v:455$657 into $flatten\u_graph_engine.$add$rtl/graph_engine.v:455$658. merging $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1625 into $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:115$1595. merging $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1621 into $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:115$1595. merging $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1623 into $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:115$1595. merging $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:455$352 into $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:455$353. merging $macc model for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:417$342 into $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:417$343. merging $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1625 into $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:115$1595. creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613. creating $alu model for $macc $flatten\u_spi_engine.$add$rtl/spi_engine.v:1121$1357. creating $alu model for $macc $flatten\u_spi_engine.$sub$rtl/spi_engine.v:1118$1355. creating $alu model for $macc $flatten\u_spi_engine.$add$rtl/spi_engine.v:1102$1354. creating $alu model for $macc $flatten\u_spi_engine.$sub$rtl/spi_engine.v:1014$1344. creating $alu model for $macc $flatten\u_spi_engine.$sub$rtl/spi_engine.v:871$1334. creating $alu model for $macc $flatten\u_spi_engine.$add$rtl/spi_engine.v:870$1333. creating $alu model for $macc $flatten\u_spi_engine.$add$rtl/spi_engine.v:794$1328. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:323$1461. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:332$1465. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:346$1466. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:347$1468. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:365$1482. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:428$1486. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:429$1487. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$sub$rtl/flash_copy_engine.v:430$1488. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:542$1491. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:543$1492. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$sub$rtl/flash_copy_engine.v:544$1493. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:580$1495. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:581$1496. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:575$673. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:558$672. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:557$671. creating $alu model for $macc $flatten\u_graph_engine.$sub$rtl/graph_engine.v:552$669. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:527$668. creating $alu model for $macc $flatten\u_graph_engine.$sub$rtl/graph_engine.v:523$666. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:503$665. creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:426$654. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:419$651. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:391$649. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:375$648. creating $alu model for $macc $flatten\u_graph_engine.$sub$rtl/graph_engine.v:346$645. creating $alu model for $macc $flatten\u_graph_engine.$add$rtl/graph_engine.v:332$644. creating $alu model for $macc $flatten\u_graph_engine.$sub$rtl/graph_engine.v:177$496. creating $alu model for $macc $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:320$262. creating $alu model for $macc $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:513$276. creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$add$rtl/neuron_parallel.v:158$1382. creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$sub$rtl/neuron_parallel.v:257$1398. creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$add$rtl/neuron_parallel.v:265$1400. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:333$1558. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:307$1550. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:280$1547. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:265$1541. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:262$1539. creating $alu model for $macc $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:160$1528. creating $alu model for $macc $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:390$269. creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615. creating $alu model for $macc $flatten\u_graph_engine.$sub$rtl/graph_engine.v:175$494. creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617. creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619. creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617. creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615. creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613. creating $alu model for $macc $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:346$762. creating $alu model for $macc $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:337$761. creating $alu model for $macc $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:336$760. creating $alu model for $macc $flatten\u_layer_sequencer.$sub$rtl/layer_sequencer.v:323$757. creating $alu model for $macc $flatten\u_layer_sequencer.$sub$rtl/layer_sequencer.v:321$755. creating $alu model for $macc $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:517$361. creating $alu model for $macc $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:516$360. creating $alu model for $macc $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:515$359. creating $alu model for $macc $flatten\u_neuron_memory.$sub$rtl/neuron_memory.v:502$357. creating $alu model for $macc $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:455$353. creating $alu model for $macc $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:259$746. creating $alu model for $macc $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:231$744. creating $alu model for $macc $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:310$751. creating $alu model for $macc $flatten\u_psram_ctrl.$sub$rtl/psram_controller.v:516$278. creating $alu model for $macc $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:417$343. creating $alu model for $macc $flatten\u_spi_slave.$add$rtl/spi_slave.v:173$1371. creating $alu model for $macc $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:415$341. creating $alu model for $macc $flatten\u_neuron_memory.$sub$rtl/neuron_memory.v:378$337. creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$sub$rtl/neuron_parallel.v:257$1398. creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$add$rtl/neuron_parallel.v:265$1400. creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$add$rtl/neuron_parallel.v:158$1382. creating $alu model for $macc $flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:549$1273. creating $alu model for $macc $flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:499$1245. creating $macc cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:455$658: $auto$alumacc.cc:399:replace_macc$14594 creating $macc cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:115$1595: $auto$alumacc.cc:399:replace_macc$14595 creating $macc cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:115$1595: $auto$alumacc.cc:399:replace_macc$14596 creating $alu model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$lt$rtl/spi_flash_master.v:261$1538 ($lt): new $alu creating $alu model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$lt$rtl/spi_flash_master.v:332$1557 ($lt): new $alu creating $alu model for $flatten\u_graph_engine.$ge$rtl/graph_engine.v:176$495 ($ge): merged with $flatten\u_graph_engine.$sub$rtl/graph_engine.v:177$496. creating $alu model for $flatten\u_graph_engine.$ge$rtl/graph_engine.v:481$660 ($ge): new $alu creating $alu model for $flatten\u_graph_engine.$ge$rtl/graph_engine.v:482$661 ($ge): new $alu creating $alu model for $flatten\u_graph_engine.$ge$rtl/graph_engine.v:483$663 ($ge): new $alu creating $alu model for $flatten\u_flash_slot_manager.\u_fce.$ge$rtl/flash_copy_engine.v:581$1497 ($ge): new $alu creating $alu model for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:513$1489 ($gt): new $alu creating $alu model for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:385$1483 ($gt): new $alu creating $alu model for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:347$1469 ($gt): new $alu creating $alu model for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:346$1467 ($gt): new $alu creating $alu model for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:323$1462 ($gt): new $alu creating $alu model for $flatten\u_spi_engine.$lt$rtl/spi_engine.v:447$1318 ($lt): new $alu creating $alu model for $flatten\u_psram_ctrl.$ge$rtl/psram_controller.v:605$282 ($ge): new $alu creating $alu model for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:305$1549 ($eq): merged with $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:333$1558. creating $alu model for $flatten\u_spi_engine.$eq$rtl/spi_engine.v:873$1335 ($eq): merged with $flatten\u_spi_engine.$sub$rtl/spi_engine.v:871$1334. creating $alu model for $flatten\u_spi_engine.$procmux$4369_CMP0 ($eq): merged with $flatten\u_spi_engine.$lt$rtl/spi_engine.v:447$1318. creating $alu cell for $flatten\u_psram_ctrl.$ge$rtl/psram_controller.v:605$282: $auto$alumacc.cc:548:replace_alu$14610 creating $alu cell for $flatten\u_spi_engine.$lt$rtl/spi_engine.v:447$1318, $flatten\u_spi_engine.$procmux$4369_CMP0: $auto$alumacc.cc:548:replace_alu$14623 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:323$1462: $auto$alumacc.cc:548:replace_alu$14630 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:346$1467: $auto$alumacc.cc:548:replace_alu$14641 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:347$1469: $auto$alumacc.cc:548:replace_alu$14652 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:385$1483: $auto$alumacc.cc:548:replace_alu$14663 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$gt$rtl/flash_copy_engine.v:513$1489: $auto$alumacc.cc:548:replace_alu$14674 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$ge$rtl/flash_copy_engine.v:581$1497: $auto$alumacc.cc:548:replace_alu$14685 creating $alu cell for $flatten\u_graph_engine.$ge$rtl/graph_engine.v:483$663: $auto$alumacc.cc:548:replace_alu$14698 creating $alu cell for $flatten\u_graph_engine.$ge$rtl/graph_engine.v:482$661: $auto$alumacc.cc:548:replace_alu$14711 creating $alu cell for $flatten\u_graph_engine.$ge$rtl/graph_engine.v:481$660: $auto$alumacc.cc:548:replace_alu$14724 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$lt$rtl/spi_flash_master.v:332$1557: $auto$alumacc.cc:548:replace_alu$14737 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$lt$rtl/spi_flash_master.v:261$1538: $auto$alumacc.cc:548:replace_alu$14742 creating $alu cell for $flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:499$1245: $auto$alumacc.cc:548:replace_alu$14747 creating $alu cell for $flatten\u_flash_slot_manager.$add$rtl/flash_slot_manager.v:549$1273: $auto$alumacc.cc:548:replace_alu$14750 creating $alu cell for $flatten\u_graph_engine.\u_neuron.$add$rtl/neuron_parallel.v:158$1382: $auto$alumacc.cc:548:replace_alu$14753 creating $alu cell for $flatten\u_graph_engine.\u_neuron.$add$rtl/neuron_parallel.v:265$1400: $auto$alumacc.cc:548:replace_alu$14756 creating $alu cell for $flatten\u_graph_engine.\u_neuron.$sub$rtl/neuron_parallel.v:257$1398: $auto$alumacc.cc:548:replace_alu$14759 creating $alu cell for $flatten\u_neuron_memory.$sub$rtl/neuron_memory.v:378$337: $auto$alumacc.cc:548:replace_alu$14762 creating $alu cell for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:415$341: $auto$alumacc.cc:548:replace_alu$14765 creating $alu cell for $flatten\u_spi_slave.$add$rtl/spi_slave.v:173$1371: $auto$alumacc.cc:548:replace_alu$14768 creating $alu cell for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:417$343: $auto$alumacc.cc:548:replace_alu$14771 creating $alu cell for $flatten\u_psram_ctrl.$sub$rtl/psram_controller.v:516$278: $auto$alumacc.cc:548:replace_alu$14774 creating $alu cell for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:310$751: $auto$alumacc.cc:548:replace_alu$14777 creating $alu cell for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:231$744: $auto$alumacc.cc:548:replace_alu$14780 creating $alu cell for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:259$746: $auto$alumacc.cc:548:replace_alu$14783 creating $alu cell for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:455$353: $auto$alumacc.cc:548:replace_alu$14786 creating $alu cell for $flatten\u_neuron_memory.$sub$rtl/neuron_memory.v:502$357: $auto$alumacc.cc:548:replace_alu$14789 creating $alu cell for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:515$359: $auto$alumacc.cc:548:replace_alu$14792 creating $alu cell for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:516$360: $auto$alumacc.cc:548:replace_alu$14795 creating $alu cell for $flatten\u_neuron_memory.$add$rtl/neuron_memory.v:517$361: $auto$alumacc.cc:548:replace_alu$14798 creating $alu cell for $flatten\u_layer_sequencer.$sub$rtl/layer_sequencer.v:321$755: $auto$alumacc.cc:548:replace_alu$14801 creating $alu cell for $flatten\u_layer_sequencer.$sub$rtl/layer_sequencer.v:323$757: $auto$alumacc.cc:548:replace_alu$14804 creating $alu cell for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:336$760: $auto$alumacc.cc:548:replace_alu$14807 creating $alu cell for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:337$761: $auto$alumacc.cc:548:replace_alu$14810 creating $alu cell for $flatten\u_layer_sequencer.$add$rtl/layer_sequencer.v:346$762: $auto$alumacc.cc:548:replace_alu$14813 creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613: $auto$alumacc.cc:548:replace_alu$14816 creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615: $auto$alumacc.cc:548:replace_alu$14819 creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617: $auto$alumacc.cc:548:replace_alu$14822 creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619: $auto$alumacc.cc:548:replace_alu$14825 creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1617: $auto$alumacc.cc:548:replace_alu$14828 creating $alu cell for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:175$494: $auto$alumacc.cc:548:replace_alu$14831 creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1615: $auto$alumacc.cc:548:replace_alu$14834 creating $alu cell for $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:390$269: $auto$alumacc.cc:548:replace_alu$14837 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:160$1528: $auto$alumacc.cc:548:replace_alu$14840 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:262$1539: $auto$alumacc.cc:548:replace_alu$14843 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:265$1541: $auto$alumacc.cc:548:replace_alu$14846 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:280$1547: $auto$alumacc.cc:548:replace_alu$14849 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$add$rtl/spi_flash_master.v:307$1550: $auto$alumacc.cc:548:replace_alu$14852 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$sub$rtl/spi_flash_master.v:333$1558, $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:305$1549: $auto$alumacc.cc:548:replace_alu$14855 creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$add$rtl/neuron_parallel.v:265$1400: $auto$alumacc.cc:548:replace_alu$14860 creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$sub$rtl/neuron_parallel.v:257$1398: $auto$alumacc.cc:548:replace_alu$14863 creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$add$rtl/neuron_parallel.v:158$1382: $auto$alumacc.cc:548:replace_alu$14866 creating $alu cell for $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:513$276: $auto$alumacc.cc:548:replace_alu$14869 creating $alu cell for $flatten\u_psram_ctrl.$add$rtl/psram_controller.v:320$262: $auto$alumacc.cc:548:replace_alu$14872 creating $alu cell for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:177$496, $flatten\u_graph_engine.$ge$rtl/graph_engine.v:176$495: $auto$alumacc.cc:548:replace_alu$14875 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:332$644: $auto$alumacc.cc:548:replace_alu$14888 creating $alu cell for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:346$645: $auto$alumacc.cc:548:replace_alu$14891 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:375$648: $auto$alumacc.cc:548:replace_alu$14894 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:391$649: $auto$alumacc.cc:548:replace_alu$14897 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:419$651: $auto$alumacc.cc:548:replace_alu$14900 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:426$654: $auto$alumacc.cc:548:replace_alu$14903 creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1619: $auto$alumacc.cc:548:replace_alu$14906 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:503$665: $auto$alumacc.cc:548:replace_alu$14909 creating $alu cell for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:523$666: $auto$alumacc.cc:548:replace_alu$14912 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:527$668: $auto$alumacc.cc:548:replace_alu$14915 creating $alu cell for $flatten\u_graph_engine.$sub$rtl/graph_engine.v:552$669: $auto$alumacc.cc:548:replace_alu$14918 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:557$671: $auto$alumacc.cc:548:replace_alu$14921 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:558$672: $auto$alumacc.cc:548:replace_alu$14924 creating $alu cell for $flatten\u_graph_engine.$add$rtl/graph_engine.v:575$673: $auto$alumacc.cc:548:replace_alu$14927 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:581$1496: $auto$alumacc.cc:548:replace_alu$14930 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:580$1495: $auto$alumacc.cc:548:replace_alu$14933 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$sub$rtl/flash_copy_engine.v:544$1493: $auto$alumacc.cc:548:replace_alu$14936 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:543$1492: $auto$alumacc.cc:548:replace_alu$14939 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:542$1491: $auto$alumacc.cc:548:replace_alu$14942 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$sub$rtl/flash_copy_engine.v:430$1488: $auto$alumacc.cc:548:replace_alu$14945 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:429$1487: $auto$alumacc.cc:548:replace_alu$14948 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:428$1486: $auto$alumacc.cc:548:replace_alu$14951 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:347$1468: $auto$alumacc.cc:548:replace_alu$14954 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:365$1482: $auto$alumacc.cc:548:replace_alu$14957 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:346$1466: $auto$alumacc.cc:548:replace_alu$14960 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:332$1465: $auto$alumacc.cc:548:replace_alu$14963 creating $alu cell for $flatten\u_flash_slot_manager.\u_fce.$add$rtl/flash_copy_engine.v:323$1461: $auto$alumacc.cc:548:replace_alu$14966 creating $alu cell for $flatten\u_spi_engine.$add$rtl/spi_engine.v:794$1328: $auto$alumacc.cc:548:replace_alu$14969 creating $alu cell for $flatten\u_spi_engine.$add$rtl/spi_engine.v:870$1333: $auto$alumacc.cc:548:replace_alu$14972 creating $alu cell for $flatten\u_spi_engine.$sub$rtl/spi_engine.v:871$1334, $flatten\u_spi_engine.$eq$rtl/spi_engine.v:873$1335: $auto$alumacc.cc:548:replace_alu$14975 creating $alu cell for $flatten\u_spi_engine.$sub$rtl/spi_engine.v:1014$1344: $auto$alumacc.cc:548:replace_alu$14980 creating $alu cell for $flatten\u_spi_engine.$add$rtl/spi_engine.v:1102$1354: $auto$alumacc.cc:548:replace_alu$14983 creating $alu cell for $flatten\u_spi_engine.$sub$rtl/spi_engine.v:1118$1355: $auto$alumacc.cc:548:replace_alu$14986 creating $alu cell for $flatten\u_spi_engine.$add$rtl/spi_engine.v:1121$1357: $auto$alumacc.cc:548:replace_alu$14989 creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$rtl/mac8.v:101$1613: $auto$alumacc.cc:548:replace_alu$14992 created 91 $alu and 3 $macc cells. 20.26. Executing OPT pass (performing simple optimizations). 20.26.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.26.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2820 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2818 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 2 cells. 20.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$13488: { \u_flash_slot_manager.u_fce.u_spi_flash_master.sclk_will_rise \u_flash_slot_manager.u_fce.u_spi_flash_master.state [1] $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$eq$rtl/spi_flash_master.v:302$1548_Y $auto$alumacc.cc:564:replace_alu$14856 } Optimizing cells in module \spi_neuron_top. Performed a total of 2 changes. 20.26.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2818 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.26.6. Executing OPT_DFF pass (perform DFF optimizations). 20.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 12 unused cells and 163 unused wires. 20.26.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.26.9. Rerunning OPT passes. (Maybe there is more to do..) 20.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.26.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2806 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.26.13. Executing OPT_DFF pass (perform DFF optimizations). 20.26.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.26.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.26.16. Finished fast OPT passes. (There is nothing left to do.) 20.27. Executing MEMORY pass. 20.27.1. Executing OPT_MEM pass (optimize memories). spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627: removing const-0 lane 6 spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627: removing const-0 lane 7 Performed a total of 1 transformations. 20.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 1592 transformations. 20.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 0. Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 1. Analyzing spi_neuron_top.u_neuron_memory.x_mem write port 0. Analyzing spi_neuron_top.u_neuron_memory.w_mem write port 0. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 0. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 1. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 2. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 3. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 4. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 5. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 6. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 7. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 8. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 9. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 10. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 11. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 12. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 13. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 14. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 15. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 16. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 17. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 18. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 19. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 20. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 21. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 22. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 23. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 24. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 25. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 26. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 27. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 28. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 29. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 30. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 31. Analyzing spi_neuron_top.u_graph_engine.x_mem write port 32. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 0. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 1. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 2. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 3. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 4. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 5. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 6. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 7. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 8. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 9. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 10. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 11. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 12. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 13. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 14. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 15. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 16. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 17. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 18. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 19. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 20. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 21. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 22. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 23. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 24. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 25. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 26. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 27. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 28. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 29. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 30. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 31. Analyzing spi_neuron_top.u_graph_engine.w_mem write port 32. Analyzing spi_neuron_top.u_graph_engine.u_act_buffer.mem write port 0. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 0. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 1. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 2. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 3. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 4. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 5. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 6. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 7. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 8. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 9. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 10. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 11. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 12. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 13. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 14. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 15. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 16. Analyzing spi_neuron_top.u_flash_slot_manager.cat_offset write port 17. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 0. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 1. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 2. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 3. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 4. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 5. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 6. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 7. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 8. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 9. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 10. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 11. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 12. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 13. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 14. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 15. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 16. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 17. Analyzing spi_neuron_top.u_flash_slot_manager.cat_length write port 18. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 0. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 1. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 2. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 3. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 4. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 5. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 6. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 7. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 8. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 9. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 10. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 11. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 12. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 13. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 14. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 15. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 16. Analyzing spi_neuron_top.u_flash_slot_manager.cat_type write port 17. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 0. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 1. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 2. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 3. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 4. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 5. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 6. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 7. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 8. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 9. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 10. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 11. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 12. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 13. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 14. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 15. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 16. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 17. Analyzing spi_neuron_top.u_flash_slot_manager.cat_valid write port 18. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 0. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 1. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 2. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 3. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 4. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 5. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 6. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 7. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 8. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 9. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 10. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 11. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 12. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 13. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 14. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 15. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 16. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 17. Analyzing spi_neuron_top.u_flash_slot_manager.cat_crc write port 18. 20.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 20.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[3] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[4] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[5] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[6] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[7] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[8] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[9] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[10] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[11] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[12] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[13] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[14] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[15] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[16] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[17] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[18] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[19] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[20] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[21] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[22] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[23] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[24] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[25] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[26] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[27] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[28] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[29] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[30] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.x_mem'[31] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[3] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[4] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[5] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[6] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[7] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[8] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[9] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[10] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[11] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[12] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[13] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[14] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[15] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[16] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[17] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[18] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[19] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[20] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[21] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[22] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[23] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[24] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[25] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[26] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[27] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[28] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[29] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[30] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.w_mem'[31] in module `\spi_neuron_top': no output FF found. Checking read port `\u_graph_engine.u_act_buffer.mem'[0] in module `\spi_neuron_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\u_flash_slot_manager.cat_offset'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_offset'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_offset'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_length'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_length'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_length'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_type'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_type'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_valid'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_valid'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_valid'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_crc'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_crc'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_flash_slot_manager.cat_crc'[2] in module `\spi_neuron_top': no output FF found. Checking read port `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627'[0] in module `\spi_neuron_top': no output FF found. Checking read port address `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[0] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[1] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[2] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[3] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[4] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[5] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[6] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[7] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[8] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[9] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[10] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[11] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[12] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[13] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[14] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[15] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[16] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[17] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[18] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[19] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[20] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[21] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[22] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[23] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[24] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[25] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[26] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[27] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[28] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[29] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[30] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.x_mem'[31] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[0] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[1] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[2] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[3] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[4] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[5] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[6] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[7] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[8] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[9] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[10] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[11] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[12] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[13] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[14] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[15] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[16] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[17] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[18] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[19] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[20] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[21] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[22] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[23] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[24] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[25] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[26] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[27] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[28] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[29] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[30] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_graph_engine.w_mem'[31] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_flash_slot_manager.cat_offset'[0] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_offset'[1] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_offset'[2] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_length'[0] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_length'[1] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_length'[2] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_type'[0] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_type'[1] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_valid'[0] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_valid'[1] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_valid'[2] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_crc'[0] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_crc'[1] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_flash_slot_manager.cat_crc'[2] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627'[0] in module `\spi_neuron_top': merged address FF to cell. 20.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 1 unused cells and 9 unused wires. 20.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg by address: Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address: Merging ports 0, 24 (address 5'10001). Merging ports 1, 13 (address 5'00001). Merging ports 1, 18 (address 5'00000). Merging ports 1, 19 (address 5'00000). Merging ports 2, 9 (address 5'00101). Merging ports 3, 4 (address 5'00110). Merging ports 5, 10 (address 5'10010). Merging ports 6, 21 (address 5'01000). Merging ports 6, 22 (address 5'01000). Merging ports 6, 25 (address 5'01000). Merging ports 8, 23 (address 5'10101). Merging ports 11, 12 (address 5'01110). Merging ports 14, 15 (address 5'10111). Merging ports 16, 17 (address 5'11001). Merging ports 16, 30 (address 5'11000). Merging ports 16, 31 (address 5'11000). Merging ports 26, 27 (address 5'11111). Merging ports 26, 28 (address 5'11110). Merging ports 26, 29 (address 5'11100). Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address: Merging ports 0, 4 (address 5'10000). Merging ports 0, 7 (address 5'10000). Merging ports 0, 9 (address 5'10000). Merging ports 0, 10 (address 5'10000). Merging ports 0, 11 (address 5'10000). Merging ports 1, 2 (address 5'00000). Merging ports 1, 3 (address 5'00000). Merging ports 1, 5 (address 5'00000). Merging ports 1, 6 (address 5'00000). Merging ports 1, 8 (address 5'00000). Merging ports 1, 12 (address 5'00000). Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address: Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address: Merging ports 0, 12 (address 5'00001). Merging ports 0, 16 (address 5'00000). Merging ports 0, 17 (address 5'00000). Merging ports 1, 18 (address 5'10001). Merging ports 2, 10 (address 5'00101). Merging ports 3, 5 (address 5'00110). Merging ports 4, 6 (address 5'01001). Merging ports 4, 19 (address 5'01000). Merging ports 4, 20 (address 5'01000). Merging ports 4, 21 (address 5'01000). Merging ports 4, 24 (address 5'01000). Merging ports 7, 23 (address 5'10101). Merging ports 8, 14 (address 5'10010). Merging ports 13, 22 (address 5'10110). Merging ports 15, 31 (address 5'11000). Merging ports 25, 26 (address 5'11111). Merging ports 25, 27 (address 5'11110). Merging ports 25, 28 (address 5'11100). Merging ports 25, 29 (address 5'11100). Merging ports 25, 30 (address 5'11000). Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address: Merging ports 0, 2 (address 5'00000). Merging ports 0, 3 (address 5'00000). Merging ports 0, 4 (address 5'00000). Merging ports 0, 5 (address 5'00000). Merging ports 1, 6 (address 5'10000). Merging ports 1, 9 (address 5'10000). Merging ports 1, 10 (address 5'10000). Merging ports 1, 11 (address 5'10000). Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address: Merging ports 1, 2 (address 5'10000). Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address: Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address: Merging ports 0, 1 (address 5'11111). Merging ports 0, 2 (address 5'11110). Merging ports 0, 3 (address 5'11100). Merging ports 0, 4 (address 5'11100). Merging ports 0, 5 (address 5'11000). Merging ports 0, 6 (address 5'11000). Merging ports 0, 7 (address 5'11000). Merging ports 0, 8 (address 5'11000). Merging ports 0, 9 (address 5'10000). Merging ports 0, 10 (address 5'10000). Merging ports 0, 11 (address 5'10000). Merging ports 0, 12 (address 5'10000). Merging ports 0, 13 (address 5'10000). Merging ports 0, 14 (address 5'10000). Merging ports 0, 15 (address 5'10000). Merging ports 0, 16 (address 5'10000). Merging ports 18, 19 (address 5'01101). Merging ports 20, 21 (address 5'01011). Merging ports 20, 22 (address 5'01010). Merging ports 20, 23 (address 5'01000). Merging ports 24, 25 (address 5'00111). Merging ports 24, 26 (address 5'00110). Merging ports 24, 27 (address 5'00100). Merging ports 24, 28 (address 5'00100). Merging ports 24, 29 (address 5'00000). Merging ports 24, 30 (address 5'00000). Merging ports 24, 31 (address 5'00000). Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address: Merging ports 1, 2 (address 5'01110). Merging ports 1, 3 (address 5'01100). Merging ports 1, 4 (address 5'01000). Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address: Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address: Merging ports 0, 1 (address 5'00000). Merging ports 0, 2 (address 5'00000). Merging ports 0, 3 (address 5'00000). Merging ports 0, 4 (address 5'00000). Merging ports 0, 5 (address 5'00000). Merging ports 0, 6 (address 5'00000). Merging ports 0, 7 (address 5'00000). Merging ports 0, 8 (address 5'00000). Merging ports 0, 9 (address 5'00000). Merging ports 0, 10 (address 5'00000). Merging ports 0, 11 (address 5'00000). Merging ports 0, 12 (address 5'00000). Merging ports 0, 13 (address 5'00000). Merging ports 0, 14 (address 5'00000). Merging ports 0, 15 (address 5'00000). Merging ports 0, 16 (address 5'00000). Merging ports 18, 19 (address 5'10010). Merging ports 20, 21 (address 5'10100). Merging ports 20, 22 (address 5'10100). Merging ports 20, 23 (address 5'10100). Merging ports 24, 25 (address 5'11000). Merging ports 24, 26 (address 5'11000). Merging ports 24, 27 (address 5'11000). Merging ports 24, 28 (address 5'11000). Merging ports 24, 29 (address 5'11000). Merging ports 24, 30 (address 5'11000). Merging ports 24, 31 (address 5'11000). Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address: Merging ports 1, 2 (address 5'10001). Merging ports 1, 3 (address 5'10000). Merging ports 1, 4 (address 5'10000). Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address: Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address: Merging ports 0, 1 (address 5'11111). Merging ports 0, 2 (address 5'11110). Merging ports 0, 3 (address 5'11100). Merging ports 0, 4 (address 5'11100). Merging ports 0, 5 (address 5'11000). Merging ports 0, 6 (address 5'11000). Merging ports 0, 7 (address 5'11000). Merging ports 0, 8 (address 5'11000). Merging ports 0, 9 (address 5'10000). Merging ports 0, 10 (address 5'10000). Merging ports 0, 11 (address 5'10000). Merging ports 0, 12 (address 5'10000). Merging ports 0, 13 (address 5'10000). Merging ports 0, 14 (address 5'10000). Merging ports 0, 15 (address 5'10000). Merging ports 0, 16 (address 5'10000). Merging ports 18, 19 (address 5'01101). Merging ports 20, 21 (address 5'01011). Merging ports 20, 22 (address 5'01010). Merging ports 20, 23 (address 5'01000). Merging ports 24, 25 (address 5'00111). Merging ports 24, 26 (address 5'00110). Merging ports 24, 27 (address 5'00100). Merging ports 24, 28 (address 5'00100). Merging ports 24, 29 (address 5'00000). Merging ports 24, 30 (address 5'00000). Merging ports 24, 31 (address 5'00000). Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address: Merging ports 1, 2 (address 5'01110). Merging ports 1, 3 (address 5'01100). Merging ports 1, 4 (address 5'01000). Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address: Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address: Merging ports 0, 1 (address 5'00000). Merging ports 0, 2 (address 5'00000). Merging ports 0, 3 (address 5'00000). Merging ports 0, 4 (address 5'00000). Merging ports 0, 5 (address 5'00000). Merging ports 0, 6 (address 5'00000). Merging ports 0, 7 (address 5'00000). Merging ports 0, 8 (address 5'00000). Merging ports 0, 9 (address 5'00000). Merging ports 0, 10 (address 5'00000). Merging ports 0, 11 (address 5'00000). Merging ports 0, 12 (address 5'00000). Merging ports 0, 13 (address 5'00000). Merging ports 0, 14 (address 5'00000). Merging ports 0, 15 (address 5'00000). Merging ports 0, 16 (address 5'00000). Merging ports 18, 19 (address 5'10010). Merging ports 20, 21 (address 5'10100). Merging ports 20, 22 (address 5'10100). Merging ports 20, 23 (address 5'10100). Merging ports 24, 25 (address 5'11000). Merging ports 24, 26 (address 5'11000). Merging ports 24, 27 (address 5'11000). Merging ports 24, 28 (address 5'11000). Merging ports 24, 29 (address 5'11000). Merging ports 24, 30 (address 5'11000). Merging ports 24, 31 (address 5'11000). Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address: Merging ports 1, 2 (address 5'10001). Merging ports 1, 3 (address 5'10000). Merging ports 1, 4 (address 5'10000). Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address: Consolidating read ports of memory spi_neuron_top.u_flash_slot_manager.cat_offset by address: Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_offset by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_offset by address: Merging ports 1, 2 (address 4'1001). Merging ports 1, 3 (address 4'1000). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_offset by address: Consolidating read ports of memory spi_neuron_top.u_flash_slot_manager.cat_length by address: Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_length by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_length by address: Merging ports 1, 2 (address 4'1001). Merging ports 1, 3 (address 4'1000). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_length by address: Consolidating read ports of memory spi_neuron_top.u_flash_slot_manager.cat_type by address: Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_type by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_type by address: Merging ports 1, 2 (address 4'1001). Merging ports 1, 3 (address 4'1000). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_type by address: Consolidating read ports of memory spi_neuron_top.u_flash_slot_manager.cat_valid by address: Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_valid by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_valid by address: Merging ports 1, 2 (address 4'1001). Merging ports 1, 3 (address 4'1000). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_valid by address: Consolidating read ports of memory spi_neuron_top.u_flash_slot_manager.cat_crc by address: Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_crc by address: Merging ports 0, 1 (address 4'0000). Merging ports 0, 2 (address 4'0000). Merging ports 0, 3 (address 4'0000). Merging ports 0, 4 (address 4'0000). Merging ports 0, 5 (address 4'0000). Merging ports 0, 6 (address 4'0000). Merging ports 0, 7 (address 4'0000). Merging ports 0, 8 (address 4'0000). Merging ports 10, 11 (address 4'1010). Merging ports 12, 13 (address 4'1100). Merging ports 12, 14 (address 4'1100). Merging ports 12, 15 (address 4'1100). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_crc by address: Merging ports 1, 2 (address 4'1001). Merging ports 1, 3 (address 4'1000). Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_crc by address: Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg using sat-based resource sharing: Checking group clocked with posedge \clk, width 8: ports 0, 1. Common input cone for all EN signals: 5 cells. Size of unconstrained SAT problem: 42 variables, 115 clauses Merging port 1 into port 0. Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem using sat-based resource sharing: Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem using sat-based resource sharing: Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_offset using sat-based resource sharing: Checking group clocked with posedge \clk, width 24: ports 2, 3. Common input cone for all EN signals: 12 cells. Size of unconstrained SAT problem: 111 variables, 270 clauses Merging port 3 into port 2. Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_length using sat-based resource sharing: Checking group clocked with posedge \clk, width 24: ports 2, 3, 4. Common input cone for all EN signals: 19 cells. Size of unconstrained SAT problem: 171 variables, 424 clauses Merging port 3 into port 2. Merging port 4 into port 2. Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_type using sat-based resource sharing: Checking group clocked with posedge \clk, width 8: ports 2, 3. Common input cone for all EN signals: 12 cells. Size of unconstrained SAT problem: 111 variables, 270 clauses Merging port 3 into port 2. Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_valid using sat-based resource sharing: Checking group clocked with posedge \clk, width 1: ports 2, 3, 4. Common input cone for all EN signals: 19 cells. Size of unconstrained SAT problem: 171 variables, 424 clauses Merging port 3 into port 2. Merging port 4 into port 2. Consolidating write ports of memory spi_neuron_top.u_flash_slot_manager.cat_crc using sat-based resource sharing: Checking group clocked with posedge \clk, width 32: ports 2, 3, 4. Common input cone for all EN signals: 19 cells. Size of unconstrained SAT problem: 171 variables, 424 clauses Merging port 3 into port 2. Merging port 4 into port 2. 20.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 20.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 1 unused cells and 108 unused wires. 20.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). 20.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). using FF mapping for memory spi_neuron_top.u_flash_slot_manager.cat_length using FF mapping for memory spi_neuron_top.u_flash_slot_manager.cat_type using FF mapping for memory spi_neuron_top.u_flash_slot_manager.cat_valid using FF mapping for memory spi_neuron_top.u_flash_slot_manager.cat_crc using FF mapping for memory spi_neuron_top.u_neuron_memory.y_reg mapping memory spi_neuron_top.u_graph_engine.u_act_buffer.mem via $__DP16KD_ using FF mapping for memory spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627 using FF mapping for memory spi_neuron_top.u_graph_engine.x_mem using FF mapping for memory spi_neuron_top.u_graph_engine.w_mem using FF mapping for memory spi_neuron_top.u_neuron_memory.x_mem using FF mapping for memory spi_neuron_top.u_neuron_memory.w_mem using FF mapping for memory spi_neuron_top.u_flash_slot_manager.cat_offset 20.30. Executing TECHMAP pass (map to technology primitives). 20.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 20.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 20.30.3. Continuing TECHMAP pass. Using template $paramod$c4aea9a221b3d95ca47d9df3d018cdac65e6baac$__DP16KD_ for cells of type $__DP16KD_. No more expansions possible. 20.31. Executing OPT pass (performing simple optimizations). 20.31.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.31.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2199 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2175 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 2161 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 38 cells. 20.31.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $auto$ff.cc:337:slice$13307 ($sdffe) from module spi_neuron_top (D = $flatten\u_flash_slot_manager.\u_fce.$procmux$2145_Y [11:0], Q = \u_flash_slot_manager.u_fce.erase_addr [11:0]). Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$15550 ($dffe) from module spi_neuron_top. 20.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 722 unused wires. 20.31.5. Rerunning OPT passes. (Removed registers in this run.) 20.31.6. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.31.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2158 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.31.8. Executing OPT_DFF pass (perform DFF optimizations). 20.31.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 6 unused wires. 20.31.10. Finished fast OPT passes. 20.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \u_neuron_memory.y_reg in module \spi_neuron_top: created 1 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 0 $mux cells. write interface: 1 write mux blocks. Mapping memory \u_flash_slot_manager.cat_crc in module \spi_neuron_top: created 16 $dff cells and 0 static cells of width 32. Extracted addr FF from read port 0 of spi_neuron_top.u_flash_slot_manager.cat_crc: $\u_flash_slot_manager.cat_crc$rdreg[0] Extracted addr FF from read port 1 of spi_neuron_top.u_flash_slot_manager.cat_crc: $\u_flash_slot_manager.cat_crc$rdreg[1] Extracted addr FF from read port 2 of spi_neuron_top.u_flash_slot_manager.cat_crc: $\u_flash_slot_manager.cat_crc$rdreg[2] read interface: 3 $dff and 45 $mux cells. write interface: 48 write mux blocks. Mapping memory \u_flash_slot_manager.cat_type in module \spi_neuron_top: created 16 $dff cells and 0 static cells of width 8. Extracted addr FF from read port 0 of spi_neuron_top.u_flash_slot_manager.cat_type: $\u_flash_slot_manager.cat_type$rdreg[0] Extracted addr FF from read port 1 of spi_neuron_top.u_flash_slot_manager.cat_type: $\u_flash_slot_manager.cat_type$rdreg[1] read interface: 2 $dff and 30 $mux cells. write interface: 48 write mux blocks. Mapping memory \u_flash_slot_manager.cat_valid in module \spi_neuron_top: created 16 $dff cells and 0 static cells of width 1. Extracted addr FF from read port 0 of spi_neuron_top.u_flash_slot_manager.cat_valid: $\u_flash_slot_manager.cat_valid$rdreg[0] Extracted addr FF from read port 1 of spi_neuron_top.u_flash_slot_manager.cat_valid: $\u_flash_slot_manager.cat_valid$rdreg[1] Extracted addr FF from read port 2 of spi_neuron_top.u_flash_slot_manager.cat_valid: $\u_flash_slot_manager.cat_valid$rdreg[2] read interface: 3 $dff and 45 $mux cells. write interface: 48 write mux blocks. Mapping memory \u_flash_slot_manager.cat_length in module \spi_neuron_top: created 16 $dff cells and 0 static cells of width 24. Extracted addr FF from read port 0 of spi_neuron_top.u_flash_slot_manager.cat_length: $\u_flash_slot_manager.cat_length$rdreg[0] Extracted addr FF from read port 1 of spi_neuron_top.u_flash_slot_manager.cat_length: $\u_flash_slot_manager.cat_length$rdreg[1] Extracted addr FF from read port 2 of spi_neuron_top.u_flash_slot_manager.cat_length: $\u_flash_slot_manager.cat_length$rdreg[2] read interface: 3 $dff and 45 $mux cells. write interface: 48 write mux blocks. Mapping memory $flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627 in module \spi_neuron_top: created 16 $dff cells and 0 static cells of width 6. Extracted data FF from read port 0 of spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627: $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdreg[0] read interface: 1 $dff and 15 $mux cells. write interface: 0 write mux blocks. Mapping memory \u_graph_engine.x_mem in module \spi_neuron_top: created 32 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 1 $mux cells. write interface: 96 write mux blocks. Mapping memory \u_graph_engine.w_mem in module \spi_neuron_top: created 32 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 1 $mux cells. write interface: 96 write mux blocks. Mapping memory \u_neuron_memory.x_mem in module \spi_neuron_top: created 32 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 0 $mux cells. write interface: 32 write mux blocks. Mapping memory \u_neuron_memory.w_mem in module \spi_neuron_top: created 32 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 31 $mux cells. write interface: 32 write mux blocks. Mapping memory \u_flash_slot_manager.cat_offset in module \spi_neuron_top: created 16 $dff cells and 0 static cells of width 24. Extracted addr FF from read port 0 of spi_neuron_top.u_flash_slot_manager.cat_offset: $\u_flash_slot_manager.cat_offset$rdreg[0] Extracted addr FF from read port 1 of spi_neuron_top.u_flash_slot_manager.cat_offset: $\u_flash_slot_manager.cat_offset$rdreg[1] Extracted addr FF from read port 2 of spi_neuron_top.u_flash_slot_manager.cat_offset: $\u_flash_slot_manager.cat_offset$rdreg[2] read interface: 3 $dff and 45 $mux cells. write interface: 48 write mux blocks. 20.33. Executing OPT pass (performing simple optimizations). 20.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 3315 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3225 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 90 cells. 20.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$15518: $auto$rtlil.cc:3271:ReduceOr$15480 -> 1'1 Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$15478: $auto$rtlil.cc:3271:ReduceOr$15472 -> 1'1 Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$15502: $auto$rtlil.cc:3271:ReduceOr$15496 -> 1'1 Analyzing evaluation results. Removed 0 multiplexer ports. 20.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$16053: { $auto$opt_dff.cc:319:make_patterns_logic$13179 $auto$opt_dff.cc:319:make_patterns_logic$13181 $auto$opt_dff.cc:319:make_patterns_logic$13185 $auto$opt_dff.cc:319:make_patterns_logic$13187 $auto$opt_dff.cc:319:make_patterns_logic$13280 $auto$opt_dff.cc:319:make_patterns_logic$13308 $auto$opt_dff.cc:319:make_patterns_logic$13310 $auto$opt_dff.cc:319:make_patterns_logic$13318 $auto$opt_dff.cc:319:make_patterns_logic$16050 } Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][3][5]$17622: Old ports: A=6'000001, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$b$17603 New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$b$17603 [0] New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$b$17603 [5:1] = 5'00000 Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][3][4]$17619: Old ports: A=6'010000, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$a$17602 New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$a$17602 [4] New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$a$17602 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$a$17602 [3:0] } = 5'00000 Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][3][3]$17616: Old ports: A=6'000000, B=6'000001, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][1]$b$17600 New ports: A=1'0, B=1'1, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][1]$b$17600 [0] New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][1]$b$17600 [5:1] = 5'00000 Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][3][1]$17610: Old ports: A=6'100000, B=6'000001, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$b$17597 New ports: A=2'10, B=2'01, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$b$17597 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$b$17597 [0] } New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$b$17597 [4:1] = 4'0000 Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][3][0]$17607: Old ports: A=6'010111, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596 New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596 [0] New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596 [5:1] = { 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596 [0] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596 [0] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596 [0] } New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8790: $auto$opt_reduce.cc:137:opt_pmux$19602 New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8808: { $auto$opt_reduce.cc:137:opt_pmux$19606 $auto$opt_reduce.cc:137:opt_pmux$19604 } Consolidated identical input bits for $mux cell $flatten\u_psram_ctrl.$ternary$rtl/psram_controller.v:377$266: Old ports: A=8'11110000, B=8'00000000, Y=$auto$wreduce.cc:514:run$14545 [7:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:514:run$14545 [4] New connections: { $auto$wreduce.cc:514:run$14545 [7:5] $auto$wreduce.cc:514:run$14545 [3:0] } = { $auto$wreduce.cc:514:run$14545 [4] $auto$wreduce.cc:514:run$14545 [4] $auto$wreduce.cc:514:run$14545 [4] 4'0000 } Consolidated identical input bits for $pmux cell $flatten\u_neuron_memory.$procmux$9192: Old ports: A=1'0, B=3'000, Y=$flatten\u_neuron_memory.$procmux$9192_Y New connections: $flatten\u_neuron_memory.$procmux$9192_Y = 1'0 Consolidated identical input bits for $mux cell $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390: Old ports: A=8'01111111, B=8'10000000, Y=$flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y New ports: A=2'01, B=2'10, Y={ $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [7] $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] } New connections: $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [6:1] = { $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] } New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8869: $auto$opt_reduce.cc:137:opt_pmux$19608 New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8637: $auto$opt_reduce.cc:137:opt_pmux$19610 New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$9279: { \u_neuron_memory.state [2] \u_neuron_memory.state [3] } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$10341: { \u_psram_ctrl.state [1] $auto$opt_reduce.cc:137:opt_pmux$19612 } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$10306: { $auto$opt_reduce.cc:137:opt_pmux$19614 \u_psram_ctrl.state [5] \u_psram_ctrl.state [3] \u_psram_ctrl.state [4] } New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$7808: \u_layer_sequencer.state [2] New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$10061: { \u_psram_ctrl.state [0] \u_psram_ctrl.state [3] \u_psram_ctrl.state [7] } New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$9344: \u_neuron_memory.state [0] New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7088: $flatten\u_flash_slot_manager.$procmux$6846_CMP New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7123: $auto$opt_reduce.cc:137:opt_pmux$11119 New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7275: $flatten\u_flash_slot_manager.$procmux$6858_CMP New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8602: { $auto$opt_reduce.cc:137:opt_pmux$19616 \u_graph_engine.state [2] } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7304: { $flatten\u_flash_slot_manager.$procmux$6858_CMP $auto$opt_reduce.cc:137:opt_pmux$19618 } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7334: { $auto$opt_reduce.cc:137:opt_pmux$19620 $auto$opt_reduce.cc:137:opt_pmux$11073 } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$7357: Old ports: A=3'011, B=3'111, Y=$auto$wreduce.cc:514:run$14518 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:514:run$14518 [2] New connections: $auto$wreduce.cc:514:run$14518 [1:0] = 2'11 Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$7359: Old ports: A=4'1111, B={ 1'1 $auto$wreduce.cc:514:run$14518 [2:0] }, Y=$flatten\u_flash_slot_manager.$procmux$7359_Y New ports: A=3'111, B=$auto$wreduce.cc:514:run$14518 [2:0], Y=$flatten\u_flash_slot_manager.$procmux$7359_Y [2:0] New connections: $flatten\u_flash_slot_manager.$procmux$7359_Y [3] = 1'1 Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$7368: Old ports: A=4'0101, B=4'1000, Y=$flatten\u_flash_slot_manager.$procmux$7368_Y New ports: A=2'01, B=2'10, Y={ $flatten\u_flash_slot_manager.$procmux$7368_Y [3] $flatten\u_flash_slot_manager.$procmux$7368_Y [0] } New connections: $flatten\u_flash_slot_manager.$procmux$7368_Y [2:1] = { $flatten\u_flash_slot_manager.$procmux$7368_Y [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$7376: Old ports: A=4'0011, B=4'1111, Y=$flatten\u_flash_slot_manager.$procmux$7376_Y New ports: A=1'0, B=1'1, Y=$flatten\u_flash_slot_manager.$procmux$7376_Y [2] New connections: { $flatten\u_flash_slot_manager.$procmux$7376_Y [3] $flatten\u_flash_slot_manager.$procmux$7376_Y [1:0] } = { $flatten\u_flash_slot_manager.$procmux$7376_Y [2] 2'11 } Consolidated identical input bits for $pmux cell $flatten\u_flash_slot_manager.$procmux$7387: Old ports: A=4'1010, B=12'101001010010, Y=$flatten\u_flash_slot_manager.$procmux$7387_Y New ports: A=3'110, B=9'110001010, Y={ $flatten\u_flash_slot_manager.$procmux$7387_Y [3] $flatten\u_flash_slot_manager.$procmux$7387_Y [1:0] } New connections: $flatten\u_flash_slot_manager.$procmux$7387_Y [2] = $flatten\u_flash_slot_manager.$procmux$7387_Y [0] New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7387: { $flatten\u_flash_slot_manager.$procmux$6858_CMP $flatten\u_flash_slot_manager.$4$memwr$\cat_crc$rtl/flash_slot_manager.v:378$847_EN[31:0]$1205 [0] } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.$procmux$7412: $auto$opt_reduce.cc:137:opt_pmux$19622 New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8660: $auto$opt_reduce.cc:137:opt_pmux$19624 New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9908: \u_psram_ctrl.state [4] New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9880: $auto$opt_reduce.cc:137:opt_pmux$19626 New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$9843: \u_psram_ctrl.state [6] Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:227$1537: Old ports: A=6'001000, B=6'100000, Y=$flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:227$1537_Y New ports: A=2'01, B=2'10, Y={ $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:227$1537_Y [5] $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:227$1537_Y [3] } New connections: { $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:227$1537_Y [4] $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$ternary$rtl/spi_flash_master.v:227$1537_Y [2:0] } = 4'0000 New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1756: { \u_flash_slot_manager.u_fce.u_spi_flash_master.state [1] \u_flash_slot_manager.u_fce.u_spi_flash_master.state [2] } New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.\u_spi_flash_master.$procmux$1817: $auto$opt_reduce.cc:137:opt_pmux$19628 Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390: Old ports: A=8'01111111, B=8'10000000, Y=$flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y New ports: A=2'01, B=2'10, Y={ $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [7] $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] } New connections: $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [6:1] = { $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$rtl/neuron_parallel.v:189$1390_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2475: Old ports: A={ 2'00 $auto$wreduce.cc:514:run$14521 [2:0] }, B=5'00101, Y=$flatten\u_flash_slot_manager.\u_fce.$procmux$2475_Y New ports: A=$auto$wreduce.cc:514:run$14521 [2:0], B=3'101, Y=$flatten\u_flash_slot_manager.\u_fce.$procmux$2475_Y [2:0] New connections: $flatten\u_flash_slot_manager.\u_fce.$procmux$2475_Y [4:3] = 2'00 Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2466: Old ports: A=3'101, B=3'001, Y=$auto$wreduce.cc:514:run$14521 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:514:run$14521 [2] New connections: $auto$wreduce.cc:514:run$14521 [1:0] = 2'01 Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2461: Old ports: A={ 2'00 $auto$wreduce.cc:514:run$14522 [2:0] }, B=5'00011, Y=$flatten\u_flash_slot_manager.\u_fce.$procmux$2461_Y New ports: A=$auto$wreduce.cc:514:run$14522 [2:0], B=3'011, Y=$flatten\u_flash_slot_manager.\u_fce.$procmux$2461_Y [2:0] New connections: $flatten\u_flash_slot_manager.\u_fce.$procmux$2461_Y [4:3] = 2'00 Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2456: Old ports: A=3'001, B=3'100, Y=$auto$wreduce.cc:514:run$14522 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:514:run$14522 [2] $auto$wreduce.cc:514:run$14522 [0] } New connections: $auto$wreduce.cc:514:run$14522 [1] = 1'0 New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2424: { $flatten\u_flash_slot_manager.\u_fce.$procmux$2146_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$1972_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$1983_CMP $auto$opt_reduce.cc:137:opt_pmux$19632 $flatten\u_flash_slot_manager.\u_fce.$procmux$2212_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$2442_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$1985_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$2215_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$1986_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$2450_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$1987_CMP $auto$opt_reduce.cc:137:opt_pmux$19630 $flatten\u_flash_slot_manager.\u_fce.$procmux$2463_CMP $flatten\u_flash_slot_manager.\u_fce.$procmux$2018_CMP } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2411: Old ports: A=4'1001, B=4'0100, Y=$auto$wreduce.cc:514:run$14526 [3:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:514:run$14526 [2] $auto$wreduce.cc:514:run$14526 [0] } New connections: { $auto$wreduce.cc:514:run$14526 [3] $auto$wreduce.cc:514:run$14526 [1] } = { $auto$wreduce.cc:514:run$14526 [0] 1'0 } Consolidated identical input bits for $pmux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2399: Old ports: A=8'00000101, B=33955843, Y=$flatten\u_flash_slot_manager.\u_fce.$procmux$2399_Y New ports: A=4'0101, B=16'0010011010000011, Y={ $flatten\u_flash_slot_manager.\u_fce.$procmux$2399_Y [5] $flatten\u_flash_slot_manager.\u_fce.$procmux$2399_Y [2:0] } New connections: { $flatten\u_flash_slot_manager.\u_fce.$procmux$2399_Y [7:6] $flatten\u_flash_slot_manager.\u_fce.$procmux$2399_Y [4:3] } = 4'0000 New ctrl vector for $pmux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2211: $flatten\u_flash_slot_manager.\u_fce.$procmux$2212_CMP Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$ternary$rtl/flash_copy_engine.v:586$1498: Old ports: A=4'1001, B=4'0100, Y=$auto$wreduce.cc:514:run$14528 [3:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:514:run$14528 [2] $auto$wreduce.cc:514:run$14528 [0] } New connections: { $auto$wreduce.cc:514:run$14528 [3] $auto$wreduce.cc:514:run$14528 [1] } = { $auto$wreduce.cc:514:run$14528 [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_crc32.$procmux$2576: Old ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [31:1] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16037 [12:11] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [29] $auto$opt_expr.cc:206:group_cell_inputs$16037 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [26] $auto$opt_expr.cc:206:group_cell_inputs$16037 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [23] $auto$opt_expr.cc:206:group_cell_inputs$16037 [6:4] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [19:17] $auto$opt_expr.cc:206:group_cell_inputs$16037 [3] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [15:11] $auto$opt_expr.cc:206:group_cell_inputs$16037 [2:1] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [8:7] $auto$opt_expr.cc:206:group_cell_inputs$16037 [0] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [5:1] }, Y=\u_flash_slot_manager.crc_next New ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [31:30] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [28:27] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [25:24] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [22:20] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [16] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [6] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16037 }, Y={ \u_flash_slot_manager.crc_next [31:29] \u_flash_slot_manager.crc_next [27:26] \u_flash_slot_manager.crc_next [24:23] \u_flash_slot_manager.crc_next [21:19] \u_flash_slot_manager.crc_next [15] \u_flash_slot_manager.crc_next [9:8] \u_flash_slot_manager.crc_next [5] } New connections: { \u_flash_slot_manager.crc_next [28] \u_flash_slot_manager.crc_next [25] \u_flash_slot_manager.crc_next [22] \u_flash_slot_manager.crc_next [18:16] \u_flash_slot_manager.crc_next [14:10] \u_flash_slot_manager.crc_next [7:6] \u_flash_slot_manager.crc_next [4:0] } = { $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [29] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [26] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [23] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [19:17] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [15:11] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [5:1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_crc32.$procmux$2579: Old ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [31:1] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16033 [12:11] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [29] $auto$opt_expr.cc:206:group_cell_inputs$16033 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [26] $auto$opt_expr.cc:206:group_cell_inputs$16033 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [23] $auto$opt_expr.cc:206:group_cell_inputs$16033 [6:4] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [19:17] $auto$opt_expr.cc:206:group_cell_inputs$16033 [3] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [15:11] $auto$opt_expr.cc:206:group_cell_inputs$16033 [2:1] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [8:7] $auto$opt_expr.cc:206:group_cell_inputs$16033 [0] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [5:1] }, Y=$flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 New ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [31:30] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [28:27] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [25:24] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [22:20] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [16] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [6] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16033 }, Y={ $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [31:29] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [27:26] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [24:23] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [21:19] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [15] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [9:8] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [5] } New connections: { $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [28] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [25] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [22] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [18:16] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [14:10] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [7:6] $flatten\u_flash_slot_manager.\u_crc32.$7\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1445 [4:0] } = { $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [29] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [26] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [23] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [19:17] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [15:11] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [5:1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_crc32.$procmux$2582: Old ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [31:1] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16029 [12:11] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [29] $auto$opt_expr.cc:206:group_cell_inputs$16029 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [26] $auto$opt_expr.cc:206:group_cell_inputs$16029 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [23] $auto$opt_expr.cc:206:group_cell_inputs$16029 [6:4] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [19:17] $auto$opt_expr.cc:206:group_cell_inputs$16029 [3] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [15:11] $auto$opt_expr.cc:206:group_cell_inputs$16029 [2:1] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [8:7] $auto$opt_expr.cc:206:group_cell_inputs$16029 [0] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [5:1] }, Y=$flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 New ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [31:30] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [28:27] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [25:24] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [22:20] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [16] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [6] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16029 }, Y={ $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [31:29] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [27:26] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [24:23] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [21:19] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [15] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [9:8] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [5] } New connections: { $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [28] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [25] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [22] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [18:16] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [14:10] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [7:6] $flatten\u_flash_slot_manager.\u_crc32.$6\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1441 [4:0] } = { $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [29] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [26] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [23] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [19:17] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [15:11] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [5:1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_crc32.$procmux$2585: Old ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [31:1] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16025 [12:11] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [29] $auto$opt_expr.cc:206:group_cell_inputs$16025 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [26] $auto$opt_expr.cc:206:group_cell_inputs$16025 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [23] $auto$opt_expr.cc:206:group_cell_inputs$16025 [6:4] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [19:17] $auto$opt_expr.cc:206:group_cell_inputs$16025 [3] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [15:11] $auto$opt_expr.cc:206:group_cell_inputs$16025 [2:1] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [8:7] $auto$opt_expr.cc:206:group_cell_inputs$16025 [0] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [5:1] }, Y=$flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 New ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [31:30] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [28:27] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [25:24] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [22:20] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [16] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [6] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16025 }, Y={ $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [31:29] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [27:26] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [24:23] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [21:19] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [15] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [9:8] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [5] } New connections: { $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [28] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [25] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [22] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [18:16] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [14:10] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [7:6] $flatten\u_flash_slot_manager.\u_crc32.$5\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1437 [4:0] } = { $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [29] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [26] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [23] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [19:17] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [15:11] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [5:1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_crc32.$procmux$2588: Old ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [31:1] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16021 [12:11] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [29] $auto$opt_expr.cc:206:group_cell_inputs$16021 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [26] $auto$opt_expr.cc:206:group_cell_inputs$16021 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [23] $auto$opt_expr.cc:206:group_cell_inputs$16021 [6:4] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [19:17] $auto$opt_expr.cc:206:group_cell_inputs$16021 [3] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [15:11] $auto$opt_expr.cc:206:group_cell_inputs$16021 [2:1] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [8:7] $auto$opt_expr.cc:206:group_cell_inputs$16021 [0] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [5:1] }, Y=$flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 New ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [31:30] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [28:27] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [25:24] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [22:20] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [16] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [6] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16021 }, Y={ $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [31:29] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [27:26] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [24:23] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [21:19] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [15] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [9:8] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [5] } New connections: { $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [28] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [25] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [22] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [18:16] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [14:10] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [7:6] $flatten\u_flash_slot_manager.\u_crc32.$4\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1433 [4:0] } = { $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [29] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [26] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [23] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [19:17] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [15:11] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [5:1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_crc32.$procmux$2591: Old ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [31:1] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16017 [12:11] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [29] $auto$opt_expr.cc:206:group_cell_inputs$16017 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [26] $auto$opt_expr.cc:206:group_cell_inputs$16017 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [23] $auto$opt_expr.cc:206:group_cell_inputs$16017 [6:4] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [19:17] $auto$opt_expr.cc:206:group_cell_inputs$16017 [3] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [15:11] $auto$opt_expr.cc:206:group_cell_inputs$16017 [2:1] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [8:7] $auto$opt_expr.cc:206:group_cell_inputs$16017 [0] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [5:1] }, Y=$flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 New ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [31:30] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [28:27] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [25:24] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [22:20] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [16] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [6] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16017 }, Y={ $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [31:29] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [27:26] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [24:23] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [21:19] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [15] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [9:8] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [5] } New connections: { $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [28] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [25] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [22] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [18:16] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [14:10] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [7:6] $flatten\u_flash_slot_manager.\u_crc32.$3\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1429 [4:0] } = { $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [29] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [26] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [23] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [19:17] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [15:11] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [5:1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_crc32.$procmux$2594: Old ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [31:1] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16013 [12:11] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [29] $auto$opt_expr.cc:206:group_cell_inputs$16013 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [26] $auto$opt_expr.cc:206:group_cell_inputs$16013 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [23] $auto$opt_expr.cc:206:group_cell_inputs$16013 [6:4] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [19:17] $auto$opt_expr.cc:206:group_cell_inputs$16013 [3] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [15:11] $auto$opt_expr.cc:206:group_cell_inputs$16013 [2:1] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [8:7] $auto$opt_expr.cc:206:group_cell_inputs$16013 [0] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [5:1] }, Y=$flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 New ports: A={ 1'0 $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [31:30] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [28:27] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [25:24] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [22:20] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [16] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [10:9] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [6] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16013 }, Y={ $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [31:29] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [27:26] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [24:23] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [21:19] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [15] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [9:8] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [5] } New connections: { $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [28] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [25] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [22] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [18:16] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [14:10] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [7:6] $flatten\u_flash_slot_manager.\u_crc32.$2\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1425 [4:0] } = { $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [29] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [26] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [23] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [19:17] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [15:11] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [8:7] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [5:1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_crc32.$procmux$2597: Old ports: A={ 1'0 \u_flash_slot_manager.crc_acc [31:8] $auto$opt_expr.cc:206:group_cell_inputs$16006 [7:1] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16009 [12:11] \u_flash_slot_manager.crc_acc [29] $auto$opt_expr.cc:206:group_cell_inputs$16009 [10:9] \u_flash_slot_manager.crc_acc [26] $auto$opt_expr.cc:206:group_cell_inputs$16009 [8:7] \u_flash_slot_manager.crc_acc [23] $auto$opt_expr.cc:206:group_cell_inputs$16009 [6:4] \u_flash_slot_manager.crc_acc [19:17] $auto$opt_expr.cc:206:group_cell_inputs$16009 [3] \u_flash_slot_manager.crc_acc [15:11] $auto$opt_expr.cc:206:group_cell_inputs$16009 [2:1] \u_flash_slot_manager.crc_acc [8] $auto$opt_expr.cc:206:group_cell_inputs$16006 [7] $auto$opt_expr.cc:206:group_cell_inputs$16009 [0] $auto$opt_expr.cc:206:group_cell_inputs$16006 [5:1] }, Y=$flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 New ports: A={ 1'0 \u_flash_slot_manager.crc_acc [31:30] \u_flash_slot_manager.crc_acc [28:27] \u_flash_slot_manager.crc_acc [25:24] \u_flash_slot_manager.crc_acc [22:20] \u_flash_slot_manager.crc_acc [16] \u_flash_slot_manager.crc_acc [10:9] $auto$opt_expr.cc:206:group_cell_inputs$16006 [6] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$16009 }, Y={ $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [31:29] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [27:26] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [24:23] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [21:19] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [15] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [9:8] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [5] } New connections: { $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [28] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [25] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [22] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [18:16] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [14:10] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [7:6] $flatten\u_flash_slot_manager.\u_crc32.$1\next_crc$func$rtl/crc32.v:48$1412.c[31:0]$1421 [4:0] } = { \u_flash_slot_manager.crc_acc [29] \u_flash_slot_manager.crc_acc [26] \u_flash_slot_manager.crc_acc [23] \u_flash_slot_manager.crc_acc [19:17] \u_flash_slot_manager.crc_acc [15:11] \u_flash_slot_manager.crc_acc [8] $auto$opt_expr.cc:206:group_cell_inputs$16006 [7] $auto$opt_expr.cc:206:group_cell_inputs$16006 [5:1] } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3198: \u_spi_engine.state [5] New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3257: $auto$opt_reduce.cc:137:opt_pmux$19634 New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3285: $auto$opt_reduce.cc:137:opt_pmux$19636 New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3334: \u_spi_engine.state [4] Consolidated identical input bits for $mux cell $flatten\u_psram_ctrl.$ternary$rtl/psram_controller.v:516$277: Old ports: A=3'110, B=3'010, Y=$auto$wreduce.cc:514:run$14543 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:514:run$14543 [2] New connections: $auto$wreduce.cc:514:run$14543 [1:0] = 2'10 Consolidated identical input bits for $mux cell $flatten\u_spi_engine.$procmux$4379: Old ports: A={ 2'00 $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$1626 [5:0] }, B=8'00000000, Y=$flatten\u_spi_engine.$4\tx_byte_comb[7:0] New ports: A=$flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$1626 [5:0], B=6'000000, Y=$flatten\u_spi_engine.$4\tx_byte_comb[7:0] [5:0] New connections: $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [7:6] = 2'00 New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$19607: { \u_graph_engine.state [10:9] \u_graph_engine.state [7] } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$19613: { \u_psram_ctrl.state [7:6] \u_psram_ctrl.state [1] } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$19619: { $flatten\u_flash_slot_manager.$procmux$6852_CMP $flatten\u_flash_slot_manager.$procmux$6857_CMP $flatten\u_flash_slot_manager.$procmux$6858_CMP } Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$17601: Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$a$17602, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$b$17603, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$a$17593 New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$a$17602 [4] 1'0 }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][2]$b$17603 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$a$17593 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$a$17593 [0] } New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$a$17593 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$a$17593 [3:1] } = 4'0000 Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][1]$17598: Old ports: A=6'001000, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][1]$b$17600, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591 New ports: A=2'10, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][1]$b$17600 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591 [0] } New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591 [5:4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591 [2:1] } = 4'0000 Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$17595: Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$b$17597, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590 New ports: A={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596 [0] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$a$17596 [0] }, B={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$b$17597 [5] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$b$17597 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590 [1:0] } New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590 [4:2] = { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590 [1] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590 [1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.$procmux$7359: Old ports: A=3'111, B=$auto$wreduce.cc:514:run$14518 [2:0], Y=$flatten\u_flash_slot_manager.$procmux$7359_Y [2:0] New ports: A=1'1, B=$auto$wreduce.cc:514:run$14518 [2], Y=$flatten\u_flash_slot_manager.$procmux$7359_Y [2] New connections: $flatten\u_flash_slot_manager.$procmux$7359_Y [1:0] = 2'11 Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2475: Old ports: A=$auto$wreduce.cc:514:run$14521 [2:0], B=3'101, Y=$flatten\u_flash_slot_manager.\u_fce.$procmux$2475_Y [2:0] New ports: A=$auto$wreduce.cc:514:run$14521 [2], B=1'1, Y=$flatten\u_flash_slot_manager.\u_fce.$procmux$2475_Y [2] New connections: $flatten\u_flash_slot_manager.\u_fce.$procmux$2475_Y [1:0] = 2'01 Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2415: Old ports: A=4'0101, B=$auto$wreduce.cc:514:run$14528 [3:0], Y=$auto$wreduce.cc:514:run$14525 [3:0] New ports: A=3'011, B={ $auto$wreduce.cc:514:run$14528 [0] $auto$wreduce.cc:514:run$14528 [2] $auto$wreduce.cc:514:run$14528 [0] }, Y={ $auto$wreduce.cc:514:run$14525 [3:2] $auto$wreduce.cc:514:run$14525 [0] } New connections: $auto$wreduce.cc:514:run$14525 [1] = 1'0 Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$17592: Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$a$17593, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$b$17588 New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$a$17593 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][1]$a$17593 [0] }, B=2'00, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$b$17588 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$b$17588 [0] } New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$b$17588 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$b$17588 [3:1] } = 4'0000 Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$17589: Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590 [5] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$a$17590 [1:0] }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591 [3] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [1:0] } New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [2] } = { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [1] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [1] } Consolidated identical input bits for $mux cell $flatten\u_flash_slot_manager.\u_fce.$procmux$2417: Old ports: A=$auto$wreduce.cc:514:run$14525 [3:0], B=$auto$wreduce.cc:514:run$14526 [3:0], Y=$auto$wreduce.cc:514:run$14524 [3:0] New ports: A={ $auto$wreduce.cc:514:run$14525 [3:2] $auto$wreduce.cc:514:run$14525 [0] }, B={ $auto$wreduce.cc:514:run$14526 [0] $auto$wreduce.cc:514:run$14526 [2] $auto$wreduce.cc:514:run$14526 [0] }, Y={ $auto$wreduce.cc:514:run$14524 [3:2] $auto$wreduce.cc:514:run$14524 [0] } New connections: $auto$wreduce.cc:514:run$14524 [1] = 1'0 Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$17586: Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$b$17588, Y=$$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdreg[0]$d New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [1] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [1:0] }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$b$17588 [4] 2'00 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$b$17588 [0] }, Y={ $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdreg[0]$d [5:3] $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdreg[0]$d [1:0] } New connections: $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdreg[0]$d [2] = $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdreg[0]$d [1] Optimizing cells in module \spi_neuron_top. Performed a total of 76 changes. 20.33.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 3242 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3236 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 6 cells. 20.33.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $auto$ff.cc:337:slice$13998 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8602_Y, Q = \u_graph_engine.desc_byte_idx). Adding EN signal on $auto$ff.cc:337:slice$14025 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8637_Y, Q = \u_graph_engine.desc_addr). Adding EN signal on $auto$ff.cc:337:slice$14039 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8660_Y, Q = \u_graph_engine.neuron_idx). Adding EN signal on $auto$ff.cc:337:slice$14096 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$8808_Y, Q = \u_graph_engine.busy). Adding SRST signal on $\u_flash_slot_manager.cat_crc$rdreg[0] ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15334, Q = $\u_flash_slot_manager.cat_crc$rdreg[0]$q, rval = 4'0000). Adding SRST signal on $\u_flash_slot_manager.cat_length$rdreg[0] ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15284, Q = $\u_flash_slot_manager.cat_length$rdreg[0]$q, rval = 4'0000). Adding SRST signal on $\u_flash_slot_manager.cat_length$rdreg[1] ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15289, Q = $\u_flash_slot_manager.cat_length$rdreg[1]$q, rval = 4'0000). Adding SRST signal on $\u_flash_slot_manager.cat_length$rdreg[2] ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15279, Q = $\u_flash_slot_manager.cat_length$rdreg[2]$q, rval = 4'0000). Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][2][0]$b$17597 [5], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$1626 [5], rval = 1'0). Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][1][0]$b$17591 [3], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$1626 [3], rval = 1'0). 20.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 4 unused cells and 1080 unused wires. 20.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.33.9. Rerunning OPT passes. (Maybe there is more to do..) 20.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$19641: { $auto$opt_dff.cc:319:make_patterns_logic$13888 $auto$opt_dff.cc:319:make_patterns_logic$13892 $auto$opt_dff.cc:319:make_patterns_logic$13924 $auto$opt_dff.cc:319:make_patterns_logic$14001 $auto$opt_dff.cc:319:make_patterns_logic$14003 $auto$opt_dff.cc:319:make_patterns_logic$14005 $auto$opt_dff.cc:319:make_patterns_logic$14007 $auto$opt_dff.cc:319:make_patterns_logic$14009 $auto$opt_dff.cc:319:make_patterns_logic$14015 $auto$opt_dff.cc:319:make_patterns_logic$19638 } New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$19646: { $auto$opt_dff.cc:319:make_patterns_logic$13888 $auto$opt_dff.cc:319:make_patterns_logic$14007 $auto$opt_dff.cc:319:make_patterns_logic$14015 $auto$opt_dff.cc:319:make_patterns_logic$14026 $auto$opt_dff.cc:319:make_patterns_logic$14028 $auto$opt_dff.cc:319:make_patterns_logic$19643 } New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$19651: { $auto$opt_dff.cc:319:make_patterns_logic$13888 $auto$opt_dff.cc:319:make_patterns_logic$14007 $auto$opt_dff.cc:319:make_patterns_logic$14015 $auto$opt_dff.cc:319:make_patterns_logic$14026 $auto$opt_dff.cc:319:make_patterns_logic$14028 $auto$opt_dff.cc:319:make_patterns_logic$19648 } New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$19656: { $auto$opt_dff.cc:319:make_patterns_logic$13888 $auto$opt_dff.cc:319:make_patterns_logic$13892 $auto$opt_dff.cc:319:make_patterns_logic$13926 $auto$opt_dff.cc:319:make_patterns_logic$14005 $auto$opt_dff.cc:319:make_patterns_logic$14007 $auto$opt_dff.cc:319:make_patterns_logic$14015 $auto$opt_dff.cc:319:make_patterns_logic$14028 $auto$opt_dff.cc:319:make_patterns_logic$14080 $auto$opt_dff.cc:319:make_patterns_logic$14082 $auto$opt_dff.cc:319:make_patterns_logic$14084 $auto$opt_dff.cc:319:make_patterns_logic$14097 $auto$opt_dff.cc:319:make_patterns_logic$14109 $auto$opt_dff.cc:319:make_patterns_logic$19653 } New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8808: $auto$opt_reduce.cc:137:opt_pmux$19740 New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$8602: \u_graph_engine.state [2] New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$19739: { \u_graph_engine.state [11] \u_graph_engine.state [9:8] \u_graph_engine.state [6] \u_graph_engine.state [4] } Optimizing cells in module \spi_neuron_top. Performed a total of 7 changes. 20.33.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 3238 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3235 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3234 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 4 cells. 20.33.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\u_neuron_memory.x_mem[14]$18677 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[14]). Adding EN signal on $memory\u_neuron_memory.y_reg[0]$16055 ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15476, Q = \u_neuron_memory.y_reg[0]). Adding SRST signal on $auto$ff.cc:337:slice$19742 ($dffe) from module spi_neuron_top (D = \u_neuron_memory.u_neuron.y, Q = \u_neuron_memory.y_reg[0], rval = 8'00000000). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[0]$16063 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[0][2][0]$y$16257, Q = \u_flash_slot_manager.cat_crc[0]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[1]$16065 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[1][2][0]$y$16275, Q = \u_flash_slot_manager.cat_crc[1]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[2]$16067 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[2][2][0]$y$16293, Q = \u_flash_slot_manager.cat_crc[2]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[3]$16069 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[3][2][0]$y$16309, Q = \u_flash_slot_manager.cat_crc[3]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[4]$16071 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[4][2][0]$y$16327, Q = \u_flash_slot_manager.cat_crc[4]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[5]$16073 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[5][2][0]$y$16341, Q = \u_flash_slot_manager.cat_crc[5]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[6]$16075 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[6][2][0]$y$16355, Q = \u_flash_slot_manager.cat_crc[6]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[7]$16077 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[7][2][0]$y$16369, Q = \u_flash_slot_manager.cat_crc[7]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[8]$16079 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[8][2][0]$y$16389, Q = \u_flash_slot_manager.cat_crc[8]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[9]$16081 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[9][2][0]$y$16403, Q = \u_flash_slot_manager.cat_crc[9]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[10]$16083 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[10][2][0]$y$16417, Q = \u_flash_slot_manager.cat_crc[10]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[11]$16085 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[11][2][0]$y$16431, Q = \u_flash_slot_manager.cat_crc[11]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[12]$16087 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[12][2][0]$y$16447, Q = \u_flash_slot_manager.cat_crc[12]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[13]$16089 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[13][2][0]$y$16461, Q = \u_flash_slot_manager.cat_crc[13]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[14]$16091 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[14][2][0]$y$16475, Q = \u_flash_slot_manager.cat_crc[14]). Adding EN signal on $memory\u_flash_slot_manager.cat_crc[15]$16093 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_crc$wrmux[15][2][0]$y$16489, Q = \u_flash_slot_manager.cat_crc[15]). Adding EN signal on $memory\u_neuron_memory.x_mem[6]$18661 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[6]). Adding EN signal on $memory\u_neuron_memory.x_mem[5]$18659 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[5]). Adding EN signal on $memory\u_neuron_memory.x_mem[16]$18681 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[16]). Adding EN signal on $memory\u_neuron_memory.x_mem[4]$18657 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[4]). Adding EN signal on $memory\u_neuron_memory.x_mem[17]$18683 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[17]). Adding EN signal on $memory\u_neuron_memory.x_mem[3]$18655 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[3]). Adding EN signal on $memory\u_neuron_memory.x_mem[2]$18653 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[2]). Adding EN signal on $memory\u_neuron_memory.x_mem[1]$18651 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[1]). Adding EN signal on $memory\u_neuron_memory.x_mem[21]$18691 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[21]). Adding EN signal on $memory\u_neuron_memory.x_mem[18]$18685 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[18]). Adding EN signal on $memory\u_neuron_memory.x_mem[0]$18649 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[0]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[0]$16490 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[0][2][0]$y$16637, Q = \u_flash_slot_manager.cat_type[0]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[1]$16492 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[1][2][0]$y$16655, Q = \u_flash_slot_manager.cat_type[1]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[2]$16494 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[2][2][0]$y$16673, Q = \u_flash_slot_manager.cat_type[2]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[3]$16496 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[3][2][0]$y$16689, Q = \u_flash_slot_manager.cat_type[3]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[4]$16498 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[4][2][0]$y$16707, Q = \u_flash_slot_manager.cat_type[4]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[5]$16500 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[5][2][0]$y$16721, Q = \u_flash_slot_manager.cat_type[5]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[6]$16502 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[6][2][0]$y$16735, Q = \u_flash_slot_manager.cat_type[6]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[7]$16504 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[7][2][0]$y$16749, Q = \u_flash_slot_manager.cat_type[7]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[8]$16506 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[8][2][0]$y$16767, Q = \u_flash_slot_manager.cat_type[8]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[9]$16508 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[9][2][0]$y$16781, Q = \u_flash_slot_manager.cat_type[9]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[10]$16510 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[10][2][0]$y$16795, Q = \u_flash_slot_manager.cat_type[10]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[11]$16512 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[11][2][0]$y$16809, Q = \u_flash_slot_manager.cat_type[11]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[12]$16514 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[12][2][0]$y$16825, Q = \u_flash_slot_manager.cat_type[12]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[13]$16516 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[13][2][0]$y$16839, Q = \u_flash_slot_manager.cat_type[13]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[14]$16518 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[14][2][0]$y$16853, Q = \u_flash_slot_manager.cat_type[14]). Adding EN signal on $memory\u_flash_slot_manager.cat_type[15]$16520 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_type$wrmux[15][2][0]$y$16867, Q = \u_flash_slot_manager.cat_type[15]). Adding EN signal on $memory\u_neuron_memory.x_mem[20]$18689 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[20]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[15]$19272 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[15][2][0]$y$19600, Q = \u_flash_slot_manager.cat_offset[15]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[14]$19270 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[14][2][0]$y$19588, Q = \u_flash_slot_manager.cat_offset[14]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[13]$19268 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[13][2][0]$y$19576, Q = \u_flash_slot_manager.cat_offset[13]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[12]$19266 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[12][2][0]$y$19564, Q = \u_flash_slot_manager.cat_offset[12]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[11]$19264 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[11][2][0]$y$19552, Q = \u_flash_slot_manager.cat_offset[11]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[10]$19262 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[10][2][0]$y$19540, Q = \u_flash_slot_manager.cat_offset[10]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[9]$19260 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[9][2][0]$y$19528, Q = \u_flash_slot_manager.cat_offset[9]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[8]$19258 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[8][2][0]$y$19516, Q = \u_flash_slot_manager.cat_offset[8]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[0]$16868 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[0][2][0]$y$17046, Q = \u_flash_slot_manager.cat_valid[0]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[1]$16870 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[1][2][0]$y$17058, Q = \u_flash_slot_manager.cat_valid[1]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[2]$16872 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[2][2][0]$y$17070, Q = \u_flash_slot_manager.cat_valid[2]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[3]$16874 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[3][2][0]$y$17082, Q = \u_flash_slot_manager.cat_valid[3]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[4]$16876 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[4][2][0]$y$17094, Q = \u_flash_slot_manager.cat_valid[4]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[5]$16878 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[5][2][0]$y$17106, Q = \u_flash_slot_manager.cat_valid[5]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[6]$16880 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[6][2][0]$y$17118, Q = \u_flash_slot_manager.cat_valid[6]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[7]$16882 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[7][2][0]$y$17130, Q = \u_flash_slot_manager.cat_valid[7]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[8]$16884 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[8][2][0]$y$17142, Q = \u_flash_slot_manager.cat_valid[8]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[9]$16886 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[9][2][0]$y$17154, Q = \u_flash_slot_manager.cat_valid[9]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[10]$16888 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[10][2][0]$y$17166, Q = \u_flash_slot_manager.cat_valid[10]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[11]$16890 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[11][2][0]$y$17178, Q = \u_flash_slot_manager.cat_valid[11]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[12]$16892 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[12][2][0]$y$17190, Q = \u_flash_slot_manager.cat_valid[12]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[13]$16894 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[13][2][0]$y$17202, Q = \u_flash_slot_manager.cat_valid[13]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[14]$16896 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[14][2][0]$y$17214, Q = \u_flash_slot_manager.cat_valid[14]). Adding EN signal on $memory\u_flash_slot_manager.cat_valid[15]$16898 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_valid$wrmux[15][2][0]$y$17226, Q = \u_flash_slot_manager.cat_valid[15]). Adding EN signal on $memory\u_neuron_memory.x_mem[19]$18687 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[19]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[7]$19256 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[7][2][0]$y$19504, Q = \u_flash_slot_manager.cat_offset[7]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[6]$19254 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[6][2][0]$y$19492, Q = \u_flash_slot_manager.cat_offset[6]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[5]$19252 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[5][2][0]$y$19480, Q = \u_flash_slot_manager.cat_offset[5]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[4]$19250 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[4][2][0]$y$19468, Q = \u_flash_slot_manager.cat_offset[4]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[3]$19248 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[3][2][0]$y$19456, Q = \u_flash_slot_manager.cat_offset[3]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[2]$19246 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[2][2][0]$y$19444, Q = \u_flash_slot_manager.cat_offset[2]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[1]$19244 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[1][2][0]$y$19432, Q = \u_flash_slot_manager.cat_offset[1]). Adding EN signal on $memory\u_flash_slot_manager.cat_offset[0]$19242 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_offset$wrmux[0][2][0]$y$19420, Q = \u_flash_slot_manager.cat_offset[0]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[0]$17227 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[0][2][0]$y$17405, Q = \u_flash_slot_manager.cat_length[0]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[1]$17229 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[1][2][0]$y$17417, Q = \u_flash_slot_manager.cat_length[1]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[2]$17231 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[2][2][0]$y$17429, Q = \u_flash_slot_manager.cat_length[2]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[3]$17233 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[3][2][0]$y$17441, Q = \u_flash_slot_manager.cat_length[3]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[4]$17235 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[4][2][0]$y$17453, Q = \u_flash_slot_manager.cat_length[4]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[5]$17237 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[5][2][0]$y$17465, Q = \u_flash_slot_manager.cat_length[5]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[6]$17239 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[6][2][0]$y$17477, Q = \u_flash_slot_manager.cat_length[6]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[7]$17241 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[7][2][0]$y$17489, Q = \u_flash_slot_manager.cat_length[7]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[8]$17243 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[8][2][0]$y$17501, Q = \u_flash_slot_manager.cat_length[8]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[9]$17245 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[9][2][0]$y$17513, Q = \u_flash_slot_manager.cat_length[9]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[10]$17247 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[10][2][0]$y$17525, Q = \u_flash_slot_manager.cat_length[10]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[11]$17249 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[11][2][0]$y$17537, Q = \u_flash_slot_manager.cat_length[11]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[12]$17251 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[12][2][0]$y$17549, Q = \u_flash_slot_manager.cat_length[12]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[13]$17253 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[13][2][0]$y$17561, Q = \u_flash_slot_manager.cat_length[13]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[14]$17255 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[14][2][0]$y$17573, Q = \u_flash_slot_manager.cat_length[14]). Adding EN signal on $memory\u_flash_slot_manager.cat_length[15]$17257 ($dff) from module spi_neuron_top (D = $memory\u_flash_slot_manager.cat_length$wrmux[15][2][0]$y$17585, Q = \u_flash_slot_manager.cat_length[15]). Adding EN signal on $memory\u_neuron_memory.x_mem[10]$18669 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[10]). Adding EN signal on $memory\u_neuron_memory.x_mem[11]$18671 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[11]). Adding EN signal on $memory\u_neuron_memory.x_mem[13]$18675 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[13]). Adding EN signal on $memory\u_neuron_memory.x_mem[12]$18673 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[12]). Adding EN signal on $memory\u_neuron_memory.x_mem[15]$18679 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[15]). Adding EN signal on $memory\u_neuron_memory.x_mem[9]$18667 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[9]). Adding EN signal on $memory\u_neuron_memory.x_mem[8]$18665 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[8]). Adding EN signal on $memory\u_graph_engine.x_mem[0]$17631 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[0][2][0]$y$17727, Q = \u_graph_engine.x_mem[0]). Adding EN signal on $memory\u_graph_engine.x_mem[1]$17633 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[1][2][0]$y$17745, Q = \u_graph_engine.x_mem[1]). Adding EN signal on $memory\u_graph_engine.x_mem[2]$17635 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[2][2][0]$y$17763, Q = \u_graph_engine.x_mem[2]). Adding EN signal on $memory\u_graph_engine.x_mem[3]$17637 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[3][2][0]$y$17779, Q = \u_graph_engine.x_mem[3]). Adding EN signal on $memory\u_graph_engine.x_mem[4]$17639 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[4][2][0]$y$17797, Q = \u_graph_engine.x_mem[4]). Adding EN signal on $memory\u_graph_engine.x_mem[5]$17641 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[5][2][0]$y$17811, Q = \u_graph_engine.x_mem[5]). Adding EN signal on $memory\u_graph_engine.x_mem[6]$17643 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[6][2][0]$y$17825, Q = \u_graph_engine.x_mem[6]). Adding EN signal on $memory\u_graph_engine.x_mem[7]$17645 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[7][2][0]$y$17839, Q = \u_graph_engine.x_mem[7]). Adding EN signal on $memory\u_graph_engine.x_mem[8]$17647 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[8][2][0]$y$17859, Q = \u_graph_engine.x_mem[8]). Adding EN signal on $memory\u_graph_engine.x_mem[9]$17649 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[9][2][0]$y$17873, Q = \u_graph_engine.x_mem[9]). Adding EN signal on $memory\u_graph_engine.x_mem[10]$17651 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[10][2][0]$y$17887, Q = \u_graph_engine.x_mem[10]). Adding EN signal on $memory\u_graph_engine.x_mem[11]$17653 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[11][2][0]$y$17901, Q = \u_graph_engine.x_mem[11]). Adding EN signal on $memory\u_graph_engine.x_mem[12]$17655 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[12][2][0]$y$17917, Q = \u_graph_engine.x_mem[12]). Adding EN signal on $memory\u_graph_engine.x_mem[13]$17657 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[13][2][0]$y$17931, Q = \u_graph_engine.x_mem[13]). Adding EN signal on $memory\u_graph_engine.x_mem[14]$17659 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[14][2][0]$y$17945, Q = \u_graph_engine.x_mem[14]). Adding EN signal on $memory\u_graph_engine.x_mem[15]$17661 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[15][2][0]$y$17959, Q = \u_graph_engine.x_mem[15]). Adding EN signal on $memory\u_graph_engine.x_mem[16]$17663 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[16][2][0]$y$17979, Q = \u_graph_engine.x_mem[16]). Adding EN signal on $memory\u_graph_engine.x_mem[17]$17665 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[17][2][0]$y$17993, Q = \u_graph_engine.x_mem[17]). Adding EN signal on $memory\u_graph_engine.x_mem[18]$17667 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[18][2][0]$y$18007, Q = \u_graph_engine.x_mem[18]). Adding EN signal on $memory\u_graph_engine.x_mem[19]$17669 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[19][2][0]$y$18021, Q = \u_graph_engine.x_mem[19]). Adding EN signal on $memory\u_graph_engine.x_mem[20]$17671 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[20][2][0]$y$18037, Q = \u_graph_engine.x_mem[20]). Adding EN signal on $memory\u_graph_engine.x_mem[21]$17673 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[21][2][0]$y$18051, Q = \u_graph_engine.x_mem[21]). Adding EN signal on $memory\u_graph_engine.x_mem[22]$17675 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[22][2][0]$y$18065, Q = \u_graph_engine.x_mem[22]). Adding EN signal on $memory\u_graph_engine.x_mem[23]$17677 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[23][2][0]$y$18079, Q = \u_graph_engine.x_mem[23]). Adding EN signal on $memory\u_graph_engine.x_mem[24]$17679 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[24][2][0]$y$18097, Q = \u_graph_engine.x_mem[24]). Adding EN signal on $memory\u_graph_engine.x_mem[25]$17681 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[25][2][0]$y$18111, Q = \u_graph_engine.x_mem[25]). Adding EN signal on $memory\u_graph_engine.x_mem[26]$17683 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[26][2][0]$y$18125, Q = \u_graph_engine.x_mem[26]). Adding EN signal on $memory\u_graph_engine.x_mem[27]$17685 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[27][2][0]$y$18139, Q = \u_graph_engine.x_mem[27]). Adding EN signal on $memory\u_graph_engine.x_mem[28]$17687 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[28][2][0]$y$18155, Q = \u_graph_engine.x_mem[28]). Adding EN signal on $memory\u_graph_engine.x_mem[29]$17689 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[29][2][0]$y$18169, Q = \u_graph_engine.x_mem[29]). Adding EN signal on $memory\u_graph_engine.x_mem[30]$17691 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[30][2][0]$y$18183, Q = \u_graph_engine.x_mem[30]). Adding EN signal on $memory\u_graph_engine.x_mem[31]$17693 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[31][2][0]$y$18197, Q = \u_graph_engine.x_mem[31]). Adding EN signal on $memory\u_neuron_memory.x_mem[7]$18663 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[7]). Adding EN signal on $memory\u_neuron_memory.w_mem[31]$19019 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[31]). Adding EN signal on $memory\u_neuron_memory.w_mem[30]$19017 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[30]). Adding EN signal on $memory\u_neuron_memory.w_mem[29]$19015 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[29]). Adding EN signal on $memory\u_neuron_memory.w_mem[28]$19013 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[28]). Adding EN signal on $memory\u_neuron_memory.x_mem[31]$18711 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[31]). Adding EN signal on $memory\u_neuron_memory.w_mem[27]$19011 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[27]). Adding EN signal on $memory\u_neuron_memory.w_mem[26]$19009 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[26]). Adding EN signal on $memory\u_neuron_memory.w_mem[25]$19007 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[25]). Adding EN signal on $memory\u_neuron_memory.w_mem[24]$19005 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[24]). Adding EN signal on $memory\u_neuron_memory.w_mem[23]$19003 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[23]). Adding EN signal on $memory\u_neuron_memory.w_mem[22]$19001 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[22]). Adding EN signal on $memory\u_neuron_memory.w_mem[21]$18999 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[21]). Adding EN signal on $memory\u_neuron_memory.w_mem[20]$18997 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[20]). Adding EN signal on $memory\u_neuron_memory.w_mem[19]$18995 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[19]). Adding EN signal on $memory\u_neuron_memory.w_mem[18]$18993 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[18]). Adding EN signal on $memory\u_neuron_memory.w_mem[17]$18991 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[17]). Adding EN signal on $memory\u_neuron_memory.w_mem[16]$18989 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[16]). Adding EN signal on $memory\u_neuron_memory.x_mem[30]$18709 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[30]). Adding EN signal on $memory\u_neuron_memory.w_mem[15]$18987 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[15]). Adding EN signal on $memory\u_neuron_memory.w_mem[14]$18985 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[14]). Adding EN signal on $memory\u_neuron_memory.w_mem[13]$18983 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[13]). Adding EN signal on $memory\u_neuron_memory.x_mem[29]$18707 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[29]). Adding EN signal on $memory\u_neuron_memory.w_mem[12]$18981 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[12]). Adding EN signal on $memory\u_neuron_memory.w_mem[11]$18979 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[11]). Adding EN signal on $memory\u_neuron_memory.w_mem[10]$18977 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[10]). Adding EN signal on $memory\u_neuron_memory.x_mem[28]$18705 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[28]). Adding EN signal on $memory\u_neuron_memory.w_mem[9]$18975 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[9]). Adding EN signal on $memory\u_neuron_memory.w_mem[8]$18973 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[8]). Adding EN signal on $memory\u_neuron_memory.w_mem[7]$18971 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[7]). Adding EN signal on $memory\u_neuron_memory.w_mem[6]$18969 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[6]). Adding EN signal on $memory\u_neuron_memory.w_mem[5]$18967 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[5]). Adding EN signal on $memory\u_neuron_memory.w_mem[4]$18965 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[4]). Adding EN signal on $memory\u_neuron_memory.w_mem[3]$18963 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[3]). Adding EN signal on $memory\u_neuron_memory.w_mem[2]$18961 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[2]). Adding EN signal on $memory\u_neuron_memory.w_mem[1]$18959 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[1]). Adding EN signal on $memory\u_neuron_memory.w_mem[0]$18957 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[0]). Adding EN signal on $memory\u_neuron_memory.x_mem[27]$18703 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[27]). Adding EN signal on $memory\u_neuron_memory.x_mem[26]$18701 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[26]). Adding EN signal on $memory\u_neuron_memory.x_mem[25]$18699 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[25]). Adding EN signal on $memory\u_neuron_memory.x_mem[24]$18697 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[24]). Adding EN signal on $memory\u_neuron_memory.x_mem[23]$18695 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[23]). Adding EN signal on $memory\u_neuron_memory.x_mem[22]$18693 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[22]). Adding EN signal on $memory\u_graph_engine.w_mem[0]$18198 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[0][2][0]$y$18276, Q = \u_graph_engine.w_mem[0]). Adding EN signal on $memory\u_graph_engine.w_mem[1]$18200 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[1][2][0]$y$18288, Q = \u_graph_engine.w_mem[1]). Adding EN signal on $memory\u_graph_engine.w_mem[2]$18202 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[2][2][0]$y$18300, Q = \u_graph_engine.w_mem[2]). Adding EN signal on $memory\u_graph_engine.w_mem[3]$18204 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[3][2][0]$y$18312, Q = \u_graph_engine.w_mem[3]). Adding EN signal on $memory\u_graph_engine.w_mem[4]$18206 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[4][2][0]$y$18324, Q = \u_graph_engine.w_mem[4]). Adding EN signal on $memory\u_graph_engine.w_mem[5]$18208 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[5][2][0]$y$18336, Q = \u_graph_engine.w_mem[5]). Adding EN signal on $memory\u_graph_engine.w_mem[6]$18210 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[6][2][0]$y$18348, Q = \u_graph_engine.w_mem[6]). Adding EN signal on $memory\u_graph_engine.w_mem[7]$18212 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[7][2][0]$y$18360, Q = \u_graph_engine.w_mem[7]). Adding EN signal on $memory\u_graph_engine.w_mem[8]$18214 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[8][2][0]$y$18372, Q = \u_graph_engine.w_mem[8]). Adding EN signal on $memory\u_graph_engine.w_mem[9]$18216 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[9][2][0]$y$18384, Q = \u_graph_engine.w_mem[9]). Adding EN signal on $memory\u_graph_engine.w_mem[10]$18218 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[10][2][0]$y$18396, Q = \u_graph_engine.w_mem[10]). Adding EN signal on $memory\u_graph_engine.w_mem[11]$18220 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[11][2][0]$y$18408, Q = \u_graph_engine.w_mem[11]). Adding EN signal on $memory\u_graph_engine.w_mem[12]$18222 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[12][2][0]$y$18420, Q = \u_graph_engine.w_mem[12]). Adding EN signal on $memory\u_graph_engine.w_mem[13]$18224 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[13][2][0]$y$18432, Q = \u_graph_engine.w_mem[13]). Adding EN signal on $memory\u_graph_engine.w_mem[14]$18226 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[14][2][0]$y$18444, Q = \u_graph_engine.w_mem[14]). Adding EN signal on $memory\u_graph_engine.w_mem[15]$18228 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[15][2][0]$y$18456, Q = \u_graph_engine.w_mem[15]). Adding EN signal on $memory\u_graph_engine.w_mem[16]$18230 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[16][2][0]$y$18468, Q = \u_graph_engine.w_mem[16]). Adding EN signal on $memory\u_graph_engine.w_mem[17]$18232 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[17][2][0]$y$18480, Q = \u_graph_engine.w_mem[17]). Adding EN signal on $memory\u_graph_engine.w_mem[18]$18234 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[18][2][0]$y$18492, Q = \u_graph_engine.w_mem[18]). Adding EN signal on $memory\u_graph_engine.w_mem[19]$18236 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[19][2][0]$y$18504, Q = \u_graph_engine.w_mem[19]). Adding EN signal on $memory\u_graph_engine.w_mem[20]$18238 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[20][2][0]$y$18516, Q = \u_graph_engine.w_mem[20]). Adding EN signal on $memory\u_graph_engine.w_mem[21]$18240 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[21][2][0]$y$18528, Q = \u_graph_engine.w_mem[21]). Adding EN signal on $memory\u_graph_engine.w_mem[22]$18242 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[22][2][0]$y$18540, Q = \u_graph_engine.w_mem[22]). Adding EN signal on $memory\u_graph_engine.w_mem[23]$18244 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[23][2][0]$y$18552, Q = \u_graph_engine.w_mem[23]). Adding EN signal on $memory\u_graph_engine.w_mem[24]$18246 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[24][2][0]$y$18564, Q = \u_graph_engine.w_mem[24]). Adding EN signal on $memory\u_graph_engine.w_mem[25]$18248 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[25][2][0]$y$18576, Q = \u_graph_engine.w_mem[25]). Adding EN signal on $memory\u_graph_engine.w_mem[26]$18250 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[26][2][0]$y$18588, Q = \u_graph_engine.w_mem[26]). Adding EN signal on $memory\u_graph_engine.w_mem[27]$18252 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[27][2][0]$y$18600, Q = \u_graph_engine.w_mem[27]). Adding EN signal on $memory\u_graph_engine.w_mem[28]$18254 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[28][2][0]$y$18612, Q = \u_graph_engine.w_mem[28]). Adding EN signal on $memory\u_graph_engine.w_mem[29]$18256 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[29][2][0]$y$18624, Q = \u_graph_engine.w_mem[29]). Adding EN signal on $memory\u_graph_engine.w_mem[30]$18258 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[30][2][0]$y$18636, Q = \u_graph_engine.w_mem[30]). Adding EN signal on $memory\u_graph_engine.w_mem[31]$18260 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[31][2][0]$y$18648, Q = \u_graph_engine.w_mem[31]). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$13777 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$13446 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$13446 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$13446 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$13446 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$13199 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$13199 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$13199 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$13199 ($sdffe) from module spi_neuron_top. 20.33.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 73 unused cells and 119 unused wires. 20.33.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.33.16. Rerunning OPT passes. (Maybe there is more to do..) 20.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.33.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 3164 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 3080 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 84 cells. 20.33.20. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$19744 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[0], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19747 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[1], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19750 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[2], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19753 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[3], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19756 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[4], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19759 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[5], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19762 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[6], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19765 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[7], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19768 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[8], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19771 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[9], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19774 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[10], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19777 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[11], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19780 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[12], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19783 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[13], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19786 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[14], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$19789 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15540, Q = \u_flash_slot_manager.cat_crc[15], rval = 0). Adding SRST signal on $auto$ff.cc:337:slice$20212 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[23], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20230 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[29], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20233 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[30], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20236 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[31], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19803 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[0], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19806 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[1], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19809 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[2], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19812 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[3], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19815 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[4], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19818 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[5], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19821 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[6], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19824 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[7], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19827 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[8], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19830 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[9], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19833 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[10], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19836 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[11], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19839 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[12], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19842 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[13], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19845 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[14], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19848 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15508, Q = \u_flash_slot_manager.cat_type[15], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20209 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[22], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20203 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[20], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19852 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[15], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19855 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[14], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19858 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[13], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19861 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[12], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19864 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[11], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19867 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[10], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19870 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[9], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19873 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[8], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19876 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19879 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19882 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[2], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19885 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[3], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19888 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[4], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19891 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[5], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19894 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[6], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19897 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[7], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19900 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[8], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19903 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[9], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19906 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[10], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19909 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[11], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19912 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[12], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19915 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[13], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19918 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[14], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19921 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15524, Q = \u_flash_slot_manager.cat_valid[15], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$19925 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[7], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19928 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[6], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19931 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[5], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19934 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[4], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19937 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[3], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19940 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[2], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19943 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[1], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19946 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15484, Q = \u_flash_slot_manager.cat_offset[0], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$20143 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[0], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20146 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[1], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20149 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[2], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20152 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[3], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20155 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[4], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20158 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[5], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20161 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[6], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20164 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[7], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20167 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[8], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20170 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[9], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20173 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[10], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20176 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[11], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20179 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[12], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20182 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[13], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20185 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[14], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20188 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[15], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$19949 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[0], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19952 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[1], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19955 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[2], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19958 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[3], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19961 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[4], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19964 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[5], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19967 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[6], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19970 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[7], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19973 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[8], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19976 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[9], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19979 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[10], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19982 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[11], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19985 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[12], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19988 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[13], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19991 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[14], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$19994 ($dffe) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$15500, Q = \u_flash_slot_manager.cat_length[15], rval = 24'000000000000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$20191 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[16], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20194 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[17], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20197 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[18], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20200 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[19], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20221 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[26], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20218 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[25], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20215 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[24], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20224 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[27], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20004 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[0], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20007 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[1], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20010 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[2], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20013 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[3], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20016 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[4], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20019 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[5], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20022 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[6], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20025 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[7], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20028 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[8], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20031 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[9], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20034 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[10], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20037 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[11], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20040 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[12], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20043 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[13], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20046 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[14], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20049 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[15], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20052 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[16], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20055 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[17], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20058 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[18], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20061 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[19], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20064 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[20], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20067 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[21], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20070 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[22], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20073 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[23], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20076 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[24], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20079 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[25], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20082 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[26], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20085 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[27], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20088 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[28], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20091 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[29], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20094 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[30], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20097 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[31], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20227 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[28], rval = 8'00000000). Adding SRST signal on $auto$ff.cc:337:slice$20206 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[21], rval = 8'00000000). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$13735 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 27 on $auto$ff.cc:337:slice$13450 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 28 on $auto$ff.cc:337:slice$13450 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 30 on $auto$ff.cc:337:slice$13450 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 31 on $auto$ff.cc:337:slice$13450 ($sdffe) from module spi_neuron_top. 20.33.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 144 unused cells and 376 unused wires. 20.33.22. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.33.23. Rerunning OPT passes. (Maybe there is more to do..) 20.33.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 20.33.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.33.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 2935 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.33.27. Executing OPT_DFF pass (perform DFF optimizations). 20.33.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.33.29. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.33.30. Finished fast OPT passes. (There is nothing left to do.) 20.34. Executing TECHMAP pass (map to technology primitives). 20.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 20.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 20.34.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $not. Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\_90_alu for cells of type $alu. Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $xor. Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $eq. Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu. Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_80_ccu2c_alu for cells of type $alu. Using template $paramod$dc04b7d98e503a7bab16fce2df70e6e2c5ca34d6\_80_ccu2c_alu for cells of type $alu. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu. Using template $paramod$a1665ef28c749ebcdbe9aecd466e644647b56463\_80_ccu2c_alu for cells of type $alu. Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ccu2c_alu for cells of type $alu. Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. Using template $paramod$d707f0beb0b2a210c8cf7f6f49d0e464a0d63ba8\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a7a1d5fc4563c49b9a54941942b1beedd64a98db\_80_ccu2c_alu for cells of type $alu. Using template $paramod$40d5af6b4f75d59ec652207d09a4399fa69b1bc8\_80_ccu2c_alu for cells of type $alu. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ccu2c_alu for cells of type $alu. Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ccu2c_alu for cells of type $alu. Using template $paramod$8f780356cb6cdb52f6a744190131b65634639c4e\_80_ccu2c_alu for cells of type $alu. Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu. Using template $paramod$7bdc7d89ea9376c9c454fd05d9b64ca6288b61c9\_80_ccu2c_alu for cells of type $alu. Using template $paramod$7945baf943a7eaf2bd95deee6e66976c53d43b8d\_80_ccu2c_alu for cells of type $alu. Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a460ba4831a5c553df03ee15bf45a690343e194f\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using template $paramod$713617589782cfade849bb573b5c36106c4b708f\_80_ccu2c_alu for cells of type $alu. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ccu2c_alu for cells of type $alu. Using template $paramod$8fdcfe020be5e507ba05385ffd706e02b549d39d\_80_ccu2c_alu for cells of type $alu. Using template $paramod$ba698a254f9a5947e85cbe7beae6b161eefc5386\_90_alu for cells of type $alu. Using template $paramod$025d767fc934a3e7d59a671de523743ebaa07759\_90_alu for cells of type $alu. Using template $paramod$9e8c19db10db5b8954224cafa0587db20bab09bd\_90_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ccu2c_alu for cells of type $alu. Using template $paramod$403a3c2fa431a154c52a6a5429d7a6260b5d144f\_80_ccu2c_alu for cells of type $alu. Using template $paramod$bb2d74554e7f3344a65c51a9d0fb34626611aac9\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a04dd9d4d8b430140c4ff94b50470fb380fda2a0\_80_ccu2c_alu for cells of type $alu. Using template $paramod$b8c0a997bce700f23568a5ada79cc6781d1f5ca0\_90_alu for cells of type $alu. Using template $paramod$4868d58a04723871777326409a611fa912defcd8\_80_ccu2c_alu for cells of type $alu. Using template $paramod$3c4ebba1937e04a3f553f5acfdf31330508b9f10\_80_ccu2c_alu for cells of type $alu. Using extmapper maccmap for cells of type $macc_v2. add \u_graph_engine.u_neuron.acc (32 bits, signed) add \u_graph_engine.u_neuron.u_mac8.tree[8] [16:0] (17 bits, signed) add \u_graph_engine.u_neuron.u_mac8.tree[10] [16:0] (17 bits, signed) add \u_graph_engine.u_neuron.u_mac8.tree[9] [16:0] (17 bits, signed) add \u_graph_engine.u_neuron.u_mac8.tree[11] [16:0] (17 bits, signed) add \u_neuron_memory.u_neuron.acc (32 bits, signed) add \u_neuron_memory.u_neuron.u_mac8.tree[8] [16:0] (17 bits, signed) add \u_neuron_memory.u_neuron.u_mac8.tree[10] [16:0] (17 bits, signed) add \u_neuron_memory.u_neuron.u_mac8.tree[9] [16:0] (17 bits, signed) add \u_neuron_memory.u_neuron.u_mac8.tree[11] [16:0] (17 bits, signed) add \u_graph_engine.conn_ptr_acc [22:0] (23 bits, unsigned) add \u_graph_engine.edge_byte_idx (2 bits, unsigned) add { \u_graph_engine.conn_i 2'00 } (8 bits, unsigned) Using extmapper simplemap for cells of type $bmux. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$constmap:79f166835d595f2da2bf7961aca1c28ae4cbc287$paramod$da28c1e8119889aec146d67645a5dbb6d6e76b9e\_90_shift_shiftx for cells of type $shiftx. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$constmap:cc394cf18054892ed7ab85dc6fb1d91048ae93af$paramod$5a4dcc7281286797ba47757650cb512f9032815c\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$constmap:9d54136fbcc1345ae1710bace3cf007c4f6743c1$paramod$91635ec743055fba51fafa061dfe48d7768a01e2\_90_shift_shiftx for cells of type $shiftx. Using extmapper simplemap for cells of type $lut. Using extmapper simplemap for cells of type $tribuf. Using template $paramod$448756c9a9dfaa49080ce4b90c6cc182883e181f\_80_ccu2c_alu for cells of type $alu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000100000 for cells of type $fa. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ccu2c_alu for cells of type $alu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. No more expansions possible. 20.35. Executing OPT pass (performing simple optimizations). 20.35.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.35.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 23518 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 22458 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 22262 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 22223 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 1295 cells. 20.35.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$29813 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$35427, Q = \u_spi_engine.flash_op_start, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$29212 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$39798, Q = \u_layer_sequencer.seq_done, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$29211 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$36221, Q = \u_flash_slot_manager.u_fce.done, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$29024 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$36194, Q = \u_flash_slot_manager.u_fce.fm_rdata_ack, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$28460 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$37520, Q = \u_flash_slot_manager.u_fce.u_spi_flash_master.wdata_req, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$27841 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$39346, Q = \u_flash_slot_manager.fce_start, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$27769 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$39242, Q = \u_flash_slot_manager.done, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$27653 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$41524, Q = \u_neuron_memory.access_req, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$27566 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$41537, Q = \u_neuron_memory.done, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$27490 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$40700, Q = \u_graph_engine.act_wr_en, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$27132 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$40690, Q = \u_graph_engine.done, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$27064 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$40710, Q = \u_graph_engine.ram_req, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$26961 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$42726, Q = \u_psram_ctrl.mem_ready, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$23142 ($_DFF_P_) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1627$rdmux[0][0][0]$a$17587 [1], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$1626 [2], rval = 1'0). 20.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 3111 unused cells and 7573 unused wires. 20.35.5. Rerunning OPT passes. (Removed registers in this run.) 20.35.6. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.35.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 19136 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.35.8. Executing OPT_DFF pass (perform DFF optimizations). 20.35.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.35.10. Finished fast OPT passes. 20.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 20.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 23024 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 21145 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 19266 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 3758 cells. 20.39. Executing TECHMAP pass (map to technology primitives). 20.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 20.39.2. Continuing TECHMAP pass. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. No more expansions possible. 20.40. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 20.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in spi_neuron_top. 20.43. Executing ATTRMVCP pass (move or copy attributes). 20.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 1 unused cells and 32333 unused wires. 20.45. Executing CHECK pass (checking for obvious problems). Checking module spi_neuron_top... Found and reported 0 problems. 20.46. Executing TECHMAP pass (map to technology primitives). 20.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 20.46.2. Continuing TECHMAP pass. No more expansions possible. 20.47. Executing ABC9 pass. 20.47.1. Executing ABC9_OPS pass (helper functions for ABC9). 20.47.2. Executing ABC9_OPS pass (helper functions for ABC9). 20.47.3. Executing SCC pass (detecting logic loops). Found an SCC: $auto$ff.cc:337:slice$28655 $auto$simplemap.cc:157:simplemap_reduce$39715 $auto$ff.cc:337:slice$28654 $auto$ff.cc:337:slice$28653 $auto$simplemap.cc:157:simplemap_reduce$39720 $auto$simplemap.cc:157:simplemap_reduce$39714 $auto$ff.cc:337:slice$28652 $auto$ff.cc:337:slice$28651 $auto$simplemap.cc:157:simplemap_reduce$39713 $auto$ff.cc:337:slice$28650 $auto$ff.cc:337:slice$28649 $auto$simplemap.cc:157:simplemap_reduce$39723 $auto$simplemap.cc:157:simplemap_reduce$39719 $auto$simplemap.cc:157:simplemap_reduce$39712 $auto$ff.cc:337:slice$28648 $auto$ff.cc:337:slice$28646 $auto$ff.cc:337:slice$28645 $auto$simplemap.cc:157:simplemap_reduce$39710 $auto$ff.cc:337:slice$28644 $auto$ff.cc:337:slice$28643 $auto$simplemap.cc:157:simplemap_reduce$39709 $auto$ff.cc:337:slice$28642 $auto$ff.cc:337:slice$28641 $auto$simplemap.cc:157:simplemap_reduce$39717 $auto$simplemap.cc:157:simplemap_reduce$39708 $auto$opt_expr.cc:607:replace_const_cells$55814 $auto$ff.cc:337:slice$28640 $auto$simplemap.cc:157:simplemap_reduce$28639 $auto$simplemap.cc:227:simplemap_lognot$39727 $auto$simplemap.cc:157:simplemap_reduce$39725 $auto$simplemap.cc:157:simplemap_reduce$39722 $auto$simplemap.cc:157:simplemap_reduce$39718 $auto$simplemap.cc:157:simplemap_reduce$39711 $auto$ff.cc:337:slice$28647 Found 1 SCCs in module spi_neuron_top. Found 1 SCCs. 20.47.4. Executing ABC9_OPS pass (helper functions for ABC9). 20.47.5. Executing TECHMAP pass (map to technology primitives). 20.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 20.47.5.2. Continuing TECHMAP pass. No more expansions possible. 20.47.6. Executing OPT pass (performing simple optimizations). 20.47.6.1. Executing OPT_EXPR pass (perform const folding). 20.47.6.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 20.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 20.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 20.47.6.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 20.47.6.6. Executing OPT_DFF pass (perform DFF optimizations). 20.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). 20.47.6.8. Executing OPT_EXPR pass (perform const folding). 20.47.6.9. Finished fast OPT passes. (There is nothing left to do.) 20.47.7. Executing TECHMAP pass (map to technology primitives). 20.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 20.47.7.2. Continuing TECHMAP pass. No more expansions possible. 20.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 20.47.9. Executing ABC9_OPS pass (helper functions for ABC9). 20.47.10. Executing ABC9_OPS pass (helper functions for ABC9). 20.47.11. Executing ABC9_OPS pass (helper functions for ABC9). 20.47.12. Executing TECHMAP pass (map to technology primitives). 20.47.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 20.47.12.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $mux. No more expansions possible. 20.47.13. Executing OPT pass (performing simple optimizations). 20.47.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.47.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 59 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 57 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 2 cells. 20.47.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 20.47.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.47.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 57 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.47.13.6. Executing OPT_DFF pass (perform DFF optimizations). 20.47.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 55 unused wires. 20.47.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.47.13.9. Rerunning OPT passes. (Maybe there is more to do..) 20.47.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 20.47.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 20.47.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 57 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 20.47.13.13. Executing OPT_DFF pass (perform DFF optimizations). 20.47.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 20.47.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 20.47.13.16. Finished fast OPT passes. (There is nothing left to do.) 20.47.14. Executing AIGMAP pass (map logic to AIG). Module spi_neuron_top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 14 $_MUX_ 2 $_OR_ 2 $_XOR_ not replaced 3 cell types: 4 $_AND_ 4 $_NOT_ 31 $specify2 20.47.15. Executing AIGMAP pass (map logic to AIG). Module spi_neuron_top: replaced 10131 cells with 62860 new cells, skipped 9068 cells. replaced 4 cell types: 6832 $_MUX_ 65 $_ORNOT_ 2599 $_OR_ 635 $_XOR_ not replaced 9 cell types: 2537 $_AND_ 986 $_NOT_ 16 $_TBUF_ 1 $__ABC9_SCC_BREAKER 35 $scopeinfo 4900 TRELLIS_FF 2 DP16KD 16 MULT18X18D 575 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 20.47.15.1. Executing ABC9_OPS pass (helper functions for ABC9). 20.47.15.2. Executing ABC9_OPS pass (helper functions for ABC9). 20.47.15.3. Executing XAIGER backend. Extracted 27602 AND gates and 75687 wires from module `spi_neuron_top' to a netlist network with 5187 inputs and 2774 outputs. 20.47.15.4. Executing ABC9_EXE pass (technology mapping using ABC9). 20.47.15.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 5187/ 2774 and = 25595 lev = 25 (1.66) mem = 0.52 MB box = 575 bb = 0 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 5187/ 2774 and = 44822 lev = 36 (1.48) mem = 0.74 MB ch = 6101 box = 557 bb = 0 ABC: cst = 0 cls = 5494 lit = 6101 unused = 40085 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 44822. Ch = 5494. Total mem = 9.75 MB. Peak cut mem = 0.36 MB. ABC: P: Del = 3795.00. Ar = 21375.0. Edge = 25633. Cut = 476743. T = 0.05 sec ABC: P: Del = 3785.00. Ar = 21148.0. Edge = 25442. Cut = 475811. T = 0.05 sec ABC: P: Del = 3785.00. Ar = 9543.0. Edge = 27983. Cut = 692617. T = 0.08 sec ABC: F: Del = 3785.00. Ar = 8110.0. Edge = 26360. Cut = 578567. T = 0.07 sec ABC: A: Del = 3785.00. Ar = 7938.0. Edge = 25183. Cut = 588762. T = 0.09 sec ABC: A: Del = 3785.00. Ar = 7913.0. Edge = 25175. Cut = 601251. T = 0.10 sec ABC: Total time = 0.43 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: + &ps -l ABC: /input : i/o = 5187/ 2774 and = 26094 lev = 19 (1.47) mem = 0.52 MB box = 556 bb = 0 ABC: Mapping (K=7) : lut = 6553 edge = 24976 lev = 8 (0.77) levB = 20 mem = 0.30 MB ABC: LUT = 6553 : 2=444 6.8 % 3=1498 22.9 % 4=3508 53.5 % 5=1067 16.3 % 6=25 0.4 % 7=11 0.2 % Ave = 3.81 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.25 sec ABC: + time ABC: elapse: 2.76 seconds, total: 2.76 seconds 20.47.15.6. Executing AIGER frontend. Removed 43966 unused cells and 57798 unused wires. 20.47.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 6567 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 556 ABC RESULTS: input signals: 331 ABC RESULTS: output signals: 677 Removing temp directory. 20.47.16. Executing TECHMAP pass (map to technology primitives). 20.47.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 20.47.16.2. Continuing TECHMAP pass. Using template $paramod$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000001 for cells of type $__ABC9_SCC_BREAKER. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. No more expansions possible. Removed 877 unused cells and 83348 unused wires. 20.48. Executing TECHMAP pass (map to technology primitives). 20.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 20.48.2. Continuing TECHMAP pass. Using template $paramod$10a6d42c84663fca6c1622800fdec61acbd34667$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101000 for cells of type $lut. Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$99d2121e179120ff7289cd4528d3fd4ca34ec992$lut for cells of type $lut. Using template $paramod$2f3577571d5c3142f074016ee0edb7ccc9033855$lut for cells of type $lut. Using template $paramod$8eff9a80f411c563818dc328d81fa62568df1508$lut for cells of type $lut. Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9$lut for cells of type $lut. Using template $paramod$354c6e12bb192c5ea1375ea4c9e81a221c8f7991$lut for cells of type $lut. Using template $paramod$8133645849acf2279193def0d1b65972d5a7eed2$lut for cells of type $lut. Using template $paramod$3937959babea1e01a60de47d9733889fc1994f6b$lut for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$5cde1509d5af7b31c38525fe119f8286ad8e474a$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a$lut for cells of type $lut. Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad$lut for cells of type $lut. Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$dcf464990597ed9f574b5d75638c55d2a4e121f4$lut for cells of type $lut. Using template $paramod$07d604fa63557df73201af3ab3c9bef4e6969c47$lut for cells of type $lut. Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889$lut for cells of type $lut. Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776$lut for cells of type $lut. Using template $paramod$d1dc785fc5b97e7bec2be30ee7302c8cf250ad22$lut for cells of type $lut. Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$29e6d4598488760861f6b73d2b7f65cb302fdcde$lut for cells of type $lut. Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707$lut for cells of type $lut. Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf$lut for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a$lut for cells of type $lut. Using template $paramod$6f149f4a0a4acdd39ef1c1fa3a4f5a4dfd75ed22$lut for cells of type $lut. Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f$lut for cells of type $lut. Using template $paramod$4b8f0a05fd2e57692c120fcc65d19c62f5c28432$lut for cells of type $lut. Using template $paramod$e461cc049764af21af4b628e5e8146437eeb087e$lut for cells of type $lut. Using template $paramod$ff74d3b36221c7c7b417c242545ab45c7d96a8ff$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a$lut for cells of type $lut. Using template $paramod$1a3391880fc221cac0bcdde8051516d949194afc$lut for cells of type $lut. Using template $paramod$ee5adfa1bcc7e4b8948c774483a7d19aaddb4759$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$9640380942618015231dc80e07fe9e6281ac216a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011111 for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$e404e4e0a49bc1f265c6a481282b448f97ae52b0$lut for cells of type $lut. Using template $paramod$0f28f6a8fd20b6590010dae0d0b075a4900ef2e8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$69cd07689187c617289e4eda75b267345c09f795$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$a82a699dba54b8465366aeb90aba90d3d29adde0$lut for cells of type $lut. Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$1b4dd6457d07f8f165ec99061b8d6c5023635c5b$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$98162d862d449f7c67182f5a43cdfe4123defff8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$d9e869de4ea8677851dc452d380224cee441f821$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010101 for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2$lut for cells of type $lut. Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae$lut for cells of type $lut. Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b$lut for cells of type $lut. Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1$lut for cells of type $lut. Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut. Using template $paramod$47b1691cce9d3422c6243f646236643e13e69f0c$lut for cells of type $lut. Using template $paramod$f92e79ccd6f3d23a5916839d2ca07e4c590942af$lut for cells of type $lut. Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc$lut for cells of type $lut. Using template $paramod$7ffc04c088a4897014506d1e561a14b627924059$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut. Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$f4db076e8f4b102a006431af47288cbfbf6df1eb$lut for cells of type $lut. Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut. Using template $paramod$346842b88e407bf40d83dc890111dffae3530202$lut for cells of type $lut. Using template $paramod$13caa797f9204188208579865e8a63f743d9eed1$lut for cells of type $lut. Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9$lut for cells of type $lut. Using template $paramod$712505941a295086314c22735153725461a87f4a$lut for cells of type $lut. Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd$lut for cells of type $lut. Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d$lut for cells of type $lut. Using template $paramod$239497b96db7e17720ca6afe567a5c67294f57b4$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$211984b6a379dcd5539a44691df4cb719d9259d4$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f$lut for cells of type $lut. Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut. Using template $paramod$05ac1639ab7543654a2476d11c1711de01f760e6$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut. Using template $paramod$fe07503be663f9fa136093aa0dea361797ccf48d$lut for cells of type $lut. Using template $paramod$9e394303e290a474880b56f98766417009256d93$lut for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut. Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4$lut for cells of type $lut. Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut. Using template $paramod$e90230c8dcea473069bf03fcce8b92040e4d209a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110011 for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a$lut for cells of type $lut. Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$1bd94726c3f238799f268790d8ad6643e16bf4cd$lut for cells of type $lut. Using template $paramod$df6b12cebabc3b2db650658c5e894d03a346e968$lut for cells of type $lut. Using template $paramod$8cbde5df415e1b1f73010b234ade0488e5afeb0b$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038$lut for cells of type $lut. Using template $paramod$a4cdb957f72e6aaffaa9b1d02bbfb29201b1957e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut. Using template $paramod$121f66828c71d3c18a58c99e9f44b94525cfca81$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut. Using template $paramod$6437c73d45b0ead0f5d31b5eac076c1bed1cdea3$lut for cells of type $lut. Using template $paramod$75e027562dd79c18e11578dd00de90e243eb679c$lut for cells of type $lut. Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54$lut for cells of type $lut. Using template $paramod$cd1f61c8ab47e7bbfb6dd61c90578a71fbb5d5f2$lut for cells of type $lut. Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b$lut for cells of type $lut. Using template $paramod$b009a0fae8aa5fc053a3b4418ccbf60a5eb404de$lut for cells of type $lut. Using template $paramod$da53b7c05049544c98d21d41bcf7ebe6dd855a06$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$dc2c740cfb6945e79b49a9aaf8c27a802a7a4d6f$lut for cells of type $lut. Using template $paramod$35a8e7ef4d16e93a4af0803a1c2593a83ec771b8$lut for cells of type $lut. Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c$lut for cells of type $lut. Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut. Using template $paramod$165be24785e4097ccfb74473951770165dd92dfc$lut for cells of type $lut. Using template $paramod$4e79aa6839e287ee36e65fa83c13a532a028e9cd$lut for cells of type $lut. Using template $paramod$1bf3509a544426de1daa8b6919ee1df60c7165ec$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut. Using template $paramod$126c776b0f5e5eef0fff11eb6abcf95b4d1189d2$lut for cells of type $lut. Using template $paramod$4be3a821fb2284ae092558dd891a9ab902259ece$lut for cells of type $lut. Using template $paramod$32dee08328e8b29c9284c987432b771d306144c4$lut for cells of type $lut. Using template $paramod$2eb372e44f7e7a0d08c60762e457cb313ddce7d2$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$f1f436aa4c139cc1446adac5bbebcc59a5d0436e$lut for cells of type $lut. Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730$lut for cells of type $lut. Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12$lut for cells of type $lut. Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568$lut for cells of type $lut. Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957$lut for cells of type $lut. Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37$lut for cells of type $lut. Using template $paramod$226baeccae2fcc7465c08d6c1f589bc29138cc7b$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221$lut for cells of type $lut. Using template $paramod$5289dac6f25369a9a495c69c724c25ee83ad0e78$lut for cells of type $lut. Using template $paramod$beffda5916ef03603af7b9daee4a6705f57d3d46$lut for cells of type $lut. Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d$lut for cells of type $lut. Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b$lut for cells of type $lut. Using template $paramod$5637f6366c0fa622e75f886ee59706323e5fe6fc$lut for cells of type $lut. Using template $paramod$39ce441bc59de263ea3b0981e788bf018a7dc0c5$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$033940914b48bd91e9c76770021d3e6fd49ac34a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$6a688d272dca85001e1b8e8b80f03e28edaccd5f$lut for cells of type $lut. Using template $paramod$949912d41b6703327b37a3cbe8a7a7bc923219b7$lut for cells of type $lut. Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061$lut for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08$lut for cells of type $lut. Using template $paramod$52d96bfa17866bab828b9f1286c638d27fce0ef0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$a988852add2bdce7c1dfac786401ba7c7bc832c1$lut for cells of type $lut. Using template $paramod$cef3d344f236016ad78f511d970c0ed55dc829c5$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$4972722c284f07fee673f7cb99e6a36ce4a244f0$lut for cells of type $lut. Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883$lut for cells of type $lut. Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e$lut for cells of type $lut. Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb$lut for cells of type $lut. Using template $paramod$e4ce17fcded6e264148ce0a4c0df3ed1b1b269a4$lut for cells of type $lut. Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95$lut for cells of type $lut. Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut. Using template $paramod$ea2ed7b6000d8bc7d418a28d22dd562f94afdeff$lut for cells of type $lut. Using template $paramod$cbea2d4d520f64cae694e02ff7f67ddafd2047d5$lut for cells of type $lut. Using template $paramod$edfe6773e2ae95f1f17ad5bea62c0e1b079fa667$lut for cells of type $lut. Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b$lut for cells of type $lut. Using template $paramod$0418d03071843846701b94589ccf64296d56c7b7$lut for cells of type $lut. Using template $paramod$e53493f89400484e4e19015869a8a6f7d3804aa9$lut for cells of type $lut. Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565$lut for cells of type $lut. Using template $paramod$b04f0510561c4bbb703d2e39c6eca682b920366b$lut for cells of type $lut. Using template $paramod$ececc55fe721b2d80098bfc00a6005f1af14b6e5$lut for cells of type $lut. Using template $paramod$c6a647d1c43f47262437ab66f342975e9aae65ea$lut for cells of type $lut. Using template $paramod$91a8c7207b2694b974cfe87bdb74cb70f78a6a1e$lut for cells of type $lut. Using template $paramod$6976c320cbf11f042ec0e427f4583d98a6de43d0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut. Using template $paramod$ea9f0804ffa1047d479d3e00429394419ff5856b$lut for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4$lut for cells of type $lut. Using template $paramod$144b75a8611498ca7a45ebee936d999bf46475cf$lut for cells of type $lut. Using template $paramod$ffc80aea4aa44f0166b2d4713ba5912f56e92991$lut for cells of type $lut. Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99$lut for cells of type $lut. Using template $paramod$eab8c2e20ad6848564bec45c7148558972138f5b$lut for cells of type $lut. Using template $paramod$0c5a54c406cdb1ed108583f5d43071050a5e4d5c$lut for cells of type $lut. Using template $paramod$0425f46a1444788a7d60572c26dbde5e7cb29de0$lut for cells of type $lut. Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a$lut for cells of type $lut. Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa$lut for cells of type $lut. Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45$lut for cells of type $lut. Using template $paramod$72d04cda0ad63fcea17225ad4256bc664683b513$lut for cells of type $lut. Using template $paramod$4888f2121a1fba4d507203534ae54782bc81e02e$lut for cells of type $lut. Using template $paramod$23b135911b7c14b5b19b5329e5903bcf58b44188$lut for cells of type $lut. Using template $paramod$fea512844f0598125018304dfe86621dbf348f27$lut for cells of type $lut. Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4$lut for cells of type $lut. Using template $paramod$192f8c3c2c46a7fd689eb7f880cfd49c9f7067c3$lut for cells of type $lut. Using template $paramod$c471af5667a682bd131a5b479e58e470d1b2b7cd$lut for cells of type $lut. Using template $paramod$d11fd0cafe28c6509f05d39c9d5671060ee4e821$lut for cells of type $lut. Using template $paramod$d750041ede21fd9873becb06293199fd1fbc9a7e$lut for cells of type $lut. Using template $paramod$b212ed9fff0ef04494d0a2749a793f265dd2e870$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut. Using template $paramod$7a02e05acb86bef14143e0e435fb2c7bb50c485b$lut for cells of type $lut. Using template $paramod$c5d60f44dd3a122f686282c39f911648d417ebbe$lut for cells of type $lut. Using template $paramod$49172ccf08cd15c8f891ff08f2ba7f1f0641e32e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$4acaad3481bccc123482c4010bb095c9612e3455$lut for cells of type $lut. Using template $paramod$2d9afc4fcdaefc1aa926013768e4628d50e32e31$lut for cells of type $lut. Using template $paramod$25f748a39f13f638a0dd44b265e145242e43bbc5$lut for cells of type $lut. Using template $paramod$3be6f9c146080e035a4bc1c761ca93e59dbe0ff0$lut for cells of type $lut. Using template $paramod$3886772a94bf9a8ad4c07a7d07d33b5ad81925f5$lut for cells of type $lut. Using template $paramod$d7816c8fe91c91c2deadbc0f27110529e1999027$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$f4e3e92a4c91ccc38cbcadd03ed0b5769fbf8483$lut for cells of type $lut. Using template $paramod$591867156335d418c390523fc0685dbbb5e9690c$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a$lut for cells of type $lut. Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$27190b166827ead7a5b229ee873e4b91ee0faf61$lut for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882$lut for cells of type $lut. Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007$lut for cells of type $lut. Using template $paramod$8fb7c2a4174bbb0f9870bcb831d0cc7f5057f41f$lut for cells of type $lut. Using template $paramod$45549367a76ca3a08d3f4ada747fe89e0c14b78a$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869$lut for cells of type $lut. Using template $paramod$37f494dcc63f6757d907b5936f5f221c6c5e4340$lut for cells of type $lut. Using template $paramod$05f19d9c2311a3d1ab38ece311a1bb9f96c62043$lut for cells of type $lut. Using template $paramod$c7754eeb17b54dfe53ea4a973db3714d78ced2f9$lut for cells of type $lut. Using template $paramod$77268019239d7d46332da9cb6aa01cbf3ba29ee3$lut for cells of type $lut. Using template $paramod$243755ea56ddd01428d9c1ddb21498635fbab0f0$lut for cells of type $lut. Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d$lut for cells of type $lut. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9$lut for cells of type $lut. Using template $paramod$d7ebeaef7104bab98c2de3262f04b026b127e6ce$lut for cells of type $lut. Using template $paramod$611e5863a30eeacc19b5015939188ef7be763eab$lut for cells of type $lut. Using template $paramod$12fb017f90e7463fe74789d2ec23494cce2be24a$lut for cells of type $lut. Using template $paramod$2af9c0976009c8f8e234579e6c381b4281e03142$lut for cells of type $lut. Using template $paramod$5a60a2ac5fa0ff621c08e76879e9692734937783$lut for cells of type $lut. Using template $paramod$ef02ea28c4f9766a22068d6502e87f79cf2d9131$lut for cells of type $lut. Using template $paramod$374867c42e74e4377eae0465720a5315b15ad5c2$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$6a54e7f3518945d7a8816f5d64e66642b37ebbb3$lut for cells of type $lut. Using template $paramod$2c01c78b93f77b5e79eae85526677e695be05a34$lut for cells of type $lut. Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9$lut for cells of type $lut. Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df$lut for cells of type $lut. Using template $paramod$df23d368a6ae8908771963811f5ab56f622887ca$lut for cells of type $lut. Using template $paramod$eec22efc31481e6a2706a92743e67f4f90bad45a$lut for cells of type $lut. Using template $paramod$cad6759fdfb8530bfd60697ced7965a714eb46fa$lut for cells of type $lut. Using template $paramod$369624b024132c6d54ca5ca0dec0683515f4f203$lut for cells of type $lut. Using template $paramod$9616fecedc1a6ce839b990a3156875e06908d6fa$lut for cells of type $lut. Using template $paramod$5073915fb3e3b6ee5612ea669fd7c36dbda7407c$lut for cells of type $lut. Using template $paramod$6daa1f38743ddf86b54e83cbcf8003e7e7d78aa1$lut for cells of type $lut. Using template $paramod$2014354416722209de7d48370ab008bc2278a034$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d$lut for cells of type $lut. Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d$lut for cells of type $lut. Using template $paramod$db5288819445fcf789b7bdd12f20bb1c181b8351$lut for cells of type $lut. Using template $paramod$a7bbd5af1e0fed26a619911b2ac6a874ef33e184$lut for cells of type $lut. Using template $paramod$beb97a17346bc250472cfd3ae14dd9589c502610$lut for cells of type $lut. Using template $paramod$6ce3ee47256136d20ed2b5b614dd995f7ead9d58$lut for cells of type $lut. Using template $paramod$d74f27ecdfbf562ce0161f824cec9778b19ee549$lut for cells of type $lut. Using template $paramod$b37e62d0dd2269ea691d26c59bccb55e4d588045$lut for cells of type $lut. Using template $paramod$f42659ffba1dfd5aeeefc0f7a9c2b1dddd6ebccb$lut for cells of type $lut. Using template $paramod$af763bca85949884aefa417266a961f9c91132de$lut for cells of type $lut. Using template $paramod$1ccc231fcbacd07540c8c4cc40a700cd23fb9536$lut for cells of type $lut. Using template $paramod$ed81c44998e0166e4e0643f02b6206dfa71dd9b3$lut for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75$lut for cells of type $lut. Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf$lut for cells of type $lut. Using template $paramod$3e527b22aa6f95535700a3751a731f573f9256f6$lut for cells of type $lut. Using template $paramod$fd23882c180d7b3b03de24a931b4a7b8ffdeeac9$lut for cells of type $lut. Using template $paramod$33b72718c79847c9c03c134c7bec663dbf06983b$lut for cells of type $lut. Using template $paramod$17f1b90a5c6d7e6613368c5e7d3f44dd634e59e2$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0$lut for cells of type $lut. Using template $paramod$7be88e0df6e4880c1c3fc451609aacef4dbeff65$lut for cells of type $lut. Using template $paramod$777f8c6c5912804953e2e0af9194699e173126cb$lut for cells of type $lut. Using template $paramod$ac0bc5d4f1e6dcfd192559e5535468fd2bd6a006$lut for cells of type $lut. Using template $paramod$23c8e0520921870d15fff1ec4c11a540f758d474$lut for cells of type $lut. Using template $paramod$5104e17aaaab74f518dfc16a38dede1ad47f619b$lut for cells of type $lut. Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3$lut for cells of type $lut. Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87$lut for cells of type $lut. Using template $paramod$e725104ab255de4508ea88ecbc241d17f264ce79$lut for cells of type $lut. Using template $paramod$8afe9f9396e222eb1bca50c99e9bab03367fbe83$lut for cells of type $lut. Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f$lut for cells of type $lut. Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8$lut for cells of type $lut. Using template $paramod$43987c9cc87683fa7a6ecfc84dddb93414b52f9f$lut for cells of type $lut. Using template $paramod$988e2eb4b36d1e7a0f83d18b254ac3090fa66d1c$lut for cells of type $lut. Using template $paramod$ee04a7397c7e60ad1a187fa314ed449c24407f97$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5$lut for cells of type $lut. Using template $paramod$c79843a7a21eda73c585e76a35dd51b0a4d6fd36$lut for cells of type $lut. Using template $paramod$3ff274181e03e6e1dc6ffedd2c2d5bc1266bc292$lut for cells of type $lut. Using template $paramod$122a4c0b007fa7ed75dbda7c4d71a52e22ce1276$lut for cells of type $lut. Using template $paramod$5f496f7a17b34803c6c54860f8e4d6216cf793ef$lut for cells of type $lut. Using template $paramod$633ea4e924c3cee46c4996099b701ece3907518d$lut for cells of type $lut. Using template $paramod$c7eaad6a588218ef0ba5a17502d003bdff2bbd3e$lut for cells of type $lut. Using template $paramod$4c0221505c29b55a66f4801128a7e9ab143964dc$lut for cells of type $lut. Using template $paramod$e66ddd071de3be1d112de63078d882cb12c0fbe3$lut for cells of type $lut. Using template $paramod$31077ee928441cddcd4404d779bfc02232a21b60$lut for cells of type $lut. Using template $paramod$9d53d1c8974e3863645d160da18ba6deff54db12$lut for cells of type $lut. Using template $paramod$12879138d1e376f344e47ea40be66b776233be75$lut for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee$lut for cells of type $lut. Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c$lut for cells of type $lut. Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41$lut for cells of type $lut. Using template $paramod$c63bcb5aac8f211c194ff3c5408c6b3684faa331$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101111 for cells of type $lut. Using template $paramod$850e9d7b3bedfea3aee4099c00addfa891dc3264$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5$lut for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f$lut for cells of type $lut. Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3$lut for cells of type $lut. Using template $paramod$fd8c3aaf82f5e6c54421b9b80186cc8de0dd28b8$lut for cells of type $lut. Using template $paramod$b5af55acc9ed13b74b99ade34d8da43614af21c0$lut for cells of type $lut. Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f$lut for cells of type $lut. Using template $paramod$22e4ab1325c04150739d788c010b5a723d98bdfb$lut for cells of type $lut. Using template $paramod$77c2a0573790d304ab2299da6d598e8d2e184867$lut for cells of type $lut. Using template $paramod$4d9437f28ee827cf4006287c53ecaa1266100fca$lut for cells of type $lut. Using template $paramod$fc6feb7ca0813ec6f9a6e104d2344b22630ad56a$lut for cells of type $lut. Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110100 for cells of type $lut. Using template $paramod$130a3185152cd3779d37df1e15e0ffb941c3d3d4$lut for cells of type $lut. Using template $paramod$723be7177967d6866729df0ff463a602326a012e$lut for cells of type $lut. Using template $paramod$47767f5c382f8b63a0774a8330636654f073ecd1$lut for cells of type $lut. Using template $paramod$027b71830bd0fbfb04ad11206c5a0de76ed9d3f5$lut for cells of type $lut. Using template $paramod$4ee1419b717efc0ba99b6b081b860ec15f3c98b8$lut for cells of type $lut. Using template $paramod$39869295d7ae0408e6194606acdccaa76520a14a$lut for cells of type $lut. Using template $paramod$3718b46f9fc8e7db62b1202aeaec21c3331ed565$lut for cells of type $lut. Using template $paramod$1393cc91c00f9520586619e5992507ad2f55f048$lut for cells of type $lut. Using template $paramod$38446ff493f776d29ea4f3122b249720a55b03df$lut for cells of type $lut. Using template $paramod$cf52221ef2d451442dd7d72d5c8ad598e89310e9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut. Using template $paramod$0939298d426d727b8afa3e9642d621400f6da76d$lut for cells of type $lut. Using template $paramod$430c22b4e8ca66a768775fe88fd6f4203d7cc091$lut for cells of type $lut. Using template $paramod$dba872b781c89965b16212b2917fdf4d5ce8b9bc$lut for cells of type $lut. Using template $paramod$709e5cb9fcade45a32caf8f458a1c724d77a2131$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut. Using template $paramod$eec08806ff838a1587a3099a4e55b87128606fb7$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$e3232e0a90c8340ac10328f8e4e3ccd56fa7779b$lut for cells of type $lut. Using template $paramod$904721edce36ee1a1c3db700015f0abf1d413695$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut. Using template $paramod$66e741791413519a466d4f44240bc83d3a191818$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3$lut for cells of type $lut. Using template $paramod$9aaf4b372e04ab3d0ad800f237c4b5bae7dadda8$lut for cells of type $lut. Using template $paramod$e098d38d00670bf1f66f3fff32b3e8f0f799bc39$lut for cells of type $lut. Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c$lut for cells of type $lut. Using template $paramod$4da50eea977d85cc9a7d214dd3ec6c80c6a6f581$lut for cells of type $lut. Using template $paramod$2bf796e0fd6e6f7f76aac424a34e617ed5d61822$lut for cells of type $lut. Using template $paramod$ac977aa0d190185160c6b377be998fa6a7e9ef34$lut for cells of type $lut. Using template $paramod$41a9017c3cf386202f51048036dec79f710305a2$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$9e9a7771774add227564d68a81c8dcc150e591da$lut for cells of type $lut. Using template $paramod$28b298702bf093d7c0103e168fd27f9dac943dc2$lut for cells of type $lut. Using template $paramod$5f2c184e719bd4e5fefb9f913b84bd9e97cd57c5$lut for cells of type $lut. Using template $paramod$5d84c8ce420ed2076cb2a96b45b5795840293404$lut for cells of type $lut. Using template $paramod$a935e73998c23d0918dc6474651b7e58909d13d3$lut for cells of type $lut. Using template $paramod$56845c05deedabdd807772e8a5692f978f6216b2$lut for cells of type $lut. Using template $paramod$18455d4fd1270af2266bf4bb1c44971b2eb6b37a$lut for cells of type $lut. Using template $paramod$441de597d9318495d3225f370c9f7379b3b0fd0d$lut for cells of type $lut. Using template $paramod$15b8a34b584db9992618c60ec40195f550bcb34b$lut for cells of type $lut. Using template $paramod$668297d993c890b0d9927f2698cd4fde1ac9009c$lut for cells of type $lut. Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc$lut for cells of type $lut. Using template $paramod$a1cfe99817bd6d57a83efd5e1c3fc26a743b692f$lut for cells of type $lut. Using template $paramod$757c055b2d591f99a56beeb4bd1bdff266f67334$lut for cells of type $lut. Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28$lut for cells of type $lut. Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e$lut for cells of type $lut. Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod$f28aede8a07a53ff316cc6f8627c7d8a2337a88a$lut for cells of type $lut. Using template $paramod$4e309f6669eadcfa589d4ae302672e3a030a20a5$lut for cells of type $lut. Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7$lut for cells of type $lut. Using template $paramod$ce57c8604805f80ab07a0434d106bb987e82ae6c$lut for cells of type $lut. Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut. Using template $paramod$9d12c15405e25608417ce779d7fe1b86619365f9$lut for cells of type $lut. Using template $paramod$d575d3554e876f643193272ee6813447059f103f$lut for cells of type $lut. Using template $paramod$6f3fbc950472d0e41d056ec72b76296a692fa52d$lut for cells of type $lut. Using template $paramod$cdcc7a011cbeb5e651cdd420fd8136c8d413e1ce$lut for cells of type $lut. Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut. Using template $paramod$b1c1fcc81573437ec158d7c629938862148f7151$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$1d411fd062123bc39f2e308cfceb6b39df8f57b9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$e20929e9403e90ee4d3e69df12e3a13ed9888c86$lut for cells of type $lut. Using template $paramod$5a3b726670ce434c27ab6d39e16edfbe9baa03b2$lut for cells of type $lut. Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a$lut for cells of type $lut. Using template $paramod$8984115c225117738e025ee023c91661c894ce0b$lut for cells of type $lut. Using template $paramod$f2882f06eb98592bf08b79342c263707b6eb5e89$lut for cells of type $lut. Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201$lut for cells of type $lut. Using template $paramod$db8d333bf66c0cdffe51960a4478272318cfbbaa$lut for cells of type $lut. Using template $paramod$d3c14dd8f90a79df7904fb46dabb4ae5b67cb3e8$lut for cells of type $lut. Using template $paramod$9c10e17a0a1ecd0e2664d222f0eb0cb2cf52c224$lut for cells of type $lut. Using template $paramod$4fbae9a10a465642752c7465a492003601f920a3$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut. Using template $paramod$b9201d137cafff7533407a0000643b3710e7387b$lut for cells of type $lut. Using template $paramod$f2c7724a377078ae43fd5553a51bddaa7059bce8$lut for cells of type $lut. Using template $paramod$193f207d7949900be3d2817b6e19e8941513342b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$a36debbcfde9e32a01ea5076ccf3d75225452c4d$lut for cells of type $lut. Using template $paramod$1d7cc7523960d07120e056db4cec420057edf3a5$lut for cells of type $lut. Using template $paramod$0bc4f6b59b5dc66cb4809a8b03fba9ed1dc56c2c$lut for cells of type $lut. Using template $paramod$fd63e7de2adef529b2855e7d028f2c82d35565e5$lut for cells of type $lut. Using template $paramod$098e58216a69950f0886b9f52f31a2a03d30183d$lut for cells of type $lut. Using template $paramod$0889b35715673a32186bd4c9c480161058a88063$lut for cells of type $lut. Using template $paramod$499a50737919ca74b1b8949afb53f2fddbc07a27$lut for cells of type $lut. Using template $paramod$1f8e053d7a35ab06d0d8752a9bfb20f6f0f83a23$lut for cells of type $lut. Using template $paramod$8b12ac3f1b5909b2c78c9ca588956c4529fbbff6$lut for cells of type $lut. Using template $paramod$32bf5cf7d2005e341bef7b640f701e2031dc4e51$lut for cells of type $lut. Using template $paramod$e3bc121185226a2e6e83e0cc96f60d319504acee$lut for cells of type $lut. Using template $paramod$16d2400469dd35743021769c21f0024b2c722465$lut for cells of type $lut. Using template $paramod$a4feb7db8ce913743fc9979ff52d0c0d3ddae42f$lut for cells of type $lut. Using template $paramod$c0be2e18e00f34600408defb32aa5b4578723dd2$lut for cells of type $lut. Using template $paramod$ac0496fcebb0f2011b0bd8f43e25017a354391ee$lut for cells of type $lut. Using template $paramod$ccf54393f919f1976d5f8c70d4f8c9206544d866$lut for cells of type $lut. Using template $paramod$efc60783c939ae41b2f3555af407b17c007b27f8$lut for cells of type $lut. Using template $paramod$bacdb2105cbfbe75cfbcc2fb021fd3aba864526b$lut for cells of type $lut. Using template $paramod$f31d9e0f506230211ce90dec8cda8f4e917ce473$lut for cells of type $lut. Using template $paramod$23651958850c9740fa4af5b0ad394d7cb5881892$lut for cells of type $lut. Using template $paramod$4773b75c97018e61f57445eeea3243adae0e285e$lut for cells of type $lut. Using template $paramod$3139ed3ee5b19849b7d0cf3feb8af16f18d1f63b$lut for cells of type $lut. Using template $paramod$6cc2e8cf339d58b651237e4afe9edc82863bc3b0$lut for cells of type $lut. Using template $paramod$383937d21a28172b345409fac698db2f2097b514$lut for cells of type $lut. Using template $paramod$ff0bb604f490b2670eaedf8f675b877816d14ea3$lut for cells of type $lut. Using template $paramod$dc828a6f122724e6c4ab2d0c2a4bb5abe04e2ece$lut for cells of type $lut. Using template $paramod$6902893557ea1f2d8c63b4b00c0a0a0dff5059d2$lut for cells of type $lut. Using template $paramod$a268b0f63addd6e02506997c66b5cb321449530f$lut for cells of type $lut. Using template $paramod$070dbfa5ca97cb63cec8a3304c847556aa755e29$lut for cells of type $lut. Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd$lut for cells of type $lut. Using template $paramod$74f3c752a04873b10175c1be7993769877a95181$lut for cells of type $lut. Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut. Using template $paramod$b9da78223373d7195fca9c4ad503c72a3e92c93b$lut for cells of type $lut. Using template $paramod$b191695349501b3c1003e90f2d9ac60d767bdeed$lut for cells of type $lut. Using template $paramod$9c07ccf4e1b3aa010820f302f972588eac1423f4$lut for cells of type $lut. Using template $paramod$b1d41c251992348e752b19c12db8a58434359feb$lut for cells of type $lut. Using template $paramod$1d249a681c3bd2ce105b9b74f280ffee082c3e51$lut for cells of type $lut. Using template $paramod$c99909b0661e592bb9701b15671a24d993e3be48$lut for cells of type $lut. Using template $paramod$c1a9782baa54a4d88687292d82ac6d7e62a3aaf7$lut for cells of type $lut. Using template $paramod$0d6e5085e7f484e8afccaf843a26899272d0f476$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$ad72f449a3fc25ae204b59a66f1bc742c88a461d$lut for cells of type $lut. Using template $paramod$cbe027e37111ee6aade26f0cde1a82629524087d$lut for cells of type $lut. Using template $paramod$fa59a299e41bd89da820f8d5404ca89afce3b1fe$lut for cells of type $lut. Using template $paramod$e41b117e7353372d5837f132df59f9328ccc4987$lut for cells of type $lut. Using template $paramod$709de57d2785ba42cbf79b5b78414e5a87816ad9$lut for cells of type $lut. Using template $paramod$72043e0aa7fa64cb454e3c2ca3dbe1636171896a$lut for cells of type $lut. Using template $paramod$853e3203592baef65d796b34492197bd287b4728$lut for cells of type $lut. Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149$lut for cells of type $lut. Using template $paramod$3830fbfbec2ed4d6e3e957e17e4fca97b7adef1f$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod$2413346fa47cf8a80719d09e44e1141a42fc9c2e$lut for cells of type $lut. Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e$lut for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2$lut for cells of type $lut. Using template $paramod$27e3caed917c05f2cc1450c082e0c10ace327002$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6$lut for cells of type $lut. Using template $paramod$e96f7749d9bd8c6a6f0a07399963402b29fd74c0$lut for cells of type $lut. Using template $paramod$e57bcb018bfe8170bc04f13a73befe2def28cdf3$lut for cells of type $lut. Using template $paramod$92e9772d13b9de8e8cb449ffb878789c64b359c7$lut for cells of type $lut. Using template $paramod$770294a51a17fe62e759640f7cb42640c4c73ae5$lut for cells of type $lut. Using template $paramod$0a8483ac0d186281217ca120ffeab9c6abf14068$lut for cells of type $lut. Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000010 for cells of type $lut. Using template $paramod$a58307339d0c3507c6c02894a0973c5adc4bcdae$lut for cells of type $lut. Using template $paramod$286d6b18e782cb14d345c8422500571fedf77570$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542$lut for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336$lut for cells of type $lut. Using template $paramod$cdfb4ce36e9b97ab980954e4bd7262833a7086a8$lut for cells of type $lut. Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e$lut for cells of type $lut. Using template $paramod$3a75385b1beb239786b9fcdc898b53110e63595f$lut for cells of type $lut. Using template $paramod$0498819220bb36cfd5ba6facabe8eab892920bd6$lut for cells of type $lut. Using template $paramod$ed4b624f477a67dbd878e676981471b9a7808c29$lut for cells of type $lut. Using template $paramod$8702d826849a5d8af6dd5fde2d287a6443f7d076$lut for cells of type $lut. Using template $paramod$758eb0872e1a359755459d5f59c38d6cbff0041c$lut for cells of type $lut. Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1$lut for cells of type $lut. Using template $paramod$480632dc6f7c037df6062cf8bf88300b5262c395$lut for cells of type $lut. Using template $paramod$3cb76330a0b3391eb0ca04a52bbe551f6e8e32d8$lut for cells of type $lut. Using template $paramod$f77a52a9c6e798df34c7ce3d09c1e2f9be59f00e$lut for cells of type $lut. Using template $paramod$b75e8306635d621cb7e96e5d2ad1327ab1afa025$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2$lut for cells of type $lut. Using template $paramod$11426815751623871d46bc9f1667ef33eaf7eced$lut for cells of type $lut. Using template $paramod$79364b9974cfc81fb54c164d10340bf9c7bccd7f$lut for cells of type $lut. Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673$lut for cells of type $lut. Using template $paramod$7c95eb9ffb3745d144aa54b7ec4727e30f2a505a$lut for cells of type $lut. Using template $paramod$ec532a5172c0d2e2cd700bfb0aad532a38b6f70d$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$6e1e2bf7f29cfe416c0ceb4dc5c676edd2a3b996$lut for cells of type $lut. Using template $paramod$3f95c15e882729f63793f446e65b165e4b662f5c$lut for cells of type $lut. Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef$lut for cells of type $lut. Using template $paramod$24b67fade1852074c0ac6a4c585dd4228e286f08$lut for cells of type $lut. Using template $paramod$4045162732ff1ef3063f7c74bcf446c45645f6c6$lut for cells of type $lut. Using template $paramod$c35492cebda5b908d10e5976bd14d50fda8ce5fd$lut for cells of type $lut. Using template $paramod$493190373199e5a39be045ba23abb29ecef89037$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a$lut for cells of type $lut. Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457$lut for cells of type $lut. Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4$lut for cells of type $lut. Using template $paramod$7b452cff12d38abbda6b7f738d3fd9233b6e59fa$lut for cells of type $lut. Using template $paramod$37f81e0845e2ea8859a016ada9b9fe63b4b71db1$lut for cells of type $lut. Using template $paramod$8ae79756898a0f2ae23b6254a1a5c8232faafe4e$lut for cells of type $lut. Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$ef69c4c98b6d69fef2eda1f8757de03523a9943d$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. Using template $paramod$d2b5e7b5429639878c0a614cf001753581eebd9c$lut for cells of type $lut. Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7$lut for cells of type $lut. Using template $paramod$18fa685a8cdb30eb6c664aa12d728a07c3fe94f1$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101011 for cells of type $lut. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut. Using template $paramod$a547ebbcb936a0942e18c1762283837f76f0003a$lut for cells of type $lut. Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713$lut for cells of type $lut. Using template $paramod$3258fabf91107b4a007ae89b2246a16c31e8ae28$lut for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54$lut for cells of type $lut. Using template $paramod$8d3ce9be81cff69f90f3cfd65305257300b4cb85$lut for cells of type $lut. Using template $paramod$8ef56ce61c9bd29babbfd13567621233255997c5$lut for cells of type $lut. Using template $paramod$ca0af2353dd5820cf82c97bfca32330d8044ad38$lut for cells of type $lut. Using template $paramod$40ed8962a201eb441a33b532af5bb42b422ed08d$lut for cells of type $lut. Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218$lut for cells of type $lut. Using template $paramod$5ce0414f30742591cfbc3ba73903b522793ddcd1$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$7e3de18263fb7d0a2e12a4401120994e66bde6a4$lut for cells of type $lut. Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut. Using template $paramod$fccc976d95e1313da5c08e66caf452a16c55301f$lut for cells of type $lut. Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072$lut for cells of type $lut. Using template $paramod$e484b1e0bd351ba5af34f5fd66a8e850cc5b8335$lut for cells of type $lut. Using template $paramod$564bd638c843438fd2caabd29849228619f2f89f$lut for cells of type $lut. Using template $paramod$24a071e37fb30533686475161ae3a85ccfc2f924$lut for cells of type $lut. Using template $paramod$053427f7f5ea07d59a8194fc808f0dbdb8dee48b$lut for cells of type $lut. Using template $paramod$cad8f5c808e91f937dcf797b89e646787b39867a$lut for cells of type $lut. Using template $paramod$21b051a1cf30565bddf1900c93a9b5e3135164a7$lut for cells of type $lut. Using template $paramod$6c22e4c9acd607e1249c5e3017b6703f378da140$lut for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4$lut for cells of type $lut. Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037$lut for cells of type $lut. Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11$lut for cells of type $lut. Using template $paramod$f79938a687f03dc06c4fb088b4b491fc2a3339e4$lut for cells of type $lut. Using template $paramod$b5014374cf525b0bffec57e9d6c8c9a9fb8feb94$lut for cells of type $lut. Using template $paramod$150ee00bee81b2fcb159e621f4ef27bccb5ede20$lut for cells of type $lut. Using template $paramod$eced46750b43aa9efabd63e9db30cd976a863157$lut for cells of type $lut. Using template $paramod$c68110307ed3a83d1f1d050a34218c458bce2221$lut for cells of type $lut. Using template $paramod$526e4703e3f9e5bf75da836fd3d4410dd76747a6$lut for cells of type $lut. Using template $paramod$82ed25b11a6a11eb861f4dd3d46f5fc9aa1eebaf$lut for cells of type $lut. Using template $paramod$368ece0cbe0dd8813956f5c0ea41432c34a980c2$lut for cells of type $lut. Using template $paramod$6507513c0010da33acd512bfc664cd54f3e32564$lut for cells of type $lut. Using template $paramod$9a269ffb0efb6ad342cb106a4e0636e23fdfd547$lut for cells of type $lut. Using template $paramod$a7d9b4ab0321c8125e5b895183ee6b84cdb4a31b$lut for cells of type $lut. Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3$lut for cells of type $lut. Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806$lut for cells of type $lut. Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d$lut for cells of type $lut. Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d$lut for cells of type $lut. Using template $paramod$5d33cfa6a45c55d19e75fa773f09299628aedc6c$lut for cells of type $lut. Using template $paramod$4658fedcd7ebe2858c93f54b88221dcf68c6bb6c$lut for cells of type $lut. Using template $paramod$6f1052a36a1a8c60ea16c5e8d31e642dc49f8d11$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. Using template $paramod$6c8df34f38f3bb4fc8db8d09eb9f20a15c6ee32e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut. Using template $paramod$008b5ddcb5e0c121c251b626652a524b7d9d3ea2$lut for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b$lut for cells of type $lut. Using template $paramod$517625bf4a7b846fd553901d881a35fcc8afe4c4$lut for cells of type $lut. Using template $paramod$8494168726d27c2200605afcf1fb7470bf987857$lut for cells of type $lut. Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4$lut for cells of type $lut. Using template $paramod$93f74d366819d1f86e5e8b91d159aa6b1cd7e9fb$lut for cells of type $lut. Using template $paramod$7ead64b4aad7d385f4026e5c8bda27e6fbb4bc78$lut for cells of type $lut. Using template $paramod$4ba6a61888dbdf77bf234a7f04a27062c9dda10a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. No more expansions possible. 20.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in spi_neuron_top. Optimizing lut $abc$196408$lut$aiger$o7377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$30387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$16937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$16937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$16746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$26173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7305.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$24853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$29439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6751.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$9475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16513.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16441.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$16653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$20401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o5433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o5433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o5433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o5433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$11520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$12288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$12288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$12335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$7552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$7486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$7087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$30217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$29923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$29519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196596.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$28966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$28440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$28381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27012.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$26766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$26484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$25830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$25352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$25010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$24282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$24256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$22300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$22300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$22300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$22300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$21916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$21870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$21706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$20145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196985.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$18889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$18395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$17665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$17665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$17665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$17665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$17665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$17161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$15530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$15148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14791.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$7490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$14231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$13865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$30496.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$7309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$26484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o5512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$30301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$7389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$7552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$23429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$19849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o5830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$30217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$20638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$30616.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$7526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$24159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$13506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o5558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o5558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196561.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$20588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$27970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196585.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$29259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o5634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$15530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$20776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$27916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$24099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$21921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$22128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$13749.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$26295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o5876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o5914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6855.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$28187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$20447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$23342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$29923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$21171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$25010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$26235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$29872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196691.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$29839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$29760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$18050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$8297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$21895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$18889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$15720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$23992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$15741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$21581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196757.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$15769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$11678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$19941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$8507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$14027.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$22375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$23239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196789.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$14073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$11782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$15840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$18946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$29519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$11949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$21874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$17229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$14167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$18967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$8834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$19920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$24967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$24757.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$8913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$11991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$8955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$8968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$21706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$22334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$19987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$27349.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$23603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$18224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$18261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17321.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$12149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$23818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$27290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$25830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$17420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6764.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$9217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$17233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$29150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$25784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$18303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$9309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$20822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$21049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$19056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$25754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$22035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$29071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$9355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$18324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$22300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$22293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17513.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$20036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$28966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$18395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12501.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$24541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$28875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6504.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$25625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$28854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$17487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$17441.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$27012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$19708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$9742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$19178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$17555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$19687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$9838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$20356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9877.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$9881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$18545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$21653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$14900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$9997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$9969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger196407$10013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$10019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$25426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$28526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$21802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$26766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$14980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$26735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$12939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$10062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$26702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$28440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$17665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$196408$lut$aiger$o6070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$10156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$10177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$10171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$13410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$10184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$22014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$25352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$12899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$13024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$28381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o7151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o6189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$13093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$10326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$13060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o5304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o7143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$16695.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$15148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$10387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$24282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$10421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$28292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$13147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$10466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$16674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o7398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o6514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o6101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$20567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$22920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o5433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger196407$22107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger$o5433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$196653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$24256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$19779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$10617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$26538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger$o5769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$196408$lut$aiger$o5769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$197104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$196408$lut$aiger196407$7037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$6987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$14146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$13819.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$6959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$196408$lut$aiger196407$7161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Removed 0 unused cells and 15860 unused wires. 20.50. Executing AUTONAME pass. Renamed 21055 objects in module spi_neuron_top. 20.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `spi_neuron_top'. Setting top module to spi_neuron_top. 20.51.1. Analyzing design hierarchy.. Top module: \spi_neuron_top 20.51.2. Analyzing design hierarchy.. Top module: \spi_neuron_top Removed 0 unused modules. 20.52. Printing statistics. === spi_neuron_top === +----------Local Count, excluding submodules. | 7504 wires 30084 wire bits 7504 public wires 30084 public wire bits 20 ports 57 port bits 69 cells 16 $_TBUF_ 35 $scopeinfo 2 DP16KD 16 MULT18X18D 14470 submodules 556 CCU2C 58 L6MUX21 7795 LUT4 1161 PFUMX 4900 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 69 spi_neuron_top +----------Count including submodules. | 7504 wires 30084 wire bits 7504 public wires 30084 public wire bits 20 ports 57 port bits - memories - memory bits - processes 69 cells 16 $_TBUF_ 35 $scopeinfo 2 DP16KD 16 MULT18X18D 14470 submodules 556 CCU2C 58 L6MUX21 7795 LUT4 1161 PFUMX 4900 TRELLIS_FF 20.53. Executing CHECK pass (checking for obvious problems). Checking module spi_neuron_top... Found and reported 0 problems. 20.54. Executing JSON backend. Warnings: 1 unique messages, 1 total End of script. Logfile hash: 8c4127eaf5, time: 6.32s, user: 3.92s, system: 0.12s, MEM: 365.02 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 40% 1x abc9_exe (2 sec), 9% 12x techmap (0 sec), ...