Info: Logic utilisation before packing:
Info:     Total LUT4s:        70/43848     0%
Info:         logic LUTs:     46/43848     0%
Info:         carry LUTs:      0/43848     0%
Info:           RAM LUTs:     16/ 5481     0%
Info:          RAMW LUTs:      8/10962     0%

Info:      Total DFFs:        69/43848     0%

Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     30 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x405aa89a

Info: Device utilisation:
Info: 	          TRELLIS_IO:      18/    245     7%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       0/    108     0%
Info: 	          MULT18X18D:       0/     72     0%
Info: 	              ALU54B:       0/     36     0%
Info: 	             EHXPLLL:       0/      4     0%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    160     0%
Info: 	            SIOLOGIC:       0/     85     0%
Info: 	                 GSR:       0/      1     0%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     10     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:      69/  43848     0%
Info: 	        TRELLIS_COMB:      72/  43848     0%
Info: 	        TRELLIS_RAMW:       4/   5481     0%

Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 74 cells, random placement wirelen = 6821.
Info:     at initial placer iter 0, wirelen = 1333
Info:     at initial placer iter 1, wirelen = 948
Info:     at initial placer iter 2, wirelen = 883
Info:     at initial placer iter 3, wirelen = 855
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type ALL: wirelen solved = 852, spread = 934, legal = 1006; time = 0.00s
Info: HeAP Placer Time: 0.02s
Info:   of which solving equations: 0.00s
Info:   of which spreading cells: 0.00s
Info:   of which strict legalisation: 0.00s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 15, wirelen = 1006
Info:   at iteration #5: temp = 0.000000, timing cost = 14, wirelen = 654
Info:   at iteration #10: temp = 0.000000, timing cost = 13, wirelen = 644
Info:   at iteration #14: temp = 0.000000, timing cost = 13, wirelen = 643 
Info: SA placement time 0.02s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 292.48 MHz (PASS at 80.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.44 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 6.59 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [  9081,   9214) |* 
Info: [  9214,   9347) | 
Info: [  9347,   9480) | 
Info: [  9480,   9613) | 
Info: [  9613,   9746) | 
Info: [  9746,   9879) | 
Info: [  9879,  10012) | 
Info: [ 10012,  10145) | 
Info: [ 10145,  10278) |*** 
Info: [ 10278,  10411) |***** 
Info: [ 10411,  10544) |**** 
Info: [ 10544,  10677) |********** 
Info: [ 10677,  10810) |**************** 
Info: [ 10810,  10943) |********************** 
Info: [ 10943,  11076) |******************************* 
Info: [ 11076,  11209) |************ 
Info: [ 11209,  11342) |** 
Info: [ 11342,  11475) |************** 
Info: [ 11475,  11608) |***** 
Info: [ 11608,  11741) |********************************* 
Info: Checksum: 0x784333ab
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 464 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        558 |       88        455 |   88   455 |         0|       0.04       0.04|
Info: Routing complete.
Info: Router1 time 0.04s
Info: Checksum: 0x7e03b65b

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info:       type curr  total name
Info:   clk-to-q  0.40  0.40 Source lfsr_TRELLIS_FF_Q_3.Q
Info:    routing  0.76  1.15 Net fill_data[38] (2,33) -> (2,32)
Info:                          Sink dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.A
Info:                          Defined in:
Info:                               hardware/v2/nms/synthesis/harness_nms_activation_banked.v:34.28-34.45
Info:      logic  0.18  1.34 Source dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info:    routing  0.00  1.34 Net dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT (2,32) -> (2,32)
Info:                          Sink dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                          Defined in:
Info:                               /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32
Info:      logic  0.13  1.46 Source dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:    routing  0.00  1.46 Net dut.win_tile_idx[1]_L6MUX21_Z_1_D1 (2,32) -> (2,32)
Info:                          Sink dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                          Defined in:
Info:                               /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40
Info:      logic  0.18  1.64 Source dut.win_tile_idx[1]_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:    routing  0.67  2.31 Net dut.ack_stage1_TRELLIS_FF_Q_DI_PFUMX_Z_ALUT_LUT4_Z_C[3] (2,32) -> (2,31)
Info:                          Sink dut.ack_stage1_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.D
Info:                          Defined in:
Info:                               hardware/v2/nms/rtl/nms_activation_banked.v:85.20-85.32
Info:      logic  0.31  2.62 Source dut.ack_stage1_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:    routing  0.32  2.94 Net dut.ack_stage1_TRELLIS_FF_Q_DI (2,31) -> (3,31)
Info:                          Sink dut.ack_stage1_TRELLIS_FF_Q.M
Info:      setup  0.00  2.94 Source dut.ack_stage1_TRELLIS_FF_Q.M
Info: 1.19 ns logic, 1.76 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info:       type curr  total name
Info:     source  0.00  0.00 Source rst$tr_io.O
Info:    routing  4.25  4.25 Net rst$TRELLIS_IO_IN (42,0) -> (2,33)
Info:                          Sink seed_LUT4_B_Z_LUT4_Z_3.C
Info:                          Defined in:
Info:                               hardware/v2/nms/synthesis/harness_nms_activation_banked.v:18.17-18.20
Info:      logic  0.18  4.43 Source seed_LUT4_B_Z_LUT4_Z_3.F
Info:    routing  0.12  4.55 Net seed_LUT4_B_Z[5] (2,33) -> (2,33)
Info:                          Sink lfsr_TRELLIS_FF_Q_2.DI
Info:      setup  0.00  4.55 Source lfsr_TRELLIS_FF_Q_2.DI
Info: 0.18 ns logic, 4.36 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info:       type curr  total name
Info:   clk-to-q  0.40  0.40 Source chk_TRELLIS_FF_Q_5.Q
Info:    routing  3.81  4.21 Net checksum[4]$TRELLIS_IO_OUT (3,30) -> (90,29)
Info:                          Sink checksum[4]$tr_io.I
Info:                          Defined in:
Info:                               hardware/v2/nms/synthesis/harness_nms_activation_banked.v:48.15-48.18
Info: 0.40 ns logic, 3.81 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 339.79 MHz (PASS at 80.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.55 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 4.21 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [  9557,   9669) |* 
Info: [  9669,   9781) | 
Info: [  9781,   9893) | 
Info: [  9893,  10005) | 
Info: [ 10005,  10117) | 
Info: [ 10117,  10229) | 
Info: [ 10229,  10341) |** 
Info: [ 10341,  10453) |* 
Info: [ 10453,  10565) |***** 
Info: [ 10565,  10677) |***** 
Info: [ 10677,  10789) |** 
Info: [ 10789,  10901) |**************** 
Info: [ 10901,  11013) |************************** 
Info: [ 11013,  11125) |*********************** 
Info: [ 11125,  11237) |*************** 
Info: [ 11237,  11349) |************************* 
Info: [ 11349,  11461) |********* 
Info: [ 11461,  11573) |****** 
Info: [ 11573,  11685) |********* 
Info: [ 11685,  11797) |************* 

Info: Program finished normally.