# V2 simulation log -- solo append, mai troncato/sovrascritto (vedi README.md)
# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.

[2026-09-05] EXP-0001/EXP-0002 -- hardware/v2/sim/tb_neural_processor.v
test: 7 cases (16/32/8/8/8/8/64-input jobs; ACT_NONE + ACT_RELU;
  extreme INT8 saturation; back-to-back zero-idle-gap tiles)
vectors: regular positive, mixed-sign cancellation, extreme INT8
  (-128,-127,-1,0,1,126,127,127 in one 8-lane tile), back-to-back
  jobs, 8-tile (64-input) job
simulator: Verilator 5.050 (--binary --timing) -- see decisions.log
  DEC-0004 for why Icarus v13.0 is not trusted for this testbench
cycles: not separately profiled at this milestone (throughput/stall
  cycle counting deferred to M9 per §22)
PASS/FAIL: 7/7 PASS (ACC_WIDTH=32); 7/7 PASS (ACC_WIDTH=24, EXP-0002)
bit-exact result: V1.y === V2.result_data for every case, both widths
stall cycles / memory wait / utilization: N/A (no Memory Manager yet,
  M1 operands fed directly by testbench per the roadmap)

[2026-09-05] EXP-0003 -- hardware/v2/sim/tb_neural_processor_array.v
(N_PROCESSORS=4)
test: 7 cases (single-processor sanity; 4-way same-cycle concurrent
  launch with different tile counts; staggered-start 2-processor test)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 7/7 PASS
bit-exact result: N/A at this milestone (hand-computed expected
  values, arithmetic itself already bit-exact-certified vs V1 at M1)
concurrency: confirmed genuine -- in the staggered test, the
  later-launched, shorter job (processor 1) completes BEFORE the
  earlier-launched, longer job (processor 0), proving independent
  progress rather than serialization.

[2026-09-05] EXP-0004 -- hardware/v2/sim/tb_buffers.v
test: 10 cases across activation_buffer/weight_buffer/result_buffer
vectors: extreme INT8 (-128, 127, -100, 100), regular values, full
  64-bit tile round-trip (weight_buffer), re-reads confirming earlier
  writes undisturbed
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 10/10 PASS

[2026-09-05] EXP-0005 -- hardware/v2/sim/tb_memory_manager.v
test: 3 end-to-end jobs (3-tile/saturating, 1-tile/non-saturating,
  5-tile/steady-state-swap), real V1 PSRAM backend chain (unmodified),
  real M1 neural_processor
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 3/3 PASS
bit-exact result: PSRAM-read-back result byte matches hand-computed
  expectation in every case (independent oracle, not derived from the
  RTL under test)
cycles: 446 (3 tiles), 166 (1 tile), 728 (5 tiles) -- real PSRAM
  latency dominates, not memory_manager's own control overhead

[2026-09-05] EXP-0006 -- hardware/v2/sim/tb_neural_director.v
test: 4 cases (3-jobs-2-slots first-free dispatch + queueing,
  backpressure fill/recover)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 4/4 PASS

[2026-09-05] EXP-0007 -- hardware/v2/sim/tb_dependency_manager.v
test: 4 cases on a 4-node DAG (2 independent + 1 dual-dependency +
  1 single-dependency-shared-producer)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 4/4 PASS

[2026-09-05] EXP-0008 -- hardware/v2/sim/tb_dataflow_core.v
test: full end-to-end M1-M6 integration through dataflow_core.v (M7),
  a 3-node DAG (node0/node1 independent, node2 depends on BOTH) run
  through the REAL dependency_manager -> neural_director -> N_SLOTS x
  (memory_manager + neural_processor) chain for the first time, each
  slot backed by its own independent behavioral byte memory
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 4/4 PASS -- node0=48, node1=8 (both real neural_processor
  computations via the full stack), node2=40 dispatched only after
  BOTH node0 and node1 genuinely completed (continuously polled every
  cycle up to completion, not just checked at the end) -- the
  dependency-manager-to-director wake-up loop closes correctly
  end-to-end with real hardware in between, not just in isolation
  (M6's own testbench already proved the wake-up logic alone)

[2026-09-05] EXP-0009 -- hardware/v2/sim/tb_neural_multiprocessor.v
test: same 3-node DAG as EXP-0008 (node0/node1 independent, node2
  depends on both), routed through neural_multiprocessor.v (M8): the
  REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access ->
  memory_interface -> psram_controller -> psram_model) shared across
  N_SLOTS=2 genuinely concurrent memory_manager instances via the new
  slot_mem_arbiter.v -- node0 and node1 are registered back-to-back
  with no dependencies, so both dispatch to their slots essentially
  simultaneously and genuinely contend for the one real PSRAM port.
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 4/4 PASS after fixing a real dropped-request bug in the
  first arbiter draft (errors.log ERR-0008) -- node0=48, node1=8
  (concurrent, real PSRAM, real arbitration), node2=40 dispatched only
  after both genuinely completed. 444 cycles end-to-end (vs 20000-cycle
  watchdog timeout with the buggy first draft, where node1's request
  was silently dropped and its slot hung forever).
regression: hardware/v2/sim/tb_memory_manager.v (M4) re-run unchanged
  (no M4 file touched) -- still 3/3 PASS, identical cycle counts
  (446/166/728), confirming slot_mem_arbiter.v is purely additive.

[2026-09-05] EXP-0013 -- hardware/v2/sim/tb_neural_multiprocessor.v,
M10 cycle-accounting instrumentation (closes decisions.log DEC-0011's
deferred stall %/utilization gap with real data, testbench-only
addition, no RTL touched)
test: same EXP-0009 scenario (3-node DAG, N_SLOTS=2, real V1 PSRAM
  chain, real slot_mem_arbiter contention), instrumented with cycle
  counters (shared PSRAM port busy cycles via
  u_nmp.u_arbiter.owner!=0, each slot's memory_manager busy cycles via
  its own state!=MM_IDLE), measured from the first node registration
  to test completion.
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 4/4 PASS (unchanged from EXP-0009), plus real measured
  data: 684 total cycles measured; shared PSRAM port busy 559/684
  (81.7% utilization, 18.3% idle); slot 0 (memory_manager) busy
  651/684 (95.2%); slot 1 (memory_manager) busy 446/684 (65.2%).
note: slot 0's higher utilization is at least partly explained by it
  serving TWO sequential jobs in this run (node0, then whichever slot
  frees first serves node2 -- likely slot 0, first-free/lowest-index)
  while slot 1 only ever serves node1 -- NOT conclusive evidence of
  harmful priority starvation on its own; see decisions.log DEC-0010's
  original fairness deferral, now informed by this real (if small)
  data point.

[2026-09-05] EXP-0014 -- hardware/v2/sim/tb_benchmark_suite.v (final
benchmark campaign, post-M10)
test: 6 workloads (16/64/128/256 independent neurons + 10-node
  multilayer with random data + 6-node 2-hop DAG), each bit-exact
  verified against a software golden model, at N_SLOTS=1/2/4/8 (24
  total runs) through the real full neural_multiprocessor.v (real V1
  PSRAM chain, real slot_mem_arbiter)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 24/24 PASS bit-exact (11,520 individual neuron/node
  comparisons, zero mismatches) after fixing 3 real issues found
  during this campaign (errors.log ERR-0009: 1 real RTL bug in
  neural_director.v at N_SLOTS=1, never exercised before; 2 testbench
  sizing bugs -- psram_model DEPTH too small, N_NODES too small
  causing a real node-id wraparound deadlock)
full data/analysis: hardware/v2/docs/benchmarks/final-benchmark.md

[2026-09-05] EXP-0015 -- regression + real improvement measurement
after word-level burst-read rewrite (DEC-0015)
test: hardware/v2/sim/tb_memory_manager.v (M4, updated to connect
  memory_manager directly to memory_interface.v, skipping
  int8_memory_access.v), hardware/v2/sim/tb_dataflow_core.v (M7,
  sim_byte_mem -> sim_word_mem), hardware/v2/sim/tb_neural_multiprocessor.v
  (M8, UNCHANGED -- black-box on neural_multiprocessor.v, no edits
  needed), hardware/v2/sim/tb_benchmark_suite.v (final campaign,
  UNCHANGED, re-run at N_SLOTS=1/2/4/8)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: M4 3/3 PASS (166/446/728 -> 84/204/322 cycles, bit-exact).
  M7 4/4 PASS (wd=67->43 cycles to first dependency check). M8 4/4
  PASS (684->337 cycles). Final campaign 24/24 PASS bit-exact,
  D-Stress cycles roughly halved to a bit more at every N_SLOTS
  (see benchmark.log EXP-0015 for the full table).
errors: none found during this implementation (clean first-pass
  correctness at every regression point).

[2026-09-05] EXP-0016 -- regression + real improvement measurement
after adding shared activation_cache.v (DEC-0016)
test: hardware/v2/sim/tb_memory_manager.v (M4, updated: memory_manager
  now wired to a real activation_cache instance + a real 2-port
  arbiter, N_SLOTS=1 scope), hardware/v2/sim/tb_dataflow_core.v (M7,
  updated: sim_word_mem array widened to N_SLOTS+1, X data poked once
  into the shared cache's own backing memory instead of duplicated
  per-slot), hardware/v2/sim/tb_neural_multiprocessor.v (M8,
  UNCHANGED -- black-box), hardware/v2/sim/tb_benchmark_suite.v (final
  campaign, UNCHANGED, re-run at N_SLOTS=1/2/4/8)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: M4 3/3 PASS (bit-exact, cycle counts higher than DEC-0015
  alone for this SPECIFIC single-instance test -- expected, no sharing
  benefit possible with only one memory_manager, only the cache's real
  arbitration overhead shows up here). M7 4/4 PASS. M8 4/4 PASS
  (unchanged testbench). Final campaign 24/24 PASS bit-exact,
  D-Stress cycles reduced a further 1.66-2.00x on top of DEC-0015's
  own reduction (see benchmark.log EXP-0016 for the full table) --
  the real sharing benefit this cache targets only manifests with
  multiple neurons genuinely sharing one x_base, which only the full
  campaign's dense-layer workloads (not M4/M7/M8's own small tests)
  exercise.
errors: 2 real bugs found and fixed during implementation (errors.log
  ERR-0010): a target-bank/pending-bank race (same class as ERR-0006,
  a new instance in the activation-cache side of memory_manager.v),
  and a repeat of ERR-0009's N_SLOTS=1 zero-width replication bug
  (this time in activation_cache.v itself).