Info: Logic utilisation before packing: Info: Total LUT4s: 40/43848 0% Info: logic LUTs: 16/43848 0% Info: carry LUTs: 0/43848 0% Info: RAM LUTs: 16/ 5481 0% Info: RAMW LUTs: 8/10962 0% Info: Total DFFs: 56/43848 0% Info: Packing IOs.. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 32 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0xd1317d1e Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 56/ 43848 0% Info: TRELLIS_COMB: 42/ 43848 0% Info: TRELLIS_RAMW: 4/ 5481 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 45 cells, random placement wirelen = 4304. Info: at initial placer iter 0, wirelen = 1329 Info: at initial placer iter 1, wirelen = 1030 Info: at initial placer iter 2, wirelen = 966 Info: at initial placer iter 3, wirelen = 959 Info: Running main analytical placer, max placement attempts per cell = 10000. Info: at iteration #1, type ALL: wirelen solved = 956, spread = 1017, legal = 1022; time = 0.00s Info: HeAP Placer Time: 0.02s Info: of which solving equations: 0.00s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 19, wirelen = 1022 Info: at iteration #5: temp = 0.000000, timing cost = 24, wirelen = 822 Info: at iteration #10: temp = 0.000000, timing cost = 20, wirelen = 797 Info: at iteration #12: temp = 0.000000, timing cost = 28, wirelen = 806 Info: SA placement time 0.01s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 654.02 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.40 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.67 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 10971, 11010) |******************* Info: [ 11010, 11049) | Info: [ 11049, 11088) |****** Info: [ 11088, 11127) |******************************* Info: [ 11127, 11166) | Info: [ 11166, 11205) |****** Info: [ 11205, 11244) |**************************** Info: [ 11244, 11283) | Info: [ 11283, 11322) |********** Info: [ 11322, 11361) |**** Info: [ 11361, 11400) |**** Info: [ 11400, 11439) |******** Info: [ 11439, 11478) | Info: [ 11478, 11517) |****** Info: [ 11517, 11556) |** Info: [ 11556, 11595) | Info: [ 11595, 11634) |************* Info: [ 11634, 11673) | Info: [ 11673, 11712) | Info: [ 11712, 11751) |************* Info: Checksum: 0x5249d1ff Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 300 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 324 | 23 301 | 23 301 | 0| 0.09 0.09| Info: Routing complete. Info: Router1 time 0.09s Info: Checksum: 0xb595ea98 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.40 0.40 Source lfsr_TRELLIS_FF_Q_13.Q Info: routing 0.94 1.33 Net fill_addr[1] (34,35) -> (36,36) Info: Sink dut.GEN_COPY[0].mem.0.1$DPRAM_COMB1.B Info: Defined in: Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:37.24-37.29 Info: logic 0.18 1.51 Source dut.GEN_COPY[0].mem.0.1$DPRAM_COMB1.F Info: routing 0.12 1.63 Net dut.GEN_COPY[0].mem.0.0_DO[5] (36,36) -> (36,36) Info: Sink dut.GEN_COPY[0].rd_data_reg_TRELLIS_FF_Q_6.DI Info: setup 0.00 1.63 Source dut.GEN_COPY[0].rd_data_reg_TRELLIS_FF_Q_6.DI Info: 0.57 ns logic, 1.05 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source rst$tr_io.O Info: routing 2.96 2.96 Net rst$TRELLIS_IO_IN (0,38) -> (36,37) Info: Sink seed_LUT4_B_Z_LUT4_Z_1.C Info: Defined in: Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:22.17-22.20 Info: logic 0.18 3.14 Source seed_LUT4_B_Z_LUT4_Z_1.F Info: routing 0.12 3.26 Net seed_LUT4_B_Z[7] (36,37) -> (36,37) Info: Sink lfsr_TRELLIS_FF_Q_24.DI Info: setup 0.00 3.26 Source lfsr_TRELLIS_FF_Q_24.DI Info: 0.18 ns logic, 3.08 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_2.Q Info: routing 2.77 3.16 Net checksum[2]$TRELLIS_IO_OUT (32,36) -> (42,0) Info: Sink checksum[2]$tr_io.I Info: Defined in: Info: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:50.15-50.18 Info: 0.40 ns logic, 2.77 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 613.87 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.26 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 3.16 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 10871, 10918) |************* Info: [ 10918, 10965) |*** Info: [ 10965, 11012) |** Info: [ 11012, 11059) | Info: [ 11059, 11106) |****** Info: [ 11106, 11153) |************** Info: [ 11153, 11200) |************************ Info: [ 11200, 11247) |****** Info: [ 11247, 11294) |** Info: [ 11294, 11341) |******************** Info: [ 11341, 11388) |**************** Info: [ 11388, 11435) |****** Info: [ 11435, 11482) |** Info: [ 11482, 11529) |*** Info: [ 11529, 11576) |*** Info: [ 11576, 11623) |********** Info: [ 11623, 11670) | Info: [ 11670, 11717) |****** Info: [ 11717, 11764) |*** Info: [ 11764, 11811) |*********** Info: Program finished normally.