/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Executing script file `synth/ecp5/spi_neuron_top_p2/synth.ys' -- 1. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v' to AST representation. Generating RTLIL representation for module `\spi_slave'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v' to AST representation. Generating RTLIL representation for module `\spi_engine'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v' to AST representation. Generating RTLIL representation for module `\layer_sequencer'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v' to AST representation. Generating RTLIL representation for module `\mem_arbiter'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v' to AST representation. Generating RTLIL representation for module `\neuron_memory'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v' to AST representation. Generating RTLIL representation for module `\int8_memory_access'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v' to AST representation. Generating RTLIL representation for module `\memory_interface'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v' to AST representation. /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:93: Warning: Yosys has only limited support for tri-state logic at the moment. Generating RTLIL representation for module `\psram_controller'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v' to AST representation. Generating RTLIL representation for module `\neuron_parallel'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v' to AST representation. Generating RTLIL representation for module `\mac8'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v' to AST representation. Generating RTLIL representation for module `\mac_unit'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v' to AST representation. Generating RTLIL representation for module `\spi_neuron_top'. Successfully finished Verilog frontend. Parameter \PARALLEL = 2 13. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_neuron_top'. Parameter \PARALLEL = 2 Generating RTLIL representation for module `$paramod\spi_neuron_top\PARALLEL=s32'00000000000000000000000000000010'. 14. Executing HIERARCHY pass (managing design hierarchy). 14.1. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: \spi_slave Used module: \spi_engine Used module: \layer_sequencer Used module: \neuron_memory Used module: \neuron_parallel Used module: \mac8 Used module: \mac_unit Used module: \int8_memory_access Used module: \mem_arbiter Used module: \memory_interface Used module: \psram_controller Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \PARALLEL = 8 Parameter \ACC_WIDTH = 32 14.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'. Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \PARALLEL = 8 Parameter \ACC_WIDTH = 32 Generating RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'. Parameter \ADDR_WIDTH = 22 14.3. Executing AST frontend in derive mode using pre-parsed AST for module `\int8_memory_access'. Parameter \ADDR_WIDTH = 22 Generating RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Parameter \PARALLEL = 8 14.4. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Parameter \PARALLEL = 8 Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 14.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Generating RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Reprocessing module mac8 because instantiated module mac_unit has become available. Generating RTLIL representation for module `\mac8'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \N_NEURONS = 1 Parameter \PARALLEL = 2 14.6. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_engine'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \N_NEURONS = 1 Parameter \PARALLEL = 2 Generating RTLIL representation for module `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 8 Parameter \N_WIDTH = 1 Parameter \N_LAYERS = 4 14.7. Executing AST frontend in derive mode using pre-parsed AST for module `\layer_sequencer'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 8 Parameter \N_WIDTH = 1 Parameter \N_LAYERS = 4 Generating RTLIL representation for module `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \N_NEURONS = 1 Parameter \PARALLEL = 2 Parameter \ACC_WIDTH = 32 14.8. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_memory'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \N_NEURONS = 1 Parameter \PARALLEL = 2 Parameter \ACC_WIDTH = 32 Generating RTLIL representation for module `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory'. Parameter \ADDR_WIDTH = 22 14.9. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_arbiter'. Parameter \ADDR_WIDTH = 22 Generating RTLIL representation for module `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110'. Parameter \ADDR_WIDTH = 22 Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 16 14.10. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_interface'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 16 Generating RTLIL representation for module `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 16 Parameter \CLK_FREQ_MHZ = 80 14.11. Executing AST frontend in derive mode using pre-parsed AST for module `\psram_controller'. Parameter \ADDR_WIDTH = 22 Parameter \DATA_WIDTH = 16 Parameter \CLK_FREQ_MHZ = 80 Generating RTLIL representation for module `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller'. 14.12. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: \spi_slave Used module: $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer Used module: $paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory Used module: \neuron_parallel Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 Used module: \mac_unit Used module: \int8_memory_access Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 14.13. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Generating RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Reprocessing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 because instantiated module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit has become available. Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'. Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \PARALLEL = 2 Parameter \ACC_WIDTH = 32 14.14. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'. Parameter \DATA_WIDTH = 8 Parameter \N_INPUTS = 32 Parameter \PARALLEL = 2 Parameter \ACC_WIDTH = 32 Generating RTLIL representation for module `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel'. Parameter \ADDR_WIDTH = 22 Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110'. 14.15. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: \spi_slave Used module: $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer Used module: $paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel Used module: \mac8 Used module: \mac_unit Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 16 Parameter \ACC_WIDTH = 40 Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Parameter \PARALLEL = 2 14.16. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Parameter \PARALLEL = 2 Generating RTLIL representation for module `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8'. 14.17. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: \spi_slave Used module: $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer Used module: $paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8 Used module: \mac_unit Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. Parameter \DATA_WIDTH = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'. 14.18. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: \spi_slave Used module: $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer Used module: $paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8 Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller 14.19. Analyzing design hierarchy.. Top module: \spi_neuron_top Used module: \spi_slave Used module: $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine Used module: $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer Used module: $paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8 Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110 Used module: $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface Used module: $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller Removing unused module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'. Removing unused module `\mac8'. Removing unused module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'. Removing unused module `\mac_unit'. Removing unused module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'. Removing unused module `\neuron_parallel'. Removing unused module `\psram_controller'. Removing unused module `\memory_interface'. Removing unused module `\int8_memory_access'. Removing unused module `\neuron_memory'. Removing unused module `\mem_arbiter'. Removing unused module `\layer_sequencer'. Removing unused module `\spi_engine'. Removed 13 unused modules. 15. Executing PROC pass (convert processes to netlists). 15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 2 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544 in module $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface. Removed 1 dead cases from process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110. Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110. Marked 8 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426 in module $paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory. Marked 5 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402 in module $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer. Marked 12 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383 in module $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine. Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:222$378 in module $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine. Marked 3 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:201$376 in module $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine. Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547 in module $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller. Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278 in module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110. Marked 8 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628 in module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel. Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12 in module spi_slave. Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2 in module spi_slave. Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1 in module spi_slave. Removed a total of 1 dead cases. 15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 36 redundant assignments. Promoted 17 assignments to connections. 15.4. Executing PROC_INIT pass (extract init attributes). 15.5. Executing PROC_ARST pass (detect async resets in processes). 15.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 1 switch. 15.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. 1/9: $0\mem_req[0:0] 2/9: $0\ready[0:0] 3/9: $0\mem_ub_n[0:0] 4/9: $0\mem_lb_n[0:0] 5/9: $0\rdata[15:0] 6/9: $0\mem_wdata[15:0] 7/9: $0\mem_addr[21:0] 8/9: $0\mem_wr[0:0] 9/9: $0\state[1:0] Creating decoders for process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. 1/11: $0\c_ready[0:0] 2/11: $0\b_ready[0:0] 3/11: $0\a_ready[0:0] 4/11: $0\m_req[0:0] 5/11: $0\owner[1:0] 6/11: $0\m_wdata[7:0] 7/11: $0\m_addr[21:0] 8/11: $0\m_wr[0:0] 9/11: $0\c_rdata[7:0] 10/11: $0\b_rdata[7:0] 11/11: $0\a_rdata[7:0] Creating decoders for process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. 1/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_EN[7:0]$472 2/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_DATA[7:0]$471 3/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_ADDR[0:0]$470 4/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_EN[7:0]$465 5/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$464 6/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_ADDR[5:0]$463 7/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_EN[7:0]$458 8/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$457 9/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_ADDR[5:0]$456 10/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_EN[7:0]$455 11/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_DATA[7:0]$454 12/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_ADDR[0:0]$453 13/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_EN[7:0]$452 14/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$451 15/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_ADDR[5:0]$450 16/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_EN[7:0]$449 17/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$448 18/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_ADDR[5:0]$447 19/42: $0\done[0:0] 20/42: $1\rst_i[31:0] 21/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:288$421_EN[7:0]$437 22/42: $0\neuron_start[0:0] 23/42: $0\access_req[0:0] 24/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_EN[7:0]$446 25/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_DATA[7:0]$445 26/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_ADDR[0:0]$444 27/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_EN[7:0]$443 28/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$442 29/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_ADDR[5:0]$441 30/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_EN[7:0]$440 31/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$439 32/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_ADDR[5:0]$438 33/42: $0\access_wdata[7:0] 34/42: $0\access_addr[21:0] 35/42: $0\access_wr[0:0] 36/42: $0\bias_reg[7:0] 37/42: $0\bias_group_addr[21:0] 38/42: $0\w_group_base[21:0] 39/42: $0\neuron_index[0:0] 40/42: $0\index[5:0] 41/42: $0\busy[0:0] 42/42: $0\state[3:0] Creating decoders for process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. 1/26: $0\bias_addr_acc[23:0] [15:8] 2/26: $0\bias_addr_acc[23:0] [7:0] 3/26: $0\bias_addr_acc[23:0] [23:16] 4/26: $0\w_base_acc[23:0] [7:0] 5/26: $0\w_base_acc[23:0] [23:16] 6/26: $0\ram_req[0:0] 7/26: $0\nm_start[0:0] 8/26: $0\copy_idx[0:0] 9/26: $0\write_sel[0:0] 10/26: $0\cur_sel[0:0] 11/26: $0\activation_acc[7:0] 12/26: $0\w_base_acc[23:0] [15:8] 13/26: $0\seq_done[0:0] 14/26: $0\desc_byte_idx[2:0] 15/26: $0\desc_table_addr[21:0] 16/26: $0\num_layers_reg[7:0] 17/26: $0\layer_idx[7:0] 18/26: $0\nm_activation[1:0] 19/26: $0\nm_bias_addr[21:0] 20/26: $0\nm_w_base[21:0] 21/26: $0\nm_x_base[21:0] 22/26: $0\state[3:0] 23/26: $0\seq_busy[0:0] 24/26: $0\ram_wdata[7:0] 25/26: $0\ram_addr[21:0] 26/26: $0\ram_wr[0:0] Creating decoders for process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. 1/30: $0\len_acc[15:0] [15:8] 2/30: $0\len_acc[15:0] [7:0] 3/30: $0\nm_soft_rst[0:0] 4/30: $0\nm_start[0:0] 5/30: $0\ram_req[0:0] 6/30: $0\status_snapshot[7:0] 7/30: $0\net_mode[0:0] 8/30: $0\resp_len[3:0] 9/30: $0\resp_index[3:0] 10/30: $0\cur_read_byte[7:0] 11/30: $0\pending_wdata[7:0] 12/30: $0\pending_write[0:0] 13/30: $0\cur_addr[21:0] 14/30: $0\len_remaining[15:0] 15/30: $0\run_start[0:0] 16/30: $0\addr_acc[23:0] 17/30: $0\byte_pos[1:0] 18/30: $0\opcode[7:0] 19/30: $0\state[3:0] 20/30: $0\run_num_layers[7:0] 21/30: $0\buf_b_base[21:0] 22/30: $0\buf_a_base[21:0] 23/30: $0\table_base[21:0] 24/30: $0\activation[1:0] 25/30: $0\bias_addr[21:0] 26/30: $0\w_base[21:0] 27/30: $0\x_base[21:0] 28/30: $0\ram_wdata[7:0] 29/30: $0\ram_addr[21:0] 30/30: $0\ram_wr[0:0] Creating decoders for process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:222$378'. 1/4: $4\tx_byte_comb[7:0] 2/4: $3\tx_byte_comb[7:0] 3/4: $2\tx_byte_comb[7:0] 4/4: $1\tx_byte_comb[7:0] Creating decoders for process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:201$376'. 1/1: $0\status_done_sticky[0:0] Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$650'. Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$649'. Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$648'. Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$647'. Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$646'. Creating decoders for process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. 1/18: $0\dq_oe[0:0] 2/18: $0\psram_zz_n[0:0] 3/18: $0\psram_ub_n[0:0] 4/18: $0\psram_lb_n[0:0] 5/18: $0\psram_we_n[0:0] 6/18: $0\psram_oe_n[0:0] 7/18: $0\psram_ce_n[0:0] 8/18: $0\mem_ready[0:0] 9/18: $0\dq_out[15:0] 10/18: $0\ub_reg[0:0] 11/18: $0\lb_reg[0:0] 12/18: $0\wr_reg[0:0] 13/18: $0\wdata_reg[15:0] 14/18: $0\address_reg[21:0] 15/18: $0\counter[13:0] 16/18: $0\psram_a[21:0] 17/18: $0\mem_rdata[15:0] 18/18: $0\state[2:0] Creating decoders for process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. 1/10: $0\mem_req[0:0] 2/10: $0\ready[0:0] 3/10: $0\addr_reg[21:0] 4/10: $0\mem_ub_n[0:0] 5/10: $0\mem_lb_n[0:0] 6/10: $0\rdata[7:0] 7/10: $0\mem_wdata[15:0] 8/10: $0\mem_addr[21:0] 9/10: $0\mem_wr[0:0] 10/10: $0\state[1:0] Creating decoders for process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628'. 1/5: $0\done[0:0] 2/5: $0\acc[31:0] 3/5: $0\group_index[3:0] 4/5: $0\busy[0:0] 5/5: $0\y[7:0] Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. 1/9: $0\cs_end[0:0] 2/9: $0\cs_start[0:0] 3/9: $0\tx_byte_req[0:0] 4/9: $0\rx_valid[0:0] 5/9: $0\tx_shift[7:0] 6/9: $0\rx_shift[7:0] 7/9: $0\bit_count[2:0] 8/9: $0\rx_byte[7:0] 9/9: $0\miso[0:0] Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'. 1/2: $0\cs_n_prev[0:0] 2/2: $0\sclk_prev[0:0] Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'. 1/3: $0\cs_n_sync[2:0] 2/3: $0\mosi_sync[2:0] 3/3: $0\sclk_sync[2:0] 15.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\tx_byte_comb' from process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:222$378'. No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[2]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$650'. No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[1]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$649'. No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[0]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$648'. No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\products[1]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$647'. No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\products[0]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$646'. 15.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\state' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3101' with positive edge clock. Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_req' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3102' with positive edge clock. Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_wr' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3103' with positive edge clock. Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_addr' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3104' with positive edge clock. Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_wdata' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3105' with positive edge clock. Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\rdata' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3106' with positive edge clock. Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\ready' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3107' with positive edge clock. Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_lb_n' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3108' with positive edge clock. Creating register for signal `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.\mem_ub_n' using process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. created $dff cell `$procdff$3109' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\a_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3110' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\a_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3111' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\b_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3112' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\b_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3113' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\c_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3114' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\c_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3115' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\m_req' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3116' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\m_wr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3117' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\m_addr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3118' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\m_wdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3119' with positive edge clock. Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.\owner' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. created $dff cell `$procdff$3120' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\state' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3121' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\busy' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3122' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\done' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3123' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\index' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3124' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\neuron_index' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3125' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\w_group_base' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3126' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\bias_group_addr' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3127' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\bias_reg' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3128' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\access_req' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3129' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\access_wr' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3130' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\access_addr' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3131' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\access_wdata' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3132' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\neuron_start' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3133' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.\rst_i' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3134' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:288$421_EN' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3135' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_ADDR' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3136' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3137' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_EN' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3138' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_ADDR' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3139' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3140' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_EN' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3141' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_ADDR' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3142' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_DATA' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3143' with positive edge clock. Creating register for signal `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_EN' using process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. created $dff cell `$procdff$3144' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\ram_req' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3145' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\ram_wr' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3146' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\ram_addr' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3147' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\ram_wdata' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3148' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_start' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3149' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\seq_busy' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3150' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\seq_done' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3151' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\state' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3152' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_x_base' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3153' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_w_base' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3154' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_bias_addr' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3155' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\nm_activation' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3156' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\layer_idx' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3157' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\num_layers_reg' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3158' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\desc_table_addr' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3159' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\desc_byte_idx' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3160' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\w_base_acc' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3161' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\bias_addr_acc' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3162' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\activation_acc' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3163' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\cur_sel' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3164' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\write_sel' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3165' with positive edge clock. Creating register for signal `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.\copy_idx' using process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. created $dff cell `$procdff$3166' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\ram_req' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3167' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\ram_wr' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3168' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\ram_addr' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3169' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\ram_wdata' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3170' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\x_base' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3171' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\w_base' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3172' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\bias_addr' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3173' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\activation' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3174' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\nm_start' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3175' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\nm_soft_rst' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3176' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\table_base' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3177' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\buf_a_base' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3178' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\buf_b_base' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3179' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\run_start' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3180' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\run_num_layers' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3181' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\state' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3182' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\opcode' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3183' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\byte_pos' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3184' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\addr_acc' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3185' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\len_acc' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3186' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\len_remaining' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3187' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\cur_addr' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3188' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\pending_write' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3189' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\pending_wdata' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3190' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\cur_read_byte' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3191' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\resp_index' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3192' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\resp_len' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3193' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\net_mode' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3194' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\status_snapshot' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. created $dff cell `$procdff$3195' with positive edge clock. Creating register for signal `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.\status_done_sticky' using process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:201$376'. created $dff cell `$procdff$3196' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\state' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3197' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\mem_rdata' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3198' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\mem_ready' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3199' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_a' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3200' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_ce_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3201' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_oe_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3202' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_we_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3203' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_lb_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3204' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_ub_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3205' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\psram_zz_n' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3206' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\counter' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3207' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\address_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3208' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\wdata_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3209' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\wr_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3210' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\lb_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3211' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\ub_reg' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3212' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\dq_out' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3213' with positive edge clock. Creating register for signal `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.\dq_oe' using process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. created $dff cell `$procdff$3214' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\state' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3215' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_req' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3216' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_wr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3217' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_addr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3218' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_wdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3219' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\rdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3220' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\ready' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3221' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_lb_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3222' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\mem_ub_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3223' with positive edge clock. Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.\addr_reg' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. created $dff cell `$procdff$3224' with positive edge clock. Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\y' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628'. created $dff cell `$procdff$3225' with positive edge clock. Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\busy' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628'. created $dff cell `$procdff$3226' with positive edge clock. Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\done' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628'. created $dff cell `$procdff$3227' with positive edge clock. Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\group_index' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628'. created $dff cell `$procdff$3228' with positive edge clock. Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\acc' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628'. created $dff cell `$procdff$3229' with positive edge clock. Creating register for signal `\spi_slave.\miso' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3230' with positive edge clock. Creating register for signal `\spi_slave.\rx_byte' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3231' with positive edge clock. Creating register for signal `\spi_slave.\rx_valid' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3232' with positive edge clock. Creating register for signal `\spi_slave.\tx_byte_req' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3233' with positive edge clock. Creating register for signal `\spi_slave.\cs_start' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3234' with positive edge clock. Creating register for signal `\spi_slave.\cs_end' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3235' with positive edge clock. Creating register for signal `\spi_slave.\bit_count' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3236' with positive edge clock. Creating register for signal `\spi_slave.\rx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3237' with positive edge clock. Creating register for signal `\spi_slave.\tx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. created $dff cell `$procdff$3238' with positive edge clock. Creating register for signal `\spi_slave.\sclk_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'. created $dff cell `$procdff$3239' with positive edge clock. Creating register for signal `\spi_slave.\cs_n_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'. created $dff cell `$procdff$3240' with positive edge clock. Creating register for signal `\spi_slave.\sclk_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'. created $dff cell `$procdff$3241' with positive edge clock. Creating register for signal `\spi_slave.\mosi_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'. created $dff cell `$procdff$3242' with positive edge clock. Creating register for signal `\spi_slave.\cs_n_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'. created $dff cell `$procdff$3243' with positive edge clock. 15.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 5 empty switches in `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. Removing empty process `$paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$544'. Found and cleaned up 8 empty switches in `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. Removing empty process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$543'. Found and cleaned up 10 empty switches in `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. Removing empty process `$paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:267$426'. Found and cleaned up 10 empty switches in `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. Removing empty process `$paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:124$402'. Found and cleaned up 26 empty switches in `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. Removing empty process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:271$383'. Found and cleaned up 4 empty switches in `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:222$378'. Removing empty process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:222$378'. Found and cleaned up 4 empty switches in `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:201$376'. Removing empty process `$paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:201$376'. Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$650'. Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$649'. Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$648'. Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$647'. Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$646'. Found and cleaned up 7 empty switches in `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. Removing empty process `$paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$547'. Found and cleaned up 6 empty switches in `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. Removing empty process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$278'. Found and cleaned up 9 empty switches in `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628'. Removing empty process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:110$628'. Found and cleaned up 8 empty switches in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'. Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'. Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'. Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'. Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'. Cleaned up 99 empty switches. 15.12. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. Optimizing module $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface. Optimizing module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110. Optimizing module $paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory. Optimizing module $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer. Optimizing module $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine. Optimizing module $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8. Optimizing module $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller. Optimizing module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit. Optimizing module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110. Optimizing module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel. Optimizing module spi_slave. 16. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$606976195f63b53ce91799ce1552927edc9dfdd0\memory_interface. Deleting now unused module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010110. Deleting now unused module $paramod$9824ca8895b178d7d5e28d1e2d44a5cbd87bdf9f\neuron_memory. Deleting now unused module $paramod$6ef4b294e25a3b4c04a5a9c8b8177ec3433db948\layer_sequencer. Deleting now unused module $paramod$3c85e57f4d722754e371c9c96b28fa38feb597a5\spi_engine. Deleting now unused module $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8. Deleting now unused module $paramod$a7831d90e36f1741b8aab496b8012d26eb45bb8d\psram_controller. Deleting now unused module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit. Deleting now unused module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010110. Deleting now unused module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel. Deleting now unused module spi_slave. 17. Executing OPT pass (performing simple optimizations). 17.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 1365 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 1125 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 1124 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 241 cells. 17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\u_layer_sequencer.$procmux$1431: \u_layer_sequencer.copy_idx -> 1'0 Replacing known input bits on port A of cell $flatten\u_neuron_memory.$procmux$1233: \u_neuron_memory.neuron_index -> 1'0 Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$2915: \u_neuron_memory.u_neuron.busy -> 1'0 Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$2913: \u_neuron_memory.u_neuron.busy -> 1'1 Analyzing evaluation results. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2496. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2498. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2506. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2508. dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$2516. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$877. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$880. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$886. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$889. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$895. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$898. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$907. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$910. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$919. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$922. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$931. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$934. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$944. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$947. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$957. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$960. dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$970. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$973. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$979. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$985. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$991. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1000. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1009. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1018. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1028. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1038. dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1048. Removed 32 multiplexer ports. 17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$2190: { $auto$opt_reduce.cc:137:opt_pmux$3262 $flatten\u_spi_engine.$procmux$2194_CMP $flatten\u_spi_engine.$procmux$2195_CMP $flatten\u_spi_engine.$procmux$2196_CTRL } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$2467: $auto$opt_reduce.cc:137:opt_pmux$3264 New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$1414: $auto$opt_reduce.cc:137:opt_pmux$3266 Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$875: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$875_Y New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$875_Y [0] New connections: $flatten\u_neuron_memory.$procmux$875_Y [7:1] = { $flatten\u_neuron_memory.$procmux$875_Y [0] $flatten\u_neuron_memory.$procmux$875_Y [0] $flatten\u_neuron_memory.$procmux$875_Y [0] $flatten\u_neuron_memory.$procmux$875_Y [0] $flatten\u_neuron_memory.$procmux$875_Y [0] $flatten\u_neuron_memory.$procmux$875_Y [0] $flatten\u_neuron_memory.$procmux$875_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$905: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$905_Y New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$905_Y [0] New connections: $flatten\u_neuron_memory.$procmux$905_Y [7:1] = { $flatten\u_neuron_memory.$procmux$905_Y [0] $flatten\u_neuron_memory.$procmux$905_Y [0] $flatten\u_neuron_memory.$procmux$905_Y [0] $flatten\u_neuron_memory.$procmux$905_Y [0] $flatten\u_neuron_memory.$procmux$905_Y [0] $flatten\u_neuron_memory.$procmux$905_Y [0] $flatten\u_neuron_memory.$procmux$905_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$942: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$942_Y New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$942_Y [0] New connections: $flatten\u_neuron_memory.$procmux$942_Y [7:1] = { $flatten\u_neuron_memory.$procmux$942_Y [0] $flatten\u_neuron_memory.$procmux$942_Y [0] $flatten\u_neuron_memory.$procmux$942_Y [0] $flatten\u_neuron_memory.$procmux$942_Y [0] $flatten\u_neuron_memory.$procmux$942_Y [0] $flatten\u_neuron_memory.$procmux$942_Y [0] $flatten\u_neuron_memory.$procmux$942_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1066: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1066_Y New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1066_Y [0] New connections: $flatten\u_neuron_memory.$procmux$1066_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1066_Y [0] $flatten\u_neuron_memory.$procmux$1066_Y [0] $flatten\u_neuron_memory.$procmux$1066_Y [0] $flatten\u_neuron_memory.$procmux$1066_Y [0] $flatten\u_neuron_memory.$procmux$1066_Y [0] $flatten\u_neuron_memory.$procmux$1066_Y [0] $flatten\u_neuron_memory.$procmux$1066_Y [0] } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$1826: $auto$opt_reduce.cc:137:opt_pmux$3268 New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$1281: { $flatten\u_neuron_memory.$procmux$878_CMP $auto$opt_reduce.cc:137:opt_pmux$3270 $flatten\u_neuron_memory.$procmux$1098_CMP } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$1903: { $flatten\u_spi_engine.$procmux$1904_CMP $auto$opt_reduce.cc:137:opt_pmux$3272 } New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$1927: $auto$opt_reduce.cc:137:opt_pmux$3274 New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$2654: { $auto$opt_reduce.cc:137:opt_pmux$3276 $flatten\u_psram_ctrl.$procmux$2542_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$2666: { $auto$opt_reduce.cc:137:opt_pmux$3278 $flatten\u_psram_ctrl.$procmux$2542_CMP } Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$976: Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_EN[7:0]$472, Y=$flatten\u_neuron_memory.$procmux$976_Y New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$875_Y [0], Y=$flatten\u_neuron_memory.$procmux$976_Y [0] New connections: $flatten\u_neuron_memory.$procmux$976_Y [7:1] = { $flatten\u_neuron_memory.$procmux$976_Y [0] $flatten\u_neuron_memory.$procmux$976_Y [0] $flatten\u_neuron_memory.$procmux$976_Y [0] $flatten\u_neuron_memory.$procmux$976_Y [0] $flatten\u_neuron_memory.$procmux$976_Y [0] $flatten\u_neuron_memory.$procmux$976_Y [0] $flatten\u_neuron_memory.$procmux$976_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$997: Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_EN[7:0]$465, Y=$flatten\u_neuron_memory.$procmux$997_Y New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$905_Y [0], Y=$flatten\u_neuron_memory.$procmux$997_Y [0] New connections: $flatten\u_neuron_memory.$procmux$997_Y [7:1] = { $flatten\u_neuron_memory.$procmux$997_Y [0] $flatten\u_neuron_memory.$procmux$997_Y [0] $flatten\u_neuron_memory.$procmux$997_Y [0] $flatten\u_neuron_memory.$procmux$997_Y [0] $flatten\u_neuron_memory.$procmux$997_Y [0] $flatten\u_neuron_memory.$procmux$997_Y [0] $flatten\u_neuron_memory.$procmux$997_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1025: Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_EN[7:0]$458, Y=$flatten\u_neuron_memory.$procmux$1025_Y New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$942_Y [0], Y=$flatten\u_neuron_memory.$procmux$1025_Y [0] New connections: $flatten\u_neuron_memory.$procmux$1025_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1025_Y [0] $flatten\u_neuron_memory.$procmux$1025_Y [0] $flatten\u_neuron_memory.$procmux$1025_Y [0] $flatten\u_neuron_memory.$procmux$1025_Y [0] $flatten\u_neuron_memory.$procmux$1025_Y [0] $flatten\u_neuron_memory.$procmux$1025_Y [0] $flatten\u_neuron_memory.$procmux$1025_Y [0] } Optimizing cells in module \spi_neuron_top. Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1103: Old ports: A=$flatten\u_neuron_memory.$2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_EN[7:0]$455, B=8'00000000, Y=$flatten\u_neuron_memory.$procmux$1103_Y New ports: A=$flatten\u_neuron_memory.$procmux$976_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$procmux$1103_Y [0] New connections: $flatten\u_neuron_memory.$procmux$1103_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1103_Y [0] $flatten\u_neuron_memory.$procmux$1103_Y [0] $flatten\u_neuron_memory.$procmux$1103_Y [0] $flatten\u_neuron_memory.$procmux$1103_Y [0] $flatten\u_neuron_memory.$procmux$1103_Y [0] $flatten\u_neuron_memory.$procmux$1103_Y [0] $flatten\u_neuron_memory.$procmux$1103_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1112: Old ports: A=$flatten\u_neuron_memory.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_EN[7:0]$452, B=8'00000000, Y=$flatten\u_neuron_memory.$procmux$1112_Y New ports: A=$flatten\u_neuron_memory.$procmux$997_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$procmux$1112_Y [0] New connections: $flatten\u_neuron_memory.$procmux$1112_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1112_Y [0] $flatten\u_neuron_memory.$procmux$1112_Y [0] $flatten\u_neuron_memory.$procmux$1112_Y [0] $flatten\u_neuron_memory.$procmux$1112_Y [0] $flatten\u_neuron_memory.$procmux$1112_Y [0] $flatten\u_neuron_memory.$procmux$1112_Y [0] $flatten\u_neuron_memory.$procmux$1112_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1121: Old ports: A=$flatten\u_neuron_memory.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_EN[7:0]$449, B=8'00000000, Y=$flatten\u_neuron_memory.$procmux$1121_Y New ports: A=$flatten\u_neuron_memory.$procmux$1025_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$procmux$1121_Y [0] New connections: $flatten\u_neuron_memory.$procmux$1121_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1121_Y [0] $flatten\u_neuron_memory.$procmux$1121_Y [0] $flatten\u_neuron_memory.$procmux$1121_Y [0] $flatten\u_neuron_memory.$procmux$1121_Y [0] $flatten\u_neuron_memory.$procmux$1121_Y [0] $flatten\u_neuron_memory.$procmux$1121_Y [0] $flatten\u_neuron_memory.$procmux$1121_Y [0] } Optimizing cells in module \spi_neuron_top. Performed a total of 19 changes. 17.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 1101 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 1080 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 1079 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 22 cells. 17.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\u_int8_access.$procdff$3224 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2798_Y, Q = \u_int8_access.addr_reg, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3279 ($sdff) from module spi_neuron_top (D = \u_int8_access.addr, Q = \u_int8_access.addr_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3214 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2535_Y, Q = \u_psram_ctrl.dq_oe, rval = 1'0). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3213 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2648_Y, Q = \u_psram_ctrl.dq_out, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3284 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_wdata, Q = \u_psram_ctrl.dq_out). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3212 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2654_Y, Q = \u_psram_ctrl.ub_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$3288 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2654_Y, Q = \u_psram_ctrl.ub_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3211 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2666_Y, Q = \u_psram_ctrl.lb_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$3296 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2666_Y, Q = \u_psram_ctrl.lb_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3210 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2683_Y, Q = \u_psram_ctrl.wr_reg, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3304 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_wr, Q = \u_psram_ctrl.wr_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3209 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2694_Y, Q = \u_psram_ctrl.wdata_reg, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3308 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_wdata, Q = \u_psram_ctrl.wdata_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3208 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2705_Y, Q = \u_psram_ctrl.address_reg, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3312 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_addr, Q = \u_psram_ctrl.address_reg). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3207 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2711_Y, Q = \u_psram_ctrl.counter, rval = 14'00000000000000). Adding EN signal on $auto$ff.cc:337:slice$3316 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2711_Y, Q = \u_psram_ctrl.counter). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3205 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2556_Y, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3204 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2570_Y, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3203 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2587_Y, Q = \u_psram_ctrl.psram_we_n, rval = 1'1). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3202 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2604_Y, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3201 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2617_Y, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3200 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2737_Y, Q = \u_psram_ctrl.psram_a, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3329 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_addr, Q = \u_psram_ctrl.psram_a). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3199 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2630_Y, Q = \u_psram_ctrl.mem_ready, rval = 1'0). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3198 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2748_Y, Q = \u_psram_ctrl.mem_rdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3334 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:93$546_Y, Q = \u_psram_ctrl.mem_rdata). Adding SRST signal on $flatten\u_psram_ctrl.$procdff$3197 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2754_Y, Q = \u_psram_ctrl.state, rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$3338 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$2754_Y, Q = \u_psram_ctrl.state). Adding SRST signal on $flatten\u_memory_if.$procdff$3109 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$677_Y, Q = \u_memory_if.mem_ub_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$3350 ($sdff) from module spi_neuron_top (D = \u_memory_if.ub_n, Q = \u_memory_if.mem_ub_n). Adding SRST signal on $flatten\u_memory_if.$procdff$3108 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$686_Y, Q = \u_memory_if.mem_lb_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$3354 ($sdff) from module spi_neuron_top (D = \u_memory_if.lb_n, Q = \u_memory_if.mem_lb_n). Adding SRST signal on $flatten\u_memory_if.$procdff$3107 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$666_Y, Q = \u_memory_if.ready, rval = 1'0). Adding SRST signal on $flatten\u_memory_if.$procdff$3106 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$696_Y, Q = \u_memory_if.rdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3363 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_rdata, Q = \u_memory_if.rdata). Adding SRST signal on $flatten\u_memory_if.$procdff$3105 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$705_Y, Q = \u_memory_if.mem_wdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3369 ($sdff) from module spi_neuron_top (D = \u_memory_if.wdata, Q = \u_memory_if.mem_wdata). Adding SRST signal on $flatten\u_memory_if.$procdff$3104 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$714_Y, Q = \u_memory_if.mem_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3373 ($sdff) from module spi_neuron_top (D = \u_memory_if.addr, Q = \u_memory_if.mem_addr). Adding SRST signal on $flatten\u_memory_if.$procdff$3103 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$723_Y, Q = \u_memory_if.mem_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3377 ($sdff) from module spi_neuron_top (D = \u_memory_if.wr, Q = \u_memory_if.mem_wr). Adding SRST signal on $flatten\u_memory_if.$procdff$3102 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$658_Y, Q = \u_memory_if.mem_req, rval = 1'0). Adding SRST signal on $flatten\u_memory_if.$procdff$3101 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$731_Y, Q = \u_memory_if.state, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$3386 ($sdff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$731_Y, Q = \u_memory_if.state). Adding SRST signal on $flatten\u_int8_access.$procdff$3223 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2804_Y, Q = \u_int8_access.mem_ub_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$3394 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2804_Y, Q = \u_int8_access.mem_ub_n). Adding SRST signal on $flatten\u_int8_access.$procdff$3222 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2816_Y, Q = \u_int8_access.mem_lb_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$3402 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2816_Y, Q = \u_int8_access.mem_lb_n). Adding SRST signal on $flatten\u_int8_access.$procdff$3221 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2787_Y, Q = \u_int8_access.ready, rval = 1'0). Adding SRST signal on $flatten\u_int8_access.$procdff$3220 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2833_Y, Q = \u_int8_access.rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3415 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2829_Y, Q = \u_int8_access.rdata). Adding SRST signal on $flatten\u_int8_access.$procdff$3219 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2845_Y, Q = \u_int8_access.mem_wdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3419 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2841_Y, Q = \u_int8_access.mem_wdata). Adding SRST signal on $flatten\u_int8_access.$procdff$3218 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2854_Y, Q = \u_int8_access.mem_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3423 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$shr$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:106$279_Y, Q = \u_int8_access.mem_addr). Adding SRST signal on $flatten\u_int8_access.$procdff$3217 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2863_Y, Q = \u_int8_access.mem_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3427 ($sdff) from module spi_neuron_top (D = \u_int8_access.wr, Q = \u_int8_access.mem_wr). Adding SRST signal on $flatten\u_int8_access.$procdff$3216 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2779_Y, Q = \u_int8_access.mem_req, rval = 1'0). Adding SRST signal on $flatten\u_int8_access.$procdff$3215 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2871_Y, Q = \u_int8_access.state, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$3436 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$2871_Y, Q = \u_int8_access.state). Adding SRST signal on $flatten\u_arbiter.$procdff$3120 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$781_Y, Q = \u_arbiter.owner, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$3444 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$781_Y, Q = \u_arbiter.owner). Adding SRST signal on $flatten\u_arbiter.$procdff$3119 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$812_Y, Q = \u_arbiter.m_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3452 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$810_Y, Q = \u_arbiter.m_wdata). Adding SRST signal on $flatten\u_arbiter.$procdff$3118 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$828_Y, Q = \u_arbiter.m_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3458 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$826_Y, Q = \u_arbiter.m_addr). Adding SRST signal on $flatten\u_arbiter.$procdff$3117 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$844_Y, Q = \u_arbiter.m_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3464 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$842_Y, Q = \u_arbiter.m_wr). Adding SRST signal on $flatten\u_arbiter.$procdff$3116 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$772_Y, Q = \u_arbiter.m_req, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$3115 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$739_Y, Q = \u_arbiter.c_ready, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$3114 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$851_Y, Q = \u_arbiter.c_rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3480 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_rdata, Q = \u_arbiter.c_rdata). Adding SRST signal on $flatten\u_arbiter.$procdff$3113 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$747_Y, Q = \u_arbiter.b_ready, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$3112 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$859_Y, Q = \u_arbiter.b_rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3489 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_rdata, Q = \u_arbiter.b_rdata). Adding SRST signal on $flatten\u_arbiter.$procdff$3111 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$756_Y, Q = \u_arbiter.a_ready, rval = 1'0). Adding SRST signal on $flatten\u_arbiter.$procdff$3110 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$868_Y, Q = \u_arbiter.a_rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3498 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_rdata, Q = \u_arbiter.a_rdata). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3225 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2944_Y, Q = \u_neuron_memory.u_neuron.y, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3502 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2937_Y, Q = \u_neuron_memory.u_neuron.y). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3226 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2918_Y, Q = \u_neuron_memory.u_neuron.busy, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3227 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2880_Y, Q = \u_neuron_memory.u_neuron.done, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3228 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2904_Y, Q = \u_neuron_memory.u_neuron.group_index, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$3514 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:174$636_Y, Q = \u_neuron_memory.u_neuron.group_index). Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$3229 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2893_Y, Q = \u_neuron_memory.u_neuron.acc, rval = 0). Adding EN signal on $auto$ff.cc:337:slice$3522 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$2891_Y, Q = \u_neuron_memory.u_neuron.acc). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3215 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2871_Y, Q = \u_neuron_memory.u_mem.state, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$3526 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2871_Y, Q = \u_neuron_memory.u_mem.state). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3216 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2779_Y, Q = \u_neuron_memory.u_mem.mem_req, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3217 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2863_Y, Q = \u_neuron_memory.u_mem.mem_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3539 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.wr, Q = \u_neuron_memory.u_mem.mem_wr). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3218 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2854_Y, Q = \u_neuron_memory.u_mem.mem_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3543 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$shr$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:106$279_Y, Q = \u_neuron_memory.u_mem.mem_addr). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3219 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2845_Y, Q = \u_neuron_memory.u_mem.mem_wdata, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3547 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2841_Y, Q = \u_neuron_memory.u_mem.mem_wdata). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3220 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2833_Y, Q = \u_neuron_memory.u_mem.rdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3551 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2829_Y, Q = \u_neuron_memory.u_mem.rdata). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3221 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2787_Y, Q = \u_neuron_memory.u_mem.ready, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3222 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2816_Y, Q = \u_neuron_memory.u_mem.mem_lb_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$3560 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2816_Y, Q = \u_neuron_memory.u_mem.mem_lb_n). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3223 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2804_Y, Q = \u_neuron_memory.u_mem.mem_ub_n, rval = 1'1). Adding EN signal on $auto$ff.cc:337:slice$3568 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2804_Y, Q = \u_neuron_memory.u_mem.mem_ub_n). Adding EN signal on $flatten\u_neuron_memory.$procdff$3134 ($dff) from module spi_neuron_top (D = 1, Q = \u_neuron_memory.rst_i). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3133 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1070_Y, Q = \u_neuron_memory.neuron_start, rval = 1'0). Adding EN signal on $flatten\u_neuron_memory.$procdff$3132 ($dff) from module spi_neuron_top (D = 8'00000000, Q = \u_neuron_memory.access_wdata). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3131 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1139_Y, Q = \u_neuron_memory.access_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3579 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1139_Y, Q = \u_neuron_memory.access_addr). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3130 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1168_Y, Q = \u_neuron_memory.access_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3595 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1168_Y, Q = \u_neuron_memory.access_wr). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3129 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1082_Y, Q = \u_neuron_memory.access_req, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3128 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1195_Y, Q = \u_neuron_memory.bias_reg, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3608 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_rdata, Q = \u_neuron_memory.bias_reg). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3127 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1207_Y, Q = \u_neuron_memory.bias_group_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3612 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1207_Y, Q = \u_neuron_memory.bias_group_addr). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3126 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1222_Y, Q = \u_neuron_memory.w_group_base, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3624 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1222_Y, Q = \u_neuron_memory.w_group_base). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3125 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1237_Y, Q = \u_neuron_memory.neuron_index, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3636 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1237_Y, Q = \u_neuron_memory.neuron_index). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3124 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1252_Y, Q = \u_neuron_memory.index, rval = 6'000000). Adding EN signal on $auto$ff.cc:337:slice$3646 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1252_Y, Q = \u_neuron_memory.index). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3123 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1053_Y, Q = \u_neuron_memory.done, rval = 1'0). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3122 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1281_Y, Q = \u_neuron_memory.busy, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3671 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1281_Y, Q = \u_neuron_memory.busy). Adding SRST signal on $flatten\u_neuron_memory.$procdff$3121 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1300_Y, Q = \u_neuron_memory.state, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$3681 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1300_Y, Q = \u_neuron_memory.state). Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$3224 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$2798_Y, Q = \u_neuron_memory.u_mem.addr_reg, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3699 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.addr, Q = \u_neuron_memory.u_mem.addr_reg). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3166 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1435_Y, Q = \u_layer_sequencer.copy_idx, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3703 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1435_Y, Q = \u_layer_sequencer.copy_idx). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3165 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1452_Y, Q = \u_layer_sequencer.write_sel, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3713 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1452_Y, Q = \u_layer_sequencer.write_sel). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3164 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1469_Y, Q = \u_layer_sequencer.cur_sel, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3727 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.write_sel, Q = \u_layer_sequencer.cur_sel). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3163 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1483_Y, Q = \u_layer_sequencer.activation_acc, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3735 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.activation_acc). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3162 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1369_Y, Q = \u_layer_sequencer.bias_addr_acc [23:16], rval = 8'00000000). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3162 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1352_Y, Q = \u_layer_sequencer.bias_addr_acc [7:0], rval = 8'00000000). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3162 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1337_Y, Q = \u_layer_sequencer.bias_addr_acc [15:8], rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3741 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.bias_addr_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$3740 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.bias_addr_acc [7:0]). Adding EN signal on $auto$ff.cc:337:slice$3739 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.bias_addr_acc [23:16]). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3161 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1502_Y, Q = \u_layer_sequencer.w_base_acc [15:8], rval = 8'00000000). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3161 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1407_Y, Q = \u_layer_sequencer.w_base_acc [23:16], rval = 8'00000000). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3161 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1387_Y, Q = \u_layer_sequencer.w_base_acc [7:0], rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3753 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.w_base_acc [7:0]). Adding EN signal on $auto$ff.cc:337:slice$3752 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.w_base_acc [23:16]). Adding EN signal on $auto$ff.cc:337:slice$3751 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.ram_rdata, Q = \u_layer_sequencer.w_base_acc [15:8]). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3160 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1530_Y, Q = \u_layer_sequencer.desc_byte_idx, rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$3763 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1530_Y, Q = \u_layer_sequencer.desc_byte_idx). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3159 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1553_Y, Q = \u_layer_sequencer.desc_table_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3779 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1553_Y, Q = \u_layer_sequencer.desc_table_addr). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3158 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1570_Y, Q = \u_layer_sequencer.num_layers_reg, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3793 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.run_num_layers, Q = \u_layer_sequencer.num_layers_reg). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3157 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1584_Y, Q = \u_layer_sequencer.layer_idx, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3797 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1584_Y, Q = \u_layer_sequencer.layer_idx). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3156 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1596_Y, Q = \u_layer_sequencer.nm_activation, rval = 2'01). Adding EN signal on $auto$ff.cc:337:slice$3811 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.activation_acc [1:0], Q = \u_layer_sequencer.nm_activation). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3155 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1605_Y, Q = \u_layer_sequencer.nm_bias_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3813 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.bias_addr_acc [21:0], Q = \u_layer_sequencer.nm_bias_addr). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3154 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1614_Y, Q = \u_layer_sequencer.nm_w_base, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3815 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.w_base_acc [21:0], Q = \u_layer_sequencer.nm_w_base). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3153 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1623_Y, Q = \u_layer_sequencer.nm_x_base, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3817 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:236$408_Y, Q = \u_layer_sequencer.nm_x_base). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3152 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1637_Y, Q = \u_layer_sequencer.state, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$3819 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1637_Y, Q = \u_layer_sequencer.state). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3151 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1510_Y, Q = \u_layer_sequencer.seq_done, rval = 1'0). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3150 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1666_Y, Q = \u_layer_sequencer.seq_busy, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3838 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1666_Y, Q = \u_layer_sequencer.seq_busy). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3149 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1424_Y, Q = \u_layer_sequencer.nm_start, rval = 1'0). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3148 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1676_Y, Q = \u_layer_sequencer.ram_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3853 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:268$413_Y, Q = \u_layer_sequencer.ram_wdata). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3147 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1683_Y, Q = \u_layer_sequencer.ram_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3855 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1683_Y, Q = \u_layer_sequencer.ram_addr). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3146 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1691_Y, Q = \u_layer_sequencer.ram_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3859 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1691_Y, Q = \u_layer_sequencer.ram_wr). Adding SRST signal on $flatten\u_layer_sequencer.$procdff$3145 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$1414_Y, Q = \u_layer_sequencer.ram_req, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$3243 ($dff) from module spi_neuron_top (D = { \u_spi_slave.cs_n_sync [1:0] \u_spi_slave.cs_n }, Q = \u_spi_slave.cs_n_sync, rval = 3'111). Adding SRST signal on $flatten\u_spi_slave.$procdff$3242 ($dff) from module spi_neuron_top (D = { \u_spi_slave.mosi_sync [1:0] \u_spi_slave.mosi }, Q = \u_spi_slave.mosi_sync, rval = 3'000). Adding SRST signal on $flatten\u_spi_slave.$procdff$3241 ($dff) from module spi_neuron_top (D = { \u_spi_slave.sclk_sync [1:0] \u_spi_slave.sclk }, Q = \u_spi_slave.sclk_sync, rval = 3'000). Adding SRST signal on $flatten\u_spi_slave.$procdff$3240 ($dff) from module spi_neuron_top (D = \u_spi_slave.cs_n_sync [2], Q = \u_spi_slave.cs_n_prev, rval = 1'1). Adding SRST signal on $flatten\u_spi_slave.$procdff$3239 ($dff) from module spi_neuron_top (D = \u_spi_slave.sclk_sync [2], Q = \u_spi_slave.sclk_prev, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$3238 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$3014_Y, Q = \u_spi_slave.tx_shift, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3869 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$3014_Y, Q = \u_spi_slave.tx_shift). Adding SRST signal on $flatten\u_spi_engine.$procdff$3196 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2525_Y, Q = \u_spi_engine.status_done_sticky, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$3881 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2525_Y, Q = \u_spi_engine.status_done_sticky). Adding SRST signal on $flatten\u_spi_engine.$procdff$3195 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1858_Y, Q = \u_spi_engine.status_snapshot, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3887 ($sdff) from module spi_neuron_top (D = { 6'000000 \u_spi_engine.status_done_sticky $flatten\u_spi_engine.$or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:179$370_Y }, Q = \u_spi_engine.status_snapshot). Adding SRST signal on $flatten\u_spi_engine.$procdff$3194 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1884_Y, Q = \u_spi_engine.net_mode, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$3193 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1912_Y, Q = \u_spi_engine.resp_len, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$3894 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1903_Y, Q = \u_spi_engine.resp_len). Adding SRST signal on $flatten\u_spi_engine.$procdff$3192 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1935_Y, Q = \u_spi_engine.resp_index, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$3902 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1924_Y, Q = \u_spi_engine.resp_index). Adding SRST signal on $flatten\u_spi_engine.$procdff$3191 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1950_Y, Q = \u_spi_engine.cur_read_byte, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3918 ($sdff) from module spi_neuron_top (D = \u_spi_engine.ram_rdata, Q = \u_spi_engine.cur_read_byte). Adding SRST signal on $flatten\u_spi_engine.$procdff$3190 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1969_Y, Q = \u_spi_engine.pending_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3924 ($sdff) from module spi_neuron_top (D = \u_spi_engine.rx_byte, Q = \u_spi_engine.pending_wdata). Adding EN signal on $flatten\u_spi_engine.$procdff$3189 ($dff) from module spi_neuron_top (D = 1'0, Q = \u_spi_engine.pending_write). Adding SRST signal on $flatten\u_spi_engine.$procdff$3188 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1998_Y, Q = \u_spi_engine.cur_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3931 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1983_Y, Q = \u_spi_engine.cur_addr). Adding SRST signal on $flatten\u_spi_engine.$procdff$3187 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2021_Y, Q = \u_spi_engine.len_remaining, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3949 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2009_Y, Q = \u_spi_engine.len_remaining). Adding SRST signal on $flatten\u_spi_engine.$procdff$3186 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1753_Y, Q = \u_spi_engine.len_acc [7:0], rval = 8'00000000). Adding SRST signal on $flatten\u_spi_engine.$procdff$3186 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1721_Y, Q = \u_spi_engine.len_acc [15:8], rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$3966 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1709_Y, Q = \u_spi_engine.len_acc [15:8]). Adding EN signal on $auto$ff.cc:337:slice$3965 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1738_Y, Q = \u_spi_engine.len_acc [7:0]). Adding SRST signal on $flatten\u_spi_engine.$procdff$3185 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2073_Y, Q = \u_spi_engine.addr_acc, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$3995 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2054_Y, Q = \u_spi_engine.addr_acc). Adding SRST signal on $flatten\u_spi_engine.$procdff$3184 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2105_Y, Q = \u_spi_engine.byte_pos, rval = 2'00). Adding EN signal on $auto$ff.cc:337:slice$4011 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2093_Y, Q = \u_spi_engine.byte_pos). Adding SRST signal on $flatten\u_spi_engine.$procdff$3183 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2128_Y, Q = \u_spi_engine.opcode, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$4025 ($sdff) from module spi_neuron_top (D = \u_spi_engine.rx_byte, Q = \u_spi_engine.opcode). Adding SRST signal on $flatten\u_spi_engine.$procdff$3182 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2134_Y, Q = \u_spi_engine.state, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$4031 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2134_Y, Q = \u_spi_engine.state). Adding SRST signal on $flatten\u_spi_engine.$procdff$3181 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2216_Y, Q = \u_spi_engine.run_num_layers, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$4065 ($sdff) from module spi_neuron_top (D = \u_spi_engine.rx_byte, Q = \u_spi_engine.run_num_layers). Adding SRST signal on $flatten\u_spi_engine.$procdff$3180 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2029_Y, Q = \u_spi_engine.run_start, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$3179 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2246_Y, Q = \u_spi_engine.buf_b_base, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$4080 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.buf_b_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$3178 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2277_Y, Q = \u_spi_engine.buf_a_base, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$4086 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.buf_a_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$3177 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2309_Y, Q = \u_spi_engine.table_base, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$4092 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.table_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$3176 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1775_Y, Q = \u_spi_engine.nm_soft_rst, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$3175 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1806_Y, Q = \u_spi_engine.nm_start, rval = 1'0). Adding SRST signal on $flatten\u_spi_engine.$procdff$3174 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2338_Y, Q = \u_spi_engine.activation, rval = 2'01). Adding EN signal on $auto$ff.cc:337:slice$4114 ($sdff) from module spi_neuron_top (D = \u_spi_engine.rx_byte [1:0], Q = \u_spi_engine.activation). Adding SRST signal on $flatten\u_spi_engine.$procdff$3173 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2371_Y, Q = \u_spi_engine.bias_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$4120 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.bias_addr). Adding SRST signal on $flatten\u_spi_engine.$procdff$3172 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2405_Y, Q = \u_spi_engine.w_base, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$4126 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.w_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$3171 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2440_Y, Q = \u_spi_engine.x_base, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$4132 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [13:0] \u_spi_engine.rx_byte }, Q = \u_spi_engine.x_base). Adding SRST signal on $flatten\u_spi_engine.$procdff$3170 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2456_Y, Q = \u_spi_engine.ram_wdata, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$4138 ($sdff) from module spi_neuron_top (D = \u_spi_engine.pending_wdata, Q = \u_spi_engine.ram_wdata). Adding SRST signal on $flatten\u_spi_engine.$procdff$3169 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2471_Y, Q = \u_spi_engine.ram_addr, rval = 22'0000000000000000000000). Adding EN signal on $auto$ff.cc:337:slice$4144 ($sdff) from module spi_neuron_top (D = \u_spi_engine.cur_addr, Q = \u_spi_engine.ram_addr). Adding SRST signal on $flatten\u_spi_engine.$procdff$3168 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2486_Y, Q = \u_spi_engine.ram_wr, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$4150 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$2482_Y, Q = \u_spi_engine.ram_wr). Adding SRST signal on $flatten\u_spi_engine.$procdff$3167 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1826_Y, Q = \u_spi_engine.ram_req, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$3237 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$3028_Y, Q = \u_spi_slave.rx_shift, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$4161 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_shift). Adding SRST signal on $flatten\u_spi_slave.$procdff$3236 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$3042_Y, Q = \u_spi_slave.bit_count, rval = 3'000). Adding EN signal on $auto$ff.cc:337:slice$4171 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$3035_Y, Q = \u_spi_slave.bit_count). Adding SRST signal on $flatten\u_spi_slave.$procdff$3235 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2950_Y, Q = \u_spi_slave.cs_end, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$3234 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2959_Y, Q = \u_spi_slave.cs_start, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$3233 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2978_Y, Q = \u_spi_slave.tx_byte_req, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$3232 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$2985_Y, Q = \u_spi_slave.rx_valid, rval = 1'0). Adding SRST signal on $flatten\u_spi_slave.$procdff$3231 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$3062_Y, Q = \u_spi_slave.rx_byte, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$4191 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_byte). Adding SRST signal on $flatten\u_spi_slave.$procdff$3230 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$3081_Y, Q = \u_spi_slave.miso, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$4201 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$3081_Y, Q = \u_spi_slave.miso). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$3930 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$3888 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$3888 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$3888 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$3888 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$3888 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$3888 ($sdffe) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$3578 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$3578 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$3578 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$3578 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$3578 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$3578 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$3578 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$3578 ($dffe) from module spi_neuron_top. Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 8 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 9 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 10 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 11 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 12 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 13 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 14 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 15 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 16 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 17 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 18 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 19 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 20 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 23 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 24 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 25 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 26 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 27 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 28 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 29 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 30 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 0-bit at position 31 on $auto$ff.cc:337:slice$3576 ($dffe) from module spi_neuron_top. Setting constant 1-bit at position 0 on $flatten\u_psram_ctrl.$procdff$3206 ($dff) from module spi_neuron_top. 17.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 432 unused cells and 1589 unused wires. 17.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 17.9. Rerunning OPT passes. (Maybe there is more to do..) 17.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 17.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$1738: { $auto$opt_reduce.cc:137:opt_pmux$4215 $flatten\u_spi_engine.$procmux$1719_CMP } New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$1082: { $flatten\u_neuron_memory.$procmux$1058_CMP $auto$opt_reduce.cc:137:opt_pmux$4217 $flatten\u_neuron_memory.$procmux$1098_CMP } New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$1168: { $flatten\u_neuron_memory.$procmux$1058_CMP $auto$opt_reduce.cc:137:opt_pmux$4219 $flatten\u_neuron_memory.$procmux$1098_CMP } New ctrl vector for $pmux cell $flatten\u_arbiter.$procmux$781: { $auto$opt_reduce.cc:137:opt_pmux$4221 $flatten\u_arbiter.$procmux$775_CMP } New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$2711: { $flatten\u_psram_ctrl.$procmux$2631_CMP $auto$opt_reduce.cc:137:opt_pmux$4223 $flatten\u_psram_ctrl.$procmux$2542_CMP $flatten\u_psram_ctrl.$procmux$2661_CMP } Optimizing cells in module \spi_neuron_top. Performed a total of 5 changes. 17.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 989 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 863 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 854 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 135 cells. 17.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $auto$ff.cc:337:slice$3982 ($sdffe) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$1738_Y, Q = \u_spi_engine.len_acc [7:0]). Adding EN signal on $auto$ff.cc:337:slice$3445 ($sdffe) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$781_Y, Q = \u_arbiter.owner). Adding EN signal on $auto$ff.cc:337:slice$3596 ($sdffe) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$1168_Y, Q = \u_neuron_memory.access_wr). Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$3424 ($sdffe) from module spi_neuron_top. 17.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 135 unused wires. 17.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 17.16. Rerunning OPT passes. (Maybe there is more to do..) 17.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 17.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4240: { $auto$opt_dff.cc:319:make_patterns_logic$3581 $auto$opt_dff.cc:319:make_patterns_logic$3583 $auto$opt_dff.cc:319:make_patterns_logic$3589 $auto$opt_dff.cc:319:make_patterns_logic$3591 $auto$opt_dff.cc:319:make_patterns_logic$4235 $auto$opt_dff.cc:319:make_patterns_logic$4237 } New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4228: { $auto$rtlil.cc:3267:Not$3890 $auto$opt_dff.cc:319:make_patterns_logic$3939 $auto$opt_dff.cc:319:make_patterns_logic$3941 $auto$opt_dff.cc:319:make_patterns_logic$3943 $auto$opt_dff.cc:319:make_patterns_logic$3983 $auto$opt_dff.cc:319:make_patterns_logic$4225 } New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$4233: { $auto$opt_dff.cc:319:make_patterns_logic$3446 $auto$opt_dff.cc:319:make_patterns_logic$3448 $auto$opt_dff.cc:319:make_patterns_logic$4230 } Optimizing cells in module \spi_neuron_top. Performed a total of 3 changes. 17.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 861 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 17.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$3374 ($sdffe) from module spi_neuron_top. 17.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 3 unused cells and 3 unused wires. 17.22. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 17.23. Rerunning OPT passes. (Maybe there is more to do..) 17.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 17.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 17.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 858 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 17.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$3330 ($sdffe) from module spi_neuron_top. 17.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 17.29. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 17.30. Rerunning OPT passes. (Maybe there is more to do..) 17.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 17.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 17.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 858 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 17.34. Executing OPT_DFF pass (perform DFF optimizations). 17.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 17.36. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 17.37. Finished fast OPT passes. (There is nothing left to do.) 18. Executing MEMORY pass. 18.1. Executing OPT_MEM pass (optimize memories). spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653: removing const-0 lane 6 spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653: removing const-0 lane 7 Performed a total of 1 transformations. 18.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 18.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 0. Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 1. Analyzing spi_neuron_top.u_neuron_memory.x_mem write port 0. Analyzing spi_neuron_top.u_neuron_memory.w_mem write port 0. 18.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 18.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no output FF found. Checking read port `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no output FF found. Checking read port address `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653'[0] in module `\spi_neuron_top': merged address FF to cell. Checking read port address `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no address FF found. Checking read port address `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no address FF found. 18.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 18.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg by address: Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address: Merging ports 0, 1 (address 31). Merging ports 0, 2 (address 30). Merging ports 0, 3 (address 28). Merging ports 0, 4 (address 28). Merging ports 0, 5 (address 24). Merging ports 0, 6 (address 24). Merging ports 0, 7 (address 24). Merging ports 0, 8 (address 24). Merging ports 0, 9 (address 16). Merging ports 0, 10 (address 16). Merging ports 0, 11 (address 16). Merging ports 0, 12 (address 16). Merging ports 0, 13 (address 16). Merging ports 0, 14 (address 16). Merging ports 0, 15 (address 16). Merging ports 0, 16 (address 16). Merging ports 0, 17 (address 0). Merging ports 0, 18 (address 0). Merging ports 0, 19 (address 0). Merging ports 0, 20 (address 0). Merging ports 0, 21 (address 0). Merging ports 0, 22 (address 0). Merging ports 0, 23 (address 0). Merging ports 0, 24 (address 0). Merging ports 0, 25 (address 0). Merging ports 0, 26 (address 0). Merging ports 0, 27 (address 0). Merging ports 0, 28 (address 0). Merging ports 0, 29 (address 0). Merging ports 0, 30 (address 0). Merging ports 0, 31 (address 0). Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address: Merging ports 0, 1 (address 31). Merging ports 0, 2 (address 30). Merging ports 0, 3 (address 28). Merging ports 0, 4 (address 28). Merging ports 0, 5 (address 24). Merging ports 0, 6 (address 24). Merging ports 0, 7 (address 24). Merging ports 0, 8 (address 24). Merging ports 0, 9 (address 16). Merging ports 0, 10 (address 16). Merging ports 0, 11 (address 16). Merging ports 0, 12 (address 16). Merging ports 0, 13 (address 16). Merging ports 0, 14 (address 16). Merging ports 0, 15 (address 16). Merging ports 0, 16 (address 16). Merging ports 0, 17 (address 0). Merging ports 0, 18 (address 0). Merging ports 0, 19 (address 0). Merging ports 0, 20 (address 0). Merging ports 0, 21 (address 0). Merging ports 0, 22 (address 0). Merging ports 0, 23 (address 0). Merging ports 0, 24 (address 0). Merging ports 0, 25 (address 0). Merging ports 0, 26 (address 0). Merging ports 0, 27 (address 0). Merging ports 0, 28 (address 0). Merging ports 0, 29 (address 0). Merging ports 0, 30 (address 0). Merging ports 0, 31 (address 0). Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg using sat-based resource sharing: Checking group clocked with posedge \clk, width 8: ports 0, 1. Common input cone for all EN signals: 6 cells. Size of unconstrained SAT problem: 53 variables, 124 clauses Merging port 1 into port 0. 18.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 18.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 62 unused wires. 18.10. Executing MEMORY_COLLECT pass (generating $mem cells). 18.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory $flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653 in module \spi_neuron_top: created 8 $dff cells and 0 static cells of width 6. Extracted data FF from read port 0 of spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653: $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653$rdreg[0] read interface: 1 $dff and 7 $mux cells. write interface: 0 write mux blocks. Mapping memory \u_neuron_memory.x_mem in module \spi_neuron_top: created 32 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 0 $mux cells. write interface: 32 write mux blocks. Mapping memory \u_neuron_memory.w_mem in module \spi_neuron_top: created 32 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 0 $mux cells. write interface: 32 write mux blocks. Mapping memory \u_neuron_memory.y_reg in module \spi_neuron_top: created 1 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 0 $mux cells. write interface: 1 write mux blocks. 19. Executing OPT pass (performing simple optimizations). 19.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 19.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 1186 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$4449: $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_EN[7:0]$436 [0] -> 1'1 Analyzing evaluation results. Removed 0 multiplexer ports. 19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 19.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 1186 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 19.6. Executing OPT_DFF pass (perform DFF optimizations). 19.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 211 unused wires. 19.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 19.9. Rerunning OPT passes. (Maybe there is more to do..) 19.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 19.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 19.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 1186 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 19.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\u_neuron_memory.x_mem[0]$4471 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[0]). Adding EN signal on $memory\u_neuron_memory.x_mem[1]$4473 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[1]). Adding EN signal on $memory\u_neuron_memory.x_mem[2]$4475 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[2]). Adding EN signal on $memory\u_neuron_memory.x_mem[3]$4477 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[3]). Adding EN signal on $memory\u_neuron_memory.x_mem[4]$4479 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[4]). Adding EN signal on $memory\u_neuron_memory.x_mem[5]$4481 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[5]). Adding EN signal on $memory\u_neuron_memory.x_mem[6]$4483 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[6]). Adding EN signal on $memory\u_neuron_memory.x_mem[7]$4485 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[7]). Adding EN signal on $memory\u_neuron_memory.x_mem[8]$4487 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[8]). Adding EN signal on $memory\u_neuron_memory.x_mem[9]$4489 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[9]). Adding EN signal on $memory\u_neuron_memory.x_mem[10]$4491 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[10]). Adding EN signal on $memory\u_neuron_memory.x_mem[11]$4493 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[11]). Adding EN signal on $memory\u_neuron_memory.x_mem[12]$4495 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[12]). Adding EN signal on $memory\u_neuron_memory.x_mem[13]$4497 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[13]). Adding EN signal on $memory\u_neuron_memory.x_mem[14]$4499 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[14]). Adding EN signal on $memory\u_neuron_memory.x_mem[15]$4501 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[15]). Adding EN signal on $memory\u_neuron_memory.x_mem[16]$4503 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[16]). Adding EN signal on $memory\u_neuron_memory.x_mem[17]$4505 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[17]). Adding EN signal on $memory\u_neuron_memory.x_mem[18]$4507 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[18]). Adding EN signal on $memory\u_neuron_memory.x_mem[19]$4509 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[19]). Adding EN signal on $memory\u_neuron_memory.x_mem[20]$4511 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[20]). Adding EN signal on $memory\u_neuron_memory.x_mem[21]$4513 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[21]). Adding EN signal on $memory\u_neuron_memory.x_mem[22]$4515 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[22]). Adding EN signal on $memory\u_neuron_memory.x_mem[23]$4517 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[23]). Adding EN signal on $memory\u_neuron_memory.x_mem[24]$4519 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[24]). Adding EN signal on $memory\u_neuron_memory.x_mem[25]$4521 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[25]). Adding EN signal on $memory\u_neuron_memory.x_mem[26]$4523 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[26]). Adding EN signal on $memory\u_neuron_memory.x_mem[27]$4525 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[27]). Adding EN signal on $memory\u_neuron_memory.x_mem[28]$4527 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[28]). Adding EN signal on $memory\u_neuron_memory.x_mem[29]$4529 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[29]). Adding EN signal on $memory\u_neuron_memory.x_mem[30]$4531 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[30]). Adding EN signal on $memory\u_neuron_memory.x_mem[31]$4533 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:341$422_DATA[7:0]$429, Q = \u_neuron_memory.x_mem[31]). Adding EN signal on $memory\u_neuron_memory.w_mem[0]$4943 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[0]). Adding EN signal on $memory\u_neuron_memory.w_mem[1]$4945 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[1]). Adding EN signal on $memory\u_neuron_memory.w_mem[2]$4947 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[2]). Adding EN signal on $memory\u_neuron_memory.w_mem[3]$4949 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[3]). Adding EN signal on $memory\u_neuron_memory.w_mem[4]$4951 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[4]). Adding EN signal on $memory\u_neuron_memory.w_mem[5]$4953 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[5]). Adding EN signal on $memory\u_neuron_memory.w_mem[6]$4955 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[6]). Adding EN signal on $memory\u_neuron_memory.w_mem[7]$4957 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[7]). Adding EN signal on $memory\u_neuron_memory.w_mem[8]$4959 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[8]). Adding EN signal on $memory\u_neuron_memory.w_mem[9]$4961 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[9]). Adding EN signal on $memory\u_neuron_memory.w_mem[10]$4963 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[10]). Adding EN signal on $memory\u_neuron_memory.w_mem[11]$4965 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[11]). Adding EN signal on $memory\u_neuron_memory.w_mem[12]$4967 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[12]). Adding EN signal on $memory\u_neuron_memory.w_mem[13]$4969 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[13]). Adding EN signal on $memory\u_neuron_memory.w_mem[14]$4971 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[14]). Adding EN signal on $memory\u_neuron_memory.w_mem[15]$4973 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[15]). Adding EN signal on $memory\u_neuron_memory.w_mem[16]$4975 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[16]). Adding EN signal on $memory\u_neuron_memory.w_mem[17]$4977 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[17]). Adding EN signal on $memory\u_neuron_memory.w_mem[18]$4979 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[18]). Adding EN signal on $memory\u_neuron_memory.w_mem[19]$4981 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[19]). Adding EN signal on $memory\u_neuron_memory.w_mem[20]$4983 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[20]). Adding EN signal on $memory\u_neuron_memory.w_mem[21]$4985 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[21]). Adding EN signal on $memory\u_neuron_memory.w_mem[22]$4987 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[22]). Adding EN signal on $memory\u_neuron_memory.w_mem[23]$4989 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[23]). Adding EN signal on $memory\u_neuron_memory.w_mem[24]$4991 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[24]). Adding EN signal on $memory\u_neuron_memory.w_mem[25]$4993 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[25]). Adding EN signal on $memory\u_neuron_memory.w_mem[26]$4995 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[26]). Adding EN signal on $memory\u_neuron_memory.w_mem[27]$4997 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[27]). Adding EN signal on $memory\u_neuron_memory.w_mem[28]$4999 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[28]). Adding EN signal on $memory\u_neuron_memory.w_mem[29]$5001 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[29]). Adding EN signal on $memory\u_neuron_memory.w_mem[30]$5003 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[30]). Adding EN signal on $memory\u_neuron_memory.w_mem[31]$5005 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:374$423_DATA[7:0]$432, Q = \u_neuron_memory.w_mem[31]). Adding EN signal on $memory\u_neuron_memory.y_reg[0]$5405 ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$4447, Q = \u_neuron_memory.y_reg[0]). Adding SRST signal on $auto$ff.cc:337:slice$5601 ($dffe) from module spi_neuron_top (D = $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:433$424_DATA[7:0]$435, Q = \u_neuron_memory.y_reg[0], rval = 8'00000000). 19.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 66 unused cells and 66 unused wires. 19.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 19.16. Rerunning OPT passes. (Maybe there is more to do..) 19.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 19.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 19.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 1120 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 19.20. Executing OPT_DFF pass (perform DFF optimizations). 19.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 19.22. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 19.23. Finished fast OPT passes. (There is nothing left to do.) 20. Executing TECHMAP pass (map to technology primitives). 20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 20.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=14:B_WIDTH=1:A_WIDTH=14:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=14:B_WIDTH=1:A_WIDTH=14:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=14:B_WIDTH=1:A_WIDTH=14:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $paramod$constmap:ebf8a2d6c81183a7f70f06a5ce0300f7890fee49$paramod$614926ddc2084829fa9e6b581df1fdf9cc20df34\_90_shift_shiftx for cells of type $shiftx. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Using extmapper simplemap for cells of type $logic_and. Running "alumacc" on wrapper $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$le:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$gt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=32:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=1:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=1:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=1:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:Y_WIDTH=16:B_WIDTH=8:A_WIDTH=8:B_SIGNED=1:A_SIGNED=1:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=1:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=1:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=1:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=32:B_WIDTH=32:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=1:B_WIDTH=1:A_WIDTH=1:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=1:B_WIDTH=1:A_WIDTH=1:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=1:B_WIDTH=1:A_WIDTH=1:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=6:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=6:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=6:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=6:B_WIDTH=1:A_WIDTH=6:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=6:B_WIDTH=1:A_WIDTH=6:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=6:B_WIDTH=1:A_WIDTH=6:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=22:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=22:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=22:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$sub:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=8:B_WIDTH=8:A_WIDTH=8:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $paramod$constmap:f1372740d55e3571b0e146ea54d721065f423f86$paramod$796607324003502d2965a80ed5fa389e4a388b81\_90_shift_shiftx for cells of type $shiftx. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=3:B_WIDTH=3:A_WIDTH=3:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=3:B_WIDTH=3:A_WIDTH=3:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=3:B_WIDTH=3:A_WIDTH=3:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=3:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=3:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=22:B_WIDTH=3:A_WIDTH=22:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$sub:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=4:B_WIDTH=4:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=16:B_WIDTH=16:A_WIDTH=16:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$sub:Y_WIDTH=16:B_WIDTH=16:A_WIDTH=16:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=16:B_WIDTH=16:A_WIDTH=16:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Running "alumacc" on wrapper $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=2:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=2:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:Y_WIDTH=2:B_WIDTH=2:A_WIDTH=2:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $paramod$constmap:72feeb675a13be11da2f7fd881bfaac01d417b2e$paramod$f799933c7a2c73f0171e55c59a9c12bb6f45de64\_90_shift_shiftx for cells of type $shiftx. Running "alumacc" on wrapper $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:Y_WIDTH=1:B_WIDTH=32:A_WIDTH=4:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47. Using extmapper simplemap for cells of type $dff. Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu. Using template $paramod$a7817265ef3ab2ee43da53bbd8a90f6450d412d9\_90_alu for cells of type $alu. Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_90_alu for cells of type $alu. Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_90_alu for cells of type $alu. Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\_90_alu for cells of type $alu. Using template $paramod$5795de66b4fd8cc5bd187dddeed92f207a6f390d\_90_alu for cells of type $alu. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_90_alu for cells of type $alu. Using template $paramod$e161c1674351796cd6dd381e70ff05458bfe7755\_90_alu for cells of type $alu. Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_90_alu for cells of type $alu. Using template $paramod$6cf9020614225d7c3916d5c4139d794ea8448572\_90_alu for cells of type $alu. Using template $paramod$7a00885c4503e0d6395d87bcf5ed878899b94083\_90_alu for cells of type $alu. Using extmapper maccmap for cells of type $macc_v2. add \u_neuron_memory.u_neuron.u_mac8.x_bus [7:0] * \u_neuron_memory.u_neuron.u_mac8.w_bus [7:0] (8x8 bits, signed) add \u_neuron_memory.u_neuron.u_mac8.x_bus [15:8] * \u_neuron_memory.u_neuron.u_mac8.w_bus [15:8] (8x8 bits, signed) Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_90_alu for cells of type $alu. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using template $paramod$713617589782cfade849bb573b5c36106c4b708f\_90_alu for cells of type $alu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001110 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000001110 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000100000 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010110 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010110 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000110 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000110 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001000 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000001000 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. No more expansions possible. 21. Executing OPT pass (performing simple optimizations). 21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 11545 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10825 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10510 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10386 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10343 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10314 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10294 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10280 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10278 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 10277 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 1268 cells. 21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 10277 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 21.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$8261 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$8848, Q = \u_psram_ctrl.dq_oe, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$8218 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$8824, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$8217 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$8794, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$8216 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$8776, Q = \u_psram_ctrl.psram_we_n, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$8215 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$8765, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$8214 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$8755, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$8211 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$8726, Q = \u_psram_ctrl.mem_ready, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$7760 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$10803, Q = \u_neuron_memory.access_req, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$14945 ($_DFF_P_) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653$rdmux[0][1][0]$b$4455 [5], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$652 [5], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$14943 ($_DFF_P_) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653$rdmux[0][1][1]$a$4457 [3], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$652 [3], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$14944 ($_DFF_P_) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653$rdmux[0][0][0]$a$4451 [4], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$652 [4], rval = 1'0). 21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 2284 unused cells and 3893 unused wires. 21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 21.9. Rerunning OPT passes. (Maybe there is more to do..) 21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 8008 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 7998 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 7995 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 13 cells. 21.13. Executing OPT_DFF pass (perform DFF optimizations). 21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 17 unused wires. 21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 21.16. Rerunning OPT passes. (Maybe there is more to do..) 21.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 21.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 7995 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 21.20. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$14940 ($_DFF_P_) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$4314 [0], Q = $flatten\u_spi_engine.$auto$proc_rom.cc:154:do_switch$652 [0], rval = 1'0). 21.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 1 unused cells and 0 unused wires. 21.22. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 21.23. Rerunning OPT passes. (Maybe there is more to do..) 21.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 21.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 7994 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 21.27. Executing OPT_DFF pass (perform DFF optimizations). 21.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 21.29. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 21.30. Finished fast OPT passes. (There is nothing left to do.) 22. Executing ABC pass (technology mapping using ABC). 22.1. Extracting gate netlist of module `\spi_neuron_top' to `/input.blif'.. Replacing 1012 occurrences of constant undef bits with constant zero bits 22.1.1. Executed ABC. Extracted 6539 gates and 7742 wires to a netlist network with 1199 inputs and 629 outputs. Running ABC script: /abc.script ABC: ======== ABC command line "source /abc.script" ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 22.1.2. Re-integrating ABC results. ABC RESULTS: AND cells: 2388 ABC RESULTS: MUX cells: 395 ABC RESULTS: NOT cells: 409 ABC RESULTS: OR cells: 1445 ABC RESULTS: XOR cells: 654 ABC RESULTS: ZERO cells: 9 ABC RESULTS: internal signals: 5914 ABC RESULTS: input signals: 1199 ABC RESULTS: output signals: 629 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 4078 unused wires. 23. Executing SYNTH_LATTICE pass. 23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 23.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 23.3. Executing HIERARCHY pass (managing design hierarchy). 23.3.1. Analyzing design hierarchy.. Top module: \spi_neuron_top 23.3.2. Analyzing design hierarchy.. Top module: \spi_neuron_top Removed 0 unused modules. 23.4. Executing PROC pass (convert processes to netlists). 23.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 23.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 23.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 23.4.4. Executing PROC_INIT pass (extract init attributes). 23.4.5. Executing PROC_ARST pass (detect async resets in processes). 23.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 23.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 23.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 23.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 23.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 23.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 23.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.5. Executing CHECK pass (checking for obvious problems). Checking module spi_neuron_top... Found and reported 0 problems. 23.6. Executing FLATTEN pass (flatten design). 23.7. Executing TRIBUF pass. 23.8. Executing DEMINOUT pass (demote inout ports to input or output). Demoting inout port spi_neuron_top.psram_dq to output. 23.9. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.11. Executing CHECK pass (checking for obvious problems). Checking module spi_neuron_top... Found and reported 0 problems. 23.12. Executing OPT pass (performing simple optimizations). 23.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6746 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 6739 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 7 cells. 23.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 23.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6739 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.12.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7221 ($_SDFFE_PP0P_) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7321 ($_SDFFE_PP0P_) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7595 ($_SDFFE_PP0P_) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7651 ($_SDFFE_PP0P_) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7698 ($_SDFFE_PP0P_) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6509 ($_SDFFE_PP0P_) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7870 ($_SDFFE_PP0P_) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$8042 ($_SDFFE_PP0P_) from module spi_neuron_top. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$8106 ($_SDFFE_PP0P_) from module spi_neuron_top. 23.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 6 unused cells and 13 unused wires. 23.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.12.9. Rerunning OPT passes. (Maybe there is more to do..) 23.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 23.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6459 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 6454 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 5 cells. 23.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7848 ($_SDFFE_PP0P_) from module spi_neuron_top. 23.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 142 unused cells and 405 unused wires. 23.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.12.16. Rerunning OPT passes. (Maybe there is more to do..) 23.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 23.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.12.20. Executing OPT_DFF pass (perform DFF optimizations). 23.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.12.23. Finished fast OPT passes. (There is nothing left to do.) 23.13. Executing FSM pass (extract and optimize FSM). 23.13.1. Executing FSM_DETECT pass (finding FSMs in design). 23.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 23.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 23.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 23.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 23.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 23.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 23.14. Executing OPT pass (performing simple optimizations). 23.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 23.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.14.6. Executing OPT_DFF pass (perform DFF optimizations). 23.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.14.9. Finished fast OPT passes. (There is nothing left to do.) 23.15. Executing WREDUCE pass (reducing word size of cells). Removed top 4 bits (of 6) from wire spi_neuron_top.$$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$653$rdreg[0]$d. Removed top 1 bits (of 22) from wire spi_neuron_top.i8_mem_addr. Removed top 1 bits (of 22) from wire spi_neuron_top.psram_mem_addr. 23.16. Executing PEEPOPT pass (run peephole optimizers). 23.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 3 unused wires. 23.18. Executing SHARE pass (SAT-based resource sharing). 23.19. Executing TECHMAP pass (map to technology primitives). 23.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 23.19.2. Continuing TECHMAP pass. No more expansions possible. 23.20. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.22. Executing TECHMAP pass (map to technology primitives). 23.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 23.22.2. Continuing TECHMAP pass. No more expansions possible. 23.23. Executing TECHMAP pass (map to technology primitives). 23.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 23.23.2. Continuing TECHMAP pass. No more expansions possible. 23.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module spi_neuron_top: created 0 $alu and 0 $macc cells. 23.25. Executing OPT pass (performing simple optimizations). 23.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 23.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.25.6. Executing OPT_DFF pass (perform DFF optimizations). 23.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.25.9. Finished fast OPT passes. (There is nothing left to do.) 23.26. Executing MEMORY pass. 23.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 23.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 23.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 23.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 23.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 23.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 23.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 23.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 23.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 23.29. Executing TECHMAP pass (map to technology primitives). 23.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 23.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 23.29.3. Continuing TECHMAP pass. No more expansions possible. 23.30. Executing OPT pass (performing simple optimizations). 23.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.30.3. Executing OPT_DFF pass (perform DFF optimizations). 23.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.30.5. Finished fast OPT passes. 23.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 23.32. Executing OPT pass (performing simple optimizations). 23.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \spi_neuron_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 23.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \spi_neuron_top. Performed a total of 0 changes. 23.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.32.6. Executing OPT_DFF pass (perform DFF optimizations). 23.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.32.9. Finished fast OPT passes. (There is nothing left to do.) 23.33. Executing TECHMAP pass (map to technology primitives). 23.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 23.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 23.33.3. Continuing TECHMAP pass. No more expansions possible. 23.34. Executing OPT pass (performing simple optimizations). 23.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6311 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 0 cells. 23.34.3. Executing OPT_DFF pass (perform DFF optimizations). 23.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.34.5. Finished fast OPT passes. 23.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. 23.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 23.37. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\spi_neuron_top'. Computing hashes of 6328 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 6321 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Computing hashes of 6314 cells of `\spi_neuron_top'. Finding duplicate cells in `\spi_neuron_top'. Removed a total of 14 cells. 23.38. Executing TECHMAP pass (map to technology primitives). 23.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 23.38.2. Continuing TECHMAP pass. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. No more expansions possible. 23.39. Executing OPT_EXPR pass (perform const folding). Optimizing module spi_neuron_top. 23.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). 23.41. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in spi_neuron_top. 23.42. Executing ATTRMVCP pass (move or copy attributes). 23.43. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \spi_neuron_top.. Removed 0 unused cells and 8046 unused wires. 23.44. Executing CHECK pass (checking for obvious problems). Checking module spi_neuron_top... Found and reported 0 problems. 23.45. Executing TECHMAP pass (map to technology primitives). 23.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 23.45.2. Continuing TECHMAP pass. No more expansions possible. 23.46. Executing ABC9 pass. 23.46.1. Executing ABC9_OPS pass (helper functions for ABC9). 23.46.2. Executing ABC9_OPS pass (helper functions for ABC9). 23.46.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module spi_neuron_top. Found 0 SCCs. 23.46.4. Executing ABC9_OPS pass (helper functions for ABC9). 23.46.5. Executing TECHMAP pass (map to technology primitives). 23.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 23.46.5.2. Continuing TECHMAP pass. No more expansions possible. 23.46.6. Executing OPT pass (performing simple optimizations). 23.46.6.1. Executing OPT_EXPR pass (perform const folding). 23.46.6.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 23.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 23.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 23.46.6.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 23.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). 23.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). 23.46.6.8. Executing OPT_EXPR pass (perform const folding). 23.46.6.9. Finished fast OPT passes. (There is nothing left to do.) 23.46.7. Executing TECHMAP pass (map to technology primitives). 23.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 23.46.7.2. Continuing TECHMAP pass. No more expansions possible. 23.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 23.46.9. Executing ABC9_OPS pass (helper functions for ABC9). 23.46.10. Executing ABC9_OPS pass (helper functions for ABC9). 23.46.11. Executing ABC9_OPS pass (helper functions for ABC9). 23.46.12. Executing AIGMAP pass (map logic to AIG). Module spi_neuron_top: replaced 2312 cells with 12349 new cells, skipped 4001 cells. replaced 4 cell types: 394 $_MUX_ 1 $_ORNOT_ 1277 $_OR_ 640 $_XOR_ not replaced 4 cell types: 2209 $_AND_ 347 $_NOT_ 13 $scopeinfo 1432 TRELLIS_FF 23.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9). 23.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9). 23.46.12.3. Executing XAIGER backend. Extracted 6589 AND gates and 16793 wires from module `spi_neuron_top' to a netlist network with 1437 inputs and 918 outputs. 23.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). 23.46.12.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 1437/ 918 and = 6085 lev = 93 (7.32) mem = 0.11 MB box = 0 bb = 0 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 1437/ 918 and = 8188 lev = 89 (7.05) mem = 0.13 MB ch = 914 box = 0 bb = 0 ABC: cst = 0 cls = 847 lit = 914 unused = 7864 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 8188. Ch = 847. Total mem = 1.73 MB. Peak cut mem = 0.18 MB. ABC: P: Del = 11531.00. Ar = 10073.0. Edge = 11446. Cut = 106947. T = 0.01 sec ABC: P: Del = 11319.00. Ar = 9893.0. Edge = 11409. Cut = 105053. T = 0.01 sec ABC: P: Del = 11319.00. Ar = 5972.0. Edge = 10220. Cut = 196765. T = 0.02 sec ABC: F: Del = 11315.00. Ar = 3882.0. Edge = 8476. Cut = 161772. T = 0.02 sec ABC: A: Del = 11315.00. Ar = 3490.0. Edge = 7766. Cut = 154100. T = 0.02 sec ABC: A: Del = 11315.00. Ar = 3430.0. Edge = 7705. Cut = 152568. T = 0.02 sec ABC: Total time = 0.11 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: Timing manager is given but there is no GIA of boxes. ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. ABC: + &ps -l ABC: /input : i/o = 1437/ 918 and = 9864 lev = 89 (7.12) mem = 0.15 MB box = 0 bb = 0 ABC: Mapping (K=7) : lut = 1993 edge = 7705 lev = 24 (3.45) mem = 0.09 MB ABC: LUT = 1993 : 2=364 18.3 % 3=387 19.4 % 4=747 37.5 % 5=260 13.0 % 6=117 5.9 % 7=118 5.9 % Ave = 3.87 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.08 sec ABC: + time ABC: elapse: 0.55 seconds, total: 0.55 seconds 23.46.12.6. Executing AIGER frontend. Removed 15522 unused cells and 17559 unused wires. 23.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 1997 ABC RESULTS: input signals: 117 ABC RESULTS: output signals: 633 Removing temp directory. 23.46.13. Executing TECHMAP pass (map to technology primitives). 23.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 23.46.13.2. Continuing TECHMAP pass. No more expansions possible. Removed 261 unused cells and 19326 unused wires. 23.47. Executing TECHMAP pass (map to technology primitives). 23.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 23.47.2. Continuing TECHMAP pass. Using template $paramod$168aeef333136ff4f1f2ce3a62c8b6d1ffc7dc28$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$ba08b704826847e4ffdf1dcbe5f855eb0c3798c5$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$bbd32bd467d62890b484fe941be0dc6df13618f5$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$7d45bd12c01d1778446c9474bd2c34ae7ad041ca$lut for cells of type $lut. Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$fca82610c4582bae0c561edc640eb928b48fbdcf$lut for cells of type $lut. Using template $paramod$5c32c59025c0b98f20e63f249d83e7ebb4b085e3$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut. Using template $paramod$62fb31b1a783eac472264027492b859f55ad08ed$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b$lut for cells of type $lut. Using template $paramod$a9233f8009cda7205cc63df2854805a5ea76ab56$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304$lut for cells of type $lut. Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2$lut for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee$lut for cells of type $lut. Using template $paramod$29f8e8d81860939642ad82bb36af3cbb544c3dea$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$faeedcc045c5fd2fbd2cb0c24e50ae83fb289140$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$b00f453fcf70c4c06b1a678153367d3ddd6cb7fd$lut for cells of type $lut. Using template $paramod$9e394303e290a474880b56f98766417009256d93$lut for cells of type $lut. Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5$lut for cells of type $lut. Using template $paramod$1c4187ad9de7edc544fc08819589445a66513fd1$lut for cells of type $lut. Using template $paramod$ff74d3b36221c7c7b417c242545ab45c7d96a8ff$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut. Using template $paramod$38204f8fb7008381b30b46c101da3517f7ab732f$lut for cells of type $lut. Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da$lut for cells of type $lut. Using template $paramod$03148d54f1229f29049ed254c2fbe5513917d0b7$lut for cells of type $lut. Using template $paramod$19457468c03b53ec09024ada785c6816b7d0407d$lut for cells of type $lut. Using template $paramod$0c051d83397849eb42a05264475ba40efb861eb2$lut for cells of type $lut. Using template $paramod$5b86c44f0efdee8d612fc46787b79cf7bb30d652$lut for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. Using template $paramod$fa874836ac64420bb7d9c67e99a0912e16a50ef2$lut for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d$lut for cells of type $lut. Using template $paramod$f91974ed76679978bb5ed737ed2baef1784b50ab$lut for cells of type $lut. Using template $paramod$9a84d44a5fa76f659813be11c22415119b3af8f1$lut for cells of type $lut. Using template $paramod$cb1df2135f5c507c11fe37ab08c1b99d340a794a$lut for cells of type $lut. Using template $paramod$38446ff493f776d29ea4f3122b249720a55b03df$lut for cells of type $lut. Using template $paramod$a6d3e5434015ec298d91d97732b52a2b55564145$lut for cells of type $lut. Using template $paramod$1558908667e18ac9fc8947e38bdcf029c2d19078$lut for cells of type $lut. Using template $paramod$fc6feb7ca0813ec6f9a6e104d2344b22630ad56a$lut for cells of type $lut. Using template $paramod$346842b88e407bf40d83dc890111dffae3530202$lut for cells of type $lut. Using template $paramod$08376f7fae321567207e85bf6db3a9f247ca9620$lut for cells of type $lut. Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73$lut for cells of type $lut. Using template $paramod$29e6d4598488760861f6b73d2b7f65cb302fdcde$lut for cells of type $lut. Using template $paramod$4eca17702cbf901fe4a5de76d2901ae05f97dbd3$lut for cells of type $lut. Using template $paramod$adb84e058b0f32ce56f004e6ffa19883ace75fc0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$47767f5c382f8b63a0774a8330636654f073ecd1$lut for cells of type $lut. Using template $paramod$5ca766f4962be8dc37343c7cd8247af8e40ef7c1$lut for cells of type $lut. Using template $paramod$133ad27679cc12d115c56a20436ffefcefb608a9$lut for cells of type $lut. Using template $paramod$1be3a10aca64bc8b3d140a9dcfb9bac7a6744be9$lut for cells of type $lut. Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f$lut for cells of type $lut. Using template $paramod$2ae42d4e581238fd3d7b098d301bf704be47f93e$lut for cells of type $lut. Using template $paramod$6204cb1477b6817575f39c70db34cb0bbff2c9bd$lut for cells of type $lut. Using template $paramod$b3f94333dbf3181a725350c53ca6d0a4f035c952$lut for cells of type $lut. Using template $paramod$baea6f3d91b804faeae4d56c21c80da6a43b531f$lut for cells of type $lut. Using template $paramod$4888f2121a1fba4d507203534ae54782bc81e02e$lut for cells of type $lut. Using template $paramod$dd1c65e4a484361739066d67f8e032a3cc8a5ec8$lut for cells of type $lut. Using template $paramod$3fad85fdb6a08fb42cfca60fefbe8b4b9331e469$lut for cells of type $lut. Using template $paramod$99e243cf2610d96af12f5e281daca78176769214$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$2ecd3bacfa12666bb202e156b018d1cec800b8e7$lut for cells of type $lut. Using template $paramod$89e81ec938a5121bf0326afabb244602c5fb5e5e$lut for cells of type $lut. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut. Using template $paramod$6eacffe18beecc5e0db5ed2bff70eb42658083f1$lut for cells of type $lut. Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$a41d0e3b97911dca5b893a7d849ab04257ab9d97$lut for cells of type $lut. Using template $paramod$51adb1afea57a9560b9534400e9af12cb2df0ba0$lut for cells of type $lut. Using template $paramod$fbbe736f93493e471cebba9fcdb41c333e605d93$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut. Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut. Using template $paramod$2f2b9b736b3ea0a0b958cef6434418c8f6a25d02$lut for cells of type $lut. Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d$lut for cells of type $lut. Using template $paramod$c01d1f1a2c22a23f58c65a92a9c94eaeebcde834$lut for cells of type $lut. Using template $paramod$2fd413483e3b791ac716008fa967f779bee6134d$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001101 for cells of type $lut. Using template $paramod$7eb64b226657f4674ae0077d65976ccd9e7d4a51$lut for cells of type $lut. Using template $paramod$29658bc1d63574cbf1a532974926e1a5cad395a7$lut for cells of type $lut. Using template $paramod$a9825d1da060129fec6106f63dced409ac7120a0$lut for cells of type $lut. Using template $paramod$a6ea67083a02e597d5520679ce03acd52291dcb5$lut for cells of type $lut. Using template $paramod$b5192abe244aeb58cb02a59d210f258ab76949c6$lut for cells of type $lut. Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut. Using template $paramod$8c21337c6ac7a2bd5198dee32c10a1fe872a76ba$lut for cells of type $lut. Using template $paramod$78e1751931755f088c8bc676bcbc3bb642c26bfc$lut for cells of type $lut. Using template $paramod$7a144b8ea62c1daaf88b55bccc0bbc1212f0de48$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010010 for cells of type $lut. Using template $paramod$43bf0031f82ff95689b294665912ae7a284f9c5c$lut for cells of type $lut. Using template $paramod$25445fb9dd8fc77490980c6bd2e9dbc53c6e84a5$lut for cells of type $lut. Using template $paramod$c627e7fc36fd5f8fca16a74816d11be60e4b9470$lut for cells of type $lut. Using template $paramod$e7f6be4a4fa0f214294a50b38b063a3361236b3b$lut for cells of type $lut. Using template $paramod$041aa1dcdd60d3c4ff6eb6326c9e544a0334c607$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$10543a732aea66b60afd87a1e19d8546d935406b$lut for cells of type $lut. Using template $paramod$1b5ba30ee2fa94d0b4c47ffd223e9408bab5fb5f$lut for cells of type $lut. Using template $paramod$4c3e441bae6a2bbcdcee7c54a3b6ae5dd40fa4d9$lut for cells of type $lut. Using template $paramod$251d5b0306124723ba7f56b3f354d58c9d465e91$lut for cells of type $lut. Using template $paramod$5d2a75dcd2d4c90fca15a1510e937941a10741dd$lut for cells of type $lut. Using template $paramod$dc6e804ccb35fa5c9574ef288c0c75396c54033e$lut for cells of type $lut. Using template $paramod$38ec4e8c9c23b1b17d100e8edc36f66555e44571$lut for cells of type $lut. Using template $paramod$5b737cfb6b9d3eeaade0be960b013e33de63164c$lut for cells of type $lut. Using template $paramod$b419762729002fa71ae327c5ca3ff5e6284cd0aa$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100001 for cells of type $lut. Using template $paramod$e6a2e542cd9c99b044e4f33f59d0b7f89e0895c5$lut for cells of type $lut. Using template $paramod$940ef9b71138555d1b6ac70ec515a82a5480d194$lut for cells of type $lut. Using template $paramod$3eb8805ccd6f91bad96dcbf190c2fb4f72f4634f$lut for cells of type $lut. Using template $paramod$787d97f746f0836288db7d4c53ced238fc5aac62$lut for cells of type $lut. Using template $paramod$70eb4781fca66a68cfee1980229b71a5008ac5fa$lut for cells of type $lut. Using template $paramod$60dcb27984c4770c7806abdf774187c5de5954b1$lut for cells of type $lut. Using template $paramod$d5a68bba96e0025d67d276c5733d283e8abf15cc$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$634be8dac7673ae6f91e2a8a3a2c0e8609542e36$lut for cells of type $lut. Using template $paramod$64830e06f35951be3da529c7e2c48aadaad1239b$lut for cells of type $lut. Using template $paramod$2e242b3870fd1c78b14e7f95ffa17bf0b3a3339c$lut for cells of type $lut. Using template $paramod$5d4df5ecb99331ee91628f3ee69af2d33735370a$lut for cells of type $lut. Using template $paramod$fa64a60d70b75aae55f88993e8d9332f5962f355$lut for cells of type $lut. Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$e0c0e98e87edd6a2508d5d59e63c1d230443d812$lut for cells of type $lut. Using template $paramod$8fbefeb634a4a275ce7207ab33dd7f7b52a837d6$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010100 for cells of type $lut. Using template $paramod$48858a0cdda2de6934604a272e0a7e64a67fda48$lut for cells of type $lut. Using template $paramod$c508ffccf3cb0d44491eb1a488b3e92b1375f011$lut for cells of type $lut. Using template $paramod$0d2473405773f58c1f62e51cfbb840d8d32f36fb$lut for cells of type $lut. Using template $paramod$74b3a94f60f921d28160ef7112e43b5a818767dc$lut for cells of type $lut. Using template $paramod$3ef8de336fbc9fc8d09ced3c3787d4bb5cd4e66b$lut for cells of type $lut. Using template $paramod$014e4a88d8709c5e683db3ba1ac730d1d968a3ee$lut for cells of type $lut. Using template $paramod$24c3eb9836f3b1174515f65be7816ca0c03f034a$lut for cells of type $lut. Using template $paramod$7044e4baed753570730e90c98a63f9e1d4e3a030$lut for cells of type $lut. Using template $paramod$05896c1110f557c6a9f9e7ecbe71099ef8aa8d6b$lut for cells of type $lut. Using template $paramod$65b734300686a441f87b09b7c8160c7e09f368c6$lut for cells of type $lut. Using template $paramod$27834a6c0d885a88b91fe215be18f269d6305094$lut for cells of type $lut. Using template $paramod$3e8a64cc89a45ddf8d248a207e64894a267a78e6$lut for cells of type $lut. Using template $paramod$206689f2304e0f7e4a12032df8114d3f691d6fec$lut for cells of type $lut. Using template $paramod$5c668e4544605270274b0788fe4c5e0d858d1c28$lut for cells of type $lut. Using template $paramod$d06dbd00bba50c9295fd0e16198b650fe226d848$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110100 for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f$lut for cells of type $lut. Using template $paramod$a848d346c879f8f00f82059f154d5c5508a704b7$lut for cells of type $lut. Using template $paramod$5964dec528c7ded1ee9f528024feacf1107270a1$lut for cells of type $lut. Using template $paramod$9f6e5a164bd392e913b309507410922801688c11$lut for cells of type $lut. Using template $paramod$a39f9d288404165872d818174c5bbc80ef526538$lut for cells of type $lut. Using template $paramod$29e36154852da57808ca43d73feff0ade0c2d8ee$lut for cells of type $lut. Using template $paramod$eb28e3bdb9860e65d4433ccbb0173831b3776b59$lut for cells of type $lut. Using template $paramod$bbff152d4fef0994ad114a073eed501d19706a5a$lut for cells of type $lut. Using template $paramod$8a6f343867429cd986d693845c1833d4d3649834$lut for cells of type $lut. Using template $paramod$480632dc6f7c037df6062cf8bf88300b5262c395$lut for cells of type $lut. Using template $paramod$fa60c71a4e37328669070deacdb6e0ef6cbbe24f$lut for cells of type $lut. Using template $paramod$962c293779973b70fbb3163d884aaaa3af55206d$lut for cells of type $lut. Using template $paramod$99c19c0566a951fe3cfad847ec3d342fd963d7b0$lut for cells of type $lut. Using template $paramod$ade0383267de8dbe56b844c039c28e7783ed4922$lut for cells of type $lut. Using template $paramod$78334e4338500d290a66d65c0b55002189f47944$lut for cells of type $lut. Using template $paramod$bd7578d8ce3e2437ea907b1d5f654d907114be68$lut for cells of type $lut. Using template $paramod$acf49cb7bd2805dee4b4ebb218aa5924b1be7704$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut. Using template $paramod$41f052d8521bcbb519ce879210c11f6b35846276$lut for cells of type $lut. Using template $paramod$da23b7235fac144f1d5285a62d4cdfdeea67122d$lut for cells of type $lut. Using template $paramod$c7bd487aeab1a353f51036693d6d2ea9ba490a2c$lut for cells of type $lut. Using template $paramod$601800bf091681efd3e3284436a11eb4e2351e2d$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010111 for cells of type $lut. Using template $paramod$bf0d22492b141397adcabc2e359ee0f860225fa5$lut for cells of type $lut. Using template $paramod$3d13670bb53a9369cfe2c5949a3d965ac0007edf$lut for cells of type $lut. Using template $paramod$8aaba135fd671c04809571309aa0ad9d27f989c9$lut for cells of type $lut. Using template $paramod$f03d9aaaf4fbe2cff8c20255e9e33601cc69ae1d$lut for cells of type $lut. Using template $paramod$f17613914840c4d145d7389e8adef07aa8377d9f$lut for cells of type $lut. Using template $paramod$84da7e8ac842b452fe07087f1c1511d957ca28ee$lut for cells of type $lut. Using template $paramod$bb0f489a0ca091d6d929b26d537a943607f01c58$lut for cells of type $lut. Using template $paramod$39fab3cd9e42af69d85d3348c9fecfc18208736a$lut for cells of type $lut. Using template $paramod$b6e4e10551601903df8eda49219da1005eff04cb$lut for cells of type $lut. Using template $paramod$4b319a6b38c4fe3311c91d81322c47ccd22d5f76$lut for cells of type $lut. Using template $paramod$f05d4b8888c79762c43743d193b4196209b4613e$lut for cells of type $lut. Using template $paramod$a34ed9a91d7de47e4f066af090537198a9c91bec$lut for cells of type $lut. Using template $paramod$543738fa1cc1f6393d22789a4b75fa0f931058d3$lut for cells of type $lut. Using template $paramod$44f5d5cf465bd602770cf7630cf2759e8971307d$lut for cells of type $lut. Using template $paramod$0d5547d8ba58ba785755b3c9dbb8756360e37b27$lut for cells of type $lut. Using template $paramod$1b1f6487666090bf61105b77be44fd01aeb6c55f$lut for cells of type $lut. Using template $paramod$74cc8577a00e3dbe2da8ecb56b5b430f4023212d$lut for cells of type $lut. Using template $paramod$27fbbd9300dccac4a4e80b606f08a7801babf71e$lut for cells of type $lut. Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6$lut for cells of type $lut. Using template $paramod$859bbf20189511d5622298a363e8f136876f0d6c$lut for cells of type $lut. Using template $paramod$6df2bdde0dda2853f5f5b9a550fd1a1d6cc3fb87$lut for cells of type $lut. Using template $paramod$5c322f0a72e282b80c0bfb25e2bc93a4db10fe91$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6$lut for cells of type $lut. Using template $paramod$387af08f62809d1df13368ad3a230b72ccfa375f$lut for cells of type $lut. Using template $paramod$0392318cefd9d15f572622bd5a88290120220d9c$lut for cells of type $lut. Using template $paramod$c4a4cf1f67c598049dd5cb5cdb183838e000e772$lut for cells of type $lut. Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut. Using template $paramod$82ed25b11a6a11eb861f4dd3d46f5fc9aa1eebaf$lut for cells of type $lut. Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc$lut for cells of type $lut. Using template $paramod$f886ac98ba76b6932c20a4ca62195a194f66375f$lut for cells of type $lut. Using template $paramod$aa8e63e374e84c30d7ae66f79dbf102fd534f010$lut for cells of type $lut. Using template $paramod$169e3ff199948acb6289d60ee69a6cbdb1d4057e$lut for cells of type $lut. Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86$lut for cells of type $lut. Using template $paramod$b4d81fbb78ba26461d6ef588eec61a5ee711f593$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut. Using template $paramod$77268019239d7d46332da9cb6aa01cbf3ba29ee3$lut for cells of type $lut. Using template $paramod$05a4da37523b12ec112a6e9a9421e62b93ec6542$lut for cells of type $lut. Using template $paramod$d75bb3a732d9c867f50421698a0c27db6612f3cd$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f$lut for cells of type $lut. Using template $paramod$1231f30cfc31e72f9355de55568a4d1b045f87cc$lut for cells of type $lut. Using template $paramod$afc24e7a0cf8a9846730b7534c40e737e0e6eb00$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110111 for cells of type $lut. Using template $paramod$52c62f00753954c6d1811f0c661112213dfd9cfd$lut for cells of type $lut. Using template $paramod$ed6a68ffc70828a235ca29ddff5b89c1f3623c68$lut for cells of type $lut. Using template $paramod$74db7ebdc203ab2b8e34f5d81b5d1b49c6ee3ec6$lut for cells of type $lut. Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut. Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005$lut for cells of type $lut. Using template $paramod$2bdfdda73873e8931790d872b72220895e67fee5$lut for cells of type $lut. Using template $paramod$f11262efd21389d1eeb38a19f7f8b3890e042480$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut. Using template $paramod$5829f5d2a4c5757263ee6385c6142d3c7cf9e5be$lut for cells of type $lut. Using template $paramod$406ee6dee2c3b14fcc8513354f3f01b38599c7d0$lut for cells of type $lut. Using template $paramod$3f0549729b9cf7d6fa6533d688d092bceca9764e$lut for cells of type $lut. Using template $paramod$bdd5c098719319f84cd1ef04ada1863fe1d59132$lut for cells of type $lut. Using template $paramod$f33df134d929df41209541eb22cf437995c56f05$lut for cells of type $lut. Using template $paramod$15a8c046d8828a044f7367eb3a2af7f547843c91$lut for cells of type $lut. Using template $paramod$94ab1798f3b06ca51ab729e563e390f3de3426d8$lut for cells of type $lut. Using template $paramod$43803e4f9134ac742f4b69c10a5388a8452a64a3$lut for cells of type $lut. Using template $paramod$919fcc7afb126bb936d8e472fdde564b8c752934$lut for cells of type $lut. Using template $paramod$6efb77fe5f6a7ac946bc72d9854a86d61592009f$lut for cells of type $lut. Using template $paramod$c459c9f8d42117424a0070526e22ab3497eb714a$lut for cells of type $lut. Using template $paramod$61b481f3fd7d0fd09fb1be7f5772ef270eebaa00$lut for cells of type $lut. Using template $paramod$c33f23e645e40bee39f6c305396bb1ddf0ae9a2e$lut for cells of type $lut. Using template $paramod$024c2bb3f5ff1692d625b5c7cbb24c13279edf89$lut for cells of type $lut. Using template $paramod$d82deb277475f8b33421a0db6bf1adaa4ca34411$lut for cells of type $lut. Using template $paramod$169354262528eb1d69aad6945f918d47258847cd$lut for cells of type $lut. Using template $paramod$c51a2e553a2e730c6c97e90d556e6578b5bce0fe$lut for cells of type $lut. Using template $paramod$f88b89e96698878b19aef1b094f333c7e9bf9caa$lut for cells of type $lut. Using template $paramod$afef1cb2141d2a56f0b2a3bc83867dcb64283860$lut for cells of type $lut. Using template $paramod$b447b693193baa761a41f4ae4f086f3968e3955e$lut for cells of type $lut. Using template $paramod$37ee8aba19dcfe7a745db3bce977540907aaaa97$lut for cells of type $lut. Using template $paramod$0d333a82fa8323cc361eec438e3cffe090346171$lut for cells of type $lut. Using template $paramod$f4fbe550883c229356ed8ed8355fb73053f53cc0$lut for cells of type $lut. Using template $paramod$8aa914641d9da3ceaab54a09681d988e5887c82c$lut for cells of type $lut. Using template $paramod$e938a1cfb0102087ff6565ba278218aee3d50474$lut for cells of type $lut. Using template $paramod$b9b068df6e89eae6dd386fde976db31bc5bec143$lut for cells of type $lut. Using template $paramod$1eec201a77fdd6302dfa51adc5e8595dd42337fa$lut for cells of type $lut. Using template $paramod$595b4955041ceff09e28d600fe79275c24ba9878$lut for cells of type $lut. Using template $paramod$d46fdc0ae38122ef837a99fc20758f41f5fdc0f9$lut for cells of type $lut. Using template $paramod$81bbc874e40fad2cf4031d03f87659982a425554$lut for cells of type $lut. Using template $paramod$cd278571482e4bd13b94e1f6cccc7aa2d54deec5$lut for cells of type $lut. Using template $paramod$5c8d7b5a93b51443dc9c404b0c0a4ca0bc32fe5d$lut for cells of type $lut. Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7$lut for cells of type $lut. Using template $paramod$cd38dd330d700016f14998ef19ebaf96246fa764$lut for cells of type $lut. Using template $paramod$ffa07dcba308405094968d873c838b3efab932a3$lut for cells of type $lut. Using template $paramod$a50d8417db0f3a51891af8670e611f7f89ddeef4$lut for cells of type $lut. Using template $paramod$67e19ffbdb63ef2d42d602c6d9c3b99cd89f2912$lut for cells of type $lut. Using template $paramod$4ac73e90cabe3fd5423b3897754e1be51d1645fa$lut for cells of type $lut. Using template $paramod$1cd96fd908c53d9fe498f054bc32117d4254c10a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. Using template $paramod$efc60783c939ae41b2f3555af407b17c007b27f8$lut for cells of type $lut. Using template $paramod$f6f13587aa6d80df94ccd5c890c878a6bf6f3422$lut for cells of type $lut. Using template $paramod$72a7ca20c2c322b69851632d7ba6c43dc06a9abc$lut for cells of type $lut. Using template $paramod$5ad93ca2929d27e9fc2e77ed42ab808e0a39492d$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101011 for cells of type $lut. Using template $paramod$bd07a63588c6a531de987eab8d5eb412f4a07b2a$lut for cells of type $lut. Using template $paramod$abc15e64d9965f43bc4fd8f2b4ec5d10ba3f4368$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001110 for cells of type $lut. Using template $paramod$abde4d7a96b3bebaf423625a91a06a0f98378163$lut for cells of type $lut. Using template $paramod$561bb6256c33c63d57495957c2e4887a167efac7$lut for cells of type $lut. Using template $paramod$0f4044dd453db744a7f1b042f112769f624ef63b$lut for cells of type $lut. Using template $paramod$df246638f5d3f970a9de6e6a9e11832153570d23$lut for cells of type $lut. Using template $paramod$512b3a3d4196585fdaac3d618860f11b6497a17b$lut for cells of type $lut. Using template $paramod$b1ce548c22fb9791b32ddb7388b153cacde40870$lut for cells of type $lut. Using template $paramod$67c6e782034cbafc402c640d2c6ecca7824eee18$lut for cells of type $lut. Using template $paramod$7ebd51bb3fff72465510dac07eb1213b94ac96b5$lut for cells of type $lut. Using template $paramod$3412f2978b7fc15d45f55b18956ffd2b3d05915d$lut for cells of type $lut. Using template $paramod$aeabeb48b7087b5ec70dcb1ccda59e429f042015$lut for cells of type $lut. Using template $paramod$72a751d204330e5fdd0b14dc115df32a8565f57f$lut for cells of type $lut. Using template $paramod$5c9d981f79c4f2253671e2dbd39b499f63da5a32$lut for cells of type $lut. Using template $paramod$ee1e198aca20a28d0ba51ddc80a4a525aa9da411$lut for cells of type $lut. Using template $paramod$704cad882e2bedddf5c55ef18de55c67afe1e0ec$lut for cells of type $lut. Using template $paramod$180f5969c275574cbe742a947fc0587eeb95730e$lut for cells of type $lut. Using template $paramod$8903eaed52e2c3967ad963e2d0350898307cebf7$lut for cells of type $lut. Using template $paramod$c9afea4c621bb52f083cc70516a5bd7e8d4100e5$lut for cells of type $lut. Using template $paramod$e9a33f8910cac64e236ca6ab60d8f2a37b45ed64$lut for cells of type $lut. Using template $paramod$70bbd34fb81bf5e2923dbf45581e0b7f74504224$lut for cells of type $lut. Using template $paramod$38beb7a014c0789e99bfd9c2c76701fc60748601$lut for cells of type $lut. Using template $paramod$734a8728c6fe40bda88b802e90e6e88fa1136b6e$lut for cells of type $lut. Using template $paramod$7435ac187c4c78975bbb99ed6b44c88afe3c603a$lut for cells of type $lut. Using template $paramod$70ae5078ad021fe1a2f1e998b6406ccee539c450$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut. Using template $paramod$30fed8dd213601fb1cbf4b3807642ecf54122a93$lut for cells of type $lut. Using template $paramod$402865a3fbba165b42dbaeeb8caceb47e55a0474$lut for cells of type $lut. Using template $paramod$0a8d89415d0b90446780c664a35ecd09d4dd9dd3$lut for cells of type $lut. Using template $paramod$dd5166e5ca5e0688b79997cdb219a81d47a07e57$lut for cells of type $lut. Using template $paramod$9ebe374dcc2b2ae8c95ff916eba1efa824ae6c73$lut for cells of type $lut. Using template $paramod$89793b010525e0c986d3101176e21df2d0cfef09$lut for cells of type $lut. Using template $paramod$d5a4dd3399445cfa6acaa6962e6c78484dbd87ff$lut for cells of type $lut. Using template $paramod$9584c686f88f088831ad7e83ec06e4ba4f14e18e$lut for cells of type $lut. Using template $paramod$8466aae7f3132f822e70bbd8738850d820750479$lut for cells of type $lut. Using template $paramod$cfb9b012afd143cf593d77173d19bfa29ab7e0e6$lut for cells of type $lut. Using template $paramod$000141567205bafc81606a3e51c02d2bacd8c71a$lut for cells of type $lut. Using template $paramod$fbc1a4b85f85cee88b9b7a35ec67f4c8ed43faf1$lut for cells of type $lut. Using template $paramod$9d2d51c431b0b64cba43ecafc110603fdeff7831$lut for cells of type $lut. Using template $paramod$e850b6d88de7519ea447582d9e402ec288ee870e$lut for cells of type $lut. Using template $paramod$3908747b0c7364656d9c2c01065501659c858bee$lut for cells of type $lut. Using template $paramod$e32c27d0fe69cce5f363a5cebc169c574b92667b$lut for cells of type $lut. Using template $paramod$6ee648cdb4309524a604b83b01d77f88eb68c886$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110010 for cells of type $lut. Using template $paramod$e550d35df88290348c8edb50efa74ad454ba0f48$lut for cells of type $lut. Using template $paramod$b37a9a890b9890104435dcad740278bbb9bf2e30$lut for cells of type $lut. Using template $paramod$64cf72dcb4f2fa35b9d0c92f75f3c38ce6ea6fe4$lut for cells of type $lut. Using template $paramod$c5ea1407fd8e80a67b3053aedf83d0261eda3cbd$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000001 for cells of type $lut. Using template $paramod$1aba9b6e8f1c33c6a5bab44a6be16f3380f4b91c$lut for cells of type $lut. Using template $paramod$d0f51dc4d6d9b62e23ff06624bbe22a0d63e11a5$lut for cells of type $lut. Using template $paramod$23953811f9a1e831a4c3afa54c7c0c00652edb7e$lut for cells of type $lut. Using template $paramod$494ebb218118c652729c67bd362281136663afb9$lut for cells of type $lut. Using template $paramod$6b0bb1918987fa2ad50fef19125719930848c0f6$lut for cells of type $lut. Using template $paramod$d04448acbf27092b2b78e72c90465e35168b30fd$lut for cells of type $lut. Using template $paramod$55ca758746ecce8fe60c5feb0d0a5f7258d68d94$lut for cells of type $lut. Using template $paramod$19cecb57bb99bb288639d89db664f407eb5957b2$lut for cells of type $lut. Using template $paramod$180ba54022037712ed46e32c1d06533d7f621b4d$lut for cells of type $lut. Using template $paramod$c49834e615a08368472dfe9f2a6974c544906164$lut for cells of type $lut. Using template $paramod$350f22be2cb4bb24eb239ce11f21f4c49cf443d5$lut for cells of type $lut. Using template $paramod$b268648c7ddc48b9b58757d8745fc0d3567999b3$lut for cells of type $lut. Using template $paramod$cfafa08438ac86f7776a1c677f6d488afacff1bd$lut for cells of type $lut. Using template $paramod$cf2d85ea839dd9c6a50c2e4842356042bd6a7761$lut for cells of type $lut. Using template $paramod$c2bfcf549a386add7b6c460577ca10e82e5037e2$lut for cells of type $lut. Using template $paramod$a9d4626c045bbf11bce3a54cbe613d1ea1f12f80$lut for cells of type $lut. Using template $paramod$ddd24cf2e4b9c281ab178a03e26fa94a5b598ef6$lut for cells of type $lut. Using template $paramod$f64bc83bda7b7349f7d4c4ab1cdaa9fe87b8ee51$lut for cells of type $lut. Using template $paramod$15014b7d315249dcb75fa13dccef5e49a06cd03f$lut for cells of type $lut. Using template $paramod$35fdc43c2397f85b3228c4d7dbf0373076b99019$lut for cells of type $lut. Using template $paramod$31c9a59c01784818899a756a6aebec6523e9185d$lut for cells of type $lut. Using template $paramod$b810c97d68147be02fc5ee03d2d60db5cca90234$lut for cells of type $lut. Using template $paramod$978987faaf09bc5e1e2692159f729f66a0307aff$lut for cells of type $lut. Using template $paramod$61dbfffe165b884726f0b461e612b712b9b17b15$lut for cells of type $lut. Using template $paramod$bf3c695b03cbb3727b63eb2bf69127329bf3a602$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$85f78d00d135d3635491ce59a590df6b1ea0a8f6$lut for cells of type $lut. Using template $paramod$fb6f4b457d4c2f256e5b7594726b985737d1813b$lut for cells of type $lut. Using template $paramod$f85a1dabc344c73ce163ff16fa13cab64c817363$lut for cells of type $lut. Using template $paramod$f3d61162ae96bf57c7a3ced00299ee3aa3ae2194$lut for cells of type $lut. Using template $paramod$3a0b4cdedfd1d4a50b6128c5b34eaf4295ec8865$lut for cells of type $lut. Using template $paramod$19f4c7cebef5466abeaff1137aadb472bf2ce597$lut for cells of type $lut. Using template $paramod$52c44a5a4cd712275a4404fc28d7decd55483f31$lut for cells of type $lut. Using template $paramod$17c000e5b0626d73f908c7f36c919149145aad13$lut for cells of type $lut. Using template $paramod$9b131ee8b1aa274389d851eded56f0dcfa848395$lut for cells of type $lut. Using template $paramod$9f60a02de95d6e0ff2a1762cc2ab4c7ed16d1b05$lut for cells of type $lut. Using template $paramod$c89935d72517132538c438743163d1f66eb557f8$lut for cells of type $lut. Using template $paramod$2d73e84762612291e953f8afba72c6f427ee09cf$lut for cells of type $lut. Using template $paramod$387c417f2a9b6aa1c37200d358f1143bb8e6fa42$lut for cells of type $lut. Using template $paramod$2dc6ce795e737764fd2f3bd9ed0e2bfc65048431$lut for cells of type $lut. Using template $paramod$35930201711023f0f35051bef3b54588cc2aae3e$lut for cells of type $lut. Using template $paramod$8376040b721abcc1766337b37677e7306a4c48d3$lut for cells of type $lut. Using template $paramod$c5a1fa2a3aebe6a71996808dbf297b0ff14402d6$lut for cells of type $lut. Using template $paramod$59999d032eb65a005b482b772dbec959ae7093cd$lut for cells of type $lut. Using template $paramod$ccbae5f9d678e1dfe19fadbcf7c51df5e42d70da$lut for cells of type $lut. Using template $paramod$0e21f56e5f5246a023d70f8fa62501d4ccc1da15$lut for cells of type $lut. Using template $paramod$75be5e4d76ca3f242645d85d194bd61653a87cc0$lut for cells of type $lut. Using template $paramod$7b08152ea80402971e9290a913b32f08cca29d03$lut for cells of type $lut. Using template $paramod$63b7f11ce515a1b17f28ce9d5fbcb50eade6cbcb$lut for cells of type $lut. Using template $paramod$2385935dc23d70dbcfc04649cd6c576ad4c62a08$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$ed0062c7ab896ac8074a6a62dbeff0a123e2d69a$lut for cells of type $lut. Using template $paramod$b652a130b66263f4b6c93a5b3f57fe3a352c04d4$lut for cells of type $lut. Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c$lut for cells of type $lut. Using template $paramod$fecacd63d9d4c3c63bdac10199b3d99c6770530a$lut for cells of type $lut. Using template $paramod$640f0b255c4baeb1d5ed3ee07d5b4acf52609838$lut for cells of type $lut. Using template $paramod$3c3fed19c6fd1d349196eeef2e653fb0a32b5a50$lut for cells of type $lut. Using template $paramod$26637370ae9d67b1e7cab488225a5f642cbfbd75$lut for cells of type $lut. Using template $paramod$e6c2f84b29bee64f450d97e51b4fe307777f0652$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110001 for cells of type $lut. Using template $paramod$fd24ba8adbaf0b75005db1aa455afcfc2d436527$lut for cells of type $lut. Using template $paramod$da7fab251b2ea21e9ef08fbcc3aff8ab43b2d020$lut for cells of type $lut. Using template $paramod$ce1370133665c21ee4ff4dbef44493d5aaf7309a$lut for cells of type $lut. Using template $paramod$ad20004ca4cc55e015f230a7d22fd8b3bc00587e$lut for cells of type $lut. Using template $paramod$78e291482b0ed033216239a9f1ceeb13da894dfe$lut for cells of type $lut. Using template $paramod$37456f7b54c113b0eb70ccca1b23d300117db887$lut for cells of type $lut. Using template $paramod$261763615ea4f49033af727bb04e9a82e86b5f59$lut for cells of type $lut. Using template $paramod$0d1ac8dbca5bc336173f9c6b6d168b98c66838f2$lut for cells of type $lut. Using template $paramod$f41b7961c00699cc5e14bfff7c9b9c12e196ba25$lut for cells of type $lut. Using template $paramod$b50ff9839195f0e6f7ecce4db2c7cef377099427$lut for cells of type $lut. Using template $paramod$d20b18e6a47f68b328f6443d7cfd188f5c29980c$lut for cells of type $lut. Using template $paramod$bffa496da31478d9dd08f2a06c04233857ce6978$lut for cells of type $lut. Using template $paramod$f5bc030b1073cb79672ac7d290c48bf966c3c7eb$lut for cells of type $lut. Using template $paramod$b53a4410d9a0244feea65258199d6090cbfeb891$lut for cells of type $lut. Using template $paramod$4e19c401216a638c5619562195a1595bdc3c8247$lut for cells of type $lut. Using template $paramod$fccba32a597e3d88b9d6cf7e465744e7c7ec5a85$lut for cells of type $lut. Using template $paramod$dc49096963428cfbc07739b6a212e07ad5030b62$lut for cells of type $lut. Using template $paramod$d6f44da5675430ca9df89fdc4a8bddeee118fab4$lut for cells of type $lut. Using template $paramod$0e9955240c87b94d6e609492a5ff9f7dc2ebd702$lut for cells of type $lut. Using template $paramod$b51b823899488243ab03e29ac644ac488e7749a8$lut for cells of type $lut. Using template $paramod$f7adceb0c7872cbff53cd1760f1eb0b7c1107e0a$lut for cells of type $lut. Using template $paramod$a032c3276bec6d4b8377b1673ded06e76d7861f5$lut for cells of type $lut. Using template $paramod$0fda2ceccd015411a37747e7badffea9681d6906$lut for cells of type $lut. Using template $paramod$15c886d51409b06bde167c2dd0b945a2fdd38c7f$lut for cells of type $lut. Using template $paramod$42a2ad0816a30244e9a7877c290e00349535c2e1$lut for cells of type $lut. Using template $paramod$f070ba22083bf2a5dcf49edd1540eb987ca7729b$lut for cells of type $lut. Using template $paramod$4bc848598a26bc59e56c30299ea770f28dd7c397$lut for cells of type $lut. Using template $paramod$d0a0b3a0e641f37030b2f04204bb9ad7deffb2ef$lut for cells of type $lut. Using template $paramod$3bf0c3ddf9d52b2b507e02c63fc8dc6fd17281bf$lut for cells of type $lut. Using template $paramod$47cc911f10b709e43709bd1ba7c34e0ea6a42bd1$lut for cells of type $lut. Using template $paramod$0f80edccafcf31d8ab2aa8a3e0e7fa3e6e1749b4$lut for cells of type $lut. Using template $paramod$8324f28fe6d34bda4df4f1aba59b40e73aacadc2$lut for cells of type $lut. Using template $paramod$118bed3232719e68e5e7310049a1e3a25b1dc920$lut for cells of type $lut. Using template $paramod$ff8471864b32221256aa97deaf91ed747bb78d90$lut for cells of type $lut. Using template $paramod$60f9b33891059047c0c08406ccd9fca5a020ef03$lut for cells of type $lut. Using template $paramod$3f43b9dc258f0ca627653860de727485be2bc700$lut for cells of type $lut. Using template $paramod$c9d18fc0bef4332ee936e2108c5cdfb7358562f3$lut for cells of type $lut. Using template $paramod$b8f173827bd6e146e8a9bde0ac7af301853d411a$lut for cells of type $lut. Using template $paramod$16ec08245342cdd0153dd13182d2624e979908fa$lut for cells of type $lut. Using template $paramod$442453bb8e9272ee512743e590c969fbe9369e61$lut for cells of type $lut. Using template $paramod$2dda7f8f6bab0f811cc916b0406c18742427f579$lut for cells of type $lut. Using template $paramod$41883d9a8b8c394440cf3d1e7b539bb24701f675$lut for cells of type $lut. Using template $paramod$3094c095b6a07bfe9b4632ad41c02097d698064d$lut for cells of type $lut. Using template $paramod$5b13d2ee598c87cdbe912286a35c6fd102e2087c$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut. Using template $paramod$f3309e1f66ef30d83bf9a81ab6e5253b84e40169$lut for cells of type $lut. Using template $paramod$179b0e3c86fd44f4de1896d8c8bf1c149444ce5d$lut for cells of type $lut. Using template $paramod$e7acaad2d79ca9d6583d9edc46f9553c36f919ec$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$18b4576fcf375b39d4742d25337302ba17d3da17$lut for cells of type $lut. Using template $paramod$49b4d47dab45283a5bca35b8996da0a3c24bef1f$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$4804ba902596a9a62ec5704b6cbf7afdc5ab29d6$lut for cells of type $lut. Using template $paramod$87d995c9509899eb095b19b358f1d0ee4e974b2d$lut for cells of type $lut. Using template $paramod$5aaf683a266233ca3958e90f61b904317f948e44$lut for cells of type $lut. Using template $paramod$934a61742d31f2588d8f6ce001251850952a9ab9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100101 for cells of type $lut. Using template $paramod$5ab8703b1aa62946296547e85dc0a19366704a74$lut for cells of type $lut. Using template $paramod$e4cede61517c69f4283b34833b70389aba0ba4b3$lut for cells of type $lut. Using template $paramod$6b46d553f9b7497d315e65ab4554beeea5656d5a$lut for cells of type $lut. Using template $paramod$fe94d8c9e91265ab708c60526b99157e8dad92bb$lut for cells of type $lut. Using template $paramod$f42dbd98f86f5900ea7cdc638d0bd7e6388738b2$lut for cells of type $lut. Using template $paramod$f21dc1be6328a927e095a2d7e735e0517631a79c$lut for cells of type $lut. Using template $paramod$ee51b4667e8174b96303ce4018c086769bccd57c$lut for cells of type $lut. Using template $paramod$d0e42eec83ea592bf45e9ec906447f1ed04bd355$lut for cells of type $lut. Using template $paramod$37f494dcc63f6757d907b5936f5f221c6c5e4340$lut for cells of type $lut. Using template $paramod$3c64762f56d2dfc9226156923515f492b69b41a9$lut for cells of type $lut. Using template $paramod$286d6b18e782cb14d345c8422500571fedf77570$lut for cells of type $lut. Using template $paramod$2f7deae5fb594b0c70bb82efd4d3682a7baaa352$lut for cells of type $lut. Using template $paramod$63826ef25639ad4449fd7146552694c41d4eb40f$lut for cells of type $lut. Using template $paramod$3a2526a6442bbada98bb0be1b78491aff5bc2923$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae$lut for cells of type $lut. Using template $paramod$6e98fea82e288eb70fa7833e8442d9b57c9d67e7$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$dc15a2d86f211cdad96681d52b19d96d6735341a$lut for cells of type $lut. Using template $paramod$c697e96f6c39333c61f6708189ec09dee5302bcc$lut for cells of type $lut. Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0$lut for cells of type $lut. Using template $paramod$5537196b57727378a8360bd7e25641fdc66dc28f$lut for cells of type $lut. Using template $paramod$eac45d17e250a7b9bea607047125ee81ec7f9634$lut for cells of type $lut. Using template $paramod$b9d8b7e91a2c68da033af948ea0bd8bdebbaf6b2$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5$lut for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445$lut for cells of type $lut. Using template $paramod$b63ad9fd189ffa249d8fcf9c31bb572267009f3b$lut for cells of type $lut. Using template $paramod$80cab36c1e0b79061673d8327974427f259d4d24$lut for cells of type $lut. Using template $paramod$7c62394fc9dcd57450f98f8754db0e3c7b377a8c$lut for cells of type $lut. Using template $paramod$9efa31767d28d0289baa2563b9d4aa22c88e279f$lut for cells of type $lut. Using template $paramod$04c5b12d4740de5f8f090d1075bb2b548203e578$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut. Using template $paramod$b1d9ad75c9fc77f607df24873df45947b987aed8$lut for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882$lut for cells of type $lut. Using template $paramod$f2c7724a377078ae43fd5553a51bddaa7059bce8$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut. Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut. Using template $paramod$e90230c8dcea473069bf03fcce8b92040e4d209a$lut for cells of type $lut. Using template $paramod$91fbcda5fe28095fdd779b73c95f4fc59d3c2bad$lut for cells of type $lut. Using template $paramod$e57bcb018bfe8170bc04f13a73befe2def28cdf3$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut. Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257$lut for cells of type $lut. Using template $paramod$aaa491af5fe1a5ae68c7139772e66d317622d9c5$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut. Using template $paramod$ffd1825386f8c6bdd61e2b8b42e648320d55fb4c$lut for cells of type $lut. Using template $paramod$9d1915f40715c7f715525567f7dfd63744c26c4a$lut for cells of type $lut. Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4$lut for cells of type $lut. Using template $paramod$b33d93970f22483a5f9c7de8e357c06241c9728e$lut for cells of type $lut. Using template $paramod$b9a74c8fb0d628811d75e37973e9ed5b54514ee0$lut for cells of type $lut. Using template $paramod$beffda5916ef03603af7b9daee4a6705f57d3d46$lut for cells of type $lut. Using template $paramod$cb92beff9eab733e7181d891fbc8c3950b9abc0a$lut for cells of type $lut. Using template $paramod$32dee08328e8b29c9284c987432b771d306144c4$lut for cells of type $lut. Using template $paramod$e515f2e0976c0588506a69d91ee57d85a230c2f4$lut for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b$lut for cells of type $lut. Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869$lut for cells of type $lut. Using template $paramod$51599577e92cd2756c2272cd36d7c29221c56d2f$lut for cells of type $lut. Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. Using template $paramod$af763bca85949884aefa417266a961f9c91132de$lut for cells of type $lut. Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$9e2e773faa2ffc8523b11bc66a79647807b39775$lut for cells of type $lut. Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae$lut for cells of type $lut. Using template $paramod$6e1e2bf7f29cfe416c0ceb4dc5c676edd2a3b996$lut for cells of type $lut. Using template $paramod$3830fbfbec2ed4d6e3e957e17e4fca97b7adef1f$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221$lut for cells of type $lut. Using template $paramod$40fc7aee2f2d49833ca09e258a134482d29300ad$lut for cells of type $lut. Using template $paramod$c11ee6bbb8d9fd9cf391261624c378fb45e86b84$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26$lut for cells of type $lut. Using template $paramod$ef26adabe6060e01077b576cfe34e95e55a26aef$lut for cells of type $lut. Using template $paramod$ab97d1bb00842ebb07c43c56b359e5465698afc2$lut for cells of type $lut. Using template $paramod$1b4dea70ff04f88e4f935829ae81088bf4d3cdf3$lut for cells of type $lut. Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a$lut for cells of type $lut. Using template $paramod$84a9bb4ea112cac05b4a6b108a4c6ec2091f4ef3$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$38a207c707820f72f67386d2619ee46ee88964f9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. Using template $paramod$38885a960d7d45af72b881f9570d043e66ed330a$lut for cells of type $lut. Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e$lut for cells of type $lut. Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6$lut for cells of type $lut. Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564$lut for cells of type $lut. Using template $paramod$71cf1e2581652e1c182b486b69228e5e0d80c23f$lut for cells of type $lut. Using template $paramod$a8a22d36f143079162a5c184cd046a0837cefb05$lut for cells of type $lut. Using template $paramod$4b6fe525e98a335a634a6584a0e70000e965f723$lut for cells of type $lut. Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$80bc945f6d438f16387422ec284dc12b4bb4e68f$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut. Using template $paramod$8c218f07f4fcb7aa89542ff3d7405186c308b9d1$lut for cells of type $lut. Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$293f13203b5ac015351d4de0dc2b1f647549f79a$lut for cells of type $lut. Using template $paramod$b16305c55e8688bbbd58bd36edbb9b6878120874$lut for cells of type $lut. Using template $paramod$114f616d49698359643297055168b99dc168021d$lut for cells of type $lut. Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f$lut for cells of type $lut. Using template $paramod$de52a65f985bb8c1904b1b12752998fc37477714$lut for cells of type $lut. Using template $paramod$848d2b023321e0badae356e7259e2c767c32a546$lut for cells of type $lut. Using template $paramod$1a64f21ea15b05b7fc930804a66f6689ebbd6394$lut for cells of type $lut. Using template $paramod$485c535cc2fb194dc6f114ba5c93554133564a61$lut for cells of type $lut. Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1$lut for cells of type $lut. Using template $paramod$a5627e8ad36aa9b4fe2f6188097d151d45fefa8a$lut for cells of type $lut. Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707$lut for cells of type $lut. Using template $paramod$1d3e3dda7513a26513dc7c9f8a4ac0e6b682116c$lut for cells of type $lut. Using template $paramod$97e5a02853f672987777ce7910dcfa9f5a3c0c0d$lut for cells of type $lut. Using template $paramod$589a3f982da79fa8946e49d2903c90d62ebf1752$lut for cells of type $lut. Using template $paramod$35369ee2661bc6f22afa7fd33e082ebba93672ba$lut for cells of type $lut. Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039$lut for cells of type $lut. Using template $paramod$011998c9bc40e79d3b9378981668ce5683b7cfe4$lut for cells of type $lut. Using template $paramod$debd9b669717840687fe3e52f7822c4b59921848$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$474bedaec9543fe0c362d2e4221204654298befe$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010110 for cells of type $lut. Using template $paramod$ba07846b1e706d3eb2010a528b0f0417e3645924$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut. Using template $paramod$e44e5aa8c219aafd07bd79428a3dd225141eed54$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52$lut for cells of type $lut. Using template $paramod$9ec4a5b0dab38d11d536d7d7382e753a30502f12$lut for cells of type $lut. Using template $paramod$5f496f7a17b34803c6c54860f8e4d6216cf793ef$lut for cells of type $lut. Using template $paramod$5f2c184e719bd4e5fefb9f913b84bd9e97cd57c5$lut for cells of type $lut. Using template $paramod$dcba541ad53a9873d71bfba6c13dc2a8e2a60a79$lut for cells of type $lut. Using template $paramod$27b7460a4c00125e5771f00ecf25f8008965d76c$lut for cells of type $lut. Using template $paramod$5811db1448469e42576a66d1a87a4f27f138e77d$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$cde361a621e929168e2e29211efd6e41391c35c1$lut for cells of type $lut. Using template $paramod$2c8bff8999f9762348ff054be3fcb16e2247ae94$lut for cells of type $lut. Using template $paramod$20aecb9a781743d0e93608b1c1e7d62ffc3a69a9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$c6aa2f195987a2cb88aa3ac3bafb14c53cce9754$lut for cells of type $lut. Using template $paramod$e412821338883e25f2e0d1a1d7fada158db69807$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$f7e977e4ab769956ecac4448595a773db86c44e8$lut for cells of type $lut. Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d$lut for cells of type $lut. Using template $paramod$b1b2b7b05ca72aa6823d1703181921044ab9115e$lut for cells of type $lut. Using template $paramod$89ddbc2adee46e16a995ee97de1cb5a2b3106788$lut for cells of type $lut. Using template $paramod$59e7850c29ed7dc1b5206cab42fa28a25e995cb5$lut for cells of type $lut. Using template $paramod$5b86013103f2e3b8c377793851b53e09a4f50731$lut for cells of type $lut. Using template $paramod$a4b528c7078096d8435877dd5148a6944de6cb8e$lut for cells of type $lut. Using template $paramod$5ddde992c8bae5d379e77b9a4f3b5144d1540e49$lut for cells of type $lut. Using template $paramod$9cf86500af1bf04251f37ee5ae92672ca221826b$lut for cells of type $lut. Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7$lut for cells of type $lut. Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c$lut for cells of type $lut. Using template $paramod$75a594fb1222912a8f084ecc3173a1411802aae0$lut for cells of type $lut. Using template $paramod$bff60da521de773f8caf46fbc0845c3d7d3e2310$lut for cells of type $lut. Using template $paramod$83a094b6fe9fb738dfff353a8cb39fb4b34c4f40$lut for cells of type $lut. Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. Using template $paramod$b2c7e1eb2b5ed48d21e2b3da2f75f0537bc7b04a$lut for cells of type $lut. Using template $paramod$9fc2d596eb96159d9766392ef1f2dc1a8bd338f2$lut for cells of type $lut. Using template $paramod$20890b177f1fac49e4c65502f15732c1fe8576d1$lut for cells of type $lut. Using template $paramod$ca26c13a6c83a8abf5dd9e6b65ae37cc7e4209cd$lut for cells of type $lut. Using template $paramod$408a02644e8d331299a8fe898306bcda6330c9a0$lut for cells of type $lut. Using template $paramod$5ee79959469d8fcab83666859472fc06a1148c78$lut for cells of type $lut. Using template $paramod$46d82f8df15fcf8dbadf16ea1c5746bac76806ac$lut for cells of type $lut. Using template $paramod$1e4eb4eb0697a6d373edc5578750f70c3fcdd708$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut. Using template $paramod$de83eee4465e5f9b490d401662e8a7412d50e2a7$lut for cells of type $lut. Using template $paramod$0fb3437f3229691986674bbb93ca3e579291b720$lut for cells of type $lut. Using template $paramod$5fa77cea652fa4c7426d3cf3622cb6c6fda90200$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod$c3f629b46750660b0db65d636d39ecdf751db7ac$lut for cells of type $lut. Using template $paramod$4044575c9df1253cc5ef353ad928cdca8bb63a13$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$b55a3b7e8f658a2e148f7d2a78c30bafdc7c70d8$lut for cells of type $lut. Using template $paramod$253a0bd852612ba17797231540596d8727a85feb$lut for cells of type $lut. Using template $paramod$9f73c7e1db678cc0d2070a03f0e931a864a755b9$lut for cells of type $lut. Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0$lut for cells of type $lut. Using template $paramod$3a813c81898bbc8cecfd0cfc6aa14244c47ec5d4$lut for cells of type $lut. Using template $paramod$6bfad119473132ff9415951cabd1d04190f1cdf6$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912$lut for cells of type $lut. Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578$lut for cells of type $lut. Using template $paramod$cae45ff85b946d8cfe295bf4feda7db55ee71cea$lut for cells of type $lut. Using template $paramod$0a2d7bf58953a93753d49686ca51ad27ef1fcac3$lut for cells of type $lut. Using template $paramod$c45e1d9e83789d6f4c598dc50ec1c59f2a53744e$lut for cells of type $lut. Using template $paramod$1d371fb9f6e4d1b0a5db1e4212eac65c4a243863$lut for cells of type $lut. Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d$lut for cells of type $lut. Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1$lut for cells of type $lut. Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3$lut for cells of type $lut. Using template $paramod$d5a5dcd2d4b11f85b993b825cfb3d9fd701df5bf$lut for cells of type $lut. Using template $paramod$e7333de18ee6329af4f3b4f3f895c96b201b11f4$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$ef3f2547cf84a471ee84948e0f16dbdee8ed5b5d$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000010 for cells of type $lut. Using template $paramod$eb65daac7c68dcb56b4c90560a9ed5fb7dab2d20$lut for cells of type $lut. Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824$lut for cells of type $lut. Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc$lut for cells of type $lut. Using template $paramod$191987e4132f69ca46dd53dfa3f15f72d990cc0a$lut for cells of type $lut. Using template $paramod$89e657d3deb4e004585d03c823ba6873736f7939$lut for cells of type $lut. Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec$lut for cells of type $lut. Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67$lut for cells of type $lut. Using template $paramod$43920eead97cfe6c48d10f084962e7b11714ac27$lut for cells of type $lut. Using template $paramod$150ee00bee81b2fcb159e621f4ef27bccb5ede20$lut for cells of type $lut. Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4$lut for cells of type $lut. Using template $paramod$801b4648f8a54abad7f2f86a1643f447cc0694f9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. No more expansions possible. 23.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in spi_neuron_top. Optimizing lut $abc$63025$lut$aiger$o509.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o485.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$9232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$7932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$7117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$7252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$6560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$6169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$2966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$2921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$5109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$2977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$2977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$2999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o19.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$9625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$10275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger$o597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63265.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$7982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o57.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5728.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$1755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$2142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o82.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$2868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger$o137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$2921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger$o171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$2977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63195.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$10053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$10842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$10818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$10062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$10779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger$o500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger$o519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger$o486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$5418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$4206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$5383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$2343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$8661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$6374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$4516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$6698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$3302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$3313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$8065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$2700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3357.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$2565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger$o210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9221.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$8881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$63025$lut$aiger63024$3397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$9193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$4311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$5673.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$4656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$7090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$6225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$5432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$8028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$63025$lut$aiger63024$7232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$63286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$10066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$63025$lut$aiger63024$3381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$63025$lut$aiger63024$9232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Removed 0 unused cells and 4725 unused wires. 23.49. Executing AUTONAME pass. Renamed 10439 objects in module spi_neuron_top. 23.50. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `spi_neuron_top'. Setting top module to spi_neuron_top. 23.50.1. Analyzing design hierarchy.. Top module: \spi_neuron_top 23.50.2. Analyzing design hierarchy.. Top module: \spi_neuron_top Removed 0 unused modules. 23.51. Printing statistics. === spi_neuron_top === +----------Local Count, excluding submodules. | 4534 wires 10801 wire bits 4534 public wires 10801 public wire bits 14 ports 50 port bits 13 cells 13 $scopeinfo 6306 submodules 471 L6MUX21 3437 LUT4 966 PFUMX 1432 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 13 spi_neuron_top +----------Count including submodules. | 4534 wires 10801 wire bits 4534 public wires 10801 public wire bits 14 ports 50 port bits - memories - memory bits - processes 13 cells 13 $scopeinfo 6306 submodules 471 L6MUX21 3437 LUT4 966 PFUMX 1432 TRELLIS_FF 23.52. Executing CHECK pass (checking for obvious problems). Checking module spi_neuron_top... Found and reported 0 problems. 23.53. Executing JSON backend. Warnings: 1 unique messages, 1 total End of script. Logfile hash: 9fa05bfc2b, time: 3.00s, user: 2.17s, system: 0.08s, MEM: 235.44 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 17% 1x abc9_exe (0 sec), 15% 1x abc (0 sec), ...