/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Running command ` read_verilog hardware/v2/rtl/neural_processor.v hardware/v2/rtl/neural_processor_array.v chparam -set N_PROCESSORS 2 neural_processor_array synth_ecp5 -json hardware/v2/synthesis/neural_processor_array_n2/top.json -top neural_processor_array ' -- 1. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_processor.v Parsing Verilog input from `hardware/v2/rtl/neural_processor.v' to AST representation. Generating RTLIL representation for module `\neural_processor'. Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193 Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151 Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122 Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121 Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_processor_array.v Parsing Verilog input from `hardware/v2/rtl/neural_processor_array.v' to AST representation. Generating RTLIL representation for module `\neural_processor_array'. Successfully finished Verilog frontend. Parameter \N_PROCESSORS = 2 3. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_processor_array'. Parameter \N_PROCESSORS = 2 Generating RTLIL representation for module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. 4. Executing SYNTH_LATTICE pass. 4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 4.3. Executing HIERARCHY pass (managing design hierarchy). 4.3.1. Analyzing design hierarchy.. Top module: \neural_processor_array Used module: \neural_processor Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \ACC_WIDTH = 32 4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_processor'. Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \ACC_WIDTH = 32 Generating RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193 Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151 Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122 Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121 Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. Reprocessing module neural_processor_array because instantiated module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor has become available. Generating RTLIL representation for module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. 4.3.3. Analyzing design hierarchy.. Top module: $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 Used module: \neural_processor Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \ACC_WIDTH = 32 Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. 4.3.4. Analyzing design hierarchy.. Top module: $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 Used module: $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor 4.3.5. Analyzing design hierarchy.. Top module: $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 Used module: $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor Removing unused module `\neural_processor'. Removed 1 unused modules. 4.4. Executing PROC pass (convert processes to netlists). 4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$359 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$354 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$345 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:305$340 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:278$330 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:245$317 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:215$314 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:143$313 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:104$308 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Removed a total of 0 dead cases. 4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 15 redundant assignments. Promoted 25 assignments to connections. 4.4.4. Executing PROC_INIT pass (extract init attributes). 4.4.5. Executing PROC_ARST pass (detect async resets in processes). 4.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$385'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$384'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$383'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$382'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$381'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$380'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$379'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$378'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$376'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$374'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$372'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$370'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$368'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$366'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$364'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$362'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$360'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$359'. 1/2: $0\last_tree[2:2] 2/2: $0\valid_tree[2:2] Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$357'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$355'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$354'. 1/2: $0\last_tree[1:1] 2/2: $0\valid_tree[1:1] Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$352'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$350'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$348'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$346'. Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$345'. 1/2: $0\last_tree[0:0] 2/2: $0\valid_tree[0:0] Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. 1/8: $0\node_id_reg[15:0] 2/8: $0\activation_reg[1:0] 3/8: $0\bias_reg[7:0] 4/8: $0\np_error[0:0] 5/8: $0\np_state[3:0] 6/8: $0\result_node_id[15:0] 7/8: $0\result_data[7:0] 8/8: $0\result_valid[0:0] Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$330'. 1/2: $0\valid7[0:0] 2/2: $0\y7[7:0] Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$317'. 1/3: $0\last6[0:0] 2/3: $0\valid6[0:0] 3/3: $0\final_acc_reg[31:0] Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$314'. 1/3: $0\last5[0:0] 2/3: $0\valid5[0:0] 3/3: $0\acc_reg[31:0] Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. 1/11: $0\last1[0:0] 2/11: $0\valid1[0:0] 3/11: $4\gi[31:0] 4/11: $0\prod1[7][31:0] 5/11: $0\prod1[6][31:0] 6/11: $0\prod1[5][31:0] 7/11: $0\prod1[4][31:0] 8/11: $0\prod1[3][31:0] 9/11: $0\prod1[2][31:0] 10/11: $0\prod1[1][31:0] 11/11: $0\prod1[0][31:0] Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. 1/20: $2\gi[31:0] 2/20: $0\last0[0:0] 3/20: $0\valid0[0:0] 4/20: $1\gi[31:0] 5/20: $0\w0[7][7:0] 6/20: $0\w0[6][7:0] 7/20: $0\w0[5][7:0] 8/20: $0\w0[4][7:0] 9/20: $0\w0[3][7:0] 10/20: $0\w0[2][7:0] 11/20: $0\w0[1][7:0] 12/20: $0\w0[0][7:0] 13/20: $0\x0[7][7:0] 14/20: $0\x0[6][7:0] 15/20: $0\x0[5][7:0] 16/20: $0\x0[4][7:0] 17/20: $0\x0[3][7:0] 18/20: $0\x0[2][7:0] 19/20: $0\x0[1][7:0] 20/20: $0\x0[0][7:0] 4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[7]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$385'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[6]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$384'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[5]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$383'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[4]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$382'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[3]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$381'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[2]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$380'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[1]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$379'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[0]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$378'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[7]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$376'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[6]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$374'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[5]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$372'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[4]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$370'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[3]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$368'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[2]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$366'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[1]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$364'. No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[0]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$362'. 4.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[16]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$360'. created $dff cell `$procdff$712' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$359'. created $dff cell `$procdff$713' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$359'. created $dff cell `$procdff$714' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[9]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$357'. created $dff cell `$procdff$715' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[8]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$355'. created $dff cell `$procdff$716' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$354'. created $dff cell `$procdff$717' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$354'. created $dff cell `$procdff$718' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$352'. created $dff cell `$procdff$719' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$350'. created $dff cell `$procdff$720' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$348'. created $dff cell `$procdff$721' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$346'. created $dff cell `$procdff$722' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$345'. created $dff cell `$procdff$723' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$345'. created $dff cell `$procdff$724' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_valid' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. created $dff cell `$procdff$725' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_data' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. created $dff cell `$procdff$726' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_node_id' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. created $dff cell `$procdff$727' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\np_state' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. created $dff cell `$procdff$728' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\np_error' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. created $dff cell `$procdff$729' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\bias_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. created $dff cell `$procdff$730' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\activation_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. created $dff cell `$procdff$731' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\node_id_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. created $dff cell `$procdff$732' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid7' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$330'. created $dff cell `$procdff$733' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\y7' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$330'. created $dff cell `$procdff$734' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid6' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$317'. created $dff cell `$procdff$735' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last6' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$317'. created $dff cell `$procdff$736' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\final_acc_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$317'. created $dff cell `$procdff$737' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\acc_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$314'. created $dff cell `$procdff$738' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid5' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$314'. created $dff cell `$procdff$739' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last5' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$314'. created $dff cell `$procdff$740' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$741' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid1' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$742' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last1' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$743' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$744' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$745' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$746' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$747' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$748' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$749' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$750' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. created $dff cell `$procdff$751' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid0' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$752' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last0' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$753' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$754' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$755' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$756' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$757' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$758' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$759' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$760' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$761' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$762' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$763' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$764' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$765' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$766' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$767' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$768' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$769' with positive edge clock. Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. created $dff cell `$procdff$770' with positive edge clock. 4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$385'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$384'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$383'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$382'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$381'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$380'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$379'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$378'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$376'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$374'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$372'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$370'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$368'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$366'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$364'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$362'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$360'. Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$359'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$359'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$357'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$355'. Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$354'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$354'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$352'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$350'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$348'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$346'. Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$345'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$345'. Found and cleaned up 6 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$340'. Found and cleaned up 2 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$330'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$330'. Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$317'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$317'. Found and cleaned up 3 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$314'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$314'. Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$313'. Found and cleaned up 2 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$308'. Cleaned up 18 empty switches. 4.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.5. Executing CHECK pass (checking for obvious problems). Checking module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor... Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [31]: port Q[31] of cell $procdff$754 ($dff) port Q[31] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [30]: port Q[30] of cell $procdff$754 ($dff) port Q[30] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [29]: port Q[29] of cell $procdff$754 ($dff) port Q[29] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [28]: port Q[28] of cell $procdff$754 ($dff) port Q[28] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [27]: port Q[27] of cell $procdff$754 ($dff) port Q[27] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [26]: port Q[26] of cell $procdff$754 ($dff) port Q[26] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [25]: port Q[25] of cell $procdff$754 ($dff) port Q[25] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [24]: port Q[24] of cell $procdff$754 ($dff) port Q[24] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [23]: port Q[23] of cell $procdff$754 ($dff) port Q[23] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [22]: port Q[22] of cell $procdff$754 ($dff) port Q[22] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [21]: port Q[21] of cell $procdff$754 ($dff) port Q[21] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [20]: port Q[20] of cell $procdff$754 ($dff) port Q[20] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [19]: port Q[19] of cell $procdff$754 ($dff) port Q[19] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [18]: port Q[18] of cell $procdff$754 ($dff) port Q[18] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [17]: port Q[17] of cell $procdff$754 ($dff) port Q[17] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [16]: port Q[16] of cell $procdff$754 ($dff) port Q[16] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [15]: port Q[15] of cell $procdff$754 ($dff) port Q[15] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [14]: port Q[14] of cell $procdff$754 ($dff) port Q[14] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [13]: port Q[13] of cell $procdff$754 ($dff) port Q[13] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [12]: port Q[12] of cell $procdff$754 ($dff) port Q[12] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [11]: port Q[11] of cell $procdff$754 ($dff) port Q[11] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [10]: port Q[10] of cell $procdff$754 ($dff) port Q[10] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [9]: port Q[9] of cell $procdff$754 ($dff) port Q[9] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [8]: port Q[8] of cell $procdff$754 ($dff) port Q[8] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [7]: port Q[7] of cell $procdff$754 ($dff) port Q[7] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [6]: port Q[6] of cell $procdff$754 ($dff) port Q[6] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [5]: port Q[5] of cell $procdff$754 ($dff) port Q[5] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [4]: port Q[4] of cell $procdff$754 ($dff) port Q[4] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [3]: port Q[3] of cell $procdff$754 ($dff) port Q[3] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [2]: port Q[2] of cell $procdff$754 ($dff) port Q[2] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [1]: port Q[1] of cell $procdff$754 ($dff) port Q[1] of cell $procdff$741 ($dff) Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [0]: port Q[0] of cell $procdff$754 ($dff) port Q[0] of cell $procdff$741 ($dff) Checking module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010... Found and reported 32 problems. 4.6. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. 4.7. Executing TRIBUF pass. 4.8. Executing DEMINOUT pass (demote inout ports to input or output). 4.9. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 12 unused cells and 432 unused wires. 4.11. Executing CHECK pass (checking for obvious problems). Checking module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010... Found and reported 0 problems. 4.12. Executing OPT pass (performing simple optimizations). 4.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 414 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 388 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 26 cells. 4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 388 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.12.6. Executing OPT_DFF pass (perform DFF optimizations). 4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 0 unused cells and 26 unused wires. 4.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.12.9. Rerunning OPT passes. (Maybe there is more to do..) 4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 388 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.12.13. Executing OPT_DFF pass (perform DFF optimizations). 4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.12.16. Finished fast OPT passes. (There is nothing left to do.) 4.13. Executing FSM pass (extract and optimize FSM). 4.13.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.GEN_NP[0].u_np.np_state as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. Not marking $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.GEN_NP[1].u_np.np_state as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. 4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 4.14. Executing OPT pass (performing simple optimizations). 4.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 388 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 388 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$770 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [63:56], Q = \GEN_NP[0].u_np.w0[7]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$769 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [55:48], Q = \GEN_NP[0].u_np.w0[6]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$768 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [47:40], Q = \GEN_NP[0].u_np.w0[5]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$767 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [39:32], Q = \GEN_NP[0].u_np.w0[4]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$766 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [31:24], Q = \GEN_NP[0].u_np.w0[3]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$765 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [23:16], Q = \GEN_NP[0].u_np.w0[2]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$764 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [15:8], Q = \GEN_NP[0].u_np.w0[1]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$763 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [7:0], Q = \GEN_NP[0].u_np.w0[0]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$762 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [63:56], Q = \GEN_NP[0].u_np.x0[7]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$761 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [55:48], Q = \GEN_NP[0].u_np.x0[6]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$760 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [47:40], Q = \GEN_NP[0].u_np.x0[5]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$759 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [39:32], Q = \GEN_NP[0].u_np.x0[4]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$758 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [31:24], Q = \GEN_NP[0].u_np.x0[3]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$757 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [23:16], Q = \GEN_NP[0].u_np.x0[2]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$756 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [15:8], Q = \GEN_NP[0].u_np.x0[1]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$755 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [7:0], Q = \GEN_NP[0].u_np.x0[0]). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$753 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \tile_last [0], Q = \GEN_NP[0].u_np.last0, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$752 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$309_Y, Q = \GEN_NP[0].u_np.valid0, rval = 1'0). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$751 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] [15] \GEN_NP[0].u_np.product_comb[7] }, Q = \GEN_NP[0].u_np.prod1[7]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$750 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] [15] \GEN_NP[0].u_np.product_comb[6] }, Q = \GEN_NP[0].u_np.prod1[6]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$749 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] [15] \GEN_NP[0].u_np.product_comb[5] }, Q = \GEN_NP[0].u_np.prod1[5]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$748 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] [15] \GEN_NP[0].u_np.product_comb[4] }, Q = \GEN_NP[0].u_np.prod1[4]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$747 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] [15] \GEN_NP[0].u_np.product_comb[3] }, Q = \GEN_NP[0].u_np.prod1[3]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$746 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] [15] \GEN_NP[0].u_np.product_comb[2] }, Q = \GEN_NP[0].u_np.prod1[2]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$745 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] [15] \GEN_NP[0].u_np.product_comb[1] }, Q = \GEN_NP[0].u_np.prod1[1]). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$744 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] [15] \GEN_NP[0].u_np.product_comb[0] }, Q = \GEN_NP[0].u_np.prod1[0]). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$743 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.last0, Q = \GEN_NP[0].u_np.last1, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$742 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.valid0, Q = \GEN_NP[0].u_np.valid1, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$740 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.last_tree [2], Q = \GEN_NP[0].u_np.last5, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$739 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.valid_tree [2], Q = \GEN_NP[0].u_np.valid5, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$738 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$560_Y, Q = \GEN_NP[0].u_np.acc_reg, rval = 0). Adding EN signal on $auto$ff.cc:337:slice$871 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$316_Y, Q = \GEN_NP[0].u_np.acc_reg). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$737 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318_Y, Q = \GEN_NP[0].u_np.final_acc_reg). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$736 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.last5, Q = \GEN_NP[0].u_np.last6, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$735 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.valid5, Q = \GEN_NP[0].u_np.valid6, rval = 1'0). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$734 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$540_Y, Q = \GEN_NP[0].u_np.y7). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$733 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.last6, Q = \GEN_NP[0].u_np.valid7, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$732 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$445_Y, Q = \GEN_NP[0].u_np.node_id_reg, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$880 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \job_node_id [15:0], Q = \GEN_NP[0].u_np.node_id_reg). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$731 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$459_Y, Q = \GEN_NP[0].u_np.activation_reg, rval = 2'01). Adding EN signal on $auto$ff.cc:337:slice$884 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \job_activation [1:0], Q = \GEN_NP[0].u_np.activation_reg). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$730 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$473_Y, Q = \GEN_NP[0].u_np.bias_reg, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$888 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \job_bias [7:0], Q = \GEN_NP[0].u_np.bias_reg). Adding EN signal on $flatten\GEN_NP[0].u_np.$procdff$729 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = 1'0, Q = \GEN_NP[0].u_np.np_error). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$728 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$482_Y, Q = \GEN_NP[0].u_np.np_state, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$893 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$482_Y, Q = \GEN_NP[0].u_np.np_state). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$727 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$507_Y, Q = \GEN_NP[0].u_np.result_node_id, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$907 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.node_id_reg, Q = \GEN_NP[0].u_np.result_node_id). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$726 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$518_Y, Q = \GEN_NP[0].u_np.result_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$911 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.y7, Q = \GEN_NP[0].u_np.result_data). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$725 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$528_Y, Q = \GEN_NP[0].u_np.result_valid, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$915 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[0].u_np.$procmux$528_Y, Q = \GEN_NP[0].u_np.result_valid). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$724 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.last1, Q = \GEN_NP[0].u_np.last_tree [0], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$723 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.valid1, Q = \GEN_NP[0].u_np.valid_tree [0], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$718 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.last_tree [0], Q = \GEN_NP[0].u_np.last_tree [1], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$717 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.valid_tree [0], Q = \GEN_NP[0].u_np.valid_tree [1], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$714 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.last_tree [1], Q = \GEN_NP[0].u_np.last_tree [2], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[0].u_np.$procdff$713 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[0].u_np.valid_tree [1], Q = \GEN_NP[0].u_np.valid_tree [2], rval = 1'0). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$770 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [127:120], Q = \GEN_NP[1].u_np.w0[7]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$769 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [119:112], Q = \GEN_NP[1].u_np.w0[6]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$768 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [111:104], Q = \GEN_NP[1].u_np.w0[5]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$767 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [103:96], Q = \GEN_NP[1].u_np.w0[4]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$766 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [95:88], Q = \GEN_NP[1].u_np.w0[3]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$765 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [87:80], Q = \GEN_NP[1].u_np.w0[2]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$764 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [79:72], Q = \GEN_NP[1].u_np.w0[1]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$763 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \weight_data [71:64], Q = \GEN_NP[1].u_np.w0[0]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$762 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [127:120], Q = \GEN_NP[1].u_np.x0[7]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$761 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [119:112], Q = \GEN_NP[1].u_np.x0[6]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$760 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [111:104], Q = \GEN_NP[1].u_np.x0[5]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$759 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [103:96], Q = \GEN_NP[1].u_np.x0[4]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$758 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [95:88], Q = \GEN_NP[1].u_np.x0[3]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$757 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [87:80], Q = \GEN_NP[1].u_np.x0[2]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$756 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [79:72], Q = \GEN_NP[1].u_np.x0[1]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$755 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \input_data [71:64], Q = \GEN_NP[1].u_np.x0[0]). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$753 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \tile_last [1], Q = \GEN_NP[1].u_np.last0, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$752 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$309_Y, Q = \GEN_NP[1].u_np.valid0, rval = 1'0). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$751 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] [15] \GEN_NP[1].u_np.product_comb[7] }, Q = \GEN_NP[1].u_np.prod1[7]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$750 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] [15] \GEN_NP[1].u_np.product_comb[6] }, Q = \GEN_NP[1].u_np.prod1[6]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$749 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] [15] \GEN_NP[1].u_np.product_comb[5] }, Q = \GEN_NP[1].u_np.prod1[5]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$748 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] [15] \GEN_NP[1].u_np.product_comb[4] }, Q = \GEN_NP[1].u_np.prod1[4]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$747 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] [15] \GEN_NP[1].u_np.product_comb[3] }, Q = \GEN_NP[1].u_np.prod1[3]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$746 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] [15] \GEN_NP[1].u_np.product_comb[2] }, Q = \GEN_NP[1].u_np.prod1[2]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$745 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] [15] \GEN_NP[1].u_np.product_comb[1] }, Q = \GEN_NP[1].u_np.prod1[1]). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$744 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = { \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] [15] \GEN_NP[1].u_np.product_comb[0] }, Q = \GEN_NP[1].u_np.prod1[0]). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$743 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.last0, Q = \GEN_NP[1].u_np.last1, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$742 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.valid0, Q = \GEN_NP[1].u_np.valid1, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$740 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.last_tree [2], Q = \GEN_NP[1].u_np.last5, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$739 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.valid_tree [2], Q = \GEN_NP[1].u_np.valid5, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$738 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$560_Y, Q = \GEN_NP[1].u_np.acc_reg, rval = 0). Adding EN signal on $auto$ff.cc:337:slice$1029 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$316_Y, Q = \GEN_NP[1].u_np.acc_reg). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$737 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318_Y, Q = \GEN_NP[1].u_np.final_acc_reg). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$736 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.last5, Q = \GEN_NP[1].u_np.last6, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$735 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.valid5, Q = \GEN_NP[1].u_np.valid6, rval = 1'0). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$734 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$540_Y, Q = \GEN_NP[1].u_np.y7). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$733 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.last6, Q = \GEN_NP[1].u_np.valid7, rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$732 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$445_Y, Q = \GEN_NP[1].u_np.node_id_reg, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$1038 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \job_node_id [31:16], Q = \GEN_NP[1].u_np.node_id_reg). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$731 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$459_Y, Q = \GEN_NP[1].u_np.activation_reg, rval = 2'01). Adding EN signal on $auto$ff.cc:337:slice$1042 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \job_activation [3:2], Q = \GEN_NP[1].u_np.activation_reg). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$730 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$473_Y, Q = \GEN_NP[1].u_np.bias_reg, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$1046 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \job_bias [15:8], Q = \GEN_NP[1].u_np.bias_reg). Adding EN signal on $flatten\GEN_NP[1].u_np.$procdff$729 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = 1'0, Q = \GEN_NP[1].u_np.np_error). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$728 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$482_Y, Q = \GEN_NP[1].u_np.np_state, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$1051 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$482_Y, Q = \GEN_NP[1].u_np.np_state). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$727 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$507_Y, Q = \GEN_NP[1].u_np.result_node_id, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$1065 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.node_id_reg, Q = \GEN_NP[1].u_np.result_node_id). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$726 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$518_Y, Q = \GEN_NP[1].u_np.result_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$1069 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.y7, Q = \GEN_NP[1].u_np.result_data). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$725 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$528_Y, Q = \GEN_NP[1].u_np.result_valid, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$1073 ($sdff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = $flatten\GEN_NP[1].u_np.$procmux$528_Y, Q = \GEN_NP[1].u_np.result_valid). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$724 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.last1, Q = \GEN_NP[1].u_np.last_tree [0], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$723 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.valid1, Q = \GEN_NP[1].u_np.valid_tree [0], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$718 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.last_tree [0], Q = \GEN_NP[1].u_np.last_tree [1], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$717 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.valid_tree [0], Q = \GEN_NP[1].u_np.valid_tree [1], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$714 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.last_tree [1], Q = \GEN_NP[1].u_np.last_tree [2], rval = 1'0). Adding SRST signal on $flatten\GEN_NP[1].u_np.$procdff$713 ($dff) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 (D = \GEN_NP[1].u_np.valid_tree [1], Q = \GEN_NP[1].u_np.valid_tree [2], rval = 1'0). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1050 ($dffe) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$892 ($dffe) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 158 unused cells and 158 unused wires. 4.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.14.9. Rerunning OPT passes. (Maybe there is more to do..) 4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 328 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 287 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 257 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 71 cells. 4.14.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 0 unused cells and 71 unused wires. 4.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.14.16. Rerunning OPT passes. (Maybe there is more to do..) 4.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.14.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 257 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.14.20. Executing OPT_DFF pass (perform DFF optimizations). 4.14.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.14.22. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.14.23. Finished fast OPT passes. (There is nothing left to do.) 4.15. Executing WREDUCE pass (reducing word size of cells). Removed top 1 bits (of 2) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$opt_dff.cc:320:make_patterns_logic$1056 ($ne). Removed top 1 bits (of 2) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$opt_dff.cc:320:make_patterns_logic$1054 ($ne). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$1024 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$1023 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$1022 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$1021 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$1020 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$1019 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$1018 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$1017 ($dffe). Removed top 1 bits (of 2) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$opt_dff.cc:320:make_patterns_logic$898 ($ne). Removed top 1 bits (of 2) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$opt_dff.cc:320:make_patterns_logic$896 ($ne). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$866 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$865 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$864 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$863 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$862 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$861 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$860 ($dffe). Removed top 16 bits (of 32) from FF cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$auto$ff.cc:337:slice$859 ($dffe). Removed top 2 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$procmux$493_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$procmux$490_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$procmux$487_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$procmux$484_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$procmux$483_CMP0 ($eq). Converting cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add). Removed top 16 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add). Removed top 15 bits (of 32) from port Y of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add). Converting cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add). Removed top 16 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add). Removed top 15 bits (of 32) from port Y of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add). Converting cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add). Removed top 16 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add). Removed top 15 bits (of 32) from port Y of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add). Converting cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add). Removed top 16 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add). Removed top 15 bits (of 32) from port Y of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add). Removed top 24 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318 ($add). Removed top 3 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$315 ($eq). Removed top 3 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$procmux$494_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$procmux$493_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$procmux$490_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$procmux$487_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$procmux$484_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$procmux$483_CMP0 ($eq). Converting cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add). Removed top 16 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add). Removed top 15 bits (of 32) from port Y of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add). Converting cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add). Removed top 16 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add). Removed top 15 bits (of 32) from port Y of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add). Converting cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add). Removed top 16 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add). Removed top 15 bits (of 32) from port Y of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add). Converting cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add). Removed top 16 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add). Removed top 15 bits (of 32) from port Y of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add). Removed top 24 bits (of 32) from port B of cell $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.$flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318 ($add). 4.16. Executing PEEPOPT pass (run peephole optimizers). 4.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.18. Executing SHARE pass (SAT-based resource sharing). 4.19. Executing TECHMAP pass (map to technology primitives). 4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 4.19.2. Continuing TECHMAP pass. No more expansions possible. 4.20. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.22. Executing TECHMAP pass (map to technology primitives). 4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 4.22.2. Continuing TECHMAP pass. Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul. No more expansions possible. 4.23. Executing TECHMAP pass (map to technology primitives). 4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 4.23.2. Continuing TECHMAP pass. Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. 4.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010: creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318 ($add). creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$316 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$316 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$356 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$358 ($add). creating $macc model for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$361 ($add). creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347 ($add). creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349 ($add). creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351 ($add). creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$361 ($add). creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353 ($add). creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$356 ($add). creating $macc model for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$358 ($add). creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$358. creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$356. creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353. creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$361. creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351. creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349. creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$361. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$358. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$356. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318. creating $alu model for $macc $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$316. creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$316. creating $alu model for $macc $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318. creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318: $auto$alumacc.cc:548:replace_alu$1122 creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$316: $auto$alumacc.cc:548:replace_alu$1125 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$316: $auto$alumacc.cc:548:replace_alu$1128 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$318: $auto$alumacc.cc:548:replace_alu$1131 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347: $auto$alumacc.cc:548:replace_alu$1134 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349: $auto$alumacc.cc:548:replace_alu$1137 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351: $auto$alumacc.cc:548:replace_alu$1140 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353: $auto$alumacc.cc:548:replace_alu$1143 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$356: $auto$alumacc.cc:548:replace_alu$1146 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$358: $auto$alumacc.cc:548:replace_alu$1149 creating $alu cell for $flatten\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$361: $auto$alumacc.cc:548:replace_alu$1152 creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$347: $auto$alumacc.cc:548:replace_alu$1155 creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$349: $auto$alumacc.cc:548:replace_alu$1158 creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$351: $auto$alumacc.cc:548:replace_alu$1161 creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$361: $auto$alumacc.cc:548:replace_alu$1164 creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$353: $auto$alumacc.cc:548:replace_alu$1167 creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$356: $auto$alumacc.cc:548:replace_alu$1170 creating $alu cell for $flatten\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$358: $auto$alumacc.cc:548:replace_alu$1173 created 18 $alu and 0 $macc cells. 4.25. Executing OPT pass (performing simple optimizations). 4.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 257 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 257 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.25.6. Executing OPT_DFF pass (perform DFF optimizations). 4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 0 unused cells and 128 unused wires. 4.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.25.9. Rerunning OPT passes. (Maybe there is more to do..) 4.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 257 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.25.13. Executing OPT_DFF pass (perform DFF optimizations). 4.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.25.16. Finished fast OPT passes. (There is nothing left to do.) 4.26. Executing MEMORY pass. 4.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 4.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 4.29. Executing TECHMAP pass (map to technology primitives). 4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 4.29.3. Continuing TECHMAP pass. No more expansions possible. 4.30. Executing OPT pass (performing simple optimizations). 4.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 245 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.30.3. Executing OPT_DFF pass (perform DFF optimizations). 4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 0 unused cells and 12 unused wires. 4.30.5. Finished fast OPT passes. 4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 4.32. Executing OPT pass (performing simple optimizations). 4.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 245 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Consolidated identical input bits for $mux cell $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326: Old ports: A=8'01111111, B=8'10000000, Y=$flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y New ports: A=2'01, B=2'10, Y={ $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [7] $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] } New connections: $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [6:1] = { $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] } Consolidated identical input bits for $mux cell $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326: Old ports: A=8'01111111, B=8'10000000, Y=$flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y New ports: A=2'01, B=2'10, Y={ $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [7] $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] } New connections: $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [6:1] = { $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] $flatten\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$326_Y [0] } Consolidated identical input bits for $pmux cell $flatten\GEN_NP[1].u_np.$procmux$482: Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\GEN_NP[1].u_np.$procmux$482_Y New ports: A=3'110, B=18'001010011100101000, Y=$flatten\GEN_NP[1].u_np.$procmux$482_Y [2:0] New connections: $flatten\GEN_NP[1].u_np.$procmux$482_Y [3] = 1'0 Consolidated identical input bits for $pmux cell $flatten\GEN_NP[0].u_np.$procmux$482: Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\GEN_NP[0].u_np.$procmux$482_Y New ports: A=3'110, B=18'001010011100101000, Y=$flatten\GEN_NP[0].u_np.$procmux$482_Y [2:0] New connections: $flatten\GEN_NP[0].u_np.$procmux$482_Y [3] = 1'0 Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 4 changes. 4.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 245 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.32.6. Executing OPT_DFF pass (perform DFF optimizations). 4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.32.9. Rerunning OPT passes. (Maybe there is more to do..) 4.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.32.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 245 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.32.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1052 ($sdffe) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$894 ($sdffe) from module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.32.15. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.32.16. Rerunning OPT passes. (Maybe there is more to do..) 4.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.32.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 245 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.32.20. Executing OPT_DFF pass (perform DFF optimizations). 4.32.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.32.22. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.32.23. Finished fast OPT passes. (There is nothing left to do.) 4.33. Executing TECHMAP pass (map to technology primitives). 4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 4.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ccu2c_alu for cells of type $alu. Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu. Using template $paramod$8fdcfe020be5e507ba05385ffd706e02b549d39d\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $pos. No more expansions possible. 4.34. Executing OPT pass (performing simple optimizations). 4.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 3677 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 3461 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 3281 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 396 cells. 4.34.3. Executing OPT_DFF pass (perform DFF optimizations). 4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 1552 unused cells and 1426 unused wires. 4.34.5. Finished fast OPT passes. 4.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 4.37. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 1729 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.38. Executing TECHMAP pass (map to technology primitives). 4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 4.38.2. Continuing TECHMAP pass. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_. Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. No more expansions possible. 4.39. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). 4.41. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.42. Executing ATTRMVCP pass (move or copy attributes). 4.43. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 0 unused cells and 5454 unused wires. 4.44. Executing CHECK pass (checking for obvious problems). Checking module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010... Found and reported 0 problems. 4.45. Executing TECHMAP pass (map to technology primitives). 4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 4.45.2. Continuing TECHMAP pass. No more expansions possible. 4.46. Executing ABC9 pass. 4.46.1. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.2. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Found 0 SCCs. 4.46.4. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.5. Executing TECHMAP pass (map to technology primitives). 4.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.46.5.2. Continuing TECHMAP pass. No more expansions possible. 4.46.6. Executing OPT pass (performing simple optimizations). 4.46.6.1. Executing OPT_EXPR pass (perform const folding). 4.46.6.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 4.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 4.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 4.46.6.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 4.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). 4.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). 4.46.6.8. Executing OPT_EXPR pass (perform const folding). 4.46.6.9. Finished fast OPT passes. (There is nothing left to do.) 4.46.7. Executing TECHMAP pass (map to technology primitives). 4.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 4.46.7.2. Continuing TECHMAP pass. No more expansions possible. 4.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 4.46.9. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.10. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.11. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.12. Executing TECHMAP pass (map to technology primitives). 4.46.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.46.12.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $mux. No more expansions possible. 4.46.13. Executing OPT pass (performing simple optimizations). 4.46.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.46.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 59 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 57 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 2 cells. 4.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.46.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 57 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.46.13.6. Executing OPT_DFF pass (perform DFF optimizations). 4.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Removed 0 unused cells and 55 unused wires. 4.46.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.46.13.9. Rerunning OPT passes. (Maybe there is more to do..) 4.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Performed a total of 0 changes. 4.46.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Computing hashes of 57 cells of `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Finding duplicate cells in `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Removed a total of 0 cells. 4.46.13.13. Executing OPT_DFF pass (perform DFF optimizations). 4.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010.. 4.46.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.46.13.16. Finished fast OPT passes. (There is nothing left to do.) 4.46.14. Executing AIGMAP pass (map logic to AIG). Module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 14 $_MUX_ 2 $_OR_ 2 $_XOR_ not replaced 3 cell types: 4 $_AND_ 4 $_NOT_ 31 $specify2 4.46.15. Executing AIGMAP pass (map logic to AIG). Module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010: replaced 252 cells with 1218 new cells, skipped 1477 cells. replaced 2 cell types: 70 $_MUX_ 182 $_OR_ not replaced 6 cell types: 76 $_AND_ 29 $_NOT_ 2 $scopeinfo 1122 TRELLIS_FF 16 MULT18X18D 232 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 4.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.15.3. Executing XAIGER backend. Extracted 468 AND gates and 3959 wires from module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010' to a netlist network with 1696 inputs and 1146 outputs. 4.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9). 4.46.15.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 1696/ 1146 and = 396 lev = 12 (0.10) mem = 0.09 MB box = 232 bb = 0 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 1696/ 1146 and = 491 lev = 10 (0.08) mem = 0.09 MB ch = 46 box = 204 bb = 0 ABC: cst = 0 cls = 41 lit = 46 unused = 2712 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 491. Ch = 41. Total mem = 0.95 MB. Peak cut mem = 0.03 MB. ABC: P: Del = 2464.00. Ar = 368.0. Edge = 527. Cut = 3907. T = 0.00 sec ABC: P: Del = 2464.00. Ar = 296.0. Edge = 463. Cut = 3968. T = 0.00 sec ABC: P: Del = 2464.00. Ar = 228.0. Edge = 453. Cut = 7100. T = 0.00 sec ABC: F: Del = 2464.00. Ar = 184.0. Edge = 415. Cut = 4287. T = 0.00 sec ABC: A: Del = 2464.00. Ar = 184.0. Edge = 402. Cut = 3855. T = 0.00 sec ABC: A: Del = 2464.00. Ar = 184.0. Edge = 402. Cut = 3817. T = 0.00 sec ABC: Total time = 0.00 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: + &ps -l ABC: /input : i/o = 1696/ 1146 and = 264 lev = 11 (0.08) mem = 0.08 MB box = 204 bb = 0 ABC: Mapping (K=7) : lut = 90 edge = 324 lev = 5 (0.05) levB = 16 mem = 0.02 MB ABC: LUT = 90 : 2=20 22.2 % 3=14 15.6 % 4=45 50.0 % 5=5 5.6 % 6=5 5.6 % 7=1 1.1 % Ave = 3.60 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.02 sec ABC: + time ABC: elapse: 0.05 seconds, total: 0.05 seconds 4.46.15.6. Executing AIGER frontend. Removed 347 unused cells and 4936 unused wires. 4.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 92 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 204 ABC RESULTS: input signals: 53 ABC RESULTS: output signals: 121 Removing temp directory. 4.46.16. Executing TECHMAP pass (map to technology primitives). 4.46.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 4.46.16.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. No more expansions possible. Removed 7 unused cells and 6828 unused wires. 4.47. Executing TECHMAP pass (map to technology primitives). 4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 4.47.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$ee19d45db61acb4c70d938b97483a4ed4b792645$lut for cells of type $lut. Using template $paramod$cbb2dfe31d344d3326d567c2ed5a4b2a29f63219$lut for cells of type $lut. Using template $paramod$c362ad8dedc7d166ed978091aca319ab1e81a2d4$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304$lut for cells of type $lut. Using template $paramod$4fec704ca41b191c5698b11d275c5f0cc4d8803f$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5$lut for cells of type $lut. Using template $paramod$3ecf9ddef4604dcf386e9244fca9c73d93eaac60$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut. Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$1578333f1a5078051b84dbcbad362e8087bf5284$lut for cells of type $lut. Using template $paramod$1c0b02bad8ada563354b10a04b512fba38cd212e$lut for cells of type $lut. Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$9f6bc32305fc769fa11e4327bee073e3fbe84018$lut for cells of type $lut. Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. No more expansions possible. 4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. Optimizing lut $abc$9965$lut$aiger9964$2459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$9967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$9968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$9965$lut$aiger9964$2434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$9965$lut$aiger9964$2459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 212 unused wires. 4.49. Executing AUTONAME pass. Renamed 1830 objects in module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.50. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `$paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010'. Setting top module to $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010. 4.50.1. Analyzing design hierarchy.. Top module: $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 4.50.2. Analyzing design hierarchy.. Top module: $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 Removed 0 unused modules. 4.51. Printing statistics. === $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 === +----------Local Count, excluding submodules. | 534 wires 4551 wire bits 534 public wires 4551 public wire bits 18 ports 382 port bits 18 cells 2 $scopeinfo 16 MULT18X18D 1472 submodules 204 CCU2C 8 L6MUX21 119 LUT4 19 PFUMX 1122 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 18 $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010 +----------Count including submodules. | 534 wires 4551 wire bits 534 public wires 4551 public wire bits 18 ports 382 port bits - memories - memory bits - processes 18 cells 2 $scopeinfo 16 MULT18X18D 1472 submodules 204 CCU2C 8 L6MUX21 119 LUT4 19 PFUMX 1122 TRELLIS_FF 4.52. Executing CHECK pass (checking for obvious problems). Checking module $paramod\neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000000010... Found and reported 0 problems. 4.53. Executing JSON backend. Warnings: 36 unique messages, 40 total End of script. Logfile hash: d4cd5d98f7, time: 0.55s, user: 0.47s, system: 0.01s, MEM: 56.42 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 32% 22x read_verilog (0 sec), 13% 1x abc9_exe (0 sec), ...