/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Running command `read_verilog hardware/v2/nms/rtl/nms_activation_replicated.v hardware/v2/nms/synthesis/harness_nms_activation_replicated.v; chparam -set N_SLOTS 4 -set MAX_TILES 16 harness_nms_activation_replicated; synth_ecp5 -json hardware/v2/nms/synthesis/act_rep_n4/top.json -top harness_nms_activation_replicated' -- 1. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_activation_replicated.v Parsing Verilog input from `hardware/v2/nms/rtl/nms_activation_replicated.v' to AST representation. Generating RTLIL representation for module `\nms_activation_replicated'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: hardware/v2/nms/synthesis/harness_nms_activation_replicated.v Parsing Verilog input from `hardware/v2/nms/synthesis/harness_nms_activation_replicated.v' to AST representation. Generating RTLIL representation for module `\harness_nms_activation_replicated'. Successfully finished Verilog frontend. Parameter \N_SLOTS = 4 Parameter \MAX_TILES = 16 3. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_nms_activation_replicated'. Parameter \N_SLOTS = 4 Parameter \MAX_TILES = 16 Generating RTLIL representation for module `$paramod$bab463222c283b5ef4688ae6b1d5a65aff51a802\harness_nms_activation_replicated'. 4. Executing SYNTH_LATTICE pass. 4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 4.3. Executing HIERARCHY pass (managing design hierarchy). 4.3.1. Analyzing design hierarchy.. Top module: \harness_nms_activation_replicated Used module: \nms_activation_replicated Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \N_SLOTS = 4 Parameter \MAX_TILES = 16 4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_activation_replicated'. Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \N_SLOTS = 4 Parameter \MAX_TILES = 16 Generating RTLIL representation for module `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated'. 4.3.3. Analyzing design hierarchy.. Top module: \harness_nms_activation_replicated Used module: $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated 4.3.4. Analyzing design hierarchy.. Top module: \harness_nms_activation_replicated Used module: $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated Removing unused module `\nms_activation_replicated'. Removed 1 unused modules. 4.4. Executing PROC pass (convert processes to netlists). 4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:28$48 in module harness_nms_activation_replicated. Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:52$53 in module harness_nms_activation_replicated. Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$311 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$303 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$295 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$287 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. Removed a total of 0 dead cases. 4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 2 redundant assignments. Promoted 14 assignments to connections. 4.4.4. Executing PROC_INIT pass (extract init attributes). 4.4.5. Executing PROC_ARST pass (detect async resets in processes). 4.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:28$48'. 1/1: $0\lfsr[31:0] Creating decoders for process `\harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:52$53'. 1/3: $0\chk[7:0] 2/3: $1\chk_next[7:0] 3/3: $1\k[31:0] Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$311'. 1/4: $1$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$317 2/4: $1$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_DATA[63:0]$316 3/4: $1$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_ADDR[3:0]$315 4/4: $0\GEN_COPY[3].rd_data_reg[63:0] Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$303'. 1/4: $1$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$309 2/4: $1$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_DATA[63:0]$308 3/4: $1$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_ADDR[3:0]$307 4/4: $0\GEN_COPY[2].rd_data_reg[63:0] Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$295'. 1/4: $1$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$301 2/4: $1$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_DATA[63:0]$300 3/4: $1$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_ADDR[3:0]$299 4/4: $0\GEN_COPY[1].rd_data_reg[63:0] Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$287'. 1/4: $1$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$293 2/4: $1$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_DATA[63:0]$292 3/4: $1$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_ADDR[3:0]$291 4/4: $0\GEN_COPY[0].rd_data_reg[63:0] 4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 4.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\harness_nms_activation_replicated.\lfsr' using process `\harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:28$48'. created $dff cell `$procdff$375' with positive edge clock. Creating register for signal `\harness_nms_activation_replicated.\k' using process `\harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:52$53'. created $dff cell `$procdff$376' with positive edge clock. Creating register for signal `\harness_nms_activation_replicated.\chk' using process `\harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:52$53'. created $dff cell `$procdff$377' with positive edge clock. Creating register for signal `\harness_nms_activation_replicated.\chk_next' using process `\harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:52$53'. created $dff cell `$procdff$378' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.\GEN_COPY[3].rd_data_reg' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$311'. created $dff cell `$procdff$379' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$311'. created $dff cell `$procdff$380' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$311'. created $dff cell `$procdff$381' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$311'. created $dff cell `$procdff$382' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.\GEN_COPY[2].rd_data_reg' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$303'. created $dff cell `$procdff$383' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$303'. created $dff cell `$procdff$384' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$303'. created $dff cell `$procdff$385' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$303'. created $dff cell `$procdff$386' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.\GEN_COPY[1].rd_data_reg' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$295'. created $dff cell `$procdff$387' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$295'. created $dff cell `$procdff$388' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$295'. created $dff cell `$procdff$389' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$295'. created $dff cell `$procdff$390' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.\GEN_COPY[0].rd_data_reg' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$287'. created $dff cell `$procdff$391' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$287'. created $dff cell `$procdff$392' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$287'. created $dff cell `$procdff$393' with positive edge clock. Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$287'. created $dff cell `$procdff$394' with positive edge clock. 4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:28$48'. Removing empty process `harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:28$48'. Found and cleaned up 1 empty switch in `\harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:52$53'. Removing empty process `harness_nms_activation_replicated.$proc$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:52$53'. Found and cleaned up 2 empty switches in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$311'. Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$311'. Found and cleaned up 2 empty switches in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$303'. Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$303'. Found and cleaned up 2 empty switches in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$295'. Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$295'. Found and cleaned up 2 empty switches in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$287'. Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:43$287'. Cleaned up 10 empty switches. 4.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. Optimizing module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. 4.5. Executing CHECK pass (checking for obvious problems). Checking module harness_nms_activation_replicated... Checking module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated... Found and reported 0 problems. 4.6. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. 4.7. Executing TRIBUF pass. 4.8. Executing DEMINOUT pass (demote inout ports to input or output). 4.9. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. Removed 16 unused cells and 71 unused wires. 4.11. Executing CHECK pass (checking for obvious problems). Checking module harness_nms_activation_replicated... Found and reported 0 problems. 4.12. Executing OPT pass (performing simple optimizations). 4.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 40 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_activation_replicated.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $flatten\dut.$procmux$368: { \lfsr \lfsr } -> { \lfsr [31:1] 1'1 \lfsr [31:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$371: \lfsr [3:0] -> { \lfsr [3:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$360: \lfsr [3:0] -> { \lfsr [3:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$357: { \lfsr \lfsr } -> { \lfsr [31:1] 1'1 \lfsr [31:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$349: \lfsr [3:0] -> { \lfsr [3:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$346: { \lfsr \lfsr } -> { \lfsr [31:1] 1'1 \lfsr [31:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$338: \lfsr [3:0] -> { \lfsr [3:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$335: { \lfsr \lfsr } -> { \lfsr [31:1] 1'1 \lfsr [31:1] 1'1 } Analyzing evaluation results. Removed 0 multiplexer ports. 4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_activation_replicated. Consolidated identical input bits for $mux cell $flatten\dut.$procmux$365: Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] New connections: $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [63:1] = { $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] $flatten\dut.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$283_EN[63:0]$290 [0] } Consolidated identical input bits for $mux cell $flatten\dut.$procmux$354: Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] New connections: $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [63:1] = { $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] $flatten\dut.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$284_EN[63:0]$298 [0] } Consolidated identical input bits for $mux cell $flatten\dut.$procmux$343: Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] New connections: $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [63:1] = { $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] $flatten\dut.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$285_EN[63:0]$306 [0] } Consolidated identical input bits for $mux cell $flatten\dut.$procmux$332: Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] New connections: $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [63:1] = { $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] $flatten\dut.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:45$286_EN[63:0]$314 [0] } Optimizing cells in module \harness_nms_activation_replicated. Performed a total of 4 changes. 4.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 40 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Computing hashes of 31 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 9 cells. 4.12.6. Executing OPT_DFF pass (perform DFF optimizations). 4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. Removed 0 unused cells and 9 unused wires. 4.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.12.9. Rerunning OPT passes. (Maybe there is more to do..) 4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_activation_replicated.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_activation_replicated. Performed a total of 0 changes. 4.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 31 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.12.13. Executing OPT_DFF pass (perform DFF optimizations). 4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.12.16. Finished fast OPT passes. (There is nothing left to do.) 4.13. Executing FSM pass (extract and optimize FSM). 4.13.1. Executing FSM_DETECT pass (finding FSMs in design). 4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 4.14. Executing OPT pass (performing simple optimizations). 4.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 31 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_activation_replicated.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_activation_replicated. Performed a total of 0 changes. 4.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 31 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$375 ($dff) from module harness_nms_activation_replicated (D = { \lfsr [30:7] $xor$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:30$52_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001). Adding SRST signal on $procdff$377 ($dff) from module harness_nms_activation_replicated (D = $xor$hardware/v2/nms/synthesis/harness_nms_activation_replicated.v:58$57_Y, Q = \chk, rval = 8'00000000). Adding EN signal on $flatten\dut.$procdff$383 ($dff) from module harness_nms_activation_replicated (D = $flatten\dut.$memrd$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:47$310_DATA, Q = \dut.GEN_COPY[2].rd_data_reg). Adding EN signal on $flatten\dut.$procdff$391 ($dff) from module harness_nms_activation_replicated (D = $flatten\dut.$memrd$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:47$294_DATA, Q = \dut.GEN_COPY[0].rd_data_reg). Adding EN signal on $flatten\dut.$procdff$379 ($dff) from module harness_nms_activation_replicated (D = $flatten\dut.$memrd$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:47$318_DATA, Q = \dut.GEN_COPY[3].rd_data_reg). Adding EN signal on $flatten\dut.$procdff$387 ($dff) from module harness_nms_activation_replicated (D = $flatten\dut.$memrd$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:47$302_DATA, Q = \dut.GEN_COPY[1].rd_data_reg). 4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. Removed 5 unused cells and 5 unused wires. 4.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.14.9. Rerunning OPT passes. (Maybe there is more to do..) 4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_activation_replicated.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_activation_replicated. Performed a total of 0 changes. 4.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 27 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.14.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.14.16. Finished fast OPT passes. (There is nothing left to do.) 4.15. Executing WREDUCE pass (reducing word size of cells). Removed top 56 bits (of 64) from FF cell harness_nms_activation_replicated.$auto$ff.cc:337:slice$406 ($dffe). Removed top 56 bits (of 64) from FF cell harness_nms_activation_replicated.$auto$ff.cc:337:slice$405 ($dffe). Removed top 56 bits (of 64) from FF cell harness_nms_activation_replicated.$auto$ff.cc:337:slice$404 ($dffe). Removed top 56 bits (of 64) from FF cell harness_nms_activation_replicated.$auto$ff.cc:337:slice$403 ($dffe). Removed top 24 bits (of 32) from mux cell harness_nms_activation_replicated.$procmux$320 ($mux). Removed top 56 bits (of 256) from wire harness_nms_activation_replicated.rd_data_flat. Removed top 24 bits (of 32) from wire harness_nms_activation_replicated.$0\lfsr[31:0]. 4.16. Executing PEEPOPT pass (run peephole optimizers). 4.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. Removed 0 unused cells and 2 unused wires. 4.18. Executing SHARE pass (SAT-based resource sharing). 4.19. Executing TECHMAP pass (map to technology primitives). 4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 4.19.2. Continuing TECHMAP pass. No more expansions possible. 4.20. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.22. Executing TECHMAP pass (map to technology primitives). 4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 4.22.2. Continuing TECHMAP pass. No more expansions possible. 4.23. Executing TECHMAP pass (map to technology primitives). 4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 4.23.2. Continuing TECHMAP pass. No more expansions possible. 4.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module harness_nms_activation_replicated: created 0 $alu and 0 $macc cells. 4.25. Executing OPT pass (performing simple optimizations). 4.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 27 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_activation_replicated.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_activation_replicated. Performed a total of 0 changes. 4.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 27 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.25.6. Executing OPT_DFF pass (perform DFF optimizations). 4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.25.9. Finished fast OPT passes. (There is nothing left to do.) 4.26. Executing MEMORY pass. 4.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing harness_nms_activation_replicated.dut.GEN_COPY[0].mem write port 0. Analyzing harness_nms_activation_replicated.dut.GEN_COPY[1].mem write port 0. Analyzing harness_nms_activation_replicated.dut.GEN_COPY[2].mem write port 0. Analyzing harness_nms_activation_replicated.dut.GEN_COPY[3].mem write port 0. 4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\dut.GEN_COPY[0].mem'[0] in module `\harness_nms_activation_replicated': merging output FF to cell. Write port 0: non-transparent. Checking read port `\dut.GEN_COPY[1].mem'[0] in module `\harness_nms_activation_replicated': merging output FF to cell. Write port 0: non-transparent. Checking read port `\dut.GEN_COPY[2].mem'[0] in module `\harness_nms_activation_replicated': merging output FF to cell. Write port 0: non-transparent. Checking read port `\dut.GEN_COPY[3].mem'[0] in module `\harness_nms_activation_replicated': merging output FF to cell. Write port 0: non-transparent. 4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. Removed 4 unused cells and 32 unused wires. 4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 4.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory harness_nms_activation_replicated.dut.GEN_COPY[2].mem via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of harness_nms_activation_replicated.dut.GEN_COPY[2].mem: $\dut.GEN_COPY[2].mem$rdreg[0] mapping memory harness_nms_activation_replicated.dut.GEN_COPY[1].mem via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of harness_nms_activation_replicated.dut.GEN_COPY[1].mem: $\dut.GEN_COPY[1].mem$rdreg[0] mapping memory harness_nms_activation_replicated.dut.GEN_COPY[3].mem via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of harness_nms_activation_replicated.dut.GEN_COPY[3].mem: $\dut.GEN_COPY[3].mem$rdreg[0] mapping memory harness_nms_activation_replicated.dut.GEN_COPY[0].mem via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of harness_nms_activation_replicated.dut.GEN_COPY[0].mem: $\dut.GEN_COPY[0].mem$rdreg[0] 4.29. Executing TECHMAP pass (map to technology primitives). 4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 4.29.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. 4.30. Executing OPT pass (performing simple optimizations). 4.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 80 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.30.3. Executing OPT_DFF pass (perform DFF optimizations). 4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. Removed 0 unused cells and 451 unused wires. 4.30.5. Finished fast OPT passes. 4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 4.32. Executing OPT pass (performing simple optimizations). 4.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 80 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_activation_replicated.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_activation_replicated. Performed a total of 0 changes. 4.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 80 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.32.6. Executing OPT_DFF pass (perform DFF optimizations). 4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.32.9. Finished fast OPT passes. (There is nothing left to do.) 4.33. Executing TECHMAP pass (map to technology primitives). 4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 4.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $dffe. No more expansions possible. 4.34. Executing OPT pass (performing simple optimizations). 4.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 404 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.34.3. Executing OPT_DFF pass (perform DFF optimizations). 4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. Removed 281 unused cells and 4 unused wires. 4.34.5. Finished fast OPT passes. 4.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 4.37. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 123 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.38. Executing TECHMAP pass (map to technology primitives). 4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 4.38.2. Continuing TECHMAP pass. Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. No more expansions possible. 4.39. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). 4.41. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in harness_nms_activation_replicated. 4.42. Executing ATTRMVCP pass (move or copy attributes). 4.43. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. Removed 0 unused cells and 353 unused wires. 4.44. Executing CHECK pass (checking for obvious problems). Checking module harness_nms_activation_replicated... Found and reported 0 problems. 4.45. Executing TECHMAP pass (map to technology primitives). 4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 4.45.2. Continuing TECHMAP pass. No more expansions possible. 4.46. Executing ABC9 pass. 4.46.1. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.2. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.3. Executing PROC pass (convert processes to netlists). 4.46.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1243'. Cleaned up 1 empty switch. 4.46.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1244 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 4.46.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 4.46.3.4. Executing PROC_INIT pass (extract init attributes). 4.46.3.5. Executing PROC_ARST pass (detect async resets in processes). 4.46.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.46.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1244'. 1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1242_EN[3:0]$1250 2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1242_DATA[3:0]$1249 3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1242_ADDR[3:0]$1248 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1243'. 4.46.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1226_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1227_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1228_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1229_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1230_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1231_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1232_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1233_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1234_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1235_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1236_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1237_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1238_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1239_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1240_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1241_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1243'. 4.46.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1242_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1244'. created $dff cell `$procdff$1294' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1242_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1244'. created $dff cell `$procdff$1295' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1242_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1244'. created $dff cell `$procdff$1296' with positive edge clock. 4.46.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.46.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1268'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1244'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1244'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1243'. Cleaned up 1 empty switch. 4.46.4. Executing SCC pass (detecting logic loops). Found 0 SCCs in module harness_nms_activation_replicated. Found 0 SCCs. 4.46.5. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.6. Executing TECHMAP pass (map to technology primitives). 4.46.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.46.6.2. Continuing TECHMAP pass. No more expansions possible. 4.46.7. Executing OPT pass (performing simple optimizations). 4.46.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 4.46.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 4.46.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.46.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Performed a total of 0 changes. 4.46.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 4.46.7.6. Executing OPT_DFF pass (perform DFF optimizations). 4.46.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. 4.46.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 4.46.7.9. Finished fast OPT passes. (There is nothing left to do.) 4.46.8. Executing TECHMAP pass (map to technology primitives). 4.46.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 4.46.8.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. 4.46.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 4.46.10. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.11. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.12. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.13. Executing TECHMAP pass (map to technology primitives). 4.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.46.13.2. Continuing TECHMAP pass. No more expansions possible. 4.46.14. Executing OPT pass (performing simple optimizations). 4.46.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.46.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 0 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.46.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_activation_replicated.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.46.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_activation_replicated. Performed a total of 0 changes. 4.46.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_activation_replicated'. Computing hashes of 0 cells of `\harness_nms_activation_replicated'. Finding duplicate cells in `\harness_nms_activation_replicated'. Removed a total of 0 cells. 4.46.14.6. Executing OPT_DFF pass (perform DFF optimizations). 4.46.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_activation_replicated.. 4.46.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_activation_replicated. 4.46.14.9. Finished fast OPT passes. (There is nothing left to do.) 4.46.15. Executing AIGMAP pass (map logic to AIG). 4.46.16. Executing AIGMAP pass (map logic to AIG). Module harness_nms_activation_replicated: replaced 42 cells with 294 new cells, skipped 89 cells. replaced 2 cell types: 7 $_MUX_ 35 $_XOR_ not replaced 4 cell types: 1 $scopeinfo 72 TRELLIS_FF 8 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 8 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 4.46.16.1. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.16.2. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.16.3. Executing XAIGER backend. Extracted 126 AND gates and 496 wires from module `harness_nms_activation_replicated' to a netlist network with 114 inputs and 87 outputs. 4.46.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). 4.46.16.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 114/ 87 and = 126 lev = 8 (0.56) mem = 0.01 MB box = 8 bb = 8 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 114/ 87 and = 204 lev = 6 (0.44) mem = 0.01 MB ch = 26 box = 8 bb = 8 ABC: cst = 0 cls = 26 lit = 26 unused = 298 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 204. Ch = 26. Total mem = 0.08 MB. Peak cut mem = 0.00 MB. ABC: P: Del = 777.00. Ar = 24.0. Edge = 65. Cut = 1646. T = 0.00 sec ABC: P: Del = 777.00. Ar = 24.0. Edge = 65. Cut = 1646. T = 0.00 sec ABC: P: Del = 777.00. Ar = 24.0. Edge = 65. Cut = 1774. T = 0.00 sec ABC: F: Del = 777.00. Ar = 24.0. Edge = 65. Cut = 1742. T = 0.00 sec ABC: A: Del = 777.00. Ar = 24.0. Edge = 65. Cut = 1742. T = 0.00 sec ABC: A: Del = 777.00. Ar = 24.0. Edge = 65. Cut = 1742. T = 0.00 sec ABC: Total time = 0.00 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: The network is not changed by "&mfs". ABC: + &ps -l ABC: /input : i/o = 114/ 87 and = 126 lev = 6 (0.44) mem = 0.01 MB box = 8 bb = 8 ABC: Mapping (K=5) : lut = 16 edge = 65 lev = 1 (0.11) levB = 1 mem = 0.00 MB ABC: LUT = 16 : 2=0 0.0 % 3=7 43.8 % 4=1 6.2 % 5=8 50.0 % Ave = 4.06 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.01 sec ABC: + time ABC: elapse: 0.01 seconds, total: 0.01 seconds 4.46.16.6. Executing AIGER frontend. Removed 265 unused cells and 523 unused wires. 4.46.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 16 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 8 ABC RESULTS: input signals: 15 ABC RESULTS: output signals: 10 Removing temp directory. 4.46.17. Executing TECHMAP pass (map to technology primitives). 4.46.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 4.46.17.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. No more expansions possible. Removed 8 unused cells and 689 unused wires. 4.47. Executing TECHMAP pass (map to technology primitives). 4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 4.47.2. Continuing TECHMAP pass. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut. No more expansions possible. 4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in harness_nms_activation_replicated. Removed 0 unused cells and 32 unused wires. 4.49. Executing AUTONAME pass. Renamed 127 objects in module harness_nms_activation_replicated. 4.50. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `harness_nms_activation_replicated'. Setting top module to harness_nms_activation_replicated. 4.50.1. Analyzing design hierarchy.. Top module: \harness_nms_activation_replicated 4.50.2. Analyzing design hierarchy.. Top module: \harness_nms_activation_replicated Removed 0 unused modules. 4.51. Printing statistics. === harness_nms_activation_replicated === +----------Local Count, excluding submodules. | 47 wires 1239 wire bits 47 public wires 1239 public wire bits 4 ports 18 port bits 1 cells 1 $scopeinfo 112 submodules 24 LUT4 8 PFUMX 8 TRELLIS_DPR16X4 72 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 1 harness_nms_activation_replicated +----------Count including submodules. | 47 wires 1239 wire bits 47 public wires 1239 public wire bits 4 ports 18 port bits - memories - memory bits - processes 1 cells 1 $scopeinfo 112 submodules 24 LUT4 8 PFUMX 8 TRELLIS_DPR16X4 72 TRELLIS_FF 4.52. Executing CHECK pass (checking for obvious problems). Checking module harness_nms_activation_replicated... Found and reported 0 problems. 4.53. Executing JSON backend. End of script. Logfile hash: b37c77c3ec, time: 0.27s, user: 0.23s, system: 0.01s, MEM: 31.14 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 64% 22x read_verilog (0 sec), 11% 1x abc9_exe (0 sec), ...