.device LFE5U-45F .comment Part: LFE5U-45F-8CABGA381 .tile CIB_R10C3:PVT_COUNT2 unknown: F2B0 unknown: F3B0 unknown: F5B0 unknown: F11B0 unknown: F13B0 .tile CIB_R10C49:CIB_EBR arc: N3_V06N0203 S3_V06N0103 .tile CIB_R17C89:CIB_LR arc: W3_H06W0303 JQ5 .tile CIB_R19C1:CIB_LR arc: S1_V02S0501 S3_V06N0303 .tile CIB_R1C17:CIB arc: E1_H02E0501 S1_V02N0501 .tile CIB_R1C18:CIB arc: JA0 H02W0701 enum: CIB.JB0MUX 0 .tile CIB_R1C19:CIB arc: JA0 W1_H02E0501 arc: W1_H02W0701 S1_V02N0701 enum: CIB.JB0MUX 0 .tile CIB_R1C20:CIB arc: E3_H06E0003 JQ0 .tile CIB_R1C21:CIB arc: E3_H06E0003 JQ0 .tile CIB_R1C22:CIB arc: JA0 E1_H02W0701 enum: CIB.JB0MUX 0 .tile CIB_R1C23:CIB arc: E1_H02E0701 S1_V02N0701 arc: E3_H06E0003 JQ0 .tile CIB_R1C24:CIB arc: JA0 H02E0701 arc: W1_H02W0701 V06N0203 enum: CIB.JB0MUX 0 .tile CIB_R1C25:CIB arc: E3_H06E0003 JQ0 .tile CIB_R1C26:CIB arc: E3_H06E0103 W3_H06E0003 .tile CIB_R1C27:CIB arc: E1_H01E0001 JQ0 arc: E3_H06E0003 W3_H06E0003 .tile CIB_R1C28:CIB arc: E3_H06E0003 JQ0 arc: E3_H06E0203 H01E0001 .tile CIB_R1C29:CIB arc: E3_H06E0003 JQ0 arc: E3_H06E0103 W3_H06E0003 .tile CIB_R1C30:CIB arc: E1_H02E0501 S3_V06N0303 arc: JA0 H02W0701 enum: CIB.JB0MUX 0 .tile CIB_R1C31:CIB arc: E1_H01E0101 JQ0 arc: E3_H06E0003 W3_H06E0003 arc: W1_H02W0701 V02N0701 .tile CIB_R1C32:CIB arc: E3_H06E0103 H01E0101 arc: E3_H06E0203 W3_H06E0103 arc: JA0 W1_H02E0501 enum: CIB.JB0MUX 0 .tile CIB_R1C33:CIB arc: E3_H06E0103 W3_H06E0003 arc: JA0 E1_H02W0701 enum: CIB.JB0MUX 0 .tile CIB_R1C34:CIB arc: E3_H06E0003 W3_H06E0003 arc: S3_V06S0003 JQ0 arc: S3_V06S0203 W3_H06E0203 .tile CIB_R1C35:CIB arc: E3_H06E0103 W3_H06E0003 arc: S3_V06S0103 W3_H06E0103 arc: W1_H02W0701 S1_V02N0701 .tile CIB_R1C36:CIB arc: S3_V06S0003 JQ0 arc: S3_V06S0103 H06E0103 arc: S3_V06S0303 E1_H01W0100 .tile CIB_R1C37:CIB arc: E1_H02E0701 S1_V02N0701 arc: E3_H06E0003 W3_H06E0003 arc: H01W0100 JQ0 arc: S3_V06S0003 H06E0003 arc: S3_V06S0103 H06W0103 arc: S3_V06S0203 H06W0203 .tile CIB_R1C38:CIB arc: E3_H06E0103 W3_H06E0103 arc: JA0 H02W0501 arc: S3_V06S0203 W3_H06E0203 arc: S3_V06S0303 H06W0303 enum: CIB.JB0MUX 0 .tile CIB_R1C39:CIB arc: JA0 W1_H02E0701 arc: S3_V06S0103 W3_H06E0103 arc: S3_V06S0203 E3_H06W0203 arc: W1_H02W0501 S1_V02N0501 enum: CIB.JB0MUX 0 .tile CIB_R1C40:CIB arc: S3_V06S0003 H06E0003 arc: S3_V06S0103 H06W0103 arc: S3_V06S0203 E3_H06W0203 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0203 E3_H06W0103 .tile CIB_R1C41:CIB arc: S1_V02S0201 W3_H06E0103 arc: S3_V06S0003 E3_H06W0003 arc: S3_V06S0103 H06E0103 arc: S3_V06S0303 E1_H01W0100 arc: W3_H06W0303 E1_H01W0100 .tile CIB_R1C42:CIB arc: E1_H02E0501 V01N0101 arc: H01W0100 JQ0 arc: S1_V02S0001 JQ0 arc: S1_V02S0201 E1_H01W0000 arc: S3_V06S0003 E3_H06W0003 arc: S3_V06S0103 E3_H06W0103 arc: S3_V06S0203 E3_H06W0203 arc: S3_V06S0303 H06W0303 .tile CIB_R1C43:CIB arc: E1_H02E0501 V01N0101 arc: H01W0000 JQ0 arc: S3_V06S0003 H06W0003 arc: W3_H06W0103 E3_H06W0003 .tile CIB_R1C44:CIB arc: JA0 W1_H02E0501 arc: S3_V06S0203 E3_H06W0203 arc: S3_V06S0303 H06W0303 enum: CIB.JB0MUX 0 .tile CIB_R1C45:CIB arc: JA0 W1_H02E0501 arc: S3_V06S0303 E3_H06W0303 arc: W3_H06W0203 E3_H06W0103 arc: W3_H06W0303 E3_H06W0203 enum: CIB.JB0MUX 0 .tile CIB_R1C46:CIB arc: S3_V06S0203 E3_H06W0203 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E1_H01W0100 arc: W3_H06W0203 E3_H06W0103 .tile CIB_R1C47:CIB arc: H01W0100 JQ0 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0303 E3_H06W0203 .tile CIB_R1C48:CIB arc: JD7 E1_H01W0100 arc: W3_H06W0003 JQ0 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0203 E3_H06W0203 .tile CIB_R1C49:CIB arc: E1_H02E0501 V06N0303 arc: H01W0100 E3_H06W0303 arc: W3_H06W0003 JQ0 .tile CIB_R1C50:CIB arc: JA0 H02E0501 arc: W3_H06W0203 E3_H06W0103 enum: CIB.JB0MUX 0 .tile CIB_R1C51:CIB arc: JA0 H02W0701 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0203 E3_H06W0103 arc: W3_H06W0303 E3_H06W0203 enum: CIB.JB0MUX 0 .tile CIB_R1C52:CIB arc: W1_H02W0701 S1_V02N0701 arc: W3_H06W0003 JQ0 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0203 E1_H01W0000 .tile CIB_R1C53:CIB arc: H01W0000 JQ0 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0203 E3_H06W0103 .tile CIB_R1C54:CIB arc: JA0 V02N0701 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0203 E3_H06W0203 enum: CIB.JB0MUX 0 .tile CIB_R1C55:CIB arc: W3_H06W0303 E1_H01W0100 .tile CIB_R1C56:CIB arc: H01W0100 JQ0 arc: W3_H06W0103 E3_H06W0003 .tile CIB_R1C57:CIB arc: E1_H02E0701 S1_V02N0701 arc: W3_H06W0003 JQ0 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0203 E3_H06W0103 .tile CIB_R1C58:CIB arc: W3_H06W0003 JQ0 .tile CIB_R1C59:CIB arc: JA0 W1_H02E0701 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0103 enum: CIB.JB0MUX 0 .tile CIB_R1C60:CIB arc: JA0 H02W0501 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0203 E3_H06W0103 enum: CIB.JB0MUX 0 .tile CIB_R1C61:CIB arc: JA0 V02N0501 arc: W1_H02W0501 S1_V02N0501 enum: CIB.JB0MUX 0 .tile CIB_R1C62:CIB arc: W3_H06W0003 JQ0 .tile CIB_R1C63:CIB arc: W3_H06W0003 JQ0 arc: W3_H06W0103 E3_H06W0003 .tile CIB_R1C65:CIB arc: W3_H06W0003 JQ0 arc: W3_H06W0103 E3_H06W0003 .tile CIB_R1C66:CIB arc: W3_H06W0003 JQ0 arc: W3_H06W0103 E3_H06W0003 .tile CIB_R1C67:CIB arc: E1_H02E0701 S3_V06N0203 arc: JA0 S1_V02N0501 enum: CIB.JB0MUX 0 .tile CIB_R1C68:CIB arc: JA0 H02E0701 enum: CIB.JB0MUX 0 .tile CIB_R1C69:CIB arc: W3_H06W0003 JQ0 .tile CIB_R1C70:CIB arc: JA0 S1_V02N0701 enum: CIB.JB0MUX 0 .tile CIB_R1C71:CIB arc: W3_H06W0003 JQ0 .tile CIB_R1C72:CIB arc: W3_H06W0003 JQ0 .tile CIB_R1C73:CIB arc: E1_H02E0501 V02N0501 .tile CIB_R1C75:CIB arc: JA0 W1_H02E0501 enum: CIB.JB0MUX 0 .tile CIB_R20C1:CIB_LR arc: JA0 E1_H02W0701 arc: JA3 V02S0501 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R20C89:CIB_LR arc: S3_V06S0303 JF5 arc: W3_H06W0303 JQ5 .tile CIB_R22C13:CIB_DSP arc: E3_H06E0303 W3_H06E0303 .tile CIB_R22C19:CIB_DSP arc: E3_H06E0303 W3_H06E0303 .tile CIB_R22C1:CIB_LR_S arc: E3_H06E0303 JQ5 arc: S3_V06S0303 JF5 .tile CIB_R22C25:CIB_DSP arc: E3_H06E0003 W3_H06E0303 .tile CIB_R22C31:CIB_DSP arc: E3_H06E0103 W3_H06E0003 .tile CIB_R22C37:CIB_DSP arc: E3_H06E0203 W3_H06E0103 arc: E3_H06E0303 S3_V06N0303 arc: S3_V06S0103 W3_H06E0103 .tile CIB_R22C41:CIB_DSP arc: S3_V06S0103 E3_H06W0103 .tile CIB_R22C43:CIB_DSP arc: E3_H06E0003 W3_H06E0303 arc: S3_V06S0203 W3_H06E0203 .tile CIB_R22C47:CIB_DSP arc: W3_H06W0103 E3_H06W0103 .tile CIB_R22C49:CIB_DSP arc: N3_V06N0003 W3_H06E0003 .tile CIB_R22C53:CIB_DSP arc: W3_H06W0103 E3_H06W0003 .tile CIB_R22C59:CIB_DSP arc: W3_H06W0003 E3_H06W0303 .tile CIB_R22C65:CIB_DSP arc: W3_H06W0303 E3_H06W0203 .tile CIB_R22C71:CIB_DSP arc: W3_H06W0203 E3_H06W0103 .tile CIB_R22C77:CIB_DSP arc: W3_H06W0103 E3_H06W0003 .tile CIB_R22C7:CIB_DSP arc: E3_H06E0303 W3_H06E0303 .tile CIB_R22C83:CIB_DSP arc: W3_H06W0003 E3_H06W0303 .tile CIB_R22C89:CIB_LR_S arc: S3_V06S0303 JF5 arc: W3_H06W0303 JQ5 .tile CIB_R23C1:CIB_LR arc: JA0 E1_H02W0501 arc: JA3 V02N0701 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R23C89:CIB_LR arc: S3_V06S0303 JF5 arc: W3_H06W0303 JQ5 .tile CIB_R24C1:CIB_LR arc: N1_V02N0701 S1_V02N0701 .tile CIB_R25C1:CIB_LR arc: E3_H06E0303 JQ5 arc: N3_V06N0303 S3_V06N0303 arc: S3_V06S0303 JF5 .tile CIB_R25C89:CIB_LR arc: S3_V06S0303 JF5 arc: W3_H06W0303 JQ5 .tile CIB_R26C1:CIB_LR arc: E1_H01E0101 JQ5 arc: E3_H06E0303 JF5 arc: N1_V02N0701 H06W0203 .tile CIB_R26C89:CIB_LR arc: JA0 W1_H02E0501 arc: JA3 W1_H02E0701 arc: W3_H06W0303 N3_V06S0303 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R27C89:CIB_LR arc: S1_V02S0501 S3_V06N0303 arc: S1_V02S0701 S3_V06N0203 .tile CIB_R28C1:CIB_LR arc: E3_H06E0303 N3_V06S0303 arc: S1_V02S0501 JF5 arc: S3_V06S0303 JQ5 .tile CIB_R28C89:CIB_LR arc: JA3 W1_H02E0701 arc: S3_V06S0003 N3_V06S0303 arc: S3_V06S0303 JF5 arc: W3_H06W0303 V06S0303 enum: CIB.JB3MUX 0 .tile CIB_R29C1:CIB_LR arc: E3_H06E0303 JQ5 arc: S1_V02S0701 E3_H06W0203 arc: S3_V06S0303 JF5 .tile CIB_R29C89:CIB_LR arc: JA0 N1_V02S0501 arc: JA3 N1_V02S0701 arc: W3_H06W0303 N3_V06S0303 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R30C1:CIB_LR arc: S3_V06S0303 N1_V02S0501 .tile CIB_R31C1:CIB_LR arc: E3_H06E0303 V06S0303 arc: JA0 E1_H02W0501 arc: JA3 N1_V02S0701 arc: N3_V06N0303 E3_H06W0303 arc: V01S0100 N3_V06S0303 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R31C89:CIB_LR arc: JA3 S1_V02N0701 arc: W1_H02W0601 V06S0303 arc: W3_H06W0003 V06S0003 arc: W3_H06W0303 JF5 enum: CIB.JB3MUX 0 .tile CIB_R32C1:CIB_LR arc: E1_H02E0501 V06S0303 arc: E1_H02E0701 JF5 arc: E3_H06E0303 N1_V01S0100 arc: JA3 E1_H02W0501 arc: S1_V02S0701 H06W0203 enum: CIB.JB3MUX 0 .tile CIB_R32C89:CIB_LR arc: JA3 W1_H02E0501 arc: W3_H06W0303 JF5 enum: CIB.JB3MUX 0 .tile CIB_R33C1:CIB_LR arc: E3_H06E0303 V06S0303 .tile CIB_R33C89:CIB_LR arc: N1_V02N0701 H01E0101 arc: N3_V06N0203 H06E0203 arc: N3_V06N0303 H06E0303 .tile CIB_R34C13:CIB_EBR arc: E3_H06E0103 W3_H06E0003 .tile CIB_R34C19:CIB_EBR arc: E3_H06E0103 W3_H06E0103 .tile CIB_R34C1:CIB_LR_S arc: E3_H06E0303 JF5 arc: JA3 N1_V02S0701 enum: CIB.JB3MUX 0 .tile CIB_R34C25:CIB_EBR arc: E3_H06E0103 W3_H06E0103 .tile CIB_R34C27:CIB_EBR arc: E1_H02E0401 E3_H06W0203 .tile CIB_R34C28:CIB_EBR arc: N1_V02N0401 H02E0401 .tile CIB_R34C29:CIB_EBR arc: S1_V02S0501 E1_H02W0501 .tile CIB_R34C30:CIB_EBR arc: E1_H02E0601 E3_H06W0303 arc: S1_V02S0101 H02W0101 .tile CIB_R34C31:CIB_EBR arc: E3_H06E0203 W3_H06E0103 arc: W1_H02W0101 E3_H06W0103 arc: W1_H02W0501 E3_H06W0303 .tile CIB_R34C32:CIB_EBR arc: S1_V02S0601 W1_H02E0601 .tile CIB_R34C33:CIB_EBR arc: V01S0000 S3_V06N0103 arc: W3_H06W0203 E3_H06W0203 .tile CIB_R34C34:CIB_EBR arc: N1_V02N0201 S3_V06N0103 arc: S1_V02S0001 E1_H02W0001 arc: S1_V02S0101 N1_V02S0001 .tile CIB_R34C35:CIB_EBR arc: N1_V02N0201 H02W0201 arc: S1_V02S0001 N1_V02S0501 arc: S1_V02S0201 H06W0103 arc: S1_V02S0401 H06W0203 arc: S1_V02S0601 H06W0303 arc: V01S0100 S3_V06N0303 .tile CIB_R34C36:CIB_EBR arc: E1_H02E0001 V02N0001 arc: E1_H02E0101 V02N0101 arc: E1_H02E0201 V02S0201 arc: E1_H02E0301 V02N0301 arc: E1_H02E0401 V06S0203 arc: E1_H02E0501 N1_V01S0100 arc: E1_H02E0601 N1_V01S0000 arc: N1_V02N0101 E1_H02W0101 arc: N1_V02N0301 E3_H06W0003 arc: S1_V02S0201 H06W0103 arc: S1_V02S0301 H06W0003 arc: W1_H02W0001 E1_H02W0501 arc: W1_H02W0201 E3_H06W0103 arc: W3_H06W0303 E1_H01W0100 .tile CIB_R34C37:CIB_EBR arc: E1_H02E0001 N3_V06S0003 arc: E1_H02E0101 N1_V02S0101 arc: E1_H02E0201 N1_V01S0000 arc: E1_H02E0301 V02S0301 arc: E1_H02E0401 N1_V02S0401 arc: E1_H02E0501 N1_V01S0100 arc: E1_H02E0601 N1_V02S0601 arc: E1_H02E0701 V06S0203 arc: E3_H06E0303 W3_H06E0203 arc: H00R0100 H02E0501 arc: H01W0100 JF7 arc: JB6 H02E0101 arc: JB7 V02S0701 arc: JD6 V00B0000 arc: JD7 H00R0100 arc: N1_V01N0001 JQ7 arc: N1_V02N0001 H02W0001 arc: N1_V02N0401 V01N0001 arc: N3_V06N0303 JF6 arc: S1_V02S0001 N1_V02S0001 arc: S1_V02S0501 E1_H01W0100 arc: S1_V02S0601 E1_H01W0000 arc: S1_V02S0701 N3_V06S0203 arc: S3_V06S0303 N3_V06S0303 arc: V00B0000 V02N0201 arc: V01S0100 N3_V06S0303 arc: W3_H06W0103 E1_H02W0201 arc: W3_H06W0303 JQ6 enum: CIB.JCE3MUX 1 enum: CIB.JCE2MUX 1 .tile CIB_R34C38:CIB_EBR arc: E1_H01E0001 JF0 arc: E1_H01E0101 JQ4 arc: E1_H02E0001 S1_V02N0001 arc: E1_H02E0101 S3_V06N0103 arc: E1_H02E0201 N3_V06S0103 arc: E1_H02E0301 V06S0003 arc: E1_H02E0401 W1_H02E0401 arc: E1_H02E0601 V06S0303 arc: E1_H02E0701 N1_V02S0701 arc: H00L0000 N1_V02S0201 arc: H00R0000 W1_H02E0601 arc: H01W0000 JF6 arc: H01W0100 JQ2 arc: JA0 H00L0000 arc: JA1 E1_H02W0701 arc: JA2 V02N0701 arc: JA3 H02E0701 arc: JA5 E1_H02W0501 arc: JA7 E1_H02W0501 arc: JB0 H02E0101 arc: JB1 H02W0101 arc: JB2 H00R0000 arc: JB3 N1_V02S0301 arc: JB4 V00B0100 arc: JB5 N1_V01S0000 arc: JB6 N1_V02S0501 arc: JB7 W1_H02E0301 arc: JC2 E1_H02W0401 arc: JC3 H02W0601 arc: JC4 E1_H02W0601 arc: JC6 E1_H02W0601 arc: JCLK0 G_HPBX0000 arc: JD0 V02S0201 arc: JD1 V02S0001 arc: JD2 W1_H02E0001 arc: JD3 S1_V02N0201 arc: JD4 N1_V02S0401 arc: JD5 H02W0001 arc: JD6 W1_H02E0201 arc: JD7 V02S0401 arc: N1_V01N0001 JF5 arc: N1_V01N0101 JQ3 arc: N1_V02N0101 JF1 arc: N1_V02N0201 JQ0 arc: N1_V02N0301 JQ1 arc: N1_V02N0401 JQ6 arc: N1_V02N0501 JQ7 arc: S1_V02S0201 JF2 arc: S3_V06S0203 E1_H01W0000 arc: V00B0100 V02S0301 arc: W1_H02W0001 S3_V06N0003 arc: W1_H02W0101 JF3 arc: W1_H02W0501 JF7 arc: W3_H06W0103 E1_H01W0100 arc: W3_H06W0203 JF4 arc: W3_H06W0303 JQ5 enum: CIB.JLSR0MUX 0 enum: CIB.JCE0MUX 1 enum: CIB.JCE3MUX 1 enum: CIB.JCE2MUX 1 enum: CIB.JCE1MUX 1 enum: CIB.JC1MUX 0 enum: CIB.JA6MUX 0 enum: CIB.JC7MUX 0 enum: CIB.JA4MUX 0 enum: CIB.JC5MUX 0 .tile CIB_R34C39:CIB_EBR arc: E1_H01E0001 JF1 arc: E3_H06E0003 JQ3 arc: H00L0100 H02E0301 arc: H00R0000 V02N0401 arc: H00R0100 V02N0501 arc: H01W0000 JF4 arc: H01W0100 JQ2 arc: JA0 H00L0100 arc: JA1 V02N0701 arc: JA4 H02E0701 arc: JA5 W1_H02E0501 arc: JA6 S1_V02N0301 arc: JA7 N1_V02S0101 arc: JB0 S1_V02N0101 arc: JB1 H02W0301 arc: JB2 V02S0301 arc: JB3 H00R0100 arc: JB4 V02S0501 arc: JB5 W1_H02E0301 arc: JB6 V02S0701 arc: JB7 H02E0101 arc: JC0 H02E0601 arc: JC1 V02S0601 arc: JC4 W1_H02E0601 arc: JC5 H02E0401 arc: JC6 W1_H02E0401 arc: JC7 V00T0100 arc: JCLK0 G_HPBX0000 arc: JD0 W1_H02E0201 arc: JD1 H02E0001 arc: JD2 H00R0000 arc: JD3 H02W0201 arc: JD4 S1_V02N0601 arc: JD5 W1_H02E0001 arc: JD6 V00B0000 arc: JD7 H02E0201 arc: N1_V01N0101 JQ5 arc: N1_V02N0001 H01E0001 arc: N1_V02N0101 JF3 arc: N1_V02N0401 JQ6 arc: N1_V02N0501 H01E0101 arc: N1_V02N0601 JF6 arc: N3_V06N0003 JF0 arc: N3_V06N0203 JQ4 arc: N3_V06N0303 JF5 arc: S1_V02S0701 H06W0203 arc: S3_V06S0203 JF7 arc: V00B0000 V02N0201 arc: V00T0100 N1_V02S0701 arc: W1_H02W0001 V02N0001 arc: W1_H02W0101 V02N0101 arc: W1_H02W0201 JF2 arc: W1_H02W0601 E1_H02W0601 arc: W3_H06W0003 JQ0 arc: W3_H06W0103 JQ1 arc: W3_H06W0203 JQ7 enum: CIB.JLSR0MUX 0 enum: CIB.JCE0MUX 1 enum: CIB.JCE3MUX 1 enum: CIB.JCE2MUX 1 enum: CIB.JCE1MUX 1 .tile CIB_R34C40:CIB_EBR arc: E1_H02E0401 N3_V06S0203 arc: E1_H02E0501 V06S0303 arc: E1_H02E0601 V02N0601 arc: E1_H02E0701 N1_V01S0100 arc: E3_H06E0203 H01E0001 arc: N1_V02N0201 E3_H06W0103 arc: N1_V02N0601 H06E0303 arc: W1_H02W0201 S1_V02N0201 arc: W1_H02W0301 V01N0101 arc: W1_H02W0401 N3_V06S0203 arc: W1_H02W0501 V02N0501 arc: W1_H02W0601 V02N0601 arc: W1_H02W0701 N1_V01S0100 .tile CIB_R34C41:CIB_EBR arc: E1_H02E0001 V02N0001 arc: E1_H02E0101 V06S0103 arc: E1_H02E0201 N3_V06S0103 arc: E1_H02E0301 N1_V02S0301 arc: E1_H02E0401 N1_V02S0401 arc: E1_H02E0601 V06S0303 arc: E1_H02E0701 V02S0701 arc: N1_V02N0401 E1_H01W0000 arc: N3_V06N0303 E1_H01W0100 arc: S1_V02S0601 S3_V06N0303 arc: W1_H02W0601 V06S0303 .tile CIB_R34C42:CIB_EBR arc: E1_H01E0001 JQ6 arc: E1_H01E0101 JF4 arc: E1_H02E0001 V01N0001 arc: E1_H02E0101 V06S0103 arc: E1_H02E0301 N3_V06S0003 arc: E1_H02E0401 V06S0203 arc: E1_H02E0501 N1_V02S0501 arc: E1_H02E0601 N3_V06S0303 arc: E3_H06E0103 JQ1 arc: E3_H06E0203 JF7 arc: E3_H06E0303 JF6 arc: H00L0000 N1_V02S0201 arc: H00L0100 N1_V02S0101 arc: H00R0000 V02N0601 arc: H01W0000 JQ7 arc: H01W0100 JF0 arc: JA0 H00L0100 arc: JA1 W1_H02E0701 arc: JA2 H02W0501 arc: JA3 W1_H02E0501 arc: JA5 V00B0000 arc: JA7 H00R0000 arc: JB0 S1_V02N0301 arc: JB1 V02N0301 arc: JB2 H00L0000 arc: JB3 H02E0301 arc: JB4 V02N0501 arc: JB5 N1_V01S0000 arc: JB6 N1_V02S0701 arc: JB7 V02S0701 arc: JC2 W1_H02E0401 arc: JC3 H02E0601 arc: JC4 W1_H02E0601 arc: JC6 W1_H02E0601 arc: JCLK0 G_HPBX0000 arc: JD0 V02N0201 arc: JD1 V00T0100 arc: JD2 V00B0100 arc: JD3 V02S0201 arc: JD4 S1_V02N0601 arc: JD5 H02E0001 arc: JD6 E1_H02W0201 arc: JD7 H02W0201 arc: N1_V01N0001 JF5 arc: N1_V02N0101 JF3 arc: N1_V02N0201 JQ2 arc: N1_V02N0601 E1_H01W0000 arc: S1_V02S0001 H06E0003 arc: S1_V02S0101 JF1 arc: S1_V02S0201 JQ0 arc: S1_V02S0401 H02W0401 arc: S1_V02S0501 E1_H01W0100 arc: S1_V02S0601 H02W0601 arc: S3_V06S0303 JQ5 arc: V00B0000 W1_H02E0601 arc: V00B0100 V02N0101 arc: V00T0100 S1_V02N0701 arc: W3_H06W0003 JQ3 arc: W3_H06W0103 JF2 arc: W3_H06W0203 JQ4 enum: CIB.JLSR0MUX 0 enum: CIB.JCE0MUX 1 enum: CIB.JCE3MUX 1 enum: CIB.JCE2MUX 1 enum: CIB.JCE1MUX 1 enum: CIB.JC1MUX 0 enum: CIB.JA6MUX 0 enum: CIB.JC7MUX 0 enum: CIB.JA4MUX 0 enum: CIB.JC5MUX 0 .tile CIB_R34C43:CIB_EBR arc: E1_H01E0001 JF2 arc: E1_H01E0101 JF0 arc: E1_H02E0101 S1_V02N0101 arc: H00L0000 W1_H02E0201 arc: H00L0100 H02E0101 arc: H00R0000 S1_V02N0401 arc: H00R0100 H02E0501 arc: H01W0000 JF3 arc: H01W0100 JF1 arc: JA0 H00L0000 arc: JA1 S1_V02N0701 arc: JA4 N1_V01N0101 arc: JA5 V02S0101 arc: JA6 V00T0100 arc: JA7 N1_V02S0101 arc: JB0 E1_H02W0101 arc: JB1 V02S0301 arc: JB3 W1_H02E0101 arc: JB5 N1_V01S0000 arc: JB7 H02E0301 arc: JC0 H00L0100 arc: JC1 H02E0401 arc: JC4 V00B0100 arc: JC5 H02E0601 arc: JC6 W1_H02E0401 arc: JC7 V02S0001 arc: JCLK0 G_HPBX0000 arc: JD0 V02N0201 arc: JD1 V02S0201 arc: JD2 H00R0000 arc: JD4 N1_V02S0401 arc: JD6 H00R0100 arc: N1_V01N0001 JF5 arc: N1_V01N0101 S3_V06N0203 arc: N1_V02N0001 JQ0 arc: N1_V02N0101 JQ1 arc: N1_V02N0201 H01E0001 arc: N1_V02N0401 JF6 arc: N1_V02N0601 H06W0303 arc: N3_V06N0203 JF7 arc: N3_V06N0303 S3_V06N0203 arc: S1_V02S0401 N1_V02S0401 arc: S1_V02S0601 N1_V02S0301 arc: S1_V02S0701 H06E0203 arc: S3_V06S0103 H01E0101 arc: V00B0100 W1_H02E0701 arc: V00T0100 V02S0701 arc: W1_H02W0201 N1_V02S0201 arc: W1_H02W0401 JF4 arc: W1_H02W0501 N3_V06S0303 arc: W1_H02W0601 E1_H01W0000 enum: CIB.JLSR0MUX 0 enum: CIB.JCE0MUX 1 enum: CIB.JB6MUX 0 enum: CIB.JD7MUX 0 enum: CIB.JB4MUX 0 enum: CIB.JD5MUX 0 enum: CIB.JB2MUX 0 enum: CIB.JD3MUX 0 enum: CIB.JCE2MUX 1 enum: CIB.JCE3MUX 1 enum: CIB.JCE1MUX 1 .tile CIB_R34C44:CIB_EBR arc: H01W0000 JF0 arc: JB1 H02E0101 arc: JD0 W1_H02E0001 arc: N1_V02N0101 JF1 arc: S1_V02S0001 H01E0001 arc: S1_V02S0101 H01E0101 arc: W1_H02W0201 V02N0201 enum: CIB.JB0MUX 0 enum: CIB.JD1MUX 0 enum: CIB.JCE3MUX 1 enum: CIB.JCE2MUX 1 .tile CIB_R34C45:CIB_EBR arc: N1_V02N0401 H06E0203 arc: S1_V02S0101 H06E0103 arc: S3_V06S0303 H06E0303 arc: W1_H02W0101 N1_V01S0100 .tile CIB_R34C46:CIB_EBR arc: S1_V02S0601 N1_V02S0301 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0303 E1_H01W0100 .tile CIB_R34C47:CIB_EBR arc: H01W0100 E3_H06W0303 .tile CIB_R34C52:CIB_EBR arc: W3_H06W0003 E3_H06W0303 .tile CIB_R34C53:CIB_EBR arc: W3_H06W0303 E3_H06W0303 .tile CIB_R34C58:CIB_EBR arc: W3_H06W0303 E3_H06W0303 .tile CIB_R34C59:CIB_EBR arc: W3_H06W0303 E3_H06W0303 .tile CIB_R34C64:CIB_EBR arc: W3_H06W0303 E3_H06W0203 .tile CIB_R34C65:CIB_EBR arc: W3_H06W0303 E3_H06W0303 .tile CIB_R34C70:CIB_EBR arc: W3_H06W0203 E3_H06W0203 .tile CIB_R34C71:CIB_EBR arc: W3_H06W0303 E3_H06W0303 .tile CIB_R34C76:CIB_EBR arc: W3_H06W0203 E3_H06W0203 .tile CIB_R34C77:CIB_EBR arc: W3_H06W0303 E3_H06W0303 .tile CIB_R34C7:CIB_EBR arc: E3_H06E0003 W3_H06E0303 .tile CIB_R34C82:CIB_EBR arc: W3_H06W0203 E3_H06W0203 .tile CIB_R34C83:CIB_EBR arc: W3_H06W0303 E3_H06W0303 .tile CIB_R34C88:CIB_EBR arc: W3_H06W0203 E1_H01W0000 .tile CIB_R34C89:CIB_LR_S arc: H01W0000 JQ5 arc: W3_H06W0303 JF5 .tile CIB_R35C1:CIB_LR arc: E1_H01E0001 E3_H06W0003 arc: E1_H02E0701 S1_V02N0701 arc: JA0 E1_H02W0501 arc: JA3 E1_H01E0001 arc: S1_V02S0701 H06W0203 arc: S3_V06S0103 H06W0103 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R35C89:CIB_LR arc: H01W0000 JQ5 arc: S1_V02S0701 W1_H02E0701 arc: W3_H06W0303 JF5 .tile CIB_R36C1:CIB_LR arc: E1_H02E0601 S1_V02N0601 .tile CIB_R37C1:CIB_LR arc: E3_H06E0303 S3_V06N0303 arc: JA0 N1_V02S0701 arc: N1_V02N0701 JQ5 enum: CIB.JB0MUX 0 .tile CIB_R37C89:CIB_LR arc: H01W0100 JQ5 arc: JA0 N1_V02S0701 arc: S3_V06S0203 H01E0001 arc: W1_H02W0601 V06N0303 arc: W3_H06W0303 S3_V06N0303 enum: CIB.JB0MUX 0 .tile CIB_R38C1:CIB_LR arc: E1_H02E0601 S1_V02N0601 arc: E3_H06E0003 S3_V06N0003 arc: E3_H06E0303 JQ5 arc: JA0 H02W0501 arc: N1_V02N0601 S3_V06N0303 enum: CIB.JB0MUX 0 .tile CIB_R38C89:CIB_LR arc: JA0 W1_H02E0501 arc: JA3 W1_H02E0701 arc: S1_V02S0701 H06E0203 arc: W3_H06W0303 V06N0303 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R39C1:CIB_LR arc: E3_H06E0003 V01N0001 .tile CIB_R40C1:CIB_LR arc: E3_H06E0303 JQ5 arc: N1_V01N0001 JF5 arc: N1_V02N0601 S3_V06N0303 .tile CIB_R40C89:CIB_LR arc: JA3 N1_V02S0701 arc: N3_V06N0303 JF5 arc: W3_H06W0303 S3_V06N0303 enum: CIB.JB3MUX 0 .tile CIB_R41C1:CIB_LR arc: JA0 H02W0701 arc: JA3 H02W0501 arc: S3_V06S0203 N3_V06S0103 enum: CIB.JB0MUX 0 enum: CIB.JB3MUX 0 .tile CIB_R41C89:CIB_LR arc: N3_V06N0303 JQ5 arc: S1_V02S0501 W1_H02E0501 arc: W3_H06W0303 JF5 .tile CIB_R42C1:CIB_LR arc: S1_V02S0501 E1_H02W0501 .tile CIB_R43C1:CIB_LR arc: E3_H06E0303 JQ5 arc: N3_V06N0303 JF5 .tile CIB_R43C89:CIB_LR arc: JA0 N1_V02S0501 arc: N3_V06N0303 JQ5 arc: S1_V02S0701 N3_V06S0203 enum: CIB.JB0MUX 0 .tile CIB_R44C1:CIB_LR arc: JA0 E1_H02W0501 arc: N3_V06N0003 S3_V06N0303 arc: N3_V06N0303 JQ5 arc: S1_V02S0501 N1_V02S0501 enum: CIB.JB0MUX 0 .tile CIB_R44C89:CIB_LR arc: JA0 H02E0701 arc: JA3 V02S0701 arc: W3_H06W0303 S3_V06N0303 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R45C89:CIB_LR arc: S1_V02S0401 W1_H02E0401 .tile CIB_R46C13:CIB_DSP arc: E3_H06E0103 W3_H06E0003 .tile CIB_R46C19:CIB_DSP arc: E3_H06E0203 W3_H06E0103 .tile CIB_R46C1:CIB_LR_S arc: E3_H06E0303 S3_V06N0303 arc: JA3 N1_V02S0501 arc: N3_V06N0303 JF5 enum: CIB.JB3MUX 0 .tile CIB_R46C25:CIB_DSP arc: E3_H06E0203 W3_H06E0203 .tile CIB_R46C31:CIB_DSP arc: E3_H06E0203 W3_H06E0203 .tile CIB_R46C33:CIB_DSP arc: N3_V06N0103 S3_V06N0103 .tile CIB_R46C34:CIB_DSP arc: N3_V06N0003 S3_V06N0303 .tile CIB_R46C35:CIB_DSP arc: N3_V06N0203 S3_V06N0203 .tile CIB_R46C36:CIB_DSP arc: N3_V06N0003 S3_V06N0003 .tile CIB_R46C37:CIB_DSP arc: N3_V06N0103 S3_V06N0103 arc: N3_V06N0203 W3_H06E0203 .tile CIB_R46C38:CIB_DSP arc: N3_V06N0003 S3_V06N0303 .tile CIB_R46C41:CIB_DSP arc: N3_V06N0203 E3_H06W0203 .tile CIB_R46C43:CIB_DSP arc: N3_V06N0203 S3_V06N0203 .tile CIB_R46C47:CIB_DSP arc: W3_H06W0203 E3_H06W0203 .tile CIB_R46C53:CIB_DSP arc: W3_H06W0203 E3_H06W0103 .tile CIB_R46C59:CIB_DSP arc: W3_H06W0103 E3_H06W0003 .tile CIB_R46C65:CIB_DSP arc: W3_H06W0003 E3_H06W0003 .tile CIB_R46C71:CIB_DSP arc: W3_H06W0003 E3_H06W0303 .tile CIB_R46C77:CIB_DSP arc: W3_H06W0303 E3_H06W0303 .tile CIB_R46C7:CIB_DSP arc: E3_H06E0003 W3_H06E0303 .tile CIB_R46C83:CIB_DSP arc: W3_H06W0303 E3_H06W0303 .tile CIB_R46C89:CIB_LR_S arc: N3_V06N0303 JF5 arc: W3_H06W0303 JQ5 .tile CIB_R47C1:CIB_LR arc: E3_H06E0303 JQ5 arc: JA0 H02W0701 arc: S1_V02S0501 H02W0501 arc: S1_V02S0701 N3_V06S0203 enum: CIB.JB0MUX 0 .tile CIB_R47C89:CIB_LR arc: JA0 H02E0701 arc: JA3 H02E0501 arc: S1_V02S0501 N1_V02S0401 enum: CIB.JB3MUX 0 enum: CIB.JB0MUX 0 .tile CIB_R49C1:CIB_LR arc: JA0 N1_V02S0701 arc: JA3 N1_V02S0501 enum: CIB.JB0MUX 0 enum: CIB.JB3MUX 0 .tile CIB_R49C89:CIB_LR arc: JA0 N1_V02S0501 arc: W3_H06W0303 JQ5 enum: CIB.JB0MUX 0 .tile CIB_R50C1:CIB_LR arc: E3_H06E0303 JQ5 arc: N3_V06N0303 JF5 arc: S1_V02S0701 E1_H02W0701 .tile CIB_R50C89:CIB_LR arc: N3_V06N0303 JQ5 arc: W3_H06W0303 JF5 .tile CIB_R52C1:CIB_LR arc: JA3 N1_V02S0701 arc: N3_V06N0303 JF5 enum: CIB.JB3MUX 0 .tile CIB_R52C89:CIB_LR arc: JA0 H02E0501 arc: W3_H06W0303 JQ5 enum: CIB.JB0MUX 0 .tile CIB_R55C89:CIB_LR arc: JA0 W1_H02E0501 enum: CIB.JB0MUX 0 .tile CIB_R58C33:CIB_EBR arc: N3_V06N0003 S3_V06N0003 .tile CIB_R58C34:CIB_EBR arc: N3_V06N0203 S3_V06N0103 .tile CIB_R58C35:CIB_EBR arc: N3_V06N0203 S3_V06N0103 .tile CIB_R58C36:CIB_EBR arc: N3_V06N0303 S3_V06N0303 .tile CIB_R58C37:CIB_EBR arc: N3_V06N0103 S3_V06N0103 .tile CIB_R58C43:CIB_EBR arc: N3_V06N0203 S3_V06N0103 .tile CIB_R5C1:CIB_PLL1 enum: CIB.JA3MUX 0 enum: CIB.JB3MUX 0 .tile CIB_R5C89:CIB_PLL1 enum: CIB.JA3MUX 0 enum: CIB.JB3MUX 0 .tile CIB_R70C10:CIB arc: E3_H06E0003 JQ0 .tile CIB_R70C11:CIB arc: JA0 N1_V02S0501 enum: CIB.JB0MUX 0 .tile CIB_R70C12:CIB arc: JA0 N1_V02S0701 enum: CIB.JB0MUX 0 .tile CIB_R70C13:CIB arc: E3_H06E0003 JQ0 .tile CIB_R70C14:CIB arc: E3_H06E0003 JQ0 .tile CIB_R70C15:CIB arc: E1_H02E0701 V06S0203 arc: E3_H06E0003 JQ0 arc: E3_H06E0103 W3_H06E0003 .tile CIB_R70C16:CIB arc: E3_H06E0103 W3_H06E0003 arc: JA0 H02E0701 enum: CIB.JB0MUX 0 .tile CIB_R70C18:CIB arc: JA0 N1_V02S0501 enum: CIB.JB0MUX 0 .tile CIB_R70C19:CIB arc: E3_H06E0003 W3_H06E0003 .tile CIB_R70C20:CIB arc: E3_H06E0003 W3_H06E0003 .tile CIB_R70C21:CIB arc: E3_H06E0103 W3_H06E0003 arc: E3_H06E0203 W3_H06E0103 .tile CIB_R70C22:CIB arc: E3_H06E0103 W3_H06E0103 .tile CIB_R70C25:CIB arc: E3_H06E0003 W3_H06E0003 .tile CIB_R70C26:CIB arc: E3_H06E0103 W3_H06E0003 .tile CIB_R70C27:CIB arc: E3_H06E0203 W3_H06E0103 arc: E3_H06E0303 W3_H06E0203 .tile CIB_R70C28:CIB arc: E3_H06E0103 W3_H06E0103 .tile CIB_R70C31:CIB arc: E3_H06E0003 W3_H06E0003 .tile CIB_R70C32:CIB arc: E3_H06E0103 W3_H06E0103 .tile CIB_R70C33:CIB arc: E3_H06E0303 W3_H06E0203 arc: N3_V06N0303 W3_H06E0303 .tile CIB_R70C34:CIB arc: N3_V06N0103 W3_H06E0103 .tile CIB_R70C35:CIB arc: N3_V06N0103 H06E0103 .tile CIB_R70C36:CIB arc: N3_V06N0303 H06E0303 .tile CIB_R70C37:CIB arc: E3_H06E0103 W3_H06E0003 arc: N3_V06N0003 W3_H06E0003 .tile CIB_R70C3:CIB_PLL3 enum: CIB.JA3MUX 0 enum: CIB.JB3MUX 0 .tile CIB_R70C42:VCIB_DCU0 enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C43:VCIB_DCUA arc: N3_V06N0103 W3_H06E0103 enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C44:VCIB_DCUB enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C45:VCIB_DCUC enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C46:VCIB_DCUD enum: CIB.JA1MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C47:VCIB_DCUF enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C48:VCIB_DCU3 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C49:VCIB_DCU2 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C50:VCIB_DCUG enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C51:VCIB_DCUH enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C52:VCIB_DCUI enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C53:VCIB_DCU1 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 .tile CIB_R70C69:VCIB_DCU0 enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C6:CIB_EFB0 enum: CIB.JB3MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C70:VCIB_DCUA enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C71:VCIB_DCUB enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C72:VCIB_DCUC enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C73:VCIB_DCUD enum: CIB.JA1MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C74:VCIB_DCUF enum: CIB.JA1MUX 0 enum: CIB.JA3MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC2MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C75:VCIB_DCU3 enum: CIB.JA5MUX 0 enum: CIB.JA7MUX 0 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JC0MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC6MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C76:VCIB_DCU2 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C77:VCIB_DCUG enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C78:VCIB_DCUH enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C79:VCIB_DCUI enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB7MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD6MUX 0 .tile CIB_R70C7:CIB_EFB1 enum: CIB.JA3MUX 0 enum: CIB.JA4MUX 0 enum: CIB.JA5MUX 0 enum: CIB.JA6MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB4MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JB6MUX 0 enum: CIB.JC3MUX 0 enum: CIB.JC4MUX 0 enum: CIB.JC5MUX 0 enum: CIB.JD3MUX 0 enum: CIB.JD4MUX 0 enum: CIB.JD5MUX 0 .tile CIB_R70C80:VCIB_DCU1 enum: CIB.JB1MUX 0 enum: CIB.JB3MUX 0 enum: CIB.JB5MUX 0 enum: CIB.JD0MUX 0 enum: CIB.JD2MUX 0 .tile CIB_R70C87:CIB_PLL3 enum: CIB.JA3MUX 0 enum: CIB.JB3MUX 0 .tile CIB_R70C9:CIB arc: E3_H06E0003 JQ0 .tile MIB_R0C18:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C19:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C20:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C21:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C22:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C23:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C24:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C25:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C27:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C28:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C29:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C30:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C31:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C32:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C33:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C34:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C36:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C37:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C38:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C39:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C3:BANKREF0 enum: BANK.VCCIO 3V3 .tile MIB_R0C40:TMID_0 arc: G_TDCC0CLKI G_JTRQPCLKCIB1 .tile MIB_R0C42:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C43:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C44:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C45:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C47:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C48:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C49:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C50:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C51:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C52:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C53:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C54:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C56:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C57:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C58:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C59:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C60:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C61:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C62:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C63:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C65:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C66:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C67:PIOT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C68:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C69:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C70:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C71:PIOT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R0C72:PIOT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R0C75:PIOT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R0C87:BANKREF1 enum: BANK.VCCIO 3V3 .tile MIB_R10C0:BANKREF7 enum: BANK.VCCIO 3V3 .tile MIB_R10C30:EBR_SPINE_UL0 arc: G_VPTX0000 G_HPRX0000 .tile MIB_R10C40:CMUX_UL_0 arc: G_DCS0CLK0 G_VPFN0000 arc: G_ULPCLK0 G_VPFS0000 .tile MIB_R10C41:CMUX_UR_0 arc: G_DCS0CLK1 G_VPFN0000 arc: G_URPCLK0 G_VPFS0000 .tile MIB_R10C50:EBR_SPINE_UR0 arc: G_VPTX0000 G_HPRX0000 .tile MIB_R10C90:BANKREF2 enum: BANK.VCCIO 3V3 .tile MIB_R17C90:PICR0_DQS2 arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R18C90:PICR1_DQS3 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R1C18:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C19:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C20:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C21:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C22:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C23:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C24:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C25:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C27:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C28:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C29:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C30:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C31:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C32:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C33:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C34:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C36:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C37:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C38:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C39:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C42:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C43:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C44:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C45:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C47:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C48:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C49:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C50:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C51:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C52:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C53:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C54:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C56:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C57:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C58:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C59:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C60:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C61:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C62:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C63:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C65:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C66:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C67:PICT0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C68:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C69:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C70:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R1C71:PICT0 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C72:PICT1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R1C75:PICT1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R20C0:PICL0 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R20C90:PICR0 arc: JDIA JPADDIA_PIO arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R21C0:PICL1 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON .tile MIB_R21C90:PICR1 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON .tile MIB_R22C0:MIB_CIB_LR enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R22C90:MIB_CIB_LR_A enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R23C0:PICL0 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R23C90:PICR0 arc: JDIA JPADDIA_PIO arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R24C0:PICL1 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON .tile MIB_R24C90:PICR1 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R25C0:PICL2 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R25C90:PICR2 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R26C0:PICL0 arc: JDIA JPADDIA_PIO arc: JDIB JPADDIB_PIO enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R26C90:PICR0 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R27C0:PICL1_DQS0 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R27C90:PICR1_DQS0 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R28C0:PICL2_DQS1 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R28C90:PICR2_DQS1 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R29C0:PICL0_DQS2 arc: JDIA JPADDIA_PIO arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R29C90:PICR0_DQS2 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R30C0:PICL1_DQS3 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R30C90:PICR1_DQS3 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R31C0:PICL2 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R31C90:PICR2 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R32C0:PICL0 arc: JDIA JPADDIA_PIO enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R32C90:PICR0 arc: JDIA JPADDIA_PIO enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R33C0:PICL1 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R33C90:PICR1 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R34C0:MIB_CIB_LR enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R34C90:MIB_CIB_LR_A enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R35C0:PICL0 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R35C90:PICR0 arc: JDIA JPADDIA_PIO arc: JDIB JPADDIB_PIO enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R36C0:PICL1 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R36C90:PICR1 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R37C0:PICL2 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R37C90:PICR2 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R38C0:PICL0 arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R38C90:PICR0 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R39C0:PICL1_DQS0 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R39C90:PICR1_DQS0 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R40C0:PICL2_DQS1 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R40C90:PICR2_DQS1 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R41C0:PICL0_DQS2 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R41C90:PICR0_DQS2 arc: JDIA JPADDIA_PIO arc: JDIB JPADDIB_PIO enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R42C0:PICL1_DQS3 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R42C90:PICR1_DQS3 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R43C0:PICL2 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R43C90:PICR2 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R44C0:PICL0 arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R44C90:PICR0 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R45C0:PICL1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R45C90:PICR1 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R46C0:MIB_CIB_LR enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R46C90:MIB_CIB_LR_A enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R47C0:PICL0 arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R47C90:PICR0 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R48C0:PICL1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R48C90:PICR1 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R49C0:PICL2 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R49C90:PICR2 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R50C0:PICL0 arc: JDIA JPADDIA_PIO arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R50C90:PICR0 arc: JDIA JPADDIA_PIO arc: JDIB JPADDIB_PIO enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 .tile MIB_R51C0:PICL1_DQS0 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R51C90:PICR1_DQS0 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.HYSTERESIS ON enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R52C0:PICL2_DQS1 enum: PIOC.BASE_TYPE INPUT_LVCMOS33 enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R52C90:PICR2_DQS1 enum: PIOD.BASE_TYPE INPUT_LVCMOS33 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R54C90:PICR1_DQS3 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R55C90:PICR2 enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R58C30:EBR_SPINE_LL0 arc: G_VPTX0000 G_HPRX0000 .tile MIB_R58C40:CMUX_LL_0 arc: G_DCS1CLK0 G_VPFN0000 arc: G_LLPCLK0 G_VPFS0000 .tile MIB_R58C41:CMUX_LR_0 arc: G_DCS1CLK1 G_VPFN0000 arc: G_LRPCLK0 G_VPFS0000 .tile MIB_R58C50:EBR_SPINE_LR0 arc: G_VPTX0000 G_HPRX0000 .tile MIB_R71C10:PICB1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R71C11:PICB0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R71C12:PICB1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R71C13:PICB0 arc: JDIA JPADDIA_PIO enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R71C14:PICB1 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.BASE_TYPE INPUT_LVCMOS33 enum: PIOB.HYSTERESIS ON .tile MIB_R71C15:PICB0 arc: JDIA JPADDIA_PIO enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile MIB_R71C16:PICB1 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R71C18:SPICB0 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 .tile MIB_R71C1:BANKREF6 enum: BANK.VCCIO 3V3 .tile MIB_R71C3:BANKREF8 enum: BANK.VCCIO 3V3 .tile MIB_R71C4:EFB0_PICB0 unknown: F54B1 unknown: F56B1 unknown: F82B1 unknown: F94B1 .tile MIB_R71C89:BANKREF3 enum: BANK.VCCIO 3V3 .tile MIB_R71C9:PICB0 arc: JDIA JPADDIA_PIO enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.BASE_TYPE INPUT_LVCMOS33 enum: PIOA.HYSTERESIS ON .tile R11C35:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R11C67:PLC2 arc: N1_V02N0501 S3_V06N0303 .tile R12C24:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R13C30:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R13C34:PLC2 arc: E3_H06E0103 N3_V06S0103 arc: S3_V06S0003 N3_V06S0303 .tile R13C35:PLC2 arc: S3_V06S0303 N3_V06S0203 .tile R13C36:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0203 N3_V06S0203 .tile R13C37:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0103 H06E0103 arc: S3_V06S0203 N3_V06S0103 arc: S3_V06S0303 N3_V06S0203 .tile R13C38:PLC2 arc: S3_V06S0003 N3_V06S0303 arc: S3_V06S0103 N3_V06S0003 .tile R13C39:PLC2 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0203 N3_V06S0203 .tile R13C40:PLC2 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0203 N3_V06S0103 arc: S3_V06S0303 N3_V06S0303 .tile R13C41:PLC2 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0203 N3_V06S0203 arc: S3_V06S0303 N3_V06S0303 .tile R13C42:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0203 N3_V06S0203 arc: S3_V06S0303 N3_V06S0303 .tile R13C43:PLC2 arc: S3_V06S0003 N3_V06S0003 .tile R13C44:PLC2 arc: S3_V06S0203 N3_V06S0203 arc: S3_V06S0303 N3_V06S0303 .tile R13C45:PLC2 arc: S3_V06S0103 N3_V06S0003 .tile R13C46:PLC2 arc: S3_V06S0203 N3_V06S0203 .tile R13C67:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R14C31:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R14C42:PLC2 arc: N3_V06N0103 S3_V06N0003 arc: S3_V06S0003 N3_V06S0303 .tile R14C43:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R14C54:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R14C61:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R14C73:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R15C15:PLC2 word: SLICEA.K0.INIT 1111111111111111 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 enum: SLICEA.B0MUX 1 enum: SLICEA.C0MUX 1 enum: SLICEA.D0MUX 1 .tile R15C17:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R15C19:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R15C23:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R15C37:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R15C39:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R15C41:PLC2 arc: S3_V06S0103 N3_V06S0103 .tile R15C42:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0203 N3_V06S0103 .tile R15C52:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R15C57:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R15C61:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R15C67:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R16C49:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R17C35:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R17C41:PLC2 arc: S3_V06S0103 E3_H06W0103 .tile R17C47:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R17C53:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R17C59:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R17C65:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R17C67:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R17C71:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R17C77:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R17C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R18C24:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R19C30:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R19C34:PLC2 arc: S3_V06S0103 N3_V06S0003 .tile R19C35:PLC2 arc: S3_V06S0003 N3_V06S0303 .tile R19C36:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0203 N3_V06S0203 .tile R19C37:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0203 N3_V06S0103 arc: S3_V06S0303 N3_V06S0203 arc: V01S0100 N3_V06S0303 .tile R19C38:PLC2 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0203 N3_V06S0103 .tile R19C39:PLC2 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0203 N3_V06S0203 .tile R19C40:PLC2 arc: S3_V06S0003 N3_V06S0303 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0303 N3_V06S0203 .tile R19C41:PLC2 arc: S3_V06S0003 N3_V06S0303 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0303 N3_V06S0203 .tile R19C42:PLC2 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0203 N3_V06S0203 arc: S3_V06S0303 N3_V06S0303 .tile R19C43:PLC2 arc: S3_V06S0003 N3_V06S0003 .tile R19C44:PLC2 arc: S3_V06S0203 N3_V06S0203 arc: S3_V06S0303 N3_V06S0303 .tile R19C45:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R19C46:PLC2 arc: S3_V06S0303 N3_V06S0203 .tile R19C67:PLC2 arc: N3_V06N0003 S3_V06N0003 .tile R20C31:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R20C37:PLC2 arc: E3_H06E0103 S3_V06N0103 arc: S3_V06S0103 N1_V01S0100 .tile R20C3:PLC2 arc: W1_H02W0701 V02N0701 .tile R20C42:PLC2 arc: N3_V06N0003 S3_V06N0003 arc: S3_V06S0103 N3_V06S0003 .tile R20C43:PLC2 arc: N3_V06N0103 W3_H06E0103 .tile R20C44:PLC2 arc: S3_V06S0303 H06W0303 .tile R20C47:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R20C53:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R20C54:PLC2 arc: N3_V06N0003 S3_V06N0303 .tile R20C59:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R20C61:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R20C65:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R20C71:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R20C73:PLC2 arc: N3_V06N0303 S3_V06N0203 .tile R20C77:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R20C83:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R21C17:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R21C19:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R21C23:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R21C37:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R21C39:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R21C3:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R21C41:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R21C42:PLC2 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0303 N3_V06S0203 .tile R21C52:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R21C57:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R21C61:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R21C67:PLC2 arc: N3_V06N0003 S3_V06N0003 .tile R23C35:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R23C3:PLC2 arc: W1_H02W0501 S1_V02N0501 .tile R23C41:PLC2 arc: S1_V02S0201 N3_V06S0103 .tile R23C44:PLC2 arc: S3_V06S0303 H06W0303 .tile R23C47:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R23C53:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R23C59:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R23C65:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R23C67:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R23C69:PLC2 word: SLICEA.K0.INIT 0000000000000000 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 enum: SLICEA.B0MUX 1 enum: SLICEA.C0MUX 1 enum: SLICEA.D0MUX 1 .tile R23C71:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R23C77:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R23C83:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R24C24:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R25C13:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R25C19:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R25C25:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R25C30:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R25C31:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R25C34:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R25C35:PLC2 arc: S3_V06S0003 N3_V06S0003 .tile R25C36:PLC2 arc: S1_V02S0101 N3_V06S0103 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0203 N3_V06S0203 .tile R25C37:PLC2 arc: S1_V02S0401 N3_V06S0203 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0103 W3_H06E0103 arc: S3_V06S0203 H06W0203 arc: S3_V06S0303 N3_V06S0303 .tile R25C38:PLC2 arc: S1_V02S0201 N3_V06S0103 arc: S3_V06S0203 H06W0203 arc: S3_V06S0303 N3_V06S0203 .tile R25C39:PLC2 arc: E3_H06E0103 N3_V06S0103 arc: S1_V02S0101 N3_V06S0103 arc: S1_V02S0701 N3_V06S0203 .tile R25C3:PLC2 arc: N1_V02N0501 S3_V06N0303 .tile R25C40:PLC2 arc: S1_V02S0201 E1_H01W0000 arc: S3_V06S0103 N3_V06S0003 arc: V00B0100 V02N0301 arc: V01S0000 N3_V06S0103 arc: V01S0100 N3_V06S0303 arc: CLK0 G_HPBX0000 arc: E1_H02E0401 Q4 arc: M4 V00B0100 arc: MUXCLK2 CLK0 arc: S3_V06S0203 Q4 arc: W3_H06W0203 Q4 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R25C41:PLC2 arc: E1_H02E0201 V06S0103 arc: H00L0000 V02N0001 arc: H00L0100 V02N0101 arc: S1_V02S0301 N1_V02S0201 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0103 E3_H06W0103 arc: S3_V06S0203 N3_V06S0103 arc: S3_V06S0303 N3_V06S0303 arc: W3_H06W0203 E1_H01W0000 arc: A7 E1_H02W0701 arc: B7 V02N0501 arc: C7 H02E0401 arc: D7 V01N0001 arc: F0 F5A_SLICE arc: F1 FXA_SLICE arc: F2 F5B_SLICE arc: F3 FXB_SLICE arc: F4 F5C_SLICE arc: F5 FXC_SLICE arc: F6 F5D_SLICE arc: H01W0000 F3 arc: M0 E1_H02W0601 arc: M1 H00L0000 arc: M2 E1_H02W0601 arc: M3 H00L0100 arc: M4 E1_H02W0401 arc: M5 H00L0000 arc: M6 E1_H02W0401 word: SLICEA.K0.INIT 0000000000000000 word: SLICEA.K1.INIT 0000000000000000 word: SLICEB.K0.INIT 0000000000000000 word: SLICEB.K1.INIT 0000000000000000 word: SLICEC.K0.INIT 0000000000000000 word: SLICEC.K1.INIT 0000000000000000 word: SLICED.K0.INIT 0000000000000000 word: SLICED.K1.INIT 1000010000100001 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 enum: SLICEA.B0MUX 1 enum: SLICEA.C0MUX 1 enum: SLICEA.D0MUX 1 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 enum: SLICEA.B1MUX 1 enum: SLICEA.C1MUX 1 enum: SLICEA.D1MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.A0MUX 1 enum: SLICEB.B0MUX 1 enum: SLICEB.C0MUX 1 enum: SLICEB.D0MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICEB.B1MUX 1 enum: SLICEB.C1MUX 1 enum: SLICEB.D1MUX 1 enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.A0MUX 1 enum: SLICEC.B0MUX 1 enum: SLICEC.C0MUX 1 enum: SLICEC.D0MUX 1 enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.A1MUX 1 enum: SLICEC.B1MUX 1 enum: SLICEC.C1MUX 1 enum: SLICEC.D1MUX 1 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.A0MUX 1 enum: SLICED.B0MUX 1 enum: SLICED.C0MUX 1 enum: SLICED.D0MUX 1 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_1 _NONE_ .tile R25C42:PLC2 arc: E3_H06E0003 S3_V06N0003 arc: S3_V06S0103 H06E0103 arc: S3_V06S0203 N3_V06S0203 arc: S3_V06S0303 N3_V06S0303 arc: V01S0000 N3_V06S0103 arc: B3 H02W0301 arc: CLK0 G_HPBX0000 arc: D3 V00T0100 arc: E1_H01E0001 F3 arc: F3 F3_SLICE arc: H01W0000 Q3 arc: M3 H02E0201 arc: MUXCLK1 CLK0 arc: S3_V06S0003 Q3 arc: V00T0100 Q3 word: SLICEB.K1.INIT 1100110000110011 enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICEB.C1MUX 1 .tile R25C43:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: W1_H02W0301 N3_V06S0003 arc: W1_H02W0401 H01E0001 arc: W1_H02W0601 H01E0001 arc: W1_H02W0701 V06S0203 .tile R25C44:PLC2 arc: S1_V02S0401 N3_V06S0203 arc: S1_V02S0601 N3_V06S0303 .tile R25C45:PLC2 arc: S3_V06S0303 N3_V06S0203 .tile R25C46:PLC2 arc: S3_V06S0303 N3_V06S0303 .tile R25C47:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R25C48:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R25C53:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R25C54:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R25C59:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R25C60:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R25C65:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R25C66:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R25C67:PLC2 arc: N3_V06N0003 S1_V02N0001 .tile R25C71:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R25C72:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R25C77:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R25C78:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R25C7:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R25C83:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R25C84:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R25C87:PLC2 arc: S3_V06S0203 H06E0203 .tile R26C10:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R26C13:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R26C14:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R26C16:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R26C19:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R26C20:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R26C22:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R26C25:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R26C26:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R26C28:PLC2 arc: S3_V06S0103 E3_H06W0103 arc: W3_H06W0303 S3_V06N0303 .tile R26C2:PLC2 arc: E3_H06E0303 H01E0101 .tile R26C31:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: N3_V06N0003 S3_V06N0303 .tile R26C32:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R26C34:PLC2 arc: S3_V06S0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0003 .tile R26C37:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: H00R0000 S1_V02N0601 arc: S1_V02S0001 H06W0003 arc: S1_V02S0201 N3_V06S0103 arc: S1_V02S0601 E1_H02W0601 arc: S3_V06S0003 H06W0003 arc: S3_V06S0103 W3_H06E0103 arc: S3_V06S0203 H06W0203 arc: S3_V06S0303 H06W0303 arc: V00T0000 V02N0601 arc: A2 E1_H02W0701 arc: A7 H00L0000 arc: C2 E1_H02W0601 arc: C7 E1_H02W0601 arc: CLK0 G_HPBX0000 arc: D2 V00B0100 arc: D7 E1_H02W0001 arc: E3_H06E0203 F7 arc: F2 F2_SLICE arc: F7 F7_SLICE arc: H00L0000 Q2 arc: M2 V00T0000 arc: M5 H00R0000 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: N3_V06N0103 F2 arc: V00B0100 Q5 word: SLICEB.K0.INIT 1111101000001010 word: SLICED.K1.INIT 1010111110100000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.B0MUX 1 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_1 _NONE_ enum: SLICED.B1MUX 1 .tile R26C38:PLC2 arc: E1_H02E0701 W3_H06E0203 arc: S3_V06S0203 H06W0203 .tile R26C39:PLC2 arc: W1_H02W0001 S1_V02N0001 arc: W1_H02W0601 E1_H01W0000 arc: W1_H02W0701 S1_V02N0701 .tile R26C40:PLC2 arc: E1_H02E0201 N1_V01S0000 arc: E1_H02E0601 N1_V01S0000 arc: E1_H02E0701 W1_H02E0701 arc: N1_V02N0301 N1_V01S0100 arc: S1_V02S0201 H06E0103 arc: S3_V06S0203 N1_V01S0000 arc: W3_H06W0203 E1_H01W0000 arc: W3_H06W0303 E1_H01W0100 arc: A0 V01N0101 arc: B0 S1_V02N0301 arc: C0 H02W0601 arc: CLK0 G_HPBX0000 arc: D0 V02S0201 arc: E1_H02E0001 Q0 arc: E3_H06E0003 Q0 arc: F0 F0_SLICE arc: H01W0000 Q0 arc: MUXCLK0 CLK0 arc: S3_V06S0003 Q0 arc: W3_H06W0003 Q0 word: SLICEA.K0.INIT 0100000000000000 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 1 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R26C41:PLC2 arc: H00L0000 H02E0201 arc: H00L0100 V02S0301 arc: H00R0100 H02E0701 arc: N1_V02N0501 E1_H02W0501 arc: S1_V02S0201 E3_H06W0103 arc: W3_H06W0203 E3_H06W0103 arc: A6 H00L0000 arc: B1 V02N0101 arc: B6 E1_H02W0101 arc: C0 H02E0601 arc: C6 V02N0001 arc: CLK0 G_HPBX0000 arc: D0 H00R0000 arc: D1 V00B0100 arc: D6 V00B0000 arc: F0 F0_SLICE arc: F1 F1_SLICE arc: F6 F6_SLICE arc: H00R0000 Q4 arc: H01W0000 Q4 arc: H01W0100 Q7 arc: M1 H00R0100 arc: M4 H02W0401 arc: M7 H00L0100 arc: MUXCLK0 CLK0 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: N1_V01N0001 Q1 arc: N1_V02N0001 F0 arc: N1_V02N0101 F1 arc: S3_V06S0103 Q1 arc: S3_V06S0203 Q4 arc: V00B0000 Q4 arc: V00B0100 Q7 arc: V01S0000 Q7 arc: V01S0100 Q7 arc: W1_H02W0601 F6 word: SLICED.K0.INIT 1100111101000101 word: SLICEA.K1.INIT 0000000011001100 word: SLICEA.K0.INIT 0000111100000000 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 enum: SLICEA.C1MUX 1 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 enum: SLICEA.B0MUX 1 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R26C42:PLC2 arc: S1_V02S0601 W1_H02E0601 arc: S3_V06S0103 N3_V06S0103 arc: V00T0000 W1_H02E0001 arc: W1_H02W0401 N1_V01S0000 arc: A3 V00T0000 arc: A6 H02W0701 arc: C3 H02W0401 arc: C6 V02N0201 arc: CLK0 G_HPBX0000 arc: D3 V01S0100 arc: D6 W1_H02E0001 arc: E3_H06E0303 F6 arc: F3 F3_SLICE arc: F6 F6_SLICE arc: M2 V00B0000 arc: M6 E1_H02W0401 arc: MUXCLK1 CLK0 arc: MUXCLK3 CLK0 arc: N3_V06N0003 F3 arc: S3_V06S0303 Q6 arc: V00B0000 Q6 arc: V01S0100 Q2 word: SLICED.K0.INIT 1111000010101010 word: SLICEB.K1.INIT 1111101001010000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.B0MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.B1MUX 1 .tile R26C43:PLC2 arc: E3_H06E0303 W3_H06E0203 arc: S3_V06S0003 H06E0003 arc: S3_V06S0103 W3_H06E0103 arc: W1_H02W0101 W3_H06E0103 arc: W1_H02W0401 S3_V06N0203 arc: W1_H02W0501 S1_V02N0501 arc: W1_H02W0701 S1_V02N0701 .tile R26C44:PLC2 arc: S3_V06S0003 N3_V06S0303 arc: W1_H02W0401 V02S0401 .tile R26C46:PLC2 arc: S3_V06S0003 W3_H06E0003 .tile R26C47:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R26C48:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R26C49:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R26C4:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R26C53:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R26C54:PLC2 arc: N3_V06N0303 W3_H06E0303 .tile R26C55:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R26C59:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R26C61:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: N3_V06N0303 S3_V06N0203 .tile R26C65:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R26C67:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R26C71:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R26C73:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: N3_V06N0203 S3_V06N0103 .tile R26C77:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R26C79:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R26C7:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R26C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R26C85:PLC2 arc: E1_H02E0701 W3_H06E0203 .tile R26C87:PLC2 arc: E1_H02E0501 V02N0501 arc: E1_H02E0701 W1_H02E0701 .tile R26C8:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R27C17:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R27C19:PLC2 arc: N3_V06N0003 S3_V06N0003 .tile R27C23:PLC2 arc: N3_V06N0003 S3_V06N0003 .tile R27C36:PLC2 arc: S1_V02S0401 N1_V02S0101 .tile R27C37:PLC2 arc: N1_V02N0601 S3_V06N0303 arc: N3_V06N0003 S3_V06N0003 arc: S3_V06S0303 H06W0303 arc: V00T0000 N1_V02S0401 arc: B6 V00B0000 arc: C6 E1_H02W0601 arc: CLK0 G_HPBX0000 arc: D6 V02S0601 arc: E1_H01E0101 Q0 arc: E3_H06E0303 F6 arc: F6 F6_SLICE arc: M0 V00T0000 arc: M3 H02W0201 arc: M4 E1_H01E0101 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: S3_V06S0003 Q0 arc: V00B0000 Q4 arc: V01S0000 Q3 word: SLICED.K0.INIT 1100110011110000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.A0MUX 1 .tile R27C38:PLC2 arc: W1_H02W0201 N1_V02S0201 .tile R27C39:PLC2 arc: E1_H02E0101 N1_V02S0101 arc: N3_V06N0303 S3_V06N0303 arc: S1_V02S0701 N1_V02S0701 arc: W1_H02W0601 V02N0601 .tile R27C3:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R27C40:PLC2 arc: V00B0000 V02S0201 arc: W3_H06W0303 E1_H01W0100 arc: C3 E1_H01W0000 arc: C6 Q6 arc: CLK0 G_HPBX0000 arc: D3 H02W0201 arc: D6 V00B0000 arc: E1_H01E0001 Q6 arc: F3 F3_SLICE arc: F6 F6_SLICE arc: M6 H02W0401 arc: MUXCLK3 CLK0 arc: N1_V01N0101 F3 arc: S1_V02S0601 F6 arc: S3_V06S0303 Q6 word: SLICED.K0.INIT 0000111100000000 word: SLICEB.K1.INIT 0000111100000000 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.A0MUX 1 enum: SLICED.B0MUX 1 enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICEB.B1MUX 1 .tile R27C41:PLC2 arc: N1_V02N0001 H01E0001 arc: N1_V02N0101 W1_H02E0101 arc: S3_V06S0203 N1_V01S0000 arc: S3_V06S0303 N3_V06S0203 arc: W1_H02W0201 V02S0201 arc: W1_H02W0401 S1_V02N0401 arc: A6 N1_V01S0100 arc: B6 W1_H02E0101 arc: C6 V02S0201 arc: CLK0 G_HPBX0000 arc: D6 H01W0000 arc: F6 F6_SLICE arc: H01W0000 Q2 arc: H01W0100 Q2 arc: M2 E1_H02W0601 arc: MUXCLK1 CLK0 arc: S3_V06S0103 Q2 arc: V01S0000 F6 word: SLICED.K0.INIT 1101000011011101 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R27C42:PLC2 arc: H00R0100 V02N0701 arc: S3_V06S0203 N3_V06S0103 arc: V01S0100 N3_V06S0303 arc: CLK0 G_HPBX0000 arc: M0 V00B0100 arc: M7 H00R0100 arc: MUXCLK0 CLK0 arc: MUXCLK3 CLK0 arc: N1_V02N0201 Q0 arc: V00B0100 Q7 arc: V01S0000 Q7 enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R27C43:PLC2 arc: E3_H06E0303 W3_H06E0303 arc: W1_H02W0601 V02N0601 .tile R27C44:PLC2 arc: S1_V02S0701 N1_V02S0601 .tile R27C45:PLC2 arc: E3_H06E0103 S3_V06N0103 .tile R27C49:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R27C51:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R27C52:PLC2 arc: N3_V06N0003 S3_V06N0003 .tile R27C55:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R27C57:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: N3_V06N0003 S3_V06N0303 .tile R27C61:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: N3_V06N0303 S3_V06N0203 .tile R27C63:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R27C67:PLC2 arc: N1_V02N0001 W3_H06E0003 arc: N3_V06N0003 S3_V06N0303 .tile R27C69:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R27C75:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R27C81:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R27C87:PLC2 arc: N1_V02N0501 W3_H06E0303 .tile R28C13:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R28C19:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R28C25:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R28C31:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R28C37:PLC2 arc: E1_H02E0201 V06S0103 arc: E3_H06E0303 W3_H06E0203 arc: H00L0000 N1_V02S0201 arc: N1_V02N0601 N1_V01S0000 arc: S1_V02S0701 N1_V02S0601 arc: S3_V06S0003 N1_V01S0000 arc: S3_V06S0203 N3_V06S0103 arc: S3_V06S0303 N1_V02S0601 arc: V01S0100 S3_V06N0303 arc: B5 S1_V02N0501 arc: C5 N1_V02S0001 arc: CLK0 G_HPBX0000 arc: D5 H01W0000 arc: E1_H01E0101 Q7 arc: F5 F5_SLICE arc: H00R0100 Q7 arc: H01W0000 Q5 arc: M5 H00R0100 arc: M7 H00L0000 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: N3_V06N0303 F5 word: SLICEC.K1.INIT 1111110000001100 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.A1MUX 1 .tile R28C38:PLC2 arc: S3_V06S0103 H01E0101 .tile R28C39:PLC2 arc: E1_H02E0201 W1_H02E0201 arc: N1_V02N0001 S3_V06N0003 arc: N1_V02N0601 S3_V06N0303 arc: N1_V02N0701 S3_V06N0203 .tile R28C40:PLC2 arc: H00R0000 V02S0601 arc: V00T0100 V02N0501 arc: A3 H02W0701 arc: B3 H02W0301 arc: C3 H00R0100 arc: CLK0 G_HPBX0000 arc: D3 V02N0201 arc: F0 F5A_SLICE arc: F1 FXA_SLICE arc: F2 F5B_SLICE arc: F3 FXB_SLICE arc: F4 F5C_SLICE arc: F5 FXC_SLICE arc: F6 F5D_SLICE arc: H00R0100 Q7 arc: M0 V00T0100 arc: M1 H00R0000 arc: M2 V00T0100 arc: M3 H02W0201 arc: M4 V00T0100 arc: M5 H00R0000 arc: M6 V00T0100 arc: M7 H02E0201 arc: MUXCLK3 CLK0 arc: N1_V02N0301 F3 arc: S3_V06S0203 Q7 word: SLICEA.K0.INIT 0000000000000000 word: SLICEA.K1.INIT 0000000000000000 word: SLICEB.K0.INIT 0000000000000000 word: SLICEB.K1.INIT 1000010000100001 word: SLICEC.K0.INIT 0000000000000000 word: SLICEC.K1.INIT 0000000000000000 word: SLICED.K0.INIT 0000000000000000 word: SLICED.K1.INIT 0000000000000000 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 enum: SLICEA.B0MUX 1 enum: SLICEA.C0MUX 1 enum: SLICEA.D0MUX 1 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 enum: SLICEA.B1MUX 1 enum: SLICEA.C1MUX 1 enum: SLICEA.D1MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.A0MUX 1 enum: SLICEB.B0MUX 1 enum: SLICEB.C0MUX 1 enum: SLICEB.D0MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.A0MUX 1 enum: SLICEC.B0MUX 1 enum: SLICEC.C0MUX 1 enum: SLICEC.D0MUX 1 enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.A1MUX 1 enum: SLICEC.B1MUX 1 enum: SLICEC.C1MUX 1 enum: SLICEC.D1MUX 1 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.A0MUX 1 enum: SLICED.B0MUX 1 enum: SLICED.C0MUX 1 enum: SLICED.D0MUX 1 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_1 _NONE_ enum: SLICED.A1MUX 1 enum: SLICED.B1MUX 1 enum: SLICED.C1MUX 1 enum: SLICED.D1MUX 1 .tile R28C41:PLC2 arc: S1_V02S0601 E3_H06W0303 arc: S3_V06S0103 N1_V02S0201 arc: V01S0100 S3_V06N0303 arc: W1_H02W0201 N1_V01S0000 arc: W1_H02W0301 V06S0003 arc: W1_H02W0701 V06S0203 .tile R28C42:PLC2 arc: N1_V02N0701 N1_V01S0100 arc: S3_V06S0003 N1_V01S0000 arc: S3_V06S0303 N1_V02S0601 .tile R28C43:PLC2 arc: N1_V02N0501 S3_V06N0303 arc: N1_V02N0601 W3_H06E0303 arc: N1_V02N0701 S3_V06N0203 arc: S3_V06S0303 N3_V06S0203 .tile R28C47:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R28C53:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R28C59:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R28C65:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R28C71:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R28C77:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R28C7:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R28C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R28C87:PLC2 arc: E1_H02E0701 V06S0203 .tile R29C13:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: W3_H06W0103 E3_H06W0003 .tile R29C19:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: W3_H06W0003 E3_H06W0003 .tile R29C25:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: W3_H06W0003 E3_H06W0003 .tile R29C31:PLC2 arc: S1_V02S0401 W3_H06E0203 arc: W3_H06W0003 E3_H06W0003 .tile R29C35:PLC2 arc: N3_V06N0003 E3_H06W0003 .tile R29C36:PLC2 arc: E1_H02E0401 N1_V02S0401 .tile R29C37:PLC2 arc: V00B0000 H02E0401 arc: A0 V02S0701 arc: C0 N1_V01S0100 arc: CLK0 G_HPBX0000 arc: D0 H00R0000 arc: E1_H01E0101 Q2 arc: F0 F0_SLICE arc: H00R0000 Q4 arc: M2 V00B0000 arc: M4 E1_H01E0101 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: S3_V06S0103 Q2 arc: W3_H06W0003 F0 word: SLICEA.K0.INIT 1111101001010000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.B0MUX 1 .tile R29C39:PLC2 arc: E1_H02E0701 N1_V02S0701 arc: S3_V06S0203 E1_H01W0000 .tile R29C40:PLC2 arc: H00R0100 H02E0701 arc: CLK0 G_HPBX0000 arc: H01W0000 Q2 arc: M2 H02W0601 arc: M5 H00R0100 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: N1_V02N0201 Q2 arc: N1_V02N0501 Q5 arc: S3_V06S0103 Q2 arc: S3_V06S0303 Q5 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R29C41:PLC2 arc: N1_V02N0401 E3_H06W0203 arc: W1_H02W0601 V02S0601 arc: B3 E1_H01W0100 arc: C3 N1_V01S0100 arc: D3 E1_H02W0001 arc: F3 F3_SLICE arc: W3_H06W0003 F3 word: SLICEB.K1.INIT 1100110011110000 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 .tile R29C42:PLC2 arc: H00R0100 H02W0701 arc: S3_V06S0103 E1_H01W0100 arc: CLK0 G_HPBX0000 arc: H01W0100 Q3 arc: M3 H00R0100 arc: MUXCLK1 CLK0 enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R29C43:PLC2 arc: H00R0100 H02W0701 arc: W1_H02W0001 V06S0003 arc: CLK0 G_HPBX0000 arc: H01W0100 Q5 arc: M5 H00R0100 arc: MUXCLK2 CLK0 arc: W1_H02W0701 Q5 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R29C44:PLC2 arc: S3_V06S0303 N3_V06S0303 arc: W1_H02W0701 N1_V02S0701 .tile R29C47:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R29C53:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R29C59:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R29C65:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R29C67:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R29C71:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R29C77:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R29C7:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: W3_H06W0203 E3_H06W0103 .tile R29C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R2C31:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R2C42:PLC2 arc: N1_V01N0101 S3_V06N0203 .tile R2C43:PLC2 arc: N1_V01N0101 S3_V06N0203 .tile R2C54:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R2C61:PLC2 arc: N1_V02N0501 S3_V06N0303 .tile R2C73:PLC2 arc: N1_V02N0501 S3_V06N0303 .tile R30C24:PLC2 arc: N3_V06N0003 E3_H06W0003 .tile R30C30:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R30C36:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R30C37:PLC2 arc: N1_V02N0501 E1_H02W0501 .tile R30C39:PLC2 arc: W1_H02W0501 S1_V02N0501 .tile R30C42:PLC2 arc: V00T0100 V02N0701 arc: A5 V00B0000 arc: C5 S1_V02N0001 arc: CLK0 G_HPBX0000 arc: D5 S1_V02N0601 arc: F5 F5_SLICE arc: M6 V00T0100 arc: MUXCLK3 CLK0 arc: V00B0000 Q6 arc: W3_H06W0303 F5 word: SLICEC.K1.INIT 1010111110100000 enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.B1MUX 1 .tile R31C12:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R31C13:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: W3_H06W0303 E3_H06W0203 .tile R31C18:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R31C19:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: W3_H06W0203 E3_H06W0203 .tile R31C24:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R31C25:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: W3_H06W0203 E3_H06W0103 .tile R31C30:PLC2 arc: N3_V06N0303 E3_H06W0303 arc: W3_H06W0203 E3_H06W0203 .tile R31C31:PLC2 arc: E3_H06E0303 W3_H06E0203 arc: S1_V02S0401 N1_V02S0401 arc: W3_H06W0103 E3_H06W0103 .tile R31C34:PLC2 arc: E1_H02E0401 N3_V06S0203 arc: S1_V02S0401 V01N0001 arc: S1_V02S0601 H06E0303 .tile R31C35:PLC2 arc: S1_V02S0001 N3_V06S0003 arc: S1_V02S0401 H02E0401 .tile R31C36:PLC2 arc: S1_V02S0201 N3_V06S0103 arc: S3_V06S0203 N3_V06S0203 arc: V00B0000 V02N0001 arc: V00B0100 H02W0501 arc: B6 V02N0501 arc: B7 E1_H02W0101 arc: C6 E1_H02W0601 arc: C7 V02N0001 arc: CLK0 G_HPBX0000 arc: D6 V00B0000 arc: D7 V02N0601 arc: E1_H01E0101 Q4 arc: F6 F6_SLICE arc: F7 F7_SLICE arc: M4 V00B0100 arc: MUXCLK2 CLK0 arc: W3_H06W0203 F7 arc: W3_H06W0303 F6 word: SLICED.K1.INIT 1100111111000000 word: SLICED.K0.INIT 1100110011110000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_1 _NONE_ enum: SLICED.A1MUX 1 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.A0MUX 1 .tile R31C37:PLC2 arc: S1_V02S0001 N3_V06S0003 arc: S1_V02S0401 E1_H02W0401 arc: S1_V02S0601 N3_V06S0303 arc: S3_V06S0203 N3_V06S0203 arc: B1 V02N0101 arc: C1 S1_V02N0601 arc: CLK0 G_HPBX0000 arc: D1 H01E0101 arc: F1 F1_SLICE arc: M5 E1_H02W0001 arc: MUXCLK2 CLK0 arc: S1_V02S0701 Q5 arc: W1_H02W0501 Q5 arc: W3_H06W0103 F1 word: SLICEA.K1.INIT 1111110000110000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 .tile R31C38:PLC2 arc: S1_V02S0101 E1_H02W0101 arc: S3_V06S0003 N3_V06S0303 arc: S3_V06S0303 N3_V06S0203 arc: W1_H02W0101 V01N0101 arc: W1_H02W0601 V02N0601 .tile R31C39:PLC2 arc: W1_H02W0001 E1_H02W0001 arc: W1_H02W0401 E3_H06W0203 .tile R31C3:PLC2 arc: N3_V06N0303 H06W0303 arc: W1_H02W0501 S1_V02N0501 .tile R31C40:PLC2 arc: S3_V06S0303 N3_V06S0203 arc: W1_H02W0101 N3_V06S0103 .tile R31C41:PLC2 arc: E1_H02E0501 N3_V06S0303 arc: E1_H02E0601 S1_V02N0601 arc: S1_V02S0201 N3_V06S0103 arc: S3_V06S0103 E1_H01W0100 arc: S3_V06S0303 N3_V06S0203 arc: W1_H02W0001 E3_H06W0003 .tile R31C42:PLC2 arc: E1_H02E0701 N3_V06S0203 arc: H00R0100 H02E0501 arc: S1_V02S0501 N3_V06S0303 arc: S1_V02S0601 H06W0303 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0203 N3_V06S0103 arc: A0 V01N0101 arc: B0 V02N0301 arc: CLK0 G_HPBX0000 arc: D0 V02N0001 arc: F0 F0_SLICE arc: H01W0100 Q7 arc: M0 H02E0601 arc: M7 H00R0100 arc: MUXCLK0 CLK0 arc: MUXCLK3 CLK0 arc: N1_V02N0701 Q7 arc: N3_V06N0003 F0 arc: S1_V02S0201 Q0 word: SLICEA.K0.INIT 1010101011001100 enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.C0MUX 1 .tile R31C43:PLC2 arc: S1_V02S0001 N3_V06S0003 arc: S1_V02S0401 H06W0203 arc: S1_V02S0701 H02E0701 .tile R31C45:PLC2 arc: W3_H06W0203 E3_H06W0203 arc: W3_H06W0303 N3_V06S0303 .tile R31C46:PLC2 arc: S1_V02S0601 N3_V06S0303 arc: W3_H06W0203 E1_H01W0000 .tile R31C47:PLC2 arc: H01W0000 E3_H06W0103 arc: W3_H06W0003 E3_H06W0003 .tile R31C51:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R31C53:PLC2 arc: W3_H06W0003 E3_H06W0303 arc: W3_H06W0103 E3_H06W0003 .tile R31C57:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R31C59:PLC2 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0303 E3_H06W0203 .tile R31C63:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R31C65:PLC2 arc: W3_H06W0003 E3_H06W0303 arc: W3_H06W0203 E3_H06W0203 .tile R31C69:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R31C6:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R31C71:PLC2 arc: W3_H06W0203 E3_H06W0103 arc: W3_H06W0303 E3_H06W0303 .tile R31C75:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R31C77:PLC2 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0303 E3_H06W0303 .tile R31C7:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: W3_H06W0303 E3_H06W0303 .tile R31C81:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R31C83:PLC2 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0303 E3_H06W0303 .tile R31C87:PLC2 arc: W3_H06W0303 E1_H02W0601 .tile R32C10:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R32C11:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R32C13:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R32C15:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: E3_H06E0303 W3_H06E0303 .tile R32C16:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R32C17:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R32C19:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R32C21:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: E3_H06E0303 W3_H06E0303 .tile R32C22:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R32C23:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R32C25:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R32C27:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: E3_H06E0203 W3_H06E0203 .tile R32C28:PLC2 arc: S3_V06S0203 N3_V06S0103 arc: V01S0000 N3_V06S0103 arc: W3_H06W0303 E3_H06W0303 arc: B5 V01S0000 arc: C5 V01N0101 arc: D5 S1_V02N0401 arc: F5 F5_SLICE arc: N3_V06N0303 F5 word: SLICEC.K1.INIT 1111001111000000 enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.A1MUX 1 .tile R32C29:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R32C31:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: N3_V06N0303 E3_H06W0303 .tile R32C33:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0303 W3_H06E0203 .tile R32C34:PLC2 arc: E1_H02E0601 V02S0601 arc: N1_V01N0001 N3_V06S0003 arc: S1_V02S0001 N3_V06S0003 arc: S3_V06S0003 N3_V06S0003 arc: A5 E1_H02W0701 arc: B5 E1_H02W0101 arc: D5 V02S0401 arc: F5 F5_SLICE arc: W3_H06W0303 F5 word: SLICEC.K1.INIT 1010101011001100 enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.C1MUX 1 .tile R32C35:PLC2 arc: E1_H02E0001 V02S0001 arc: W3_H06W0203 E3_H06W0203 arc: CLK0 G_HPBX0000 arc: E1_H02E0201 Q0 arc: E3_H06E0003 Q0 arc: E3_H06E0203 Q7 arc: M0 H02E0601 arc: M7 E1_H02W0201 arc: MUXCLK0 CLK0 arc: MUXCLK3 CLK0 arc: S1_V02S0501 Q7 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R32C36:PLC2 arc: N1_V02N0001 H02W0001 arc: N1_V02N0501 E1_H01W0100 arc: N1_V02N0601 S1_V02N0301 arc: S1_V02S0301 H02W0301 arc: W1_H02W0101 S1_V02N0101 arc: CLK0 G_HPBX0000 arc: M1 H02E0001 arc: M7 H02E0201 arc: MUXCLK0 CLK0 arc: MUXCLK3 CLK0 arc: S3_V06S0103 Q1 arc: V01S0000 Q1 arc: W1_H02W0701 Q7 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R32C37:PLC2 arc: E1_H02E0201 N3_V06S0103 arc: H00R0000 V02S0401 arc: N1_V02N0101 H02W0101 arc: S1_V02S0001 N3_V06S0003 arc: S1_V02S0401 N3_V06S0203 arc: S1_V02S0601 N3_V06S0303 arc: S3_V06S0103 N3_V06S0003 arc: V00B0100 H02W0501 arc: V00T0100 V02N0701 arc: W1_H02W0001 N3_V06S0003 arc: W1_H02W0201 W3_H06E0103 arc: W1_H02W0301 N3_V06S0003 arc: A2 V00B0000 arc: B2 H02W0101 arc: B5 H02W0101 arc: B6 H02W0101 arc: C5 V01N0101 arc: C6 E1_H02W0601 arc: CLK0 G_HPBX0000 arc: D2 V00B0100 arc: D5 E1_H02W0001 arc: D6 V01N0001 arc: E1_H01E0101 Q2 arc: E3_H06E0103 F2 arc: E3_H06E0303 F6 arc: F2 F2_SLICE arc: F5 F5_SLICE arc: F6 F6_SLICE arc: H01W0100 Q5 arc: M1 H00R0000 arc: M2 V00T0100 arc: M5 V01S0000 arc: M6 V00T0000 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: S1_V02S0101 Q1 arc: V00B0000 Q6 arc: V00T0000 Q2 arc: V01S0000 Q1 arc: W3_H06W0303 F5 word: SLICEC.K1.INIT 1111001111000000 word: SLICEB.K0.INIT 1011101110001000 word: SLICED.K0.INIT 1111110000110000 enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.A1MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.C0MUX 1 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.A0MUX 1 .tile R32C38:PLC2 arc: N1_V02N0601 S1_V02N0301 arc: S1_V02S0201 H02E0201 arc: S1_V02S0301 H06E0003 arc: S1_V02S0401 H06E0203 arc: S1_V02S0501 H01E0101 arc: S1_V02S0601 H06W0303 arc: S1_V02S0701 N3_V06S0203 arc: V00T0000 E1_H02W0201 arc: W1_H02W0101 E1_H02W0001 arc: W1_H02W0501 S1_V02N0501 arc: CLK0 G_HPBX0000 arc: M4 V00T0000 arc: MUXCLK2 CLK0 arc: N1_V01N0101 Q4 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R32C39:PLC2 arc: E1_H01E0001 W3_H06E0003 arc: E1_H02E0501 W3_H06E0303 arc: N1_V02N0501 S1_V02N0401 arc: S1_V02S0001 H02W0001 arc: S1_V02S0101 E1_H02W0101 arc: S1_V02S0701 H02W0701 arc: W1_H02W0001 S1_V02N0001 arc: W1_H02W0601 S1_V02N0601 .tile R32C3:PLC2 arc: E3_H06E0203 W1_H02E0701 arc: E3_H06E0303 W1_H02E0501 arc: W1_H02W0501 E1_H02W0501 .tile R32C40:PLC2 arc: E1_H02E0301 N3_V06S0003 arc: E1_H02E0601 S1_V02N0601 arc: S1_V02S0301 N3_V06S0003 arc: W1_H02W0001 N3_V06S0003 arc: W1_H02W0701 N3_V06S0203 arc: CLK0 G_HPBX0000 arc: E1_H02E0201 Q0 arc: M0 H01E0001 arc: MUXCLK0 CLK0 arc: W1_H02W0201 Q0 enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R32C41:PLC2 arc: E1_H02E0101 N3_V06S0103 arc: H00R0000 H02E0601 arc: H00R0100 W1_H02E0501 arc: S1_V02S0401 N3_V06S0203 arc: S1_V02S0701 E1_H01W0100 arc: W1_H02W0101 N3_V06S0103 arc: W3_H06W0303 E3_H06W0303 arc: B4 H02E0301 arc: C4 V00B0100 arc: CLK0 G_HPBX0000 arc: D4 S1_V02N0401 arc: E1_H01E0101 Q3 arc: E1_H02E0301 Q1 arc: F4 F4_SLICE arc: M1 H00R0000 arc: M3 H00R0100 arc: M5 V01S0000 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: S1_V02S0301 Q1 arc: V00B0100 Q5 arc: V01S0000 Q3 arc: W3_H06W0203 F4 word: SLICEC.K0.INIT 1111001111000000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.A0MUX 1 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R32C42:PLC2 arc: H00L0000 V02S0201 arc: N1_V02N0001 H02W0001 arc: N1_V02N0301 S1_V02N0201 arc: N1_V02N0601 S1_V02N0601 arc: S1_V02S0001 H02W0001 arc: S1_V02S0101 H02W0101 arc: S1_V02S0201 W1_H02E0201 arc: S1_V02S0501 N3_V06S0303 arc: S1_V02S0701 H01E0101 arc: V00T0000 H02W0001 arc: V00T0100 H02E0301 arc: V01S0000 N3_V06S0103 arc: A4 S1_V02N0101 arc: C4 V00T0000 arc: CLK0 G_HPBX0000 arc: D4 V00B0000 arc: E3_H06E0203 F4 arc: F4 F4_SLICE arc: H01W0100 Q7 arc: M1 H00L0000 arc: M5 V01S0000 arc: M6 V00T0100 arc: M7 E1_H01W0000 arc: MUXCLK0 CLK0 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: N1_V01N0101 Q1 arc: V00B0000 Q6 arc: V01S0100 Q5 word: SLICEC.K0.INIT 1111101000001010 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.B0MUX 1 enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R32C43:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: E3_H06E0103 W3_H06E0103 arc: H00R0000 V02S0401 arc: N3_V06N0203 S1_V02N0401 arc: S1_V02S0101 W1_H02E0101 arc: S1_V02S0301 N3_V06S0003 arc: S3_V06S0103 N3_V06S0003 arc: V00B0000 H02W0601 arc: V00T0100 H02W0301 arc: W1_H02W0001 N3_V06S0003 arc: W1_H02W0101 N3_V06S0103 arc: CLK0 G_HPBX0000 arc: H01W0000 Q1 arc: M0 V00T0100 arc: M1 H00R0000 arc: M6 V00B0000 arc: MUXCLK0 CLK0 arc: MUXCLK3 CLK0 arc: S1_V02S0201 Q0 arc: S1_V02S0401 Q6 arc: V01S0000 Q1 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R32C44:PLC2 arc: W1_H02W0301 N3_V06S0003 arc: W1_H02W0601 V06S0303 .tile R32C46:PLC2 arc: S1_V02S0301 N3_V06S0003 arc: S3_V06S0003 N3_V06S0003 .tile R32C47:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R32C48:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R32C49:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0103 W3_H06E0103 .tile R32C4:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R32C53:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R32C54:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R32C55:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: E3_H06E0203 W3_H06E0103 .tile R32C59:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R32C5:PLC2 arc: W1_H02W0501 E3_H06W0303 .tile R32C60:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R32C61:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: N3_V06N0203 W3_H06E0203 .tile R32C65:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R32C66:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R32C67:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R32C71:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R32C72:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R32C73:PLC2 arc: N3_V06N0103 W3_H06E0103 .tile R32C77:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R32C78:PLC2 arc: E1_H01E0101 W3_H06E0203 .tile R32C79:PLC2 arc: E3_H06E0303 H01E0101 .tile R32C7:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R32C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R32C85:PLC2 arc: E1_H02E0501 W3_H06E0303 .tile R32C87:PLC2 arc: E1_H02E0501 W1_H02E0501 .tile R32C9:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: E3_H06E0303 W3_H06E0203 .tile R33C12:PLC2 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0303 E3_H06W0303 .tile R33C13:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R33C17:PLC2 arc: N3_V06N0303 E3_H06W0303 .tile R33C18:PLC2 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0303 E3_H06W0203 .tile R33C19:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: N3_V06N0003 E3_H06W0003 .tile R33C23:PLC2 arc: N3_V06N0003 E3_H06W0003 arc: W3_H06W0303 E3_H06W0303 .tile R33C24:PLC2 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0203 E3_H06W0103 .tile R33C25:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: W3_H06W0003 E3_H06W0003 .tile R33C28:PLC2 arc: H00L0100 E1_H02W0101 arc: CLK0 G_HPBX0000 arc: M1 H00L0100 arc: MUXCLK0 CLK0 arc: N1_V01N0101 Q1 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R33C29:PLC2 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0303 E3_H06W0203 .tile R33C30:PLC2 arc: H00R0000 H02W0401 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0103 arc: CLK0 G_HPBX0000 arc: E3_H06E0103 Q1 arc: M1 H00R0000 arc: MUXCLK0 CLK0 arc: W1_H02W0101 Q1 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R33C31:PLC2 arc: E3_H06E0203 W3_H06E0203 arc: W1_H02W0401 N1_V02S0401 arc: W3_H06W0003 E3_H06W0303 .tile R33C32:PLC2 arc: S1_V02S0601 H06W0303 .tile R33C34:PLC2 arc: E1_H02E0201 V02N0201 arc: E1_H02E0401 N1_V02S0401 .tile R33C35:PLC2 arc: H00R0000 N1_V02S0401 arc: H00R0100 S1_V02N0501 arc: V00B0100 S1_V02N0101 arc: W3_H06W0203 E3_H06W0103 arc: W3_H06W0303 E1_H01W0100 arc: B0 H01W0100 arc: C0 H02E0401 arc: CLK0 G_HPBX0000 arc: D0 V02N0201 arc: E3_H06E0003 Q3 arc: F0 F0_SLICE arc: H01W0100 Q7 arc: M1 V01S0100 arc: M3 H00R0000 arc: M6 V00B0100 arc: M7 H00R0100 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK3 CLK0 arc: S1_V02S0101 Q1 arc: S1_V02S0401 Q6 arc: V01S0100 Q3 arc: W3_H06W0003 F0 word: SLICEA.K0.INIT 1100111111000000 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 .tile R33C36:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: S1_V02S0201 N1_V01S0000 arc: V00B0000 N1_V02S0201 arc: V00B0100 E1_H02W0701 arc: W3_H06W0103 E3_H06W0103 arc: B0 V02S0301 arc: C0 H00R0100 arc: CLK0 G_HPBX0000 arc: D0 V00B0100 arc: F0 F0_SLICE arc: H00R0000 Q6 arc: H00R0100 Q5 arc: H01W0100 Q7 arc: M5 H00R0000 arc: M6 V00B0000 arc: M7 W1_H02E0201 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: V01S0000 Q6 arc: V01S0100 Q7 arc: W3_H06W0003 F0 word: SLICEA.K0.INIT 1111001111000000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 .tile R33C37:PLC2 arc: E1_H02E0601 N1_V02S0601 arc: H00L0000 N1_V02S0001 arc: N1_V02N0601 V01N0001 arc: N1_V02N0701 W3_H06E0203 arc: N3_V06N0003 E3_H06W0003 arc: S1_V02S0301 N3_V06S0003 arc: S1_V02S0701 N1_V02S0701 arc: V00B0000 V02N0001 arc: V00B0100 S1_V02N0301 arc: V01S0100 N3_V06S0303 arc: A5 E1_H01W0000 arc: B0 E1_H02W0101 arc: C0 V02N0401 arc: C5 V02S0001 arc: CLK0 G_HPBX0000 arc: D0 V02S0001 arc: D5 H02W0201 arc: E1_H01E0001 Q4 arc: E3_H06E0003 F0 arc: F0 F0_SLICE arc: F5 F5_SLICE arc: H00R0000 Q4 arc: M0 V00B0100 arc: M1 H00R0000 arc: M4 V00B0000 arc: M5 H00L0000 arc: MUXCLK0 CLK0 arc: MUXCLK2 CLK0 arc: N1_V01N0001 Q0 arc: N1_V01N0101 Q1 arc: N3_V06N0303 Q5 arc: V01S0000 Q5 arc: W3_H06W0303 F5 word: SLICEC.K1.INIT 1010111110100000 word: SLICEA.K0.INIT 1111000011001100 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.B1MUX 1 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 .tile R33C38:PLC2 arc: E1_H02E0101 V02N0101 arc: E1_H02E0201 V01N0001 arc: S1_V02S0201 H01E0001 arc: S1_V02S0301 H06E0003 arc: V00B0100 N1_V02S0101 arc: V00T0000 V02S0601 arc: W1_H02W0201 V02N0201 arc: W1_H02W0701 V01N0101 arc: B1 E1_H02W0301 arc: C1 V02N0401 arc: CLK0 G_HPBX0000 arc: D1 V01S0100 arc: E1_H02E0701 Q7 arc: E3_H06E0103 F1 arc: F1 F1_SLICE arc: H00L0000 Q0 arc: H01W0000 Q5 arc: M0 V00T0000 arc: M2 V00B0000 arc: M5 H00L0000 arc: M6 V00B0100 arc: M7 E1_H02W0201 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: S1_V02S0001 Q0 arc: S1_V02S0401 Q6 arc: V00B0000 Q6 arc: V01S0000 Q7 arc: V01S0100 Q2 word: SLICEA.K1.INIT 1111110000110000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 .tile R33C39:PLC2 arc: E1_H02E0001 S1_V02N0001 arc: E3_H06E0103 V01N0101 arc: H00R0100 H02W0701 arc: N3_V06N0303 H06W0303 arc: S1_V02S0301 H06W0003 arc: S1_V02S0501 E1_H01W0100 arc: S1_V02S0601 W1_H02E0601 arc: S1_V02S0701 H06E0203 arc: W1_H02W0101 V02N0101 arc: B4 V02N0501 arc: C4 V02S0001 arc: D4 H00R0100 arc: E3_H06E0203 F4 arc: F4 F4_SLICE word: SLICEC.K0.INIT 1111110000001100 enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.A0MUX 1 .tile R33C3:PLC2 arc: N1_V02N0501 H06W0303 arc: N3_V06N0103 H06W0103 .tile R33C40:PLC2 arc: E1_H02E0301 V02S0301 arc: V00B0100 W1_H02E0701 arc: V00T0000 H02W0201 arc: V01S0100 N3_V06S0303 arc: W1_H02W0201 V02N0201 arc: W1_H02W0301 V02S0301 arc: A6 V02S0301 arc: B3 V02S0301 arc: B6 W1_H02E0101 arc: C3 H00L0000 arc: CLK0 G_HPBX0000 arc: D3 W1_H02E0201 arc: D6 V00B0000 arc: E1_H01E0001 Q2 arc: E3_H06E0003 F3 arc: E3_H06E0303 F6 arc: F3 F3_SLICE arc: F6 F6_SLICE arc: H00L0000 Q0 arc: H01W0100 Q2 arc: M0 V00B0100 arc: M2 V00T0000 arc: M4 E1_H02W0401 arc: M5 H02E0001 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: V00B0000 Q4 arc: W1_H02W0701 Q5 word: SLICEB.K1.INIT 1111001111000000 word: SLICED.K0.INIT 1110111001000100 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.C0MUX 1 .tile R33C41:PLC2 arc: E1_H02E0101 N3_V06S0103 arc: E1_H02E0601 H01E0001 arc: E1_H02E0701 V02S0701 arc: H00L0100 E1_H02W0301 arc: N1_V02N0601 N3_V06S0303 arc: S1_V02S0701 N3_V06S0203 arc: W1_H02W0201 N1_V02S0201 arc: B2 H02E0301 arc: C2 E1_H02W0401 arc: CLK0 G_HPBX0000 arc: D2 V00T0100 arc: F2 F2_SLICE arc: M3 H00L0100 arc: MUXCLK1 CLK0 arc: V00T0100 Q3 arc: W3_H06W0103 F2 word: SLICEB.K0.INIT 1111110000110000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.A0MUX 1 .tile R33C42:PLC2 arc: E1_H02E0501 N1_V01S0100 arc: E1_H02E0701 N3_V06S0203 arc: H00L0000 V02S0001 arc: S1_V02S0201 N1_V02S0201 arc: S1_V02S0701 N1_V01S0100 arc: V00B0000 S1_V02N0001 arc: V00T0000 N1_V02S0601 arc: V00T0100 N1_V02S0501 arc: W1_H02W0401 S1_V02N0401 arc: W3_H06W0003 E1_H01W0000 arc: A3 H02E0701 arc: B1 V01N0001 arc: B6 E1_H02W0101 arc: C1 H00L0000 arc: C3 H00L0000 arc: C6 V02S0001 arc: CLK0 G_HPBX0000 arc: D1 V00B0100 arc: D3 H02W0001 arc: D6 H01W0000 arc: E1_H01E0101 Q4 arc: E3_H06E0003 F3 arc: F1 F1_SLICE arc: F3 F3_SLICE arc: F6 F6_SLICE arc: H00R0000 Q6 arc: H01W0000 Q2 arc: M2 V00B0000 arc: M4 V00T0100 arc: M6 V00T0000 arc: M7 H00R0000 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: S1_V02S0601 Q4 arc: V00B0100 Q7 arc: V01S0000 Q6 arc: W3_H06W0103 F1 arc: W3_H06W0303 F6 word: SLICED.K0.INIT 1111110000001100 word: SLICEA.K1.INIT 1111110000001100 word: SLICEB.K1.INIT 1010111110100000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.A0MUX 1 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.B1MUX 1 .tile R33C43:PLC2 arc: E1_H02E0101 V02N0101 arc: E1_H02E0301 V02S0301 arc: E3_H06E0003 W3_H06E0003 arc: H00L0100 V02S0301 arc: H00R0000 V02N0601 arc: H00R0100 N1_V02S0701 arc: S1_V02S0001 N1_V02S0001 arc: S1_V02S0101 W1_H02E0101 arc: S1_V02S0201 N1_V01S0000 arc: S1_V02S0301 H01E0101 arc: S1_V02S0701 H02E0701 arc: V00B0000 V02S0201 arc: W1_H02W0001 V02N0001 arc: W1_H02W0401 V01N0001 arc: A4 V02S0301 arc: B3 H01W0100 arc: C3 H00L0100 arc: C4 V00T0000 arc: CLK0 G_HPBX0000 arc: D3 V02N0201 arc: D4 E1_H02W0201 arc: E3_H06E0203 F4 arc: F3 F3_SLICE arc: F4 F4_SLICE arc: H01W0000 Q5 arc: H01W0100 Q4 arc: M0 W1_H02E0601 arc: M3 H00R0000 arc: M4 V00B0000 arc: M5 H00R0100 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: S1_V02S0501 Q5 arc: V00T0000 Q0 arc: V01S0000 Q3 arc: W1_H02W0301 Q3 arc: W3_H06W0003 F3 word: SLICEB.K1.INIT 1100111111000000 word: SLICEC.K0.INIT 1111010110100000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.B0MUX 1 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R33C44:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: H00R0100 W1_H02E0501 arc: V00T0100 H02E0101 arc: W1_H02W0101 V02N0101 arc: B0 H02E0301 arc: C0 E1_H01W0000 arc: CLK0 G_HPBX0000 arc: D0 V00T0100 arc: E1_H02E0501 Q5 arc: E3_H06E0003 F0 arc: F0 F0_SLICE arc: M5 H00R0100 arc: MUXCLK2 CLK0 word: SLICEA.K0.INIT 1111001111000000 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R33C45:PLC2 arc: E3_H06E0303 W3_H06E0203 arc: V00B0000 H02W0601 arc: V00T0100 W1_H02E0301 arc: W1_H02W0201 W3_H06E0103 arc: A2 H02E0501 arc: C2 V02N0401 arc: CLK0 G_HPBX0000 arc: D2 V00T0100 arc: F2 F2_SLICE arc: H00R0000 Q6 arc: H01W0000 Q7 arc: M6 V00B0000 arc: M7 H00R0000 arc: MUXCLK3 CLK0 arc: N3_V06N0103 F2 arc: V01S0100 Q6 word: SLICEB.K0.INIT 1010101011110000 enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.B0MUX 1 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R33C46:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0303 W3_H06E0303 arc: W1_H02W0601 N1_V02S0601 .tile R33C48:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R33C49:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: E3_H06E0303 W3_H06E0203 .tile R33C50:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0103 W3_H06E0103 .tile R33C51:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R33C52:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: N3_V06N0003 W3_H06E0003 .tile R33C54:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R33C55:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: E3_H06E0303 W3_H06E0303 .tile R33C56:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0203 W3_H06E0103 .tile R33C57:PLC2 arc: N3_V06N0303 W3_H06E0303 .tile R33C58:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R33C60:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R33C61:PLC2 arc: E3_H06E0303 W3_H06E0303 arc: N3_V06N0203 W3_H06E0203 .tile R33C62:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0303 W3_H06E0203 .tile R33C64:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R33C66:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R33C67:PLC2 arc: N3_V06N0303 W3_H06E0303 .tile R33C68:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: E3_H06E0103 W3_H06E0003 .tile R33C6:PLC2 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0303 E3_H06W0303 .tile R33C70:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R33C72:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R33C74:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: E3_H06E0203 W3_H06E0103 .tile R33C76:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R33C78:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R33C7:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R33C80:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: E3_H06E0203 W3_H06E0203 .tile R33C82:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R33C84:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R33C86:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: E3_H06E0303 W3_H06E0203 .tile R33C87:PLC2 arc: S3_V06S0103 H06E0103 .tile R33C88:PLC2 arc: E1_H01E0101 W3_H06E0203 .tile R35C10:PLC2 arc: S3_V06S0003 E3_H06W0003 arc: W3_H06W0103 E1_H01W0100 arc: W3_H06W0203 E3_H06W0103 .tile R35C11:PLC2 arc: H01W0100 E3_H06W0303 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0203 E3_H06W0203 arc: W3_H06W0303 E1_H01W0100 .tile R35C12:PLC2 arc: H01W0100 E3_H06W0303 arc: W3_H06W0203 E3_H06W0103 .tile R35C13:PLC2 arc: S3_V06S0303 E3_H06W0303 arc: W3_H06W0303 E3_H06W0203 .tile R35C14:PLC2 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0303 E3_H06W0303 .tile R35C15:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R35C16:PLC2 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0103 .tile R35C17:PLC2 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0203 E3_H06W0203 arc: W3_H06W0303 E3_H06W0303 .tile R35C18:PLC2 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0303 E3_H06W0203 .tile R35C19:PLC2 arc: W3_H06W0203 E3_H06W0103 arc: W3_H06W0303 E3_H06W0303 .tile R35C20:PLC2 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0303 E3_H06W0303 .tile R35C21:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R35C22:PLC2 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0103 .tile R35C23:PLC2 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0203 E3_H06W0203 arc: W3_H06W0303 E3_H06W0303 .tile R35C24:PLC2 arc: W3_H06W0003 E3_H06W0303 arc: W3_H06W0203 E3_H06W0103 .tile R35C25:PLC2 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0303 E3_H06W0303 .tile R35C26:PLC2 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0303 E3_H06W0203 .tile R35C27:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R35C28:PLC2 arc: E1_H02E0401 V06S0203 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0103 E3_H06W0103 .tile R35C29:PLC2 arc: H00L0100 H02W0101 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0203 E3_H06W0103 arc: W3_H06W0303 E3_H06W0203 arc: A1 V02S0501 arc: C1 H02E0401 arc: CLK0 G_HPBX0000 arc: D1 V00T0100 arc: F1 F1_SLICE arc: M3 H00L0100 arc: MUXCLK1 CLK0 arc: V00T0100 Q3 arc: W3_H06W0103 F1 word: SLICEA.K1.INIT 1111101000001010 enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.B1MUX 1 .tile R35C2:PLC2 arc: S3_V06S0103 H06W0103 arc: S3_V06S0203 E3_H06W0203 arc: S3_V06S0303 H06W0303 .tile R35C30:PLC2 arc: H00R0000 V02N0401 arc: W3_H06W0103 E3_H06W0003 arc: A6 V02S0101 arc: C6 V00T0000 arc: CLK0 G_HPBX0000 arc: D6 E1_H02W0001 arc: E3_H06E0103 Q1 arc: F6 F6_SLICE arc: M1 H00R0000 arc: M2 H02W0601 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: V00T0000 Q2 arc: W1_H02W0101 Q1 arc: W3_H06W0303 F6 word: SLICED.K0.INIT 1111000010101010 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.B0MUX 1 .tile R35C31:PLC2 arc: W1_H02W0601 E3_H06W0303 arc: W3_H06W0003 E3_H06W0003 arc: W3_H06W0303 E3_H06W0203 .tile R35C32:PLC2 arc: V00T0000 N1_V02S0601 arc: W1_H02W0001 E1_H02W0001 arc: W3_H06W0203 E3_H06W0103 arc: A0 H00L0000 arc: C0 V02S0601 arc: CLK0 G_HPBX0000 arc: D0 E1_H02W0001 arc: F0 F0_SLICE arc: H00L0000 Q2 arc: M2 V00T0000 arc: MUXCLK1 CLK0 arc: W3_H06W0003 F0 word: SLICEA.K0.INIT 1010101011110000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.B0MUX 1 .tile R35C33:PLC2 arc: E1_H02E0201 N1_V01S0000 arc: E3_H06E0003 W3_H06E0003 .tile R35C34:PLC2 arc: E1_H02E0001 V06S0003 arc: E1_H02E0501 S1_V02N0501 arc: H00R0000 S1_V02N0401 arc: W1_H02W0001 V06S0003 arc: W3_H06W0003 E1_H01W0000 arc: B1 V02S0101 arc: C1 H00R0100 arc: CLK0 G_HPBX0000 arc: D1 V02S0001 arc: E1_H02E0301 Q3 arc: F1 F1_SLICE arc: H00R0100 Q5 arc: M3 H00R0000 arc: M5 V01S0000 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: V01S0000 Q3 arc: W3_H06W0103 F1 word: SLICEA.K1.INIT 1111001111000000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 .tile R35C35:PLC2 arc: E1_H02E0401 N1_V02S0401 arc: E1_H02E0701 N1_V01S0100 arc: H00L0000 H02E0001 arc: H00R0000 V02S0401 arc: N1_V02N0101 V01N0101 arc: V00B0000 V02S0001 arc: V00B0100 H02E0501 arc: W3_H06W0203 E1_H01W0000 arc: B0 H01W0100 arc: B2 V01N0001 arc: B3 N1_V02S0101 arc: C0 H00L0000 arc: C2 H00L0000 arc: C3 V02S0601 arc: CLK0 G_HPBX0000 arc: D0 H00R0000 arc: D2 V02S0201 arc: D3 H02E0001 arc: E1_H01E0001 Q6 arc: E1_H02E0601 Q6 arc: E3_H06E0203 Q7 arc: F0 F0_SLICE arc: F2 F2_SLICE arc: F3 F3_SLICE arc: H01W0000 F3 arc: H01W0100 Q4 arc: M4 V00B0000 arc: M6 V00B0100 arc: M7 W1_H02E0201 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: N1_V02N0501 Q7 arc: W3_H06W0003 F0 arc: W3_H06W0103 F2 word: SLICEA.K0.INIT 1100111111000000 word: SLICEB.K0.INIT 1100111111000000 word: SLICEB.K1.INIT 1100110011110000 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.A0MUX 1 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.A0MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 .tile R35C36:PLC2 arc: E1_H02E0101 V06S0103 arc: E1_H02E0301 V02S0301 arc: N1_V02N0001 H01E0001 arc: N1_V02N0101 W3_H06E0103 arc: N1_V02N0301 W1_H02E0301 arc: V00B0100 H02E0701 arc: W3_H06W0003 E3_H06W0003 arc: B3 H02W0101 arc: C3 H02E0401 arc: CLK0 G_HPBX0000 arc: D3 V02S0201 arc: E1_H01E0101 Q2 arc: E3_H06E0103 Q2 arc: F3 F3_SLICE arc: H01W0000 F3 arc: M2 V00B0100 arc: MUXCLK1 CLK0 word: SLICEB.K1.INIT 1111001111000000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 .tile R35C37:PLC2 arc: E1_H02E0101 N1_V01S0100 arc: E1_H02E0701 V02S0701 arc: H00L0000 V02S0001 arc: H00L0100 H02E0101 arc: H00R0100 S1_V02N0701 arc: N1_V02N0201 N3_V06S0103 arc: N1_V02N0301 H01E0101 arc: V00B0000 V02N0001 arc: V00T0100 V02S0501 arc: W1_H02W0101 V06S0103 arc: A5 N1_V01S0100 arc: B3 H02W0301 arc: B4 V01S0000 arc: B6 H02E0301 arc: C3 H00L0000 arc: C4 V02S0001 arc: C5 V00T0000 arc: C6 V02S0001 arc: CLK0 G_HPBX0000 arc: D3 V00T0100 arc: D4 V02S0601 arc: D5 H02W0201 arc: D6 H01W0000 arc: E1_H02E0401 Q6 arc: E1_H02E0501 Q7 arc: E3_H06E0303 F6 arc: F3 F3_SLICE arc: F4 F4_SLICE arc: F5 F5_SLICE arc: F6 F6_SLICE arc: H01W0000 Q1 arc: M0 V00B0100 arc: M1 H02W0001 arc: M2 W1_H02E0601 arc: M5 H00L0100 arc: M6 V00B0000 arc: M7 H00R0100 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: N1_V01N0001 Q0 arc: S3_V06S0303 F5 arc: V00B0100 Q7 arc: V00T0000 Q2 arc: V01S0000 Q5 arc: W3_H06W0003 F3 arc: W3_H06W0203 F4 arc: W3_H06W0303 Q6 word: SLICEC.K1.INIT 1111010110100000 word: SLICED.K0.INIT 1111110000001100 word: SLICEB.K1.INIT 1100111111000000 word: SLICEC.K0.INIT 1100111111000000 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.B1MUX 1 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.A0MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.A0MUX 1 .tile R35C38:PLC2 arc: N1_V02N0701 H02E0701 arc: V00B0100 H02W0701 arc: V00T0100 S1_V02N0701 arc: W1_H02W0001 V02N0001 arc: W1_H02W0201 V02S0201 arc: B1 H02E0101 arc: C1 E1_H01W0000 arc: CLK0 G_HPBX0000 arc: D1 V00B0100 arc: F1 F1_SLICE arc: H00R0000 Q4 arc: M1 H00R0000 arc: M4 V00T0100 arc: MUXCLK0 CLK0 arc: MUXCLK2 CLK0 arc: V01S0000 Q4 arc: W1_H02W0301 Q1 arc: W3_H06W0103 F1 word: SLICEA.K1.INIT 1111001111000000 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R35C39:PLC2 arc: E1_H01E0001 W3_H06E0003 arc: N1_V02N0001 E1_H02W0001 arc: N1_V02N0101 H06W0103 arc: N1_V02N0201 H06E0103 arc: N1_V02N0401 W1_H02E0401 arc: N1_V02N0501 W1_H02E0501 arc: N1_V02N0701 N3_V06S0203 arc: V00B0000 V02N0201 arc: W1_H02W0701 V02S0701 arc: CLK0 G_HPBX0000 arc: E1_H02E0001 Q0 arc: H00L0000 Q0 arc: H01W0000 Q7 arc: M0 V00B0000 arc: M7 H00L0000 arc: MUXCLK0 CLK0 arc: MUXCLK3 CLK0 enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R35C3:PLC2 arc: E3_H06E0203 W1_H02E0701 arc: S3_V06S0303 H06W0303 arc: W1_H02W0501 E1_H02W0501 .tile R35C40:PLC2 arc: E1_H02E0401 H01E0001 arc: E1_H02E0501 S1_V02N0501 arc: E1_H02E0601 N3_V06S0303 arc: N1_V02N0501 N3_V06S0303 arc: N1_V02N0601 N3_V06S0303 arc: V01S0000 N3_V06S0103 arc: CLK0 G_HPBX0000 arc: E1_H02E0201 Q0 arc: M0 H02W0601 arc: MUXCLK0 CLK0 arc: N1_V01N0101 Q0 enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R35C41:PLC2 arc: E1_H01E0101 W3_H06E0203 arc: E1_H02E0401 E1_H01W0000 arc: E1_H02E0601 V02S0601 arc: N1_V02N0001 W1_H02E0001 arc: V00B0100 V02N0301 arc: W1_H02W0601 V06N0303 arc: CLK0 G_HPBX0000 arc: M0 V00B0100 arc: MUXCLK0 CLK0 arc: W1_H02W0001 Q0 enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R35C42:PLC2 arc: E1_H02E0001 V02S0001 arc: N1_V02N0001 V01N0001 arc: N1_V02N0101 H01E0101 arc: N1_V02N0201 N3_V06S0103 arc: N1_V02N0301 S1_V02N0201 arc: N1_V02N0401 E1_H01W0000 arc: N1_V02N0501 W1_H02E0501 arc: N1_V02N0601 W1_H02E0601 arc: S1_V02S0201 H02W0201 arc: S1_V02S0601 N1_V02S0601 arc: W3_H06W0103 E1_H01W0100 arc: A3 V01N0101 arc: B2 H00R0100 arc: C2 V02S0601 arc: C3 V02S0401 arc: CLK0 G_HPBX0000 arc: D2 H02W0201 arc: D3 H02W0201 arc: E1_H02E0201 Q0 arc: E3_H06E0103 F2 arc: F2 F2_SLICE arc: F3 F3_SLICE arc: H00R0000 Q4 arc: H00R0100 Q5 arc: H01W0000 Q7 arc: M0 H02E0601 arc: M4 W1_H02E0401 arc: M5 H00R0000 arc: M7 W1_H02E0201 arc: MUXCLK0 CLK0 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: N1_V01N0001 Q4 arc: V01S0100 Q0 arc: W3_H06W0003 F3 word: SLICEB.K0.INIT 1100110011110000 word: SLICEB.K1.INIT 1010101011110000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.A0MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.B1MUX 1 .tile R35C43:PLC2 arc: E1_H02E0201 V06S0103 arc: E3_H06E0303 W3_H06E0303 arc: H00R0000 V02S0601 arc: H00R0100 N1_V02S0501 arc: N1_V02N0201 H06W0103 arc: W1_H02W0201 V06S0103 arc: A2 V02S0701 arc: B3 V02N0301 arc: C2 W1_H02E0401 arc: C3 N1_V01N0001 arc: CLK0 G_HPBX0000 arc: D2 H00R0000 arc: D3 H02E0001 arc: E3_H06E0003 F3 arc: E3_H06E0103 F2 arc: F2 F2_SLICE arc: F3 F3_SLICE arc: H01W0000 Q6 arc: H01W0100 Q6 arc: M6 H02W0401 arc: M7 H00R0100 arc: MUXCLK3 CLK0 arc: N1_V01N0001 Q7 word: SLICEB.K1.INIT 1111001111000000 word: SLICEB.K0.INIT 1111000010101010 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_0 _NONE_ enum: SLICEB.B0MUX 1 .tile R35C44:PLC2 arc: E1_H02E0101 V02S0101 arc: E1_H02E0201 W1_H02E0201 arc: N1_V02N0201 E1_H01W0000 arc: W1_H02W0401 E1_H02W0401 .tile R35C45:PLC2 arc: E1_H02E0101 V02S0101 arc: H00R0000 S1_V02N0401 arc: B3 H02E0101 arc: C3 E1_H01W0000 arc: CLK0 G_HPBX0000 arc: D3 W1_H02E0201 arc: E1_H01E0101 Q3 arc: E3_H06E0003 F3 arc: F3 F3_SLICE arc: H01W0000 Q1 arc: M1 H00R0000 arc: M3 H02E0201 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: V01S0000 Q1 word: SLICEB.K1.INIT 1111000011001100 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R35C46:PLC2 arc: W1_H02W0401 E3_H06W0203 arc: B3 H02E0101 arc: C3 V02S0601 arc: CLK0 G_HPBX0000 arc: D3 H01E0101 arc: E3_H06E0003 F3 arc: F3 F3_SLICE arc: H00L0100 Q1 arc: H01W0000 Q7 arc: M1 H02W0001 arc: M7 H00L0100 arc: MUXCLK0 CLK0 arc: MUXCLK3 CLK0 arc: W3_H06W0103 Q1 word: SLICEB.K1.INIT 1111110000001100 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.MODE LOGIC enum: SLICEB.CCU2.INJECT1_1 _NONE_ enum: SLICEB.A1MUX 1 enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R35C47:PLC2 arc: W1_H02W0001 E3_H06W0003 .tile R35C48:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R35C49:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0103 W3_H06E0103 arc: E3_H06E0303 W3_H06E0303 .tile R35C4:PLC2 arc: S3_V06S0203 E3_H06W0203 arc: W3_H06W0103 E3_H06W0103 arc: W3_H06W0203 E1_H01W0000 .tile R35C51:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R35C52:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: W3_H06W0203 E3_H06W0203 .tile R35C53:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R35C54:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R35C55:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0103 W3_H06E0103 arc: E3_H06E0303 W3_H06E0303 .tile R35C57:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R35C58:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: W3_H06W0203 E3_H06W0203 .tile R35C59:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R35C5:PLC2 arc: H01W0000 E3_H06W0103 arc: W1_H02W0501 E3_H06W0303 arc: W3_H06W0103 E3_H06W0003 arc: W3_H06W0303 E3_H06W0203 .tile R35C60:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R35C61:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: E3_H06E0203 W3_H06E0103 arc: E3_H06E0303 W3_H06E0303 .tile R35C63:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R35C64:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: W3_H06W0203 E3_H06W0103 .tile R35C65:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R35C66:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R35C67:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: E3_H06E0303 W3_H06E0203 arc: N3_V06N0303 W3_H06E0303 .tile R35C69:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R35C6:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R35C70:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: W3_H06W0103 E3_H06W0103 .tile R35C71:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R35C72:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R35C73:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: E3_H06E0303 W3_H06E0203 .tile R35C75:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R35C76:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: W3_H06W0103 E3_H06W0003 .tile R35C77:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R35C78:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R35C79:PLC2 arc: E3_H06E0303 W3_H06E0303 arc: S3_V06S0003 W3_H06E0003 .tile R35C7:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R35C81:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R35C82:PLC2 arc: E3_H06E0203 W3_H06E0103 arc: W3_H06W0003 E3_H06W0003 .tile R35C83:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R35C84:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R35C85:PLC2 arc: S3_V06S0303 W3_H06E0303 .tile R35C87:PLC2 arc: E1_H02E0701 W3_H06E0203 arc: S3_V06S0203 H06E0203 .tile R35C88:PLC2 arc: S3_V06S0203 W3_H06E0203 arc: W3_H06W0003 E1_H01W0000 .tile R35C8:PLC2 arc: S3_V06S0303 E3_H06W0303 arc: W3_H06W0203 E3_H06W0103 .tile R35C9:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R36C12:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R36C15:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R36C18:PLC2 arc: S3_V06S0003 E3_H06W0003 arc: W3_H06W0203 E3_H06W0103 .tile R36C21:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R36C24:PLC2 arc: W3_H06W0003 E3_H06W0303 arc: W3_H06W0103 E3_H06W0003 .tile R36C27:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R36C30:PLC2 arc: N1_V02N0401 H06E0203 arc: W3_H06W0003 E3_H06W0303 arc: W3_H06W0303 E3_H06W0203 .tile R36C33:PLC2 arc: E1_H02E0001 V02N0001 .tile R36C34:PLC2 arc: E1_H02E0601 S1_V02N0601 .tile R36C35:PLC2 arc: CLK0 G_HPBX0000 arc: E1_H01E0101 Q5 arc: M2 H02E0601 arc: M5 W1_H02E0001 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: N1_V01N0001 Q2 arc: N1_V01N0101 Q5 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R36C36:PLC2 arc: E3_H06E0103 H01E0101 arc: W3_H06W0203 E3_H06W0203 arc: W3_H06W0303 E3_H06W0303 .tile R36C37:PLC2 arc: E1_H02E0201 S1_V02N0201 arc: E1_H02E0301 S1_V02N0301 arc: H00R0100 S1_V02N0701 arc: N1_V02N0001 S1_V02N0501 arc: CLK0 G_HPBX0000 arc: E1_H01E0001 Q1 arc: M1 H00R0100 arc: MUXCLK0 CLK0 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R36C38:PLC2 arc: N1_V02N0001 H01E0001 arc: N1_V02N0201 N1_V01S0000 .tile R36C39:PLC2 arc: N1_V02N0101 H06E0103 arc: N1_V02N0201 W1_H02E0201 arc: N1_V02N0301 W1_H02E0301 arc: N1_V02N0601 S1_V02N0301 .tile R36C3:PLC2 arc: E3_H06E0303 W1_H02E0601 arc: S3_V06S0303 H06W0303 .tile R36C40:PLC2 arc: E3_H06E0203 N1_V01S0000 arc: N1_V02N0201 S1_V02N0701 .tile R36C41:PLC2 arc: E1_H02E0401 S1_V02N0401 arc: N1_V02N0301 S1_V02N0201 .tile R36C42:PLC2 arc: H00L0100 N1_V02S0101 arc: H00R0000 H02W0401 arc: H00R0100 N1_V02S0501 arc: N1_V02N0301 N1_V01S0100 arc: N1_V02N0601 V01N0001 arc: N1_V02N0701 V01N0101 arc: S1_V02S0201 N1_V02S0201 arc: V00B0000 V02N0201 arc: V00T0000 V02S0601 arc: A6 H00L0000 arc: B7 V01S0000 arc: C6 V02S0201 arc: C7 V02S0201 arc: CLK0 G_HPBX0000 arc: D6 H00R0100 arc: D7 H00L0100 arc: E1_H01E0101 Q6 arc: F6 F6_SLICE arc: F7 F7_SLICE arc: H00L0000 Q0 arc: M0 V00T0000 arc: M3 H00R0000 arc: M4 V00B0000 arc: M6 H02E0401 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: N1_V01N0001 Q6 arc: N1_V01N0101 Q3 arc: V01S0000 Q4 arc: W3_H06W0203 F7 arc: W3_H06W0303 F6 word: SLICED.K0.INIT 1010111110100000 word: SLICED.K1.INIT 1100111111000000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_0 _NONE_ enum: SLICED.B0MUX 1 enum: SLICED.MODE LOGIC enum: SLICED.CCU2.INJECT1_1 _NONE_ enum: SLICED.A1MUX 1 enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R36C43:PLC2 arc: N1_V02N0101 H01E0101 arc: N1_V02N0301 S1_V02N0201 arc: N1_V02N0401 E1_H02W0401 arc: N1_V02N0701 H06E0203 arc: W1_H02W0401 N1_V02S0401 .tile R36C44:PLC2 arc: E1_H02E0001 N1_V02S0001 .tile R36C45:PLC2 arc: E1_H02E0601 N1_V01S0000 arc: V00B0100 V02N0101 arc: A0 H00R0000 arc: C0 V02N0601 arc: CLK0 G_HPBX0000 arc: D0 H02E0001 arc: E3_H06E0003 F0 arc: F0 F0_SLICE arc: H00R0000 Q4 arc: M4 V00B0000 arc: M6 V00B0100 arc: MUXCLK2 CLK0 arc: MUXCLK3 CLK0 arc: V00B0000 Q6 arc: W1_H02W0401 Q6 word: SLICEA.K0.INIT 1010111110100000 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.B0MUX 1 .tile R36C46:PLC2 arc: CLK0 G_HPBX0000 arc: M2 H02E0601 arc: MUXCLK1 CLK0 arc: V01S0000 Q2 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R36C51:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R36C57:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R36C63:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R36C69:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R36C6:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R36C75:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R36C81:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R36C87:PLC2 arc: S3_V06S0203 W3_H06E0203 .tile R36C9:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R37C13:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R37C15:PLC2 arc: E3_H06E0303 W3_H06E0303 arc: S3_V06S0203 H06W0203 .tile R37C18:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R37C19:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R37C21:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R37C24:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R37C25:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R37C27:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R37C30:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R37C31:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R37C33:PLC2 arc: N1_V02N0001 W3_H06E0003 .tile R37C34:PLC2 arc: N1_V02N0401 S1_V02N0101 arc: N1_V02N0501 H06E0303 .tile R37C36:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R37C37:PLC2 arc: N1_V02N0701 E1_H02W0701 .tile R37C38:PLC2 arc: N1_V02N0701 H06W0203 .tile R37C39:PLC2 arc: W1_H02W0701 E1_H02W0701 .tile R37C40:PLC2 arc: H00R0000 V02N0601 arc: CLK0 G_HPBX0000 arc: E1_H02E0501 Q5 arc: M5 H00R0000 arc: MUXCLK2 CLK0 arc: N1_V02N0501 Q5 enum: SLICEC.GSR DISABLED enum: SLICEC.REG1.SD 0 enum: SLICEC.REG1.REGSET RESET enum: SLICEC.REG1.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R37C41:PLC2 arc: E1_H02E0201 E3_H06W0103 arc: E1_H02E0601 S1_V02N0601 arc: W1_H02W0701 V06N0203 arc: W3_H06W0203 S3_V06N0203 .tile R37C42:PLC2 arc: E1_H02E0501 W1_H02E0501 arc: E1_H02E0601 V06S0303 arc: H00R0000 H02W0601 arc: A0 E1_H01E0001 arc: A5 V02N0101 arc: B0 V02N0101 arc: C5 V02S0201 arc: CLK0 G_HPBX0000 arc: D0 H02W0201 arc: D5 H01W0000 arc: E1_H01E0001 Q6 arc: E3_H06E0303 F5 arc: F0 F0_SLICE arc: F5 F5_SLICE arc: H01W0000 Q1 arc: M0 H02E0601 arc: M1 V01S0100 arc: M3 H00R0000 arc: M6 V00B0100 arc: M7 H02E0201 arc: MUXCLK0 CLK0 arc: MUXCLK1 CLK0 arc: MUXCLK3 CLK0 arc: N1_V01N0001 Q7 arc: N1_V01N0101 Q3 arc: N1_V02N0201 Q0 arc: V00B0100 Q7 arc: V01S0100 Q3 arc: W3_H06W0003 F0 word: SLICEC.K1.INIT 1111101001010000 word: SLICEA.K0.INIT 1011101110001000 enum: SLICEB.GSR DISABLED enum: SLICEB.REG1.SD 0 enum: SLICEB.REG1.REGSET RESET enum: SLICEB.REG1.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICED.GSR DISABLED enum: SLICED.REG1.SD 0 enum: SLICED.REG1.REGSET RESET enum: SLICED.REG1.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_1 _NONE_ enum: SLICEC.B1MUX 1 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_0 _NONE_ enum: SLICEA.C0MUX 1 enum: SLICED.GSR DISABLED enum: SLICED.REG0.SD 0 enum: SLICED.REG0.REGSET RESET enum: SLICED.REG0.LSRMODE LSR enum: SLICED.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R37C43:PLC2 arc: V00B0100 H02E0501 arc: W1_H02W0201 V06S0103 arc: W1_H02W0601 V06N0303 arc: B1 V00T0000 arc: C1 H02E0601 arc: CLK0 G_HPBX0000 arc: D1 V02N0201 arc: E3_H06E0103 F1 arc: F1 F1_SLICE arc: M2 V00B0100 arc: MUXCLK1 CLK0 arc: V00T0000 Q2 word: SLICEA.K1.INIT 1100110011110000 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.A1MUX 1 enum: SLICEB.GSR DISABLED enum: SLICEB.REG0.SD 0 enum: SLICEB.REG0.REGSET RESET enum: SLICEB.REG0.LSRMODE LSR enum: SLICEB.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R37C45:PLC2 arc: E1_H02E0601 V06S0303 arc: N1_V02N0101 E3_H06W0103 arc: N1_V02N0401 E1_H01W0000 arc: N1_V02N0601 H02W0601 .tile R37C46:PLC2 arc: H01W0000 E3_H06W0103 arc: W1_H02W0601 V01N0001 arc: B4 N1_V01S0000 arc: C4 H02E0601 arc: D4 V01N0001 arc: E3_H06E0203 F4 arc: F4 F4_SLICE word: SLICEC.K0.INIT 1100110011110000 enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.A0MUX 1 .tile R37C47:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R37C48:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R37C49:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R37C51:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R37C52:PLC2 arc: E3_H06E0203 W3_H06E0203 arc: W3_H06W0103 E3_H06W0003 .tile R37C53:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R37C54:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R37C55:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R37C57:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R37C58:PLC2 arc: E3_H06E0203 W3_H06E0203 arc: W3_H06W0003 E3_H06W0303 .tile R37C59:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R37C60:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R37C61:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R37C63:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R37C64:PLC2 arc: E3_H06E0203 W3_H06E0203 arc: W3_H06W0303 E3_H06W0203 .tile R37C65:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R37C66:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R37C67:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R37C69:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R37C70:PLC2 arc: E3_H06E0303 W3_H06E0203 arc: W3_H06W0203 E3_H06W0103 .tile R37C71:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R37C72:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R37C73:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R37C75:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R37C76:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: W3_H06W0103 E3_H06W0103 .tile R37C77:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R37C78:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R37C79:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R37C7:PLC2 arc: E1_H02E0501 S3_V06N0303 arc: E3_H06E0303 W3_H06E0303 .tile R37C81:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R37C82:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: W3_H06W0103 E3_H06W0103 .tile R37C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R37C84:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R37C85:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R37C87:PLC2 arc: S1_V02S0501 H06E0303 arc: W3_H06W0303 E1_H02W0601 .tile R37C88:PLC2 arc: E1_H01E0001 W3_H06E0003 arc: S3_V06S0203 H06E0203 arc: W3_H06W0103 E1_H01W0100 .tile R37C9:PLC2 arc: E3_H06E0303 W1_H02E0501 .tile R38C12:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R38C13:PLC2 arc: E3_H06E0003 W3_H06E0303 arc: E3_H06E0103 W3_H06E0103 .tile R38C15:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R38C18:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R38C19:PLC2 arc: E3_H06E0003 W3_H06E0003 arc: E3_H06E0203 W3_H06E0103 .tile R38C21:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R38C24:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R38C25:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: E3_H06E0303 W3_H06E0203 .tile R38C27:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R38C2:PLC2 arc: W1_H02W0501 E3_H06W0303 .tile R38C30:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R38C31:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: E3_H06E0303 W3_H06E0303 .tile R38C33:PLC2 arc: E1_H02E0101 W3_H06E0103 .tile R38C34:PLC2 arc: V00T0100 H02E0101 arc: CLK0 G_HPBX0000 arc: E3_H06E0203 Q4 arc: M4 V00T0100 arc: MUXCLK2 CLK0 arc: N1_V02N0601 Q4 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R38C36:PLC2 arc: B4 H02W0101 arc: C4 V00T0100 arc: CLK0 G_HPBX0000 arc: D4 S1_V02N0401 arc: E3_H06E0003 Q0 arc: F4 F4_SLICE arc: M0 H02W0601 arc: M1 V01S0100 arc: MUXCLK0 CLK0 arc: V00T0100 Q1 arc: V01S0100 Q0 arc: W3_H06W0203 F4 word: SLICEC.K0.INIT 1111001111000000 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEA.GSR DISABLED enum: SLICEA.REG0.SD 0 enum: SLICEA.REG0.REGSET RESET enum: SLICEA.REG0.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK enum: SLICEC.MODE LOGIC enum: SLICEC.CCU2.INJECT1_0 _NONE_ enum: SLICEC.A0MUX 1 .tile R38C37:PLC2 arc: E3_H06E0303 W3_H06E0303 arc: N1_V02N0201 W3_H06E0103 arc: N1_V02N0301 S1_V02N0201 arc: N1_V02N0501 S3_V06N0303 arc: N1_V02N0701 S1_V02N0701 arc: W1_H02W0101 N3_V06S0103 arc: W1_H02W0601 V02N0601 arc: A1 E1_H02W0701 arc: C1 S1_V02N0601 arc: D1 S1_V02N0001 arc: E3_H06E0103 F1 arc: F1 F1_SLICE word: SLICEA.K1.INIT 1111101000001010 enum: SLICEA.MODE LOGIC enum: SLICEA.CCU2.INJECT1_1 _NONE_ enum: SLICEA.B1MUX 1 .tile R38C39:PLC2 arc: N1_V02N0301 H06E0003 arc: W1_H02W0701 S1_V02N0701 .tile R38C3:PLC2 arc: E3_H06E0303 W1_H02E0601 arc: S3_V06S0103 H06W0103 .tile R38C40:PLC2 arc: N1_V02N0601 H06E0303 arc: N1_V02N0701 W3_H06E0203 .tile R38C41:PLC2 arc: N1_V02N0201 S3_V06N0103 arc: N1_V02N0401 E3_H06W0203 arc: N3_V06N0303 S3_V06N0203 .tile R38C42:PLC2 arc: N1_V02N0101 H02W0101 .tile R38C43:PLC2 arc: E3_H06E0103 W3_H06E0103 arc: N1_V02N0201 N3_V06S0103 arc: W1_H02W0101 N3_V06S0103 .tile R38C46:PLC2 arc: N1_V01N0001 N3_V06S0003 .tile R38C47:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R38C49:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R38C53:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R38C55:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R38C59:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R38C61:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R38C65:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R38C67:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R38C6:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R38C71:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R38C73:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R38C77:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R38C79:PLC2 arc: E3_H06E0003 V06S0003 arc: E3_H06E0103 W3_H06E0003 .tile R38C7:PLC2 arc: E3_H06E0103 W3_H06E0003 arc: E3_H06E0303 W3_H06E0303 .tile R38C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R38C85:PLC2 arc: E1_H01E0001 W3_H06E0003 arc: E3_H06E0203 W3_H06E0103 .tile R38C86:PLC2 arc: E3_H06E0203 H01E0001 .tile R38C87:PLC2 arc: E1_H02E0501 V02S0501 arc: E1_H02E0701 V06S0203 .tile R38C88:PLC2 arc: S3_V06S0203 H06E0203 .tile R38C8:PLC2 arc: W3_H06W0303 V06S0303 .tile R38C9:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R39C13:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R39C19:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R39C25:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R39C31:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R39C34:PLC2 arc: N1_V02N0101 S1_V02N0101 .tile R39C37:PLC2 arc: H00R0000 V02N0401 arc: N1_V02N0601 W3_H06E0303 arc: CLK0 G_HPBX0000 arc: M1 H00R0000 arc: MUXCLK0 CLK0 arc: V01S0000 Q1 enum: SLICEA.GSR DISABLED enum: SLICEA.REG1.SD 0 enum: SLICEA.REG1.REGSET RESET enum: SLICEA.REG1.LSRMODE LSR enum: SLICEA.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R39C41:PLC2 arc: N1_V02N0601 S1_V02N0601 .tile R39C7:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R39C87:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R3C17:PLC2 arc: N1_V02N0501 S3_V06N0303 .tile R3C19:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R3C23:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R3C35:PLC2 arc: N1_V02N0701 S1_V02N0701 .tile R3C37:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R3C39:PLC2 arc: N1_V02N0501 S3_V06N0303 .tile R3C41:PLC2 arc: S3_V06S0103 N1_V02S0201 .tile R3C42:PLC2 arc: S3_V06S0003 N1_V02S0001 arc: S3_V06S0103 N1_V02S0201 .tile R3C52:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R3C57:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R3C61:PLC2 arc: N1_V02N0501 S3_V06N0303 .tile R3C67:PLC2 arc: E3_H06E0203 S3_V06N0203 arc: N1_V02N0501 S3_V06N0303 .tile R3C70:PLC2 arc: N1_V02N0701 H06E0203 .tile R40C13:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R40C19:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R40C25:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R40C31:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R40C33:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R40C34:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R40C35:PLC2 arc: N3_V06N0303 S3_V06N0203 .tile R40C36:PLC2 arc: E1_H02E0301 S3_V06N0003 arc: N1_V02N0401 E1_H02W0401 .tile R40C37:PLC2 arc: E3_H06E0303 W3_H06E0203 arc: N1_V02N0001 N1_V01S0000 arc: N1_V02N0201 S3_V06N0103 arc: N1_V02N0601 N3_V06S0303 arc: N1_V02N0701 S3_V06N0203 arc: V00T0100 H02E0301 arc: CLK0 G_HPBX0000 arc: E1_H01E0101 Q4 arc: M4 V00T0100 arc: MUXCLK2 CLK0 arc: N1_V02N0401 Q4 enum: SLICEC.GSR DISABLED enum: SLICEC.REG0.SD 0 enum: SLICEC.REG0.REGSET RESET enum: SLICEC.REG0.LSRMODE LSR enum: SLICEC.CEMUX 1 enum: LSR0.SRMODE LSR_OVER_CE enum: LSR0.LSRMUX LSR enum: LSR1.SRMODE LSR_OVER_CE enum: LSR1.LSRMUX LSR enum: CLK0.CLKMUX CLK .tile R40C38:PLC2 arc: N3_V06N0003 S3_V06N0003 arc: N3_V06N0103 H01E0101 arc: W1_H02W0401 N3_V06S0203 .tile R40C39:PLC2 arc: N1_V02N0701 N3_V06S0203 .tile R40C41:PLC2 arc: N3_V06N0203 E3_H06W0203 arc: N3_V06N0303 S3_V06N0203 .tile R40C43:PLC2 arc: N3_V06N0203 S3_V06N0203 arc: N3_V06N0303 W3_H06E0303 .tile R40C47:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R40C53:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R40C59:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R40C65:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R40C71:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R40C77:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R40C7:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R40C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R41C10:PLC2 arc: S3_V06S0103 N3_V06S0003 .tile R41C13:PLC2 arc: S3_V06S0003 N3_V06S0303 .tile R41C2:PLC2 arc: S3_V06S0203 N3_V06S0103 arc: S3_V06S0303 N3_V06S0303 arc: W1_H02W0501 E1_H02W0401 arc: W1_H02W0701 N3_V06S0203 .tile R41C34:PLC2 arc: N1_V02N0101 S3_V06N0103 .tile R41C37:PLC2 arc: E3_H06E0303 N3_V06S0303 .tile R41C3:PLC2 arc: S3_V06S0303 N3_V06S0303 .tile R41C41:PLC2 arc: N1_V02N0601 E3_H06W0303 .tile R41C43:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R41C47:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R41C49:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R41C4:PLC2 arc: W1_H02W0401 N3_V06S0203 .tile R41C53:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R41C55:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R41C59:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R41C61:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R41C65:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R41C67:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R41C71:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R41C73:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R41C77:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R41C79:PLC2 arc: E3_H06E0203 W3_H06E0203 .tile R41C83:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R41C85:PLC2 arc: E1_H02E0501 N3_V06S0303 arc: E3_H06E0303 W3_H06E0203 .tile R41C87:PLC2 arc: E1_H02E0501 W1_H02E0501 .tile R41C88:PLC2 arc: S3_V06S0203 N3_V06S0203 arc: S3_V06S0303 H06E0303 .tile R42C18:PLC2 arc: S3_V06S0103 N3_V06S0003 .tile R42C3:PLC2 arc: W1_H02W0501 N3_V06S0303 .tile R42C87:PLC2 arc: S3_V06S0303 N3_V06S0203 .tile R43C15:PLC2 arc: S3_V06S0303 N3_V06S0203 .tile R43C41:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R43C7:PLC2 arc: N3_V06N0303 W3_H06E0303 .tile R43C88:PLC2 arc: S3_V06S0203 N3_V06S0203 .tile R44C37:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R44C3:PLC2 arc: S3_V06S0203 N3_V06S0103 arc: W1_H02W0501 V06S0303 .tile R44C41:PLC2 arc: N3_V06N0103 S3_V06N0003 arc: N3_V06N0203 E3_H06W0203 .tile R44C47:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R44C53:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R44C59:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R44C65:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R44C71:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R44C77:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R44C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R44C88:PLC2 arc: E1_H02E0701 V06S0203 arc: S3_V06S0203 N3_V06S0203 .tile R45C87:PLC2 arc: E1_H02E0401 N3_V06S0203 .tile R47C10:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R47C13:PLC2 arc: E3_H06E0303 W3_H06E0303 arc: S3_V06S0103 N3_V06S0003 .tile R47C19:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R47C25:PLC2 arc: E3_H06E0003 W3_H06E0003 .tile R47C2:PLC2 arc: W1_H02W0501 N3_V06S0303 arc: W1_H02W0701 N3_V06S0203 .tile R47C31:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R47C34:PLC2 arc: N3_V06N0103 H06E0103 .tile R47C7:PLC2 arc: E3_H06E0303 W3_H06E0303 .tile R47C88:PLC2 arc: E1_H02E0501 N3_V06S0303 arc: E1_H02E0701 V06S0203 .tile R48C18:PLC2 arc: S3_V06S0103 N3_V06S0103 .tile R48C87:PLC2 arc: S3_V06S0303 N3_V06S0303 .tile R49C15:PLC2 arc: S3_V06S0303 N3_V06S0303 .tile R49C41:PLC2 arc: N3_V06N0103 E3_H06W0103 .tile R49C47:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R49C53:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R49C59:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R49C65:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R49C71:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R49C77:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R49C83:PLC2 arc: W3_H06W0303 E3_H06W0303 .tile R49C88:PLC2 arc: S3_V06S0303 N3_V06S0203 .tile R4C24:PLC2 arc: N3_V06N0203 S1_V02N0401 .tile R4C49:PLC2 arc: N3_V06N0303 S3_V06N0203 .tile R50C13:PLC2 arc: E3_H06E0103 W3_H06E0003 .tile R50C19:PLC2 arc: E3_H06E0103 W3_H06E0103 .tile R50C25:PLC2 arc: E3_H06E0203 W3_H06E0103 .tile R50C31:PLC2 arc: E3_H06E0303 W3_H06E0203 .tile R50C37:PLC2 arc: N3_V06N0303 W3_H06E0303 .tile R50C3:PLC2 arc: W1_H02W0701 N3_V06S0203 .tile R50C41:PLC2 arc: N3_V06N0003 E3_H06W0003 .tile R50C47:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R50C53:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R50C59:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R50C65:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R50C71:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R50C77:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R50C7:PLC2 arc: E3_H06E0003 W3_H06E0303 .tile R50C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R52C33:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R52C34:PLC2 arc: N3_V06N0303 S3_V06N0203 .tile R52C35:PLC2 arc: N3_V06N0203 S3_V06N0203 .tile R52C36:PLC2 arc: N3_V06N0003 S3_V06N0303 .tile R52C37:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R52C38:PLC2 arc: N3_V06N0303 H06W0303 .tile R52C41:PLC2 arc: W3_H06W0303 E3_H06W0203 .tile R52C43:PLC2 arc: N3_V06N0203 S3_V06N0203 .tile R52C47:PLC2 arc: W3_H06W0203 E3_H06W0203 .tile R52C53:PLC2 arc: W3_H06W0203 E3_H06W0103 .tile R52C59:PLC2 arc: W3_H06W0103 E3_H06W0103 .tile R52C65:PLC2 arc: W3_H06W0103 E3_H06W0003 .tile R52C71:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R52C77:PLC2 arc: W3_H06W0003 E3_H06W0003 .tile R52C83:PLC2 arc: W3_H06W0003 E3_H06W0303 .tile R52C88:PLC2 arc: E1_H02E0501 V06S0303 .tile R53C10:PLC2 arc: S3_V06S0203 N3_V06S0203 .tile R53C13:PLC2 arc: S3_V06S0103 N3_V06S0103 .tile R54C18:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R54C87:PLC2 arc: V01S0100 N3_V06S0303 .tile R55C15:PLC2 arc: S3_V06S0003 N3_V06S0303 .tile R55C87:PLC2 arc: E1_H02E0501 N1_V01S0100 .tile R59C10:PLC2 arc: S3_V06S0303 N3_V06S0203 .tile R59C13:PLC2 arc: S3_V06S0103 N3_V06S0103 .tile R5C35:PLC2 arc: N1_V02N0701 S3_V06N0203 .tile R60C18:PLC2 arc: S3_V06S0203 N3_V06S0203 .tile R61C15:PLC2 arc: S3_V06S0103 N3_V06S0003 .tile R64C33:PLC2 arc: N3_V06N0003 S3_V06N0303 .tile R64C34:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R64C35:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R64C36:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R64C37:PLC2 arc: N3_V06N0103 S3_V06N0003 .tile R64C43:PLC2 arc: N3_V06N0103 S3_V06N0103 .tile R65C10:PLC2 arc: S3_V06S0303 N3_V06S0303 .tile R65C13:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R66C18:PLC2 arc: S1_V02S0401 N3_V06S0203 .tile R67C15:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R68C10:PLC2 arc: E1_H02E0501 V06S0303 .tile R68C11:PLC2 arc: S1_V02S0501 H02E0501 .tile R68C12:PLC2 arc: S1_V02S0701 H02W0701 .tile R68C13:PLC2 arc: W1_H02W0701 V06S0203 .tile R68C18:PLC2 arc: S1_V02S0501 N1_V02S0401 .tile R6C24:PLC2 arc: N1_V02N0401 S3_V06N0203 .tile R7C30:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R7C34:PLC2 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0303 N3_V06S0203 .tile R7C35:PLC2 arc: S3_V06S0203 N3_V06S0103 .tile R7C36:PLC2 arc: S3_V06S0003 N3_V06S0303 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0203 N3_V06S0103 .tile R7C37:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0203 N3_V06S0203 .tile R7C38:PLC2 arc: S3_V06S0003 N3_V06S0303 arc: S3_V06S0303 N3_V06S0203 .tile R7C39:PLC2 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0203 N3_V06S0203 .tile R7C40:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0103 N3_V06S0103 arc: S3_V06S0303 N3_V06S0203 .tile R7C41:PLC2 arc: S3_V06S0103 N3_V06S0003 arc: S3_V06S0203 N3_V06S0103 arc: S3_V06S0303 N3_V06S0303 .tile R7C42:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0203 N3_V06S0103 arc: S3_V06S0303 N3_V06S0203 arc: V01S0100 N3_V06S0303 .tile R7C43:PLC2 arc: S3_V06S0003 N3_V06S0003 .tile R7C44:PLC2 arc: S3_V06S0203 N3_V06S0203 arc: S3_V06S0303 N3_V06S0303 .tile R7C45:PLC2 arc: S3_V06S0003 N3_V06S0303 .tile R7C46:PLC2 arc: S3_V06S0203 N3_V06S0203 .tile R7C67:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R8C31:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R8C42:PLC2 arc: N3_V06N0203 S3_V06N0103 arc: S3_V06S0303 N1_V01S0100 .tile R8C43:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R8C54:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R8C61:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R8C73:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R9C17:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R9C19:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R9C23:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R9C37:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R9C39:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R9C41:PLC2 arc: S3_V06S0103 N3_V06S0103 .tile R9C42:PLC2 arc: S3_V06S0003 N3_V06S0003 arc: S3_V06S0103 N3_V06S0103 .tile R9C52:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R9C57:PLC2 arc: N3_V06N0203 S3_V06N0103 .tile R9C61:PLC2 arc: N3_V06N0303 S3_V06N0303 .tile R9C67:PLC2 arc: N3_V06N0203 S3_V06N0103 arc: N3_V06N0303 S1_V02N0501 .tile TAP_R25C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R25C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R26C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R26C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R27C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R27C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R28C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R29C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R29C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R30C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R31C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R31C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R32C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R32C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R33C31:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 arc: R_HPBX0000 G_VPTX0000 .tile TAP_R33C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R34C31:TAP_DRIVE_CIB arc: R_HPBX0000 G_VPTX0000 .tile TAP_R34C51:TAP_DRIVE_CIB arc: L_HPBX0000 G_VPTX0000 .tile TAP_R35C31:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 arc: R_HPBX0000 G_VPTX0000 .tile TAP_R35C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R36C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R36C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R37C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R37C51:TAP_DRIVE arc: L_HPBX0000 G_VPTX0000 .tile TAP_R38C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R39C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .tile TAP_R40C31:TAP_DRIVE arc: R_HPBX0000 G_VPTX0000 .bram_init 3 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 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