/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Parsing `hardware/v2/rtl/neural_processor.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_processor.v Parsing Verilog input from `hardware/v2/rtl/neural_processor.v' to AST representation. Storing AST representation for module `$abstract\neural_processor'. Successfully finished Verilog frontend. -- Running command `synth_ecp5 -json hardware/v2/synthesis/neural_processor_p8/top.json -top neural_processor' -- 2. Executing SYNTH_LATTICE pass. 2.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 2.3. Executing HIERARCHY pass (managing design hierarchy). 2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_processor'. Generating RTLIL representation for module `\neural_processor'. Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193 Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151 Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122 Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121 2.4.1. Analyzing design hierarchy.. Top module: \neural_processor 2.4.2. Analyzing design hierarchy.. Top module: \neural_processor Removing unused module `$abstract\neural_processor'. Removed 1 unused modules. 2.5. Executing PROC pass (convert processes to netlists). 2.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$280 in module neural_processor. Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$275 in module neural_processor. Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$266 in module neural_processor. Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:305$261 in module neural_processor. Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:278$251 in module neural_processor. Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:245$238 in module neural_processor. Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:215$235 in module neural_processor. Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:143$234 in module neural_processor. Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:104$229 in module neural_processor. Removed a total of 0 dead cases. 2.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 15 redundant assignments. Promoted 25 assignments to connections. 2.5.4. Executing PROC_INIT pass (extract init attributes). 2.5.5. Executing PROC_ARST pass (detect async resets in processes). 2.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$306'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$305'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$304'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$303'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$302'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$301'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$300'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$299'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$297'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$295'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$293'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$291'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$289'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$287'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$285'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$283'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$281'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$280'. 1/2: $0\last_tree[2:2] 2/2: $0\valid_tree[2:2] Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$278'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$276'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$275'. 1/2: $0\last_tree[1:1] 2/2: $0\valid_tree[1:1] Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$273'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$271'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$269'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$267'. Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$266'. 1/2: $0\last_tree[0:0] 2/2: $0\valid_tree[0:0] Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. 1/8: $0\node_id_reg[15:0] 2/8: $0\activation_reg[1:0] 3/8: $0\bias_reg[7:0] 4/8: $0\np_error[0:0] 5/8: $0\np_state[3:0] 6/8: $0\result_node_id[15:0] 7/8: $0\result_data[7:0] 8/8: $0\result_valid[0:0] Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$251'. 1/2: $0\valid7[0:0] 2/2: $0\y7[7:0] Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$238'. 1/3: $0\last6[0:0] 2/3: $0\valid6[0:0] 3/3: $0\final_acc_reg[31:0] Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$235'. 1/3: $0\last5[0:0] 2/3: $0\valid5[0:0] 3/3: $0\acc_reg[31:0] Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. 1/11: $0\last1[0:0] 2/11: $0\valid1[0:0] 3/11: $4\gi[31:0] 4/11: $0\prod1[7][31:0] 5/11: $0\prod1[6][31:0] 6/11: $0\prod1[5][31:0] 7/11: $0\prod1[4][31:0] 8/11: $0\prod1[3][31:0] 9/11: $0\prod1[2][31:0] 10/11: $0\prod1[1][31:0] 11/11: $0\prod1[0][31:0] Creating decoders for process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. 1/20: $2\gi[31:0] 2/20: $0\last0[0:0] 3/20: $0\valid0[0:0] 4/20: $1\gi[31:0] 5/20: $0\w0[7][7:0] 6/20: $0\w0[6][7:0] 7/20: $0\w0[5][7:0] 8/20: $0\w0[4][7:0] 9/20: $0\w0[3][7:0] 10/20: $0\w0[2][7:0] 11/20: $0\w0[1][7:0] 12/20: $0\w0[0][7:0] 13/20: $0\x0[7][7:0] 14/20: $0\x0[6][7:0] 15/20: $0\x0[5][7:0] 16/20: $0\x0[4][7:0] 17/20: $0\x0[3][7:0] 18/20: $0\x0[2][7:0] 19/20: $0\x0[1][7:0] 20/20: $0\x0[0][7:0] 2.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\neural_processor.\level0[7]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$306'. No latch inferred for signal `\neural_processor.\level0[6]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$305'. No latch inferred for signal `\neural_processor.\level0[5]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$304'. No latch inferred for signal `\neural_processor.\level0[4]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$303'. No latch inferred for signal `\neural_processor.\level0[3]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$302'. No latch inferred for signal `\neural_processor.\level0[2]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$301'. No latch inferred for signal `\neural_processor.\level0[1]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$300'. No latch inferred for signal `\neural_processor.\level0[0]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$299'. No latch inferred for signal `\neural_processor.\product_comb[7]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$297'. No latch inferred for signal `\neural_processor.\product_comb[6]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$295'. No latch inferred for signal `\neural_processor.\product_comb[5]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$293'. No latch inferred for signal `\neural_processor.\product_comb[4]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$291'. No latch inferred for signal `\neural_processor.\product_comb[3]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$289'. No latch inferred for signal `\neural_processor.\product_comb[2]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$287'. No latch inferred for signal `\neural_processor.\product_comb[1]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$285'. No latch inferred for signal `\neural_processor.\product_comb[0]' from process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$283'. 2.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\neural_processor.\tree[16]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$281'. created $dff cell `$procdff$601' with positive edge clock. Creating register for signal `\neural_processor.\valid_tree [2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$280'. created $dff cell `$procdff$602' with positive edge clock. Creating register for signal `\neural_processor.\last_tree [2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$280'. created $dff cell `$procdff$603' with positive edge clock. Creating register for signal `\neural_processor.\tree[9]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$278'. created $dff cell `$procdff$604' with positive edge clock. Creating register for signal `\neural_processor.\tree[8]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$276'. created $dff cell `$procdff$605' with positive edge clock. Creating register for signal `\neural_processor.\valid_tree [1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$275'. created $dff cell `$procdff$606' with positive edge clock. Creating register for signal `\neural_processor.\last_tree [1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$275'. created $dff cell `$procdff$607' with positive edge clock. Creating register for signal `\neural_processor.\tree[3]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$273'. created $dff cell `$procdff$608' with positive edge clock. Creating register for signal `\neural_processor.\tree[2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$271'. created $dff cell `$procdff$609' with positive edge clock. Creating register for signal `\neural_processor.\tree[1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$269'. created $dff cell `$procdff$610' with positive edge clock. Creating register for signal `\neural_processor.\tree[0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$267'. created $dff cell `$procdff$611' with positive edge clock. Creating register for signal `\neural_processor.\valid_tree [0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$266'. created $dff cell `$procdff$612' with positive edge clock. Creating register for signal `\neural_processor.\last_tree [0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$266'. created $dff cell `$procdff$613' with positive edge clock. Creating register for signal `\neural_processor.\result_valid' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. created $dff cell `$procdff$614' with positive edge clock. Creating register for signal `\neural_processor.\result_data' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. created $dff cell `$procdff$615' with positive edge clock. Creating register for signal `\neural_processor.\result_node_id' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. created $dff cell `$procdff$616' with positive edge clock. Creating register for signal `\neural_processor.\np_state' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. created $dff cell `$procdff$617' with positive edge clock. Creating register for signal `\neural_processor.\np_error' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. created $dff cell `$procdff$618' with positive edge clock. Creating register for signal `\neural_processor.\bias_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. created $dff cell `$procdff$619' with positive edge clock. Creating register for signal `\neural_processor.\activation_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. created $dff cell `$procdff$620' with positive edge clock. Creating register for signal `\neural_processor.\node_id_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. created $dff cell `$procdff$621' with positive edge clock. Creating register for signal `\neural_processor.\valid7' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$251'. created $dff cell `$procdff$622' with positive edge clock. Creating register for signal `\neural_processor.\y7' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$251'. created $dff cell `$procdff$623' with positive edge clock. Creating register for signal `\neural_processor.\valid6' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$238'. created $dff cell `$procdff$624' with positive edge clock. Creating register for signal `\neural_processor.\last6' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$238'. created $dff cell `$procdff$625' with positive edge clock. Creating register for signal `\neural_processor.\final_acc_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$238'. created $dff cell `$procdff$626' with positive edge clock. Creating register for signal `\neural_processor.\acc_reg' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$235'. created $dff cell `$procdff$627' with positive edge clock. Creating register for signal `\neural_processor.\valid5' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$235'. created $dff cell `$procdff$628' with positive edge clock. Creating register for signal `\neural_processor.\last5' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$235'. created $dff cell `$procdff$629' with positive edge clock. Creating register for signal `\neural_processor.\gi' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$630' with positive edge clock. Creating register for signal `\neural_processor.\valid1' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$631' with positive edge clock. Creating register for signal `\neural_processor.\last1' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$632' with positive edge clock. Creating register for signal `\neural_processor.\prod1[0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$633' with positive edge clock. Creating register for signal `\neural_processor.\prod1[1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$634' with positive edge clock. Creating register for signal `\neural_processor.\prod1[2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$635' with positive edge clock. Creating register for signal `\neural_processor.\prod1[3]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$636' with positive edge clock. Creating register for signal `\neural_processor.\prod1[4]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$637' with positive edge clock. Creating register for signal `\neural_processor.\prod1[5]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$638' with positive edge clock. Creating register for signal `\neural_processor.\prod1[6]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$639' with positive edge clock. Creating register for signal `\neural_processor.\prod1[7]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. created $dff cell `$procdff$640' with positive edge clock. Creating register for signal `\neural_processor.\valid0' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$641' with positive edge clock. Creating register for signal `\neural_processor.\last0' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$642' with positive edge clock. Creating register for signal `\neural_processor.\gi' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$643' with positive edge clock. Creating register for signal `\neural_processor.\x0[0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$644' with positive edge clock. Creating register for signal `\neural_processor.\x0[1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$645' with positive edge clock. Creating register for signal `\neural_processor.\x0[2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$646' with positive edge clock. Creating register for signal `\neural_processor.\x0[3]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$647' with positive edge clock. Creating register for signal `\neural_processor.\x0[4]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$648' with positive edge clock. Creating register for signal `\neural_processor.\x0[5]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$649' with positive edge clock. Creating register for signal `\neural_processor.\x0[6]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$650' with positive edge clock. Creating register for signal `\neural_processor.\x0[7]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$651' with positive edge clock. Creating register for signal `\neural_processor.\w0[0]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$652' with positive edge clock. Creating register for signal `\neural_processor.\w0[1]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$653' with positive edge clock. Creating register for signal `\neural_processor.\w0[2]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$654' with positive edge clock. Creating register for signal `\neural_processor.\w0[3]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$655' with positive edge clock. Creating register for signal `\neural_processor.\w0[4]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$656' with positive edge clock. Creating register for signal `\neural_processor.\w0[5]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$657' with positive edge clock. Creating register for signal `\neural_processor.\w0[6]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$658' with positive edge clock. Creating register for signal `\neural_processor.\w0[7]' using process `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. created $dff cell `$procdff$659' with positive edge clock. 2.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$306'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$305'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$304'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$303'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$302'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$301'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$300'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$299'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$297'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$295'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$293'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$291'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$289'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$287'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$285'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$283'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$281'. Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$280'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$280'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$278'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$276'. Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$275'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$275'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$273'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$271'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$269'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$267'. Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$266'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$266'. Found and cleaned up 6 empty switches in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$261'. Found and cleaned up 2 empty switches in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$251'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$251'. Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$238'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$238'. Found and cleaned up 3 empty switches in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$235'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$235'. Found and cleaned up 1 empty switch in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$234'. Found and cleaned up 2 empty switches in `\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. Removing empty process `neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$229'. Cleaned up 18 empty switches. 2.5.12. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.6. Executing CHECK pass (checking for obvious problems). Checking module neural_processor... Warning: multiple conflicting drivers for neural_processor.\gi [31]: port Q[31] of cell $procdff$643 ($dff) port Q[31] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [30]: port Q[30] of cell $procdff$643 ($dff) port Q[30] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [29]: port Q[29] of cell $procdff$643 ($dff) port Q[29] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [28]: port Q[28] of cell $procdff$643 ($dff) port Q[28] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [27]: port Q[27] of cell $procdff$643 ($dff) port Q[27] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [26]: port Q[26] of cell $procdff$643 ($dff) port Q[26] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [25]: port Q[25] of cell $procdff$643 ($dff) port Q[25] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [24]: port Q[24] of cell $procdff$643 ($dff) port Q[24] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [23]: port Q[23] of cell $procdff$643 ($dff) port Q[23] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [22]: port Q[22] of cell $procdff$643 ($dff) port Q[22] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [21]: port Q[21] of cell $procdff$643 ($dff) port Q[21] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [20]: port Q[20] of cell $procdff$643 ($dff) port Q[20] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [19]: port Q[19] of cell $procdff$643 ($dff) port Q[19] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [18]: port Q[18] of cell $procdff$643 ($dff) port Q[18] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [17]: port Q[17] of cell $procdff$643 ($dff) port Q[17] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [16]: port Q[16] of cell $procdff$643 ($dff) port Q[16] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [15]: port Q[15] of cell $procdff$643 ($dff) port Q[15] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [14]: port Q[14] of cell $procdff$643 ($dff) port Q[14] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [13]: port Q[13] of cell $procdff$643 ($dff) port Q[13] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [12]: port Q[12] of cell $procdff$643 ($dff) port Q[12] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [11]: port Q[11] of cell $procdff$643 ($dff) port Q[11] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [10]: port Q[10] of cell $procdff$643 ($dff) port Q[10] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [9]: port Q[9] of cell $procdff$643 ($dff) port Q[9] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [8]: port Q[8] of cell $procdff$643 ($dff) port Q[8] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [7]: port Q[7] of cell $procdff$643 ($dff) port Q[7] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [6]: port Q[6] of cell $procdff$643 ($dff) port Q[6] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [5]: port Q[5] of cell $procdff$643 ($dff) port Q[5] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [4]: port Q[4] of cell $procdff$643 ($dff) port Q[4] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [3]: port Q[3] of cell $procdff$643 ($dff) port Q[3] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [2]: port Q[2] of cell $procdff$643 ($dff) port Q[2] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [1]: port Q[1] of cell $procdff$643 ($dff) port Q[1] of cell $procdff$630 ($dff) Warning: multiple conflicting drivers for neural_processor.\gi [0]: port Q[0] of cell $procdff$643 ($dff) port Q[0] of cell $procdff$630 ($dff) Found and reported 32 problems. 2.7. Executing FLATTEN pass (flatten design). 2.8. Executing TRIBUF pass. 2.9. Executing DEMINOUT pass (demote inout ports to input or output). 2.10. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 6 unused cells and 200 unused wires. 2.12. Executing CHECK pass (checking for obvious problems). Checking module neural_processor... Found and reported 0 problems. 2.13. Executing OPT pass (performing simple optimizations). 2.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 206 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Computing hashes of 193 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 13 cells. 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 193 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 0 unused cells and 13 unused wires. 2.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.13.9. Rerunning OPT passes. (Maybe there is more to do..) 2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 193 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.13.13. Executing OPT_DFF pass (perform DFF optimizations). 2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.13.16. Finished fast OPT passes. (There is nothing left to do.) 2.14. Executing FSM pass (extract and optimize FSM). 2.14.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking neural_processor.np_state as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. 2.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.15. Executing OPT pass (performing simple optimizations). 2.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 193 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 193 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.15.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$641 ($dff) from module neural_processor (D = $logic_and$hardware/v2/rtl/neural_processor.v:109$230_Y, Q = \valid0, rval = 1'0). Adding SRST signal on $procdff$642 ($dff) from module neural_processor (D = \tile_last, Q = \last0, rval = 1'0). Adding EN signal on $procdff$654 ($dff) from module neural_processor (D = \weight_data [23:16], Q = \w0[2]). Adding EN signal on $procdff$644 ($dff) from module neural_processor (D = \input_data [7:0], Q = \x0[0]). Adding EN signal on $procdff$645 ($dff) from module neural_processor (D = \input_data [15:8], Q = \x0[1]). Adding EN signal on $procdff$646 ($dff) from module neural_processor (D = \input_data [23:16], Q = \x0[2]). Adding EN signal on $procdff$647 ($dff) from module neural_processor (D = \input_data [31:24], Q = \x0[3]). Adding EN signal on $procdff$648 ($dff) from module neural_processor (D = \input_data [39:32], Q = \x0[4]). Adding EN signal on $procdff$649 ($dff) from module neural_processor (D = \input_data [47:40], Q = \x0[5]). Adding EN signal on $procdff$650 ($dff) from module neural_processor (D = \input_data [55:48], Q = \x0[6]). Adding EN signal on $procdff$651 ($dff) from module neural_processor (D = \input_data [63:56], Q = \x0[7]). Adding EN signal on $procdff$652 ($dff) from module neural_processor (D = \weight_data [7:0], Q = \w0[0]). Adding EN signal on $procdff$653 ($dff) from module neural_processor (D = \weight_data [15:8], Q = \w0[1]). Adding EN signal on $procdff$659 ($dff) from module neural_processor (D = \weight_data [63:56], Q = \w0[7]). Adding EN signal on $procdff$658 ($dff) from module neural_processor (D = \weight_data [55:48], Q = \w0[6]). Adding EN signal on $procdff$657 ($dff) from module neural_processor (D = \weight_data [47:40], Q = \w0[5]). Adding EN signal on $procdff$656 ($dff) from module neural_processor (D = \weight_data [39:32], Q = \w0[4]). Adding SRST signal on $procdff$602 ($dff) from module neural_processor (D = \valid_tree [1], Q = \valid_tree [2], rval = 1'0). Adding SRST signal on $procdff$603 ($dff) from module neural_processor (D = \last_tree [1], Q = \last_tree [2], rval = 1'0). Adding SRST signal on $procdff$606 ($dff) from module neural_processor (D = \valid_tree [0], Q = \valid_tree [1], rval = 1'0). Adding SRST signal on $procdff$607 ($dff) from module neural_processor (D = \last_tree [0], Q = \last_tree [1], rval = 1'0). Adding SRST signal on $procdff$612 ($dff) from module neural_processor (D = \valid1, Q = \valid_tree [0], rval = 1'0). Adding SRST signal on $procdff$613 ($dff) from module neural_processor (D = \last1, Q = \last_tree [0], rval = 1'0). Adding SRST signal on $procdff$614 ($dff) from module neural_processor (D = $procmux$417_Y, Q = \result_valid, rval = 1'0). Adding EN signal on $auto$ff.cc:337:slice$747 ($sdff) from module neural_processor (D = $procmux$417_Y, Q = \result_valid). Adding SRST signal on $procdff$615 ($dff) from module neural_processor (D = $procmux$407_Y, Q = \result_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$757 ($sdff) from module neural_processor (D = \y7, Q = \result_data). Adding SRST signal on $procdff$616 ($dff) from module neural_processor (D = $procmux$396_Y, Q = \result_node_id, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$761 ($sdff) from module neural_processor (D = \node_id_reg, Q = \result_node_id). Adding SRST signal on $procdff$617 ($dff) from module neural_processor (D = $procmux$371_Y, Q = \np_state, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$765 ($sdff) from module neural_processor (D = $procmux$371_Y, Q = \np_state). Adding EN signal on $procdff$618 ($dff) from module neural_processor (D = 1'0, Q = \np_error). Adding SRST signal on $procdff$619 ($dff) from module neural_processor (D = $procmux$362_Y, Q = \bias_reg, rval = 8'00000000). Adding EN signal on $auto$ff.cc:337:slice$780 ($sdff) from module neural_processor (D = \job_bias, Q = \bias_reg). Adding SRST signal on $procdff$620 ($dff) from module neural_processor (D = $procmux$348_Y, Q = \activation_reg, rval = 2'01). Adding EN signal on $auto$ff.cc:337:slice$784 ($sdff) from module neural_processor (D = \job_activation, Q = \activation_reg). Adding SRST signal on $procdff$621 ($dff) from module neural_processor (D = $procmux$334_Y, Q = \node_id_reg, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:337:slice$788 ($sdff) from module neural_processor (D = \job_node_id, Q = \node_id_reg). Adding SRST signal on $procdff$622 ($dff) from module neural_processor (D = \last6, Q = \valid7, rval = 1'0). Adding EN signal on $procdff$623 ($dff) from module neural_processor (D = $procmux$429_Y, Q = \y7). Adding SRST signal on $procdff$624 ($dff) from module neural_processor (D = \valid5, Q = \valid6, rval = 1'0). Adding SRST signal on $procdff$625 ($dff) from module neural_processor (D = \last5, Q = \last6, rval = 1'0). Adding EN signal on $procdff$626 ($dff) from module neural_processor (D = $add$hardware/v2/rtl/neural_processor.v:252$239_Y, Q = \final_acc_reg). Adding SRST signal on $procdff$627 ($dff) from module neural_processor (D = $procmux$449_Y, Q = \acc_reg, rval = 0). Adding EN signal on $auto$ff.cc:337:slice$797 ($sdff) from module neural_processor (D = $add$hardware/v2/rtl/neural_processor.v:226$237_Y, Q = \acc_reg). Adding SRST signal on $procdff$628 ($dff) from module neural_processor (D = \valid_tree [2], Q = \valid5, rval = 1'0). Adding SRST signal on $procdff$629 ($dff) from module neural_processor (D = \last_tree [2], Q = \last5, rval = 1'0). Adding EN signal on $procdff$655 ($dff) from module neural_processor (D = \weight_data [31:24], Q = \w0[3]). Adding SRST signal on $procdff$631 ($dff) from module neural_processor (D = \valid0, Q = \valid1, rval = 1'0). Adding SRST signal on $procdff$632 ($dff) from module neural_processor (D = \last0, Q = \last1, rval = 1'0). Adding EN signal on $procdff$633 ($dff) from module neural_processor (D = { \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] [15] \product_comb[0] }, Q = \prod1[0]). Adding EN signal on $procdff$634 ($dff) from module neural_processor (D = { \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] [15] \product_comb[1] }, Q = \prod1[1]). Adding EN signal on $procdff$635 ($dff) from module neural_processor (D = { \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] [15] \product_comb[2] }, Q = \prod1[2]). Adding EN signal on $procdff$636 ($dff) from module neural_processor (D = { \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] [15] \product_comb[3] }, Q = \prod1[3]). Adding EN signal on $procdff$637 ($dff) from module neural_processor (D = { \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] [15] \product_comb[4] }, Q = \prod1[4]). Adding EN signal on $procdff$638 ($dff) from module neural_processor (D = { \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] [15] \product_comb[5] }, Q = \prod1[5]). Adding EN signal on $procdff$639 ($dff) from module neural_processor (D = { \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] [15] \product_comb[6] }, Q = \prod1[6]). Adding EN signal on $procdff$640 ($dff) from module neural_processor (D = { \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] [15] \product_comb[7] }, Q = \prod1[7]). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$779 ($dffe) from module neural_processor. 2.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 79 unused cells and 79 unused wires. 2.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.15.9. Rerunning OPT passes. (Maybe there is more to do..) 2.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 163 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Computing hashes of 143 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Computing hashes of 128 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 35 cells. 2.15.13. Executing OPT_DFF pass (perform DFF optimizations). 2.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 0 unused cells and 35 unused wires. 2.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.15.16. Rerunning OPT passes. (Maybe there is more to do..) 2.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.15.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 128 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.15.20. Executing OPT_DFF pass (perform DFF optimizations). 2.15.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.15.22. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.15.23. Finished fast OPT passes. (There is nothing left to do.) 2.16. Executing WREDUCE pass (reducing word size of cells). Removed top 16 bits (of 32) from FF cell neural_processor.$auto$ff.cc:337:slice$817 ($dffe). Removed top 16 bits (of 32) from FF cell neural_processor.$auto$ff.cc:337:slice$816 ($dffe). Removed top 16 bits (of 32) from FF cell neural_processor.$auto$ff.cc:337:slice$815 ($dffe). Removed top 16 bits (of 32) from FF cell neural_processor.$auto$ff.cc:337:slice$814 ($dffe). Removed top 16 bits (of 32) from FF cell neural_processor.$auto$ff.cc:337:slice$813 ($dffe). Removed top 16 bits (of 32) from FF cell neural_processor.$auto$ff.cc:337:slice$812 ($dffe). Removed top 16 bits (of 32) from FF cell neural_processor.$auto$ff.cc:337:slice$811 ($dffe). Removed top 16 bits (of 32) from FF cell neural_processor.$auto$ff.cc:337:slice$810 ($dffe). Removed top 1 bits (of 2) from port B of cell neural_processor.$auto$opt_dff.cc:320:make_patterns_logic$772 ($ne). Removed top 1 bits (of 2) from port B of cell neural_processor.$auto$opt_dff.cc:320:make_patterns_logic$768 ($ne). Removed top 24 bits (of 32) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:252$239 ($add). Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$268 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$268 ($add). Removed top 16 bits (of 32) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$268 ($add). Removed top 15 bits (of 32) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$268 ($add). Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$270 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$270 ($add). Removed top 16 bits (of 32) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$270 ($add). Removed top 15 bits (of 32) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$270 ($add). Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$272 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$272 ($add). Removed top 16 bits (of 32) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$272 ($add). Removed top 15 bits (of 32) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$272 ($add). Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$274 ($add) from unsigned to signed. Removed top 16 bits (of 32) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$274 ($add). Removed top 16 bits (of 32) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$274 ($add). Removed top 15 bits (of 32) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:193$274 ($add). Removed top 1 bits (of 4) from port B of cell neural_processor.$procmux$372_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell neural_processor.$procmux$373_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell neural_processor.$procmux$382_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell neural_processor.$procmux$383_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell neural_processor.$procmux$418_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell neural_processor.$procmux$421_CMP0 ($eq). Removed top 15 bits (of 32) from FF cell neural_processor.$procdff$608 ($dff). Removed top 15 bits (of 32) from FF cell neural_processor.$procdff$609 ($dff). Removed top 15 bits (of 32) from FF cell neural_processor.$procdff$610 ($dff). Removed top 15 bits (of 32) from FF cell neural_processor.$procdff$611 ($dff). Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$277 ($add) from unsigned to signed. Removed top 15 bits (of 32) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$277 ($add). Removed top 15 bits (of 32) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$277 ($add). Removed top 14 bits (of 32) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$277 ($add). Converting cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$279 ($add) from unsigned to signed. Removed top 15 bits (of 32) from port A of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$279 ($add). Removed top 15 bits (of 32) from port B of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$279 ($add). Removed top 14 bits (of 32) from port Y of cell neural_processor.$add$hardware/v2/rtl/neural_processor.v:197$279 ($add). 2.17. Executing PEEPOPT pass (run peephole optimizers). 2.18. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.19. Executing SHARE pass (SAT-based resource sharing). 2.20. Executing TECHMAP pass (map to technology primitives). 2.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.20.2. Continuing TECHMAP pass. No more expansions possible. 2.21. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.22. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 2.23.2. Continuing TECHMAP pass. Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul. No more expansions possible. 2.24. Executing TECHMAP pass (map to technology primitives). 2.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 2.24.2. Continuing TECHMAP pass. Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. 2.25. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module neural_processor: creating $macc model for $add$hardware/v2/rtl/neural_processor.v:197$282 ($add). creating $macc model for $add$hardware/v2/rtl/neural_processor.v:197$279 ($add). creating $macc model for $add$hardware/v2/rtl/neural_processor.v:197$277 ($add). creating $macc model for $add$hardware/v2/rtl/neural_processor.v:193$274 ($add). creating $macc model for $add$hardware/v2/rtl/neural_processor.v:193$272 ($add). creating $macc model for $add$hardware/v2/rtl/neural_processor.v:193$270 ($add). creating $macc model for $add$hardware/v2/rtl/neural_processor.v:193$268 ($add). creating $macc model for $add$hardware/v2/rtl/neural_processor.v:252$239 ($add). creating $macc model for $add$hardware/v2/rtl/neural_processor.v:226$237 ($add). creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:226$237. creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:252$239. creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:193$268. creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:193$270. creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:193$272. creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:193$274. creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:197$277. creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:197$279. creating $alu model for $macc $add$hardware/v2/rtl/neural_processor.v:197$282. creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:197$282: $auto$alumacc.cc:548:replace_alu$835 creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:197$279: $auto$alumacc.cc:548:replace_alu$838 creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:197$277: $auto$alumacc.cc:548:replace_alu$841 creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:193$274: $auto$alumacc.cc:548:replace_alu$844 creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:193$272: $auto$alumacc.cc:548:replace_alu$847 creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:193$270: $auto$alumacc.cc:548:replace_alu$850 creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:193$268: $auto$alumacc.cc:548:replace_alu$853 creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:252$239: $auto$alumacc.cc:548:replace_alu$856 creating $alu cell for $add$hardware/v2/rtl/neural_processor.v:226$237: $auto$alumacc.cc:548:replace_alu$859 created 9 $alu and 0 $macc cells. 2.26. Executing OPT pass (performing simple optimizations). 2.26.1. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.26.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 128 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.26.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 128 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.26.6. Executing OPT_DFF pass (perform DFF optimizations). 2.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 0 unused cells and 64 unused wires. 2.26.8. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.26.9. Rerunning OPT passes. (Maybe there is more to do..) 2.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.26.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 128 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.26.13. Executing OPT_DFF pass (perform DFF optimizations). 2.26.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.26.15. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.26.16. Finished fast OPT passes. (There is nothing left to do.) 2.27. Executing MEMORY pass. 2.27.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2.30. Executing TECHMAP pass (map to technology primitives). 2.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 2.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 2.30.3. Continuing TECHMAP pass. No more expansions possible. 2.31. Executing OPT pass (performing simple optimizations). 2.31.1. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.31.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 122 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.31.3. Executing OPT_DFF pass (perform DFF optimizations). 2.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 0 unused cells and 6 unused wires. 2.31.5. Finished fast OPT passes. 2.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.33. Executing OPT pass (performing simple optimizations). 2.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 122 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Consolidated identical input bits for $pmux cell $procmux$371: Old ports: A=4'0110, B=24'000100100011010001010000, Y=$procmux$371_Y New ports: A=3'110, B=18'001010011100101000, Y=$procmux$371_Y [2:0] New connections: $procmux$371_Y [3] = 1'0 Consolidated identical input bits for $mux cell $ternary$hardware/v2/rtl/neural_processor.v:264$247: Old ports: A=8'01111111, B=8'10000000, Y=$ternary$hardware/v2/rtl/neural_processor.v:264$247_Y New ports: A=2'01, B=2'10, Y={ $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [7] $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [0] } New connections: $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [6:1] = { $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [0] $ternary$hardware/v2/rtl/neural_processor.v:264$247_Y [0] } Optimizing cells in module \neural_processor. Performed a total of 2 changes. 2.33.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 122 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.33.6. Executing OPT_DFF pass (perform DFF optimizations). 2.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.33.9. Rerunning OPT passes. (Maybe there is more to do..) 2.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.33.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 122 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.33.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$766 ($sdffe) from module neural_processor. 2.33.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.33.15. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.33.16. Rerunning OPT passes. (Maybe there is more to do..) 2.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.33.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 122 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.33.20. Executing OPT_DFF pass (perform DFF optimizations). 2.33.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.33.22. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.33.23. Finished fast OPT passes. (There is nothing left to do.) 2.34. Executing TECHMAP pass (map to technology primitives). 2.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 2.34.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ccu2c_alu for cells of type $alu. Using template $paramod$8fdcfe020be5e507ba05385ffd706e02b549d39d\_80_ccu2c_alu for cells of type $alu. Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu. Using template $paramod$5e21cfa2ff6d644e10a0fc1dcdb22e5eb183bcd3\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $pos. No more expansions possible. 2.35. Executing OPT pass (performing simple optimizations). 2.35.1. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.35.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 1652 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Computing hashes of 1604 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Computing hashes of 1562 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 90 cells. 2.35.3. Executing OPT_DFF pass (perform DFF optimizations). 2.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 740 unused cells and 657 unused wires. 2.35.5. Finished fast OPT passes. 2.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 822 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $paramod$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_. Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. No more expansions possible. 2.40. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in neural_processor. 2.43. Executing ATTRMVCP pass (move or copy attributes). 2.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 0 unused cells and 2615 unused wires. 2.45. Executing CHECK pass (checking for obvious problems). Checking module neural_processor... Found and reported 0 problems. 2.46. Executing TECHMAP pass (map to technology primitives). 2.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 2.46.2. Continuing TECHMAP pass. No more expansions possible. 2.47. Executing ABC9 pass. 2.47.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module neural_processor. Found 0 SCCs. 2.47.4. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.5. Executing TECHMAP pass (map to technology primitives). 2.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.47.5.2. Continuing TECHMAP pass. No more expansions possible. 2.47.6. Executing OPT pass (performing simple optimizations). 2.47.6.1. Executing OPT_EXPR pass (perform const folding). 2.47.6.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 2.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 2.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 2.47.6.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 2.47.6.6. Executing OPT_DFF pass (perform DFF optimizations). 2.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2.47.6.8. Executing OPT_EXPR pass (perform const folding). 2.47.6.9. Finished fast OPT passes. (There is nothing left to do.) 2.47.7. Executing TECHMAP pass (map to technology primitives). 2.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 2.47.7.2. Continuing TECHMAP pass. No more expansions possible. 2.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 2.47.9. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.10. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.11. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.12. Executing TECHMAP pass (map to technology primitives). 2.47.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.47.12.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $mux. No more expansions possible. 2.47.13. Executing OPT pass (performing simple optimizations). 2.47.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.47.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 59 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Computing hashes of 57 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 2 cells. 2.47.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.47.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.47.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 57 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.47.13.6. Executing OPT_DFF pass (perform DFF optimizations). 2.47.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. Removed 0 unused cells and 55 unused wires. 2.47.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.47.13.9. Rerunning OPT passes. (Maybe there is more to do..) 2.47.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \neural_processor.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.47.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \neural_processor. Performed a total of 0 changes. 2.47.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\neural_processor'. Computing hashes of 57 cells of `\neural_processor'. Finding duplicate cells in `\neural_processor'. Removed a total of 0 cells. 2.47.13.13. Executing OPT_DFF pass (perform DFF optimizations). 2.47.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \neural_processor.. 2.47.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module neural_processor. 2.47.13.16. Finished fast OPT passes. (There is nothing left to do.) 2.47.14. Executing AIGMAP pass (map logic to AIG). Module neural_processor: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 14 $_MUX_ 2 $_OR_ 2 $_XOR_ not replaced 3 cell types: 4 $_AND_ 4 $_NOT_ 31 $specify2 2.47.15. Executing AIGMAP pass (map logic to AIG). Module neural_processor: replaced 126 cells with 609 new cells, skipped 696 cells. replaced 2 cell types: 35 $_MUX_ 91 $_OR_ not replaced 5 cell types: 38 $_AND_ 15 $_NOT_ 533 TRELLIS_FF 8 MULT18X18D 102 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 2.47.15.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.15.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.47.15.3. Executing XAIGER backend. Extracted 234 AND gates and 1855 wires from module `neural_processor' to a netlist network with 821 inputs and 545 outputs. 2.47.15.4. Executing ABC9_EXE pass (technology mapping using ABC9). 2.47.15.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 821/ 545 and = 198 lev = 12 (0.11) mem = 0.04 MB box = 102 bb = 0 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 821/ 545 and = 245 lev = 10 (0.09) mem = 0.04 MB ch = 22 box = 96 bb = 0 ABC: cst = 0 cls = 19 lit = 22 unused = 1313 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 245. Ch = 19. Total mem = 0.45 MB. Peak cut mem = 0.02 MB. ABC: P: Del = 2426.00. Ar = 147.0. Edge = 230. Cut = 1868. T = 0.00 sec ABC: P: Del = 2426.00. Ar = 168.0. Edge = 253. Cut = 1938. T = 0.00 sec ABC: P: Del = 2426.00. Ar = 118.0. Edge = 243. Cut = 3491. T = 0.00 sec ABC: F: Del = 2385.00. Ar = 89.0. Edge = 206. Cut = 2386. T = 0.00 sec ABC: A: Del = 2385.00. Ar = 84.0. Edge = 195. Cut = 2188. T = 0.00 sec ABC: A: Del = 2385.00. Ar = 84.0. Edge = 194. Cut = 2177. T = 0.00 sec ABC: Total time = 0.00 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: + &ps -l ABC: /input : i/o = 821/ 545 and = 129 lev = 10 (0.09) mem = 0.04 MB box = 96 bb = 0 ABC: Mapping (K=6) : lut = 45 edge = 160 lev = 5 (0.05) levB = 16 mem = 0.01 MB ABC: LUT = 45 : 2=12 26.7 % 3=4 8.9 % 4=22 48.9 % 5=6 13.3 % 6=1 2.2 % Ave = 3.56 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.01 sec ABC: + time ABC: elapse: 0.04 seconds, total: 0.04 seconds 2.47.15.6. Executing AIGER frontend. Removed 172 unused cells and 2355 unused wires. 2.47.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 46 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 96 ABC RESULTS: input signals: 32 ABC RESULTS: output signals: 64 Removing temp directory. 2.47.16. Executing TECHMAP pass (map to technology primitives). 2.47.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 2.47.16.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. No more expansions possible. Removed 3 unused cells and 3288 unused wires. 2.48. Executing TECHMAP pass (map to technology primitives). 2.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 2.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3$lut for cells of type $lut. Using template $paramod$1c0b02bad8ada563354b10a04b512fba38cd212e$lut for cells of type $lut. Using template $paramod$a87031c2ad22c31d10ffb6798d33e1e3354ff4f9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut. Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e$lut for cells of type $lut. Using template $paramod$cae45ff85b946d8cfe295bf4feda7db55ee71cea$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. No more expansions possible. 2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in neural_processor. Optimizing lut $abc$5518$lut$aiger5517$1150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5518$lut$aiger5517$1199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$5518$lut$aiger5517$1189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$5518$lut$aiger5517$1181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5518$lut$aiger5517$1164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5518$lut$aiger5517$1150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$5518$lut$aiger5517$1154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5518$lut$aiger5517$1150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5518$lut$aiger5517$1145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 108 unused wires. 2.50. Executing AUTONAME pass. Renamed 856 objects in module neural_processor. 2.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `neural_processor'. Setting top module to neural_processor. 2.51.1. Analyzing design hierarchy.. Top module: \neural_processor 2.51.2. Analyzing design hierarchy.. Top module: \neural_processor Removed 0 unused modules. 2.52. Printing statistics. === neural_processor === +----------Local Count, excluding submodules. | 242 wires 2031 wire bits 242 public wires 2031 public wire bits 18 ports 192 port bits 8 cells 8 MULT18X18D 693 submodules 96 CCU2C 1 L6MUX21 55 LUT4 8 PFUMX 533 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 8 neural_processor +----------Count including submodules. | 242 wires 2031 wire bits 242 public wires 2031 public wire bits 18 ports 192 port bits - memories - memory bits - processes 8 cells 8 MULT18X18D 693 submodules 96 CCU2C 1 L6MUX21 55 LUT4 8 PFUMX 533 TRELLIS_FF 2.53. Executing CHECK pass (checking for obvious problems). Checking module neural_processor... Found and reported 0 problems. 2.54. Executing JSON backend. Warnings: 36 unique messages, 36 total End of script. Logfile hash: 07cd07051f, time: 0.43s, user: 0.34s, system: 0.03s, MEM: 42.59 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 44% 21x read_verilog (0 sec), 12% 1x abc9_exe (0 sec), ...