# V2 simulation log -- solo append, mai troncato/sovrascritto (vedi README.md)
# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.

[2026-09-05] EXP-0001/EXP-0002 -- hardware/v2/sim/tb_neural_processor.v
test: 7 cases (16/32/8/8/8/8/64-input jobs; ACT_NONE + ACT_RELU;
  extreme INT8 saturation; back-to-back zero-idle-gap tiles)
vectors: regular positive, mixed-sign cancellation, extreme INT8
  (-128,-127,-1,0,1,126,127,127 in one 8-lane tile), back-to-back
  jobs, 8-tile (64-input) job
simulator: Verilator 5.050 (--binary --timing) -- see decisions.log
  DEC-0004 for why Icarus v13.0 is not trusted for this testbench
cycles: not separately profiled at this milestone (throughput/stall
  cycle counting deferred to M9 per §22)
PASS/FAIL: 7/7 PASS (ACC_WIDTH=32); 7/7 PASS (ACC_WIDTH=24, EXP-0002)
bit-exact result: V1.y === V2.result_data for every case, both widths
stall cycles / memory wait / utilization: N/A (no Memory Manager yet,
  M1 operands fed directly by testbench per the roadmap)

[2026-09-05] EXP-0003 -- hardware/v2/sim/tb_neural_processor_array.v
(N_PROCESSORS=4)
test: 7 cases (single-processor sanity; 4-way same-cycle concurrent
  launch with different tile counts; staggered-start 2-processor test)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 7/7 PASS
bit-exact result: N/A at this milestone (hand-computed expected
  values, arithmetic itself already bit-exact-certified vs V1 at M1)
concurrency: confirmed genuine -- in the staggered test, the
  later-launched, shorter job (processor 1) completes BEFORE the
  earlier-launched, longer job (processor 0), proving independent
  progress rather than serialization.

[2026-09-05] EXP-0004 -- hardware/v2/sim/tb_buffers.v
test: 10 cases across activation_buffer/weight_buffer/result_buffer
vectors: extreme INT8 (-128, 127, -100, 100), regular values, full
  64-bit tile round-trip (weight_buffer), re-reads confirming earlier
  writes undisturbed
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 10/10 PASS

[2026-09-05] EXP-0005 -- hardware/v2/sim/tb_memory_manager.v
test: 3 end-to-end jobs (3-tile/saturating, 1-tile/non-saturating,
  5-tile/steady-state-swap), real V1 PSRAM backend chain (unmodified),
  real M1 neural_processor
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 3/3 PASS
bit-exact result: PSRAM-read-back result byte matches hand-computed
  expectation in every case (independent oracle, not derived from the
  RTL under test)
cycles: 446 (3 tiles), 166 (1 tile), 728 (5 tiles) -- real PSRAM
  latency dominates, not memory_manager's own control overhead