Info: Logic utilisation before packing: Info: Total LUT4s: 72/43848 0% Info: logic LUTs: 24/43848 0% Info: carry LUTs: 0/43848 0% Info: RAM LUTs: 32/ 5481 0% Info: RAMW LUTs: 16/10962 0% Info: Total DFFs: 72/43848 0% Info: Packing IOs.. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 40 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x08e681ff Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 72/ 43848 0% Info: TRELLIS_COMB: 74/ 43848 0% Info: TRELLIS_RAMW: 8/ 5481 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 57 cells, random placement wirelen = 5888. Info: at initial placer iter 0, wirelen = 1162 Info: at initial placer iter 1, wirelen = 1051 Info: at initial placer iter 2, wirelen = 1014 Info: at initial placer iter 3, wirelen = 984 Info: Running main analytical placer, max placement attempts per cell = 10000. Info: at iteration #1, type ALL: wirelen solved = 983, spread = 1123, legal = 1130; time = 0.00s Info: HeAP Placer Time: 0.02s Info: of which solving equations: 0.00s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 15, wirelen = 1130 Info: at iteration #5: temp = 0.000000, timing cost = 22, wirelen = 763 Info: at iteration #10: temp = 0.000000, timing cost = 30, wirelen = 741 Info: at iteration #14: temp = 0.000000, timing cost = 18, wirelen = 742 Info: SA placement time 0.02s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 432.34 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.71 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.61 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 10187, 10265) |* Info: [ 10265, 10343) |*** Info: [ 10343, 10421) | Info: [ 10421, 10499) |**** Info: [ 10499, 10577) | Info: [ 10577, 10655) |****** Info: [ 10655, 10733) |**** Info: [ 10733, 10811) |********************************** Info: [ 10811, 10889) |*************** Info: [ 10889, 10967) |************* Info: [ 10967, 11045) |******************************* Info: [ 11045, 11123) |****************************************************** Info: [ 11123, 11201) |***** Info: [ 11201, 11279) |************************************************ Info: [ 11279, 11357) |**************** Info: [ 11357, 11435) |********* Info: [ 11435, 11513) |************** Info: [ 11513, 11591) |* Info: [ 11591, 11669) |*************** Info: [ 11669, 11747) |*********** Info: Checksum: 0x3a3fcdd5 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 532 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 687 | 134 545 | 134 545 | 0| 0.05 0.05| Info: Routing complete. Info: Router1 time 0.05s Info: Checksum: 0x452b9643 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[2].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_7.Q Info: routing 0.75 1.14 Net rd_data_flat[135] (36,12) -> (35,11) Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT_LUT4_Z.B Info: Defined in: Info: hardware/v2/nms/rtl/nms_weight_packed.v:30.50-30.62 Info: logic 0.18 1.32 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT_LUT4_Z.F Info: routing 0.00 1.32 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT (35,11) -> (35,11) Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.F1 Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24 Info: logic 0.13 1.45 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.OFX Info: routing 0.46 1.91 Net chk_TRELLIS_FF_Q_DI[7] (35,11) -> (36,11) Info: Sink chk_TRELLIS_FF_Q_7.M Info: setup 0.00 1.91 Source chk_TRELLIS_FF_Q_7.M Info: 0.70 ns logic, 1.21 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source rst$tr_io.O Info: routing 3.14 3.14 Net rst$TRELLIS_IO_IN (90,11) -> (34,14) Info: Sink seed_LUT4_B_Z_LUT4_Z_2.C Info: Defined in: Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:13.17-13.20 Info: logic 0.18 3.32 Source seed_LUT4_B_Z_LUT4_Z_2.F Info: routing 0.12 3.44 Net seed_LUT4_B_Z[6] (34,14) -> (34,14) Info: Sink lfsr_TRELLIS_FF_Q_7.DI Info: setup 0.00 3.44 Source lfsr_TRELLIS_FF_Q_7.DI Info: 0.18 ns logic, 3.26 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_6.Q Info: routing 2.79 3.18 Net checksum[6]$TRELLIS_IO_OUT (35,13) -> (90,14) Info: Sink checksum[6]$tr_io.I Info: Defined in: Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:40.15-40.18 Info: 0.40 ns logic, 2.79 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 523.29 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.44 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 3.18 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 10589, 10650) |*** Info: [ 10650, 10711) |*************** Info: [ 10711, 10772) |**** Info: [ 10772, 10833) |** Info: [ 10833, 10894) |****************** Info: [ 10894, 10955) |******************* Info: [ 10955, 11016) |***** Info: [ 11016, 11077) |************ Info: [ 11077, 11138) |************************ Info: [ 11138, 11199) |*********************** Info: [ 11199, 11260) |****************** Info: [ 11260, 11321) |******************* Info: [ 11321, 11382) |****************************** Info: [ 11382, 11443) |******************************* Info: [ 11443, 11504) |** Info: [ 11504, 11565) |**************** Info: [ 11565, 11626) |****************** Info: [ 11626, 11687) |********* Info: [ 11687, 11748) |********** Info: [ 11748, 11809) |****** Info: Program finished normally.