/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) -- Running command `read_verilog hardware/v2/nms/rtl/nms_weight_direct.v hardware/v2/nms/synthesis/harness_nms_weight_direct.v; chparam -set N_SLOTS 2 -set MAX_TILES 256 harness_nms_weight_direct; synth_ecp5 -json hardware/v2/nms/synthesis/wt_direct_n2_t256/top.json -top harness_nms_weight_direct' -- 1. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_weight_direct.v Parsing Verilog input from `hardware/v2/nms/rtl/nms_weight_direct.v' to AST representation. Generating RTLIL representation for module `\nms_weight_direct'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: hardware/v2/nms/synthesis/harness_nms_weight_direct.v Parsing Verilog input from `hardware/v2/nms/synthesis/harness_nms_weight_direct.v' to AST representation. Generating RTLIL representation for module `\harness_nms_weight_direct'. Successfully finished Verilog frontend. Parameter \N_SLOTS = 2 Parameter \MAX_TILES = 256 3. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_nms_weight_direct'. Parameter \N_SLOTS = 2 Parameter \MAX_TILES = 256 Generating RTLIL representation for module `$paramod$7193915ee0431049e824335a3ae9bf45b4132570\harness_nms_weight_direct'. 4. Executing SYNTH_LATTICE pass. 4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 4.3. Executing HIERARCHY pass (managing design hierarchy). 4.3.1. Analyzing design hierarchy.. Top module: \harness_nms_weight_direct Used module: \nms_weight_direct Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \N_SLOTS = 2 Parameter \MAX_TILES = 256 4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_weight_direct'. Parameter \DATA_WIDTH = 8 Parameter \P_IN = 8 Parameter \N_SLOTS = 2 Parameter \MAX_TILES = 256 Generating RTLIL representation for module `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct'. 4.3.3. Analyzing design hierarchy.. Top module: \harness_nms_weight_direct Used module: $paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct 4.3.4. Analyzing design hierarchy.. Top module: \harness_nms_weight_direct Used module: $paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct Removing unused module `\nms_weight_direct'. Removed 1 unused modules. 4.4. Executing PROC pass (convert processes to netlists). 4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:19$48 in module harness_nms_weight_direct. Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:41$53 in module harness_nms_weight_direct. Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$291 in module $paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct. Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$283 in module $paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct. Removed a total of 0 dead cases. 4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 2 redundant assignments. Promoted 8 assignments to connections. 4.4.4. Executing PROC_INIT pass (extract init attributes). 4.4.5. Executing PROC_ARST pass (detect async resets in processes). 4.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:19$48'. 1/1: $0\lfsr[31:0] Creating decoders for process `\harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:41$53'. 1/3: $0\chk[7:0] 2/3: $1\chk_next[7:0] 3/3: $1\k[31:0] Creating decoders for process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$291'. 1/4: $1$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$297 2/4: $1$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_DATA[63:0]$296 3/4: $1$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_ADDR[7:0]$295 4/4: $0\GEN_SLOT[1].rd_data_reg[63:0] Creating decoders for process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$283'. 1/4: $1$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$289 2/4: $1$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_DATA[63:0]$288 3/4: $1$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_ADDR[7:0]$287 4/4: $0\GEN_SLOT[0].rd_data_reg[63:0] 4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 4.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\harness_nms_weight_direct.\lfsr' using process `\harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:19$48'. created $dff cell `$procdff$333' with positive edge clock. Creating register for signal `\harness_nms_weight_direct.\k' using process `\harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:41$53'. created $dff cell `$procdff$334' with positive edge clock. Creating register for signal `\harness_nms_weight_direct.\chk' using process `\harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:41$53'. created $dff cell `$procdff$335' with positive edge clock. Creating register for signal `\harness_nms_weight_direct.\chk_next' using process `\harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:41$53'. created $dff cell `$procdff$336' with positive edge clock. Creating register for signal `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.\GEN_SLOT[1].rd_data_reg' using process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$291'. created $dff cell `$procdff$337' with positive edge clock. Creating register for signal `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_ADDR' using process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$291'. created $dff cell `$procdff$338' with positive edge clock. Creating register for signal `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_DATA' using process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$291'. created $dff cell `$procdff$339' with positive edge clock. Creating register for signal `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN' using process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$291'. created $dff cell `$procdff$340' with positive edge clock. Creating register for signal `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.\GEN_SLOT[0].rd_data_reg' using process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$283'. created $dff cell `$procdff$341' with positive edge clock. Creating register for signal `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_ADDR' using process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$283'. created $dff cell `$procdff$342' with positive edge clock. Creating register for signal `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_DATA' using process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$283'. created $dff cell `$procdff$343' with positive edge clock. Creating register for signal `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN' using process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$283'. created $dff cell `$procdff$344' with positive edge clock. 4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:19$48'. Removing empty process `harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:19$48'. Found and cleaned up 1 empty switch in `\harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:41$53'. Removing empty process `harness_nms_weight_direct.$proc$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:41$53'. Found and cleaned up 2 empty switches in `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$291'. Removing empty process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$291'. Found and cleaned up 2 empty switches in `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$283'. Removing empty process `$paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct.$proc$hardware/v2/nms/rtl/nms_weight_direct.v:37$283'. Cleaned up 6 empty switches. 4.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. Optimizing module $paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct. 4.5. Executing CHECK pass (checking for obvious problems). Checking module harness_nms_weight_direct... Checking module $paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct... Found and reported 0 problems. 4.6. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$27a803cce942e1f560e779e4a3d1dbb24e7b50e9\nms_weight_direct. 4.7. Executing TRIBUF pass. 4.8. Executing DEMINOUT pass (demote inout ports to input or output). 4.9. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. Removed 10 unused cells and 43 unused wires. 4.11. Executing CHECK pass (checking for obvious problems). Checking module harness_nms_weight_direct... Found and reported 0 problems. 4.12. Executing OPT pass (performing simple optimizations). 4.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 24 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_weight_direct.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $flatten\dut.$procmux$329: \lfsr [7:0] -> { \lfsr [7:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$326: { \lfsr \lfsr } -> { \lfsr [31:1] 1'1 \lfsr [31:1] 1'1 } Replacing known input bits on port B of cell $flatten\dut.$procmux$315: { \lfsr \lfsr } -> { \lfsr [31:2] 1'1 \lfsr [0] \lfsr [31:2] 1'1 \lfsr [0] } Analyzing evaluation results. Removed 0 multiplexer ports. 4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_weight_direct. Consolidated identical input bits for $mux cell $flatten\dut.$procmux$323: Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] New connections: $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [63:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$281_EN[63:0]$286 [0] } Consolidated identical input bits for $mux cell $flatten\dut.$procmux$312: Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] New connections: $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [63:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:39$282_EN[63:0]$294 [0] } Optimizing cells in module \harness_nms_weight_direct. Performed a total of 2 changes. 4.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 24 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.12.6. Executing OPT_DFF pass (perform DFF optimizations). 4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.12.9. Rerunning OPT passes. (Maybe there is more to do..) 4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_weight_direct.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_weight_direct. Performed a total of 0 changes. 4.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 24 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.12.13. Executing OPT_DFF pass (perform DFF optimizations). 4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.12.16. Finished fast OPT passes. (There is nothing left to do.) 4.13. Executing FSM pass (extract and optimize FSM). 4.13.1. Executing FSM_DETECT pass (finding FSMs in design). 4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 4.14. Executing OPT pass (performing simple optimizations). 4.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 24 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_weight_direct.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_weight_direct. Performed a total of 0 changes. 4.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 24 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$333 ($dff) from module harness_nms_weight_direct (D = { \lfsr [30:7] $xor$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:21$52_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001). Adding SRST signal on $procdff$335 ($dff) from module harness_nms_weight_direct (D = $xor$hardware/v2/nms/synthesis/harness_nms_weight_direct.v:47$55_Y, Q = \chk, rval = 8'00000000). Adding EN signal on $flatten\dut.$procdff$341 ($dff) from module harness_nms_weight_direct (D = $flatten\dut.$memrd$\GEN_SLOT[0].mem$hardware/v2/nms/rtl/nms_weight_direct.v:41$290_DATA, Q = \dut.GEN_SLOT[0].rd_data_reg). Adding EN signal on $flatten\dut.$procdff$337 ($dff) from module harness_nms_weight_direct (D = $flatten\dut.$memrd$\GEN_SLOT[1].mem$hardware/v2/nms/rtl/nms_weight_direct.v:41$298_DATA, Q = \dut.GEN_SLOT[1].rd_data_reg). 4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. Removed 3 unused cells and 3 unused wires. 4.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.14.9. Rerunning OPT passes. (Maybe there is more to do..) 4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_weight_direct.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_weight_direct. Performed a total of 0 changes. 4.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 22 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.14.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.14.16. Finished fast OPT passes. (There is nothing left to do.) 4.15. Executing WREDUCE pass (reducing word size of cells). Removed top 56 bits (of 64) from FF cell harness_nms_weight_direct.$auto$ff.cc:337:slice$352 ($dffe). Removed top 56 bits (of 64) from FF cell harness_nms_weight_direct.$auto$ff.cc:337:slice$351 ($dffe). Removed top 24 bits (of 32) from mux cell harness_nms_weight_direct.$procmux$300 ($mux). Removed top 56 bits (of 128) from wire harness_nms_weight_direct.rd_data_flat. Removed top 24 bits (of 32) from wire harness_nms_weight_direct.$0\lfsr[31:0]. 4.16. Executing PEEPOPT pass (run peephole optimizers). 4.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. Removed 0 unused cells and 2 unused wires. 4.18. Executing SHARE pass (SAT-based resource sharing). 4.19. Executing TECHMAP pass (map to technology primitives). 4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 4.19.2. Continuing TECHMAP pass. No more expansions possible. 4.20. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.22. Executing TECHMAP pass (map to technology primitives). 4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 4.22.2. Continuing TECHMAP pass. No more expansions possible. 4.23. Executing TECHMAP pass (map to technology primitives). 4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 4.23.2. Continuing TECHMAP pass. No more expansions possible. 4.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module harness_nms_weight_direct: created 0 $alu and 0 $macc cells. 4.25. Executing OPT pass (performing simple optimizations). 4.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 22 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_weight_direct.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_weight_direct. Performed a total of 0 changes. 4.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 22 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.25.6. Executing OPT_DFF pass (perform DFF optimizations). 4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.25.9. Finished fast OPT passes. (There is nothing left to do.) 4.26. Executing MEMORY pass. 4.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing harness_nms_weight_direct.dut.GEN_SLOT[0].mem write port 0. Analyzing harness_nms_weight_direct.dut.GEN_SLOT[1].mem write port 0. 4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\dut.GEN_SLOT[0].mem'[0] in module `\harness_nms_weight_direct': merging output FF to cell. Write port 0: non-transparent. Checking read port `\dut.GEN_SLOT[1].mem'[0] in module `\harness_nms_weight_direct': merging output FF to cell. Write port 0: non-transparent. 4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. Removed 2 unused cells and 16 unused wires. 4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 4.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory harness_nms_weight_direct.dut.GEN_SLOT[1].mem via $__PDPW16KD_ mapping memory harness_nms_weight_direct.dut.GEN_SLOT[0].mem via $__PDPW16KD_ 4.29. Executing TECHMAP pass (map to technology primitives). 4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 4.29.3. Continuing TECHMAP pass. Using template $paramod$02d10cc8049219b734b94ed56325542341e7b150$__PDPW16KD_ for cells of type $__PDPW16KD_. No more expansions possible. 4.30. Executing OPT pass (performing simple optimizations). 4.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 30 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.30.3. Executing OPT_DFF pass (perform DFF optimizations). 4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. Removed 0 unused cells and 60 unused wires. 4.30.5. Finished fast OPT passes. 4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 4.32. Executing OPT pass (performing simple optimizations). 4.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 30 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_weight_direct.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_weight_direct. Performed a total of 0 changes. 4.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 30 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.32.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 0 on $auto$mem.cc:1647:emulate_read_first$396 ($dff) from module harness_nms_weight_direct. Setting constant 1-bit at position 0 on $auto$mem.cc:1646:emulate_read_first$395 ($dff) from module harness_nms_weight_direct. Setting constant 1-bit at position 32 on $auto$mem.cc:1646:emulate_read_first$395 ($dff) from module harness_nms_weight_direct. Setting constant 1-bit at position 1 on $auto$mem.cc:1646:emulate_read_first$377 ($dff) from module harness_nms_weight_direct. Setting constant 1-bit at position 33 on $auto$mem.cc:1646:emulate_read_first$377 ($dff) from module harness_nms_weight_direct. 4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.32.9. Rerunning OPT passes. (Maybe there is more to do..) 4.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_weight_direct.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_weight_direct. Performed a total of 0 changes. 4.32.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 30 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.32.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 1 on $auto$mem.cc:1169:emulate_transparency$381 ($dffe) from module harness_nms_weight_direct. Setting constant 1-bit at position 33 on $auto$mem.cc:1169:emulate_transparency$381 ($dffe) from module harness_nms_weight_direct. Setting constant 1-bit at position 0 on $auto$mem.cc:1169:emulate_transparency$399 ($dffe) from module harness_nms_weight_direct. Setting constant 1-bit at position 32 on $auto$mem.cc:1169:emulate_transparency$399 ($dffe) from module harness_nms_weight_direct. 4.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.32.15. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.32.16. Rerunning OPT passes. (Maybe there is more to do..) 4.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \harness_nms_weight_direct.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \harness_nms_weight_direct. Performed a total of 0 changes. 4.32.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 30 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.32.20. Executing OPT_DFF pass (perform DFF optimizations). 4.32.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.32.22. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.32.23. Finished fast OPT passes. (There is nothing left to do.) 4.33. Executing TECHMAP pass (map to technology primitives). 4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 4.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $xor. No more expansions possible. 4.34. Executing OPT pass (performing simple optimizations). 4.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 501 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Computing hashes of 392 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Computing hashes of 330 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 171 cells. 4.34.3. Executing OPT_DFF pass (perform DFF optimizations). 4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. Removed 163 unused cells and 10 unused wires. 4.34.5. Finished fast OPT passes. 4.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. 4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 4.37. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\harness_nms_weight_direct'. Computing hashes of 167 cells of `\harness_nms_weight_direct'. Finding duplicate cells in `\harness_nms_weight_direct'. Removed a total of 0 cells. 4.38. Executing TECHMAP pass (map to technology primitives). 4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 4.38.2. Continuing TECHMAP pass. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. No more expansions possible. 4.39. Executing OPT_EXPR pass (perform const folding). Optimizing module harness_nms_weight_direct. 4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). 4.41. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in harness_nms_weight_direct. 4.42. Executing ATTRMVCP pass (move or copy attributes). 4.43. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \harness_nms_weight_direct.. Removed 0 unused cells and 401 unused wires. 4.44. Executing CHECK pass (checking for obvious problems). Checking module harness_nms_weight_direct... Found and reported 0 problems. 4.45. Executing TECHMAP pass (map to technology primitives). 4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 4.45.2. Continuing TECHMAP pass. No more expansions possible. 4.46. Executing ABC9 pass. 4.46.1. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.2. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module harness_nms_weight_direct. Found 0 SCCs. 4.46.4. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.5. Executing TECHMAP pass (map to technology primitives). 4.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.46.5.2. Continuing TECHMAP pass. No more expansions possible. 4.46.6. Executing OPT pass (performing simple optimizations). 4.46.6.1. Executing OPT_EXPR pass (perform const folding). 4.46.6.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 4.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 4.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 4.46.6.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 4.46.6.6. Executing OPT_DFF pass (perform DFF optimizations). 4.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). 4.46.6.8. Executing OPT_EXPR pass (perform const folding). 4.46.6.9. Finished fast OPT passes. (There is nothing left to do.) 4.46.7. Executing TECHMAP pass (map to technology primitives). 4.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 4.46.7.2. Continuing TECHMAP pass. No more expansions possible. 4.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 4.46.9. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.10. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.11. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.12. Executing AIGMAP pass (map logic to AIG). Module harness_nms_weight_direct: replaced 71 cells with 455 new cells, skipped 96 cells. replaced 3 cell types: 23 $_MUX_ 14 $_OR_ 34 $_XOR_ not replaced 5 cell types: 2 $_AND_ 3 $_NOT_ 1 $scopeinfo 88 TRELLIS_FF 2 DP16KD 4.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9). 4.46.12.3. Executing XAIGER backend. Extracted 187 AND gates and 632 wires from module `harness_nms_weight_direct' to a netlist network with 114 inputs and 90 outputs. 4.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9). 4.46.12.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ======== ABC command line "source /abc.script" ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 114/ 90 and = 185 lev = 6 (0.89) mem = 0.01 MB box = 0 bb = 0 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f -r ABC: + &ps ABC: /input : i/o = 114/ 90 and = 303 lev = 6 (0.83) mem = 0.01 MB ch = 40 box = 0 bb = 0 ABC: cst = 0 cls = 40 lit = 40 unused = 337 proof = 0 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no ABC: Node = 303. Ch = 40. Total mem = 0.08 MB. Peak cut mem = 0.01 MB. ABC: P: Del = 1749.00. Ar = 101.0. Edge = 132. Cut = 4383. T = 0.00 sec ABC: P: Del = 1749.00. Ar = 99.0. Edge = 133. Cut = 4383. T = 0.00 sec ABC: P: Del = 1749.00. Ar = 50.0. Edge = 141. Cut = 5302. T = 0.00 sec ABC: F: Del = 1749.00. Ar = 48.0. Edge = 141. Cut = 5162. T = 0.00 sec ABC: A: Del = 1749.00. Ar = 48.0. Edge = 141. Cut = 5311. T = 0.00 sec ABC: A: Del = 1749.00. Ar = 48.0. Edge = 141. Cut = 5309. T = 0.00 sec ABC: Total time = 0.00 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: Timing manager is given but there is no GIA of boxes. ABC: Error: Abc_FrameUpdateGia(): Transformation has failed. ABC: + &ps -l ABC: /input : i/o = 114/ 90 and = 183 lev = 6 (0.83) mem = 0.01 MB box = 0 bb = 0 ABC: Mapping (K=7) : lut = 39 edge = 141 lev = 3 (0.33) mem = 0.00 MB ABC: LUT = 39 : 2=5 12.8 % 3=10 25.6 % 4=21 53.8 % 5=2 5.1 % 6=0 0.0 % 7=1 2.6 % Ave = 3.62 ABC: + &write -n /output.aig ABC: + &verify ABC: Networks are equivalent. Time = 0.01 sec ABC: + time ABC: elapse: 0.01 seconds, total: 0.01 seconds 4.46.12.6. Executing AIGER frontend. Removed 329 unused cells and 461 unused wires. 4.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). ABC RESULTS: $lut cells: 39 ABC RESULTS: input signals: 13 ABC RESULTS: output signals: 9 Removing temp directory. 4.46.13. Executing TECHMAP pass (map to technology primitives). 4.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 4.46.13.2. Continuing TECHMAP pass. No more expansions possible. Removed 10 unused cells and 666 unused wires. 4.47. Executing TECHMAP pass (map to technology primitives). 4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 4.47.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut. Using template $paramod$70aaf70eb32e221098b6eb52bf2b64b3c0b4a0fb$lut for cells of type $lut. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$6da36b00000992020b7b7eba5fbe42bbd326035f$lut for cells of type $lut. Using template $paramod$a5decf35c8e89d7ee0a60057106759110775301b$lut for cells of type $lut. Using template $paramod$17f1b90a5c6d7e6613368c5e7d3f44dd634e59e2$lut for cells of type $lut. Using template $paramod$debd9b669717840687fe3e52f7822c4b59921848$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$581d7e5f451b6b3ddd4ad06c99f094a0a6e88e05$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011$lut for cells of type $lut. Using template $paramod$d2b5e7b5429639878c0a614cf001753581eebd9c$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$a77dfb140d1f5ab821361c4c4292c9c152574ecd$lut for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$5f3abb125a0361a143f12eec230ed33f6f988a00$lut for cells of type $lut. Using template $paramod$80bc945f6d438f16387422ec284dc12b4bb4e68f$lut for cells of type $lut. Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039$lut for cells of type $lut. Using template $paramod$ffbdf3001f0d2972a014e8e8948b59dcda97f633$lut for cells of type $lut. No more expansions possible. 4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in harness_nms_weight_direct. Optimizing lut $abc$2322$lut$aiger2321$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$2322$lut$aiger2321$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$2322$lut$aiger2321$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$2322$lut$aiger2321$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$2322$lut$aiger2321$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$2322$lut$aiger2321$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$2322$lut$aiger2321$134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$2322$lut$aiger2321$172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$2322$lut$aiger2321$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 92 unused wires. 4.49. Executing AUTONAME pass. Renamed 215 objects in module harness_nms_weight_direct. 4.50. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `harness_nms_weight_direct'. Setting top module to harness_nms_weight_direct. 4.50.1. Analyzing design hierarchy.. Top module: \harness_nms_weight_direct 4.50.2. Analyzing design hierarchy.. Top module: \harness_nms_weight_direct Removed 0 unused modules. 4.51. Printing statistics. === harness_nms_weight_direct === +----------Local Count, excluding submodules. | 92 wires 1008 wire bits 92 public wires 1008 public wire bits 4 ports 18 port bits 3 cells 1 $scopeinfo 2 DP16KD 145 submodules 3 L6MUX21 48 LUT4 6 PFUMX 88 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 3 harness_nms_weight_direct +----------Count including submodules. | 92 wires 1008 wire bits 92 public wires 1008 public wire bits 4 ports 18 port bits - memories - memory bits - processes 3 cells 1 $scopeinfo 2 DP16KD 145 submodules 3 L6MUX21 48 LUT4 6 PFUMX 88 TRELLIS_FF 4.52. Executing CHECK pass (checking for obvious problems). Checking module harness_nms_weight_direct... Found and reported 0 problems. 4.53. Executing JSON backend. End of script. Logfile hash: 63a91f6500, time: 0.34s, user: 0.30s, system: 0.01s, MEM: 33.88 MB peak Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) Time spent: 50% 21x read_verilog (0 sec), 23% 11x techmap (0 sec), ...