Info: Logic utilisation before packing: Info: Total LUT4s: 258/43848 0% Info: logic LUTs: 220/43848 0% Info: carry LUTs: 38/43848 0% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 116/43848 0% Info: Packing IOs.. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 78 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0xe15ce51e Info: Device utilisation: Info: TRELLIS_IO: 80/ 245 32% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 116/ 43848 0% Info: TRELLIS_COMB: 272/ 43848 0% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 217 cells, random placement wirelen = 23682. Info: at initial placer iter 0, wirelen = 5228 Info: at initial placer iter 1, wirelen = 4908 Info: at initial placer iter 2, wirelen = 4860 Info: at initial placer iter 3, wirelen = 4812 Info: Running main analytical placer, max placement attempts per cell = 27495. Info: at iteration #1, type ALL: wirelen solved = 4801, spread = 5389, legal = 5418; time = 0.01s Info: HeAP Placer Time: 0.02s Info: of which solving equations: 0.01s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 51, wirelen = 5418 Info: at iteration #5: temp = 0.000000, timing cost = 51, wirelen = 4248 Info: at iteration #10: temp = 0.000000, timing cost = 65, wirelen = 4183 Info: at iteration #11: temp = 0.000000, timing cost = 53, wirelen = 4170 Info: SA placement time 0.05s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 175.41 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.64 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 5.29 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 6799, 7056) |****** Info: [ 7056, 7313) |**** Info: [ 7313, 7570) | Info: [ 7570, 7827) | Info: [ 7827, 8084) |*************** Info: [ 8084, 8341) |******************** Info: [ 8341, 8598) |*** Info: [ 8598, 8855) |******** Info: [ 8855, 9112) |************ Info: [ 9112, 9369) |**** Info: [ 9369, 9626) |********* Info: [ 9626, 9883) |******************* Info: [ 9883, 10140) |******************************** Info: [ 10140, 10397) |************** Info: [ 10397, 10654) |********** Info: [ 10654, 10911) |*********** Info: [ 10911, 11168) |***** Info: [ 11168, 11425) |**** Info: [ 11425, 11682) | Info: [ 11682, 11939) |*** Info: Checksum: 0xf59d6768 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 1088 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 324 641 | 324 641 | 436| 0.07 0.07| Info: 1466 | 354 1054 | 30 413 | 0| 0.10 0.17| Info: Routing complete. Info: Router1 time 0.17s Info: Checksum: 0x58327738 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.40 0.40 Source data_idx_TRELLIS_FF_Q_2.Q Info: routing 0.82 1.22 Net data_idx[2] (39,18) -> (39,20) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S1$CCU2_COMB0.B Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.35 1.57 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S1$CCU2_COMB0.FCO Info: routing 0.00 1.57 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S1$CCU2_FCI_INT (39,20) -> (39,20) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S1$CCU2_COMB1.FCI Info: logic 0.00 1.57 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S1$CCU2_COMB1.FCO Info: routing 0.00 1.57 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S1_COUT (39,20) -> (39,20) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0$CCU2_COMB0.FCI Info: Defined in: Info: rtl/spi_flash_master.v:315.37-315.53 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 1.63 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0$CCU2_COMB0.FCO Info: routing 0.00 1.63 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0$CCU2_FCI_INT (39,20) -> (39,20) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0$CCU2_COMB1.FCI Info: logic 0.00 1.63 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0$CCU2_COMB1.FCO Info: routing 0.00 1.63 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_COUT (39,20) -> (40,20) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0$CCU2_COMB0.FCI Info: Defined in: Info: rtl/spi_flash_master.v:315.37-315.53 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 1.68 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0$CCU2_COMB0.FCO Info: routing 0.00 1.68 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0$CCU2_FCI_INT (40,20) -> (40,20) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0$CCU2_COMB1.FCI Info: logic 0.00 1.68 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0$CCU2_COMB1.FCO Info: routing 0.00 1.68 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_COUT (40,20) -> (40,20) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0$CCU2_COMB0.FCI Info: Defined in: Info: rtl/spi_flash_master.v:315.37-315.53 Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 Info: logic 0.06 1.74 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0$CCU2_COMB0.FCO Info: routing 0.00 1.74 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0$CCU2_FCI_INT (40,20) -> (40,20) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0$CCU2_COMB1.FCI Info: logic 0.29 2.03 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0$CCU2_COMB1.F Info: routing 0.56 2.59 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_S1[1] (40,20) -> (41,21) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT_CCU2C_CIN_S0_LUT4_Z.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 2.77 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT_CCU2C_CIN_S0_LUT4_Z.F Info: routing 0.35 3.12 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_D_CCU2C_S0_S1_CCU2C_S0_S1_CCU2C_S0_COUT_CCU2C_CIN_S0[5] (41,21) -> (41,21) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C.M Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.19 3.31 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C.OFX Info: routing 0.61 3.92 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] (41,21) -> (39,21) Info: Sink rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_D.D Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 4.10 Source rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_D.F Info: routing 0.51 4.61 Net rdata_ack_LUT4_A_1_B_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_LUT4_C_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_D_Z[5] (39,21) -> (39,23) Info: Sink wdata_req_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.19 4.81 Source wdata_req_TRELLIS_FF_Q_DI_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: routing 0.71 5.51 Net wdata_req_TRELLIS_FF_Q_DI (39,23) -> (39,20) Info: Sink wdata_req_TRELLIS_FF_Q.M Info: setup 0.00 5.51 Source wdata_req_TRELLIS_FF_Q.M Info: 1.96 ns logic, 3.56 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source wdata_valid$tr_io.O Info: routing 2.59 2.59 Net wdata_valid$TRELLIS_IO_IN (90,26) -> (40,24) Info: Sink wdata_valid_LUT4_C.C Info: Defined in: Info: rtl/spi_flash_master.v:125.26-125.37 Info: logic 0.18 2.77 Source wdata_valid_LUT4_C.F Info: routing 0.67 3.43 Net rdata_ack_LUT4_A_1_D[2] (40,24) -> (40,25) Info: Sink rdata_ack_LUT4_A_1.C Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.18 3.61 Source rdata_ack_LUT4_A_1.F Info: routing 0.31 3.93 Net rdata_ack_LUT4_A_1_D_LUT4_C_D[1] (40,25) -> (40,25) Info: Sink rdata_ack_LUT4_A_1_Z_LUT4_D_1_Z_PFUMX_ALUT_BLUT_LUT4_Z.M Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.19 4.12 Source rdata_ack_LUT4_A_1_Z_LUT4_D_1_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX Info: routing 0.32 4.45 Net rdata_ack_LUT4_A_1_Z_LUT4_D_1_Z_PFUMX_ALUT_Z[4] (40,25) -> (41,25) Info: Sink shifting_TRELLIS_FF_Q_CE_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.19 4.64 Source shifting_TRELLIS_FF_Q_CE_PFUMX_Z_BLUT_LUT4_Z.OFX Info: routing 0.47 5.11 Net shifting_TRELLIS_FF_Q_CE (41,25) -> (40,25) Info: Sink shifting_TRELLIS_FF_Q.CE Info: setup 0.00 5.11 Source shifting_TRELLIS_FF_Q.CE Info: 0.75 ns logic, 4.37 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.40 0.40 Source state_TRELLIS_FF_Q_1.Q Info: routing 0.76 1.15 Net rdata_ack_LUT4_A_1_Z[1] (41,25) -> (39,24) Info: Sink busy_LUT4_Z.C Info: Defined in: Info: rtl/spi_flash_master.v:182.16-182.21 Info: logic 0.18 1.33 Source busy_LUT4_Z.F Info: routing 2.52 3.85 Net busy$TRELLIS_IO_OUT (39,24) -> (90,23) Info: Sink busy$tr_io.I Info: Defined in: Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: 0.57 ns logic, 3.28 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 181.36 MHz (PASS at 80.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.11 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 3.85 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 6986, 7223) |**** Info: [ 7223, 7460) |***** Info: [ 7460, 7697) |***** Info: [ 7697, 7934) |** Info: [ 7934, 8171) |******* Info: [ 8171, 8408) |*********** Info: [ 8408, 8645) |************* Info: [ 8645, 8882) |*** Info: [ 8882, 9119) |****************** Info: [ 9119, 9356) |*** Info: [ 9356, 9593) |**************** Info: [ 9593, 9830) |********************* Info: [ 9830, 10067) |*************************** Info: [ 10067, 10304) |******************* Info: [ 10304, 10541) |********** Info: [ 10541, 10778) |*** Info: [ 10778, 11015) |*** Info: [ 11015, 11252) |** Info: [ 11252, 11489) |*** Info: [ 11489, 11726) |**** Info: Program finished normally.