read_verilog -sv \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v

hierarchy -top graph_engine
synth_ecp5 -top graph_engine -json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/graph_engine/top.json
stat