% ======================================================================
%  FPGA-Neural V2 -- Neural Multiprocessor / Dataflow Machine
%  Datasheet / Technical reference manual
%  Repository: github.com/manvalan/FPGA-Neural
% ======================================================================
\documentclass[11pt,a4paper,openany]{report}

\newcommand{\datasheetrev}{B2}
\newcommand{\datasheetdate}{September 2026}

\input{preamble}

\begin{document}
\sloppy

% ======================================================================
%  TITLE PAGE
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\begin{titlepage}
\thispagestyle{empty}
\begin{tikzpicture}[remember picture,overlay]
  \fill[fnDark] (current page.north west) rectangle
       ([yshift=-4.3cm]current page.north east);
  \fill[fnTeal] ([yshift=-4.3cm]current page.north west) rectangle
       ([yshift=-4.55cm]current page.north east);
  \node[anchor=north west,text=white,font=\Huge\bfseries]
       at ([xshift=2.2cm,yshift=-1.15cm]current page.north west)
       {FPGA\,--\,Neural~V2};
  \node[anchor=north west,text=fnLight,font=\large]
       at ([xshift=2.25cm,yshift=-2.15cm]current page.north west)
       {Neural Multiprocessor / Dataflow Machine};
  \node[anchor=north west,text=fnLight2,font=\normalsize]
       at ([xshift=2.25cm,yshift=-2.85cm]current page.north west)
       {N\_SLOTS-way concurrent INT8 accelerator -- Datasheet and reference manual};
  \node[anchor=north east,text=white,font=\ttfamily\small]
       at ([xshift=-2.2cm,yshift=-3.55cm]current page.north east)
       {Rev.~\datasheetrev~~\textbullet~~\datasheetdate};
\end{tikzpicture}

\vspace*{5.0cm}

% --- compact block diagram on the title page ---
\begin{center}
\resizebox{\textwidth}{!}{%
\begin{tikzpicture}[node distance=7mm and 10mm]
  \node[fnblockD,minimum width=26mm] (host) {HOST\\{\scriptsize graph loader}};
  \node[fnblockT,right=14mm of host,minimum width=30mm] (dm) {Dependency\\Manager};
  \node[fnblockT,right=14mm of dm,minimum width=28mm] (dir) {Neural\\Director};
  \node[fnblock,right=14mm of dir,minimum width=34mm] (slots) {N\_SLOTS $\times$ (Memory\\Manager $+$ Neural Proc.)};
  \node[fnblock,right=10mm of slots,minimum width=20mm] (ram) {SDRAM\\{\scriptsize 64\,MB}};
  \draw[fnbus] (host) -- (dm);
  \draw[fnbus] (dm) -- (dir);
  \draw[fnbus] (dir) -- (slots);
  \draw[fnbus] (slots) -- node[fnlbl,above]{16-bit word} (ram);
  \node[below=1mm of slots,font=\scriptsize\itshape,text=fnGrey]
       {computation entirely on-chip, dependency graph resolved autonomously};
\end{tikzpicture}%
}
\end{center}

\vfill
\begin{center}
\begin{tikzpicture}
\node[draw=fnRule,rounded corners=3pt,inner sep=10pt,fill=fnLight,text width=15.5cm]{
\footnotesize
\textbf{\color{fnDark}Reference target device:} Lattice ECP5 \code{LFE5U-45F-8BG381C}
(speed grade $-8$, CABGA381) --- identical device and board as V1.\\[2pt]
\textbf{\color{fnDark}Production configuration:} INT8/INT32, \code{P\_IN}=8,
\code{N\_SLOTS}=4 (real 8/8-seed timing closure at 64\,MHz --- see
ch.~\ref{ch:hw}), single unified SDR SDRAM (Alliance Memory
\code{AS4C32M16SB-7BIN}, 64\,MB), real board-level pinout and KiCad
schematic/BOM.\\[2pt]
\textbf{\color{fnDark}Status:} RTL verified in real Verilator simulation and real
synthesis + place\&route (Yosys + nextpnr-ecp5). Full benchmark campaign, two
post-campaign memory optimizations, an alternative memory-subsystem
redesign that became the current architecture (the Neural Memory System,
ch.~\ref{ch:nms}), and a real, board-level schematic/BOM verification pass
(ch.~\ref{ch:hw}) all complete and measured. Document describing the
project as of \datasheetdate.
};
\end{tikzpicture}
\end{center}
\vspace{0.6cm}
{\footnotesize\color{fnGrey}\raggedright
Project author: Michele Bigi \textbullet{} MIKILAB / manvalan.\\
This datasheet documents V2 of the RTL code, documentation and benchmarks
present in the repository \texttt{github.com/manvalan/FPGA-Neural}. V1 remains
frozen and unmodified as the project's golden functional/performance
reference; its own datasheet previously lived alongside this one in this
repository and was consolidated out of the working tree as part of a
2026-09-09 documentation cleanup (recoverable from git history).\par}
\end{titlepage}

% ======================================================================
%  "FEATURES" PAGE (datasheet style)
% ======================================================================
\input{chapters/00-features}

% ======================================================================
%  PINOUT SUMMARY (real, board-verified ball assignment)
% ======================================================================
\newpage
\input{chapters/00b-pinout}

% ======================================================================
%  TABLE OF CONTENTS
% ======================================================================
\newpage
\pagenumbering{roman}
{\color{fnDark}\tableofcontents}
\newpage
\pagenumbering{arabic}

% ======================================================================
%  CHAPTERS
% ======================================================================
\include{chapters/01-overview}
\include{chapters/02-architecture}
\include{chapters/03-datapath}
\include{chapters/04-parameters}
\include{chapters/05-memory}
\include{chapters/06-scheduling}
\include{chapters/07-hostinterface}
\include{chapters/08-toplevel}
\include{chapters/09-implementation}
\include{chapters/10-hardware}
\include{chapters/11-registers}
\include{chapters/12-roadmap}
\include{chapters/13-nms}

\appendix
\include{chapters/A-modules}

\end{document}