docs: Phase 7 placement-seed sweep + hardware design document
Phase 7 (docs/FPGA-NeuralNetwork-Engine.md): re-ran nextpnr-ecp5 on the already-synthesized Phase 5 spi_neuron_top netlists (top.json reused, only placement re-seeded) at --seed 1/2/3 for both P8 and P2. Both land in a tight band regardless of seed (P8: 39.5-40.6 MHz, 2.6% spread; P2: 42.5-45.0 MHz, 5.8% spread) -- confirms the Phase 5 timing shortfall is a real structural bottleneck, not placement noise, unlike the much smaller same-tier benchmark design (<2% utilization, huge placer freedom, genuinely noisy). Corrected the earlier "pipeline the saturate stage" candidate fix, which targeted Phase 4's critical path and not the one Phase 5's logic actually shifted to; block RAM for x_mem/w_mem remains the leading candidate, not yet implemented. New docs/FPGA-Neural-Hardware-Design.md: draft hardware design doc for a board carrying the project's actual target device (LFE5U-45F-8BG381C) plus the parallel PSRAM rtl/psram_controller.v is written for. Covers: why not the basic-ecp5-pcb reference board (wrong package/speed grade, no RAM), a real I/O pin budget from Lattice's own CABGA381 pinout table, a researched PSRAM part (ISSI IS66WVE4M16EBLL-70BLI -- 70ns access matches the controller's timing assumption exactly, with a note on the byte/word address shift in int8_memory_access.v so the chip's top address line is correctly left as spare headroom, not a wiring error), clock (16 MHz, no PLL exists yet so CLK_FREQ_MHZ must match whatever oscillator is fitted), power/config reusing the reference board's proven circuitry and errata (config-SPI pin can't double as the application SPI interface), and a BOM/open-items list. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
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Claude Sonnet 5
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# FPGA-Neural — Hardware Design Document
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Status: draft, pre-schematic. Component choices below are researched
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against current distributor listings (2026-09-02) but not yet
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ordered/prototyped. No PCB layout exists yet.
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Goal: a board carrying the project's actual target device
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(`LFE5U-45F-8BG381C`) plus the parallel PSRAM the current RTL
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(`rtl/psram_controller.v`) is written for, so real hardware exists
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to run everything already synthesized/benchmarked in this repo.
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---
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## 1. Why a new board (not `basic-ecp5-pcb`)
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A reference ECP5 dev board (Matt Venn's `basic-ecp5-pcb`,
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OSHWA-approved, in this workspace at `../basic-ecp5-pcb`) exists and
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is a useful source of **proven power/config circuitry** — but it
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carries the wrong chip for this project and has no RAM at all:
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| | `basic-ecp5-pcb` | This project's target |
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|---|---|---|
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| Device | `LFE5U-45F-6BG256C` | `LFE5U-45F-8BG381C` |
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| Package | 256-ball CABGA | 381-ball CABGA |
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| Speed grade | -6 (slowest ECP5 grade) | -8 (fastest ECP5 grade) |
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| RAM | none (6 PMODs, no memory chip) | parallel PSRAM required |
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Same die (`LFE5U-45F`, same 44K LUT / 72 DSP), different package and
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a materially slower speed grade. All Fmax numbers measured so far in
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this repo (`docs/FPGA-NeuralNetwork-Engine.md` §15 "Phase 7 — Optimization") target
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the -8 grade; they do not directly transfer to a -6 part.
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**What we reuse from it anyway:** the power tree and bitstream-config
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approach (§4, §5) are package-independent and already validated on
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real, shipped hardware — no reason to redesign those from scratch.
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---
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## 2. I/O pin budget (real ball data, CABGA381)
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Extracted from Lattice's own ECP5-45 pinout table (`../basic-ecp5-pcb/docs/ECP5Upinouts.ods`,
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sheet `ECP5U45Pinout`, `CABGA381` column) — not estimated:
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| Bank | Usable I/O balls |
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|---|---|
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| 0 | 29 |
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| 1 | 35 |
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| 2 | 35 |
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| 3 | 36 |
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| 6 | 36 |
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| 7 | 35 |
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| 8 | 22 |
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| 40 (config-related) | 4 |
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| **Total usable** | **~232** |
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| Power/ground/NC (remaining of 381 balls) | 149 |
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Signal budget this design actually needs:
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| Function | Pins |
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|---|---|
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| PSRAM (`psram_a` 22b worst case, `psram_dq` 16b, `ce_n/oe_n/we_n/lb_n/ub_n/zz_n` 6b) | up to 44 (real usage likely less — see §3, address lines can be trimmed to match actual chip density) |
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| Application SPI (`sclk/mosi/miso/cs_n`) | 4 |
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| `clk`, `rst` | 2 |
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| Config SPI (to onboard FLASH) | 4 |
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| JTAG (recommended, for bring-up/debug) | 4 |
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| **Total** | **~58** |
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~58 of ~232 usable I/O used — **plenty of headroom** (~170+ spare
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pins) for LEDs, buttons, a debug PMOD-style header, or a second SPI
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host, without any pin-count pressure. This board does not need to be
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pin-constrained the way a 256-ball/PMOD-only design would.
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---
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## 3. PSRAM subsystem (the piece `basic-ecp5-pcb` doesn't have)
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`rtl/psram_controller.v` implements a plain **asynchronous parallel**
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interface — address bus, 16-bit data bus, `ce_n`/`oe_n`/`we_n` and
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byte-lane `lb_n`/`ub_n`, plus `zz_n` — and its timing already
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hardcodes a **70 ns access latency** assumption
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(`ACCESS_CYCLES = ceil(70ns × CLK_FREQ_MHZ / 1000)`). This is a
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classic async-SRAM-style bus, not QSPI — most "PSRAM" sold today
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(including what's on typical ESP32 boards) is serial/QSPI and **will
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not** plug into this controller without a rewrite.
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**Recommended part: ISSI IS66WVE4M16EBLL-70BLI**
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- 64 Mbit (4M × 16), parallel pseudo-SRAM, async, **70 ns
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access** — matches the controller's timing assumption exactly, no
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RTL change needed.
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- TSOP-44/48 package — hand-solderable-adjacent, real distributor
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listings (DigiKey, Mouser) at time of writing.
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- **Address bus note:** the chip is 4M×16 words (8 MB total,
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needs a real 22-bit word address, A0–A21). The current RTL's
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`ADDR_WIDTH=22` is a **byte** address (4 MiB space) that
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`int8_memory_access.v` right-shifts by 1 (`addr >> 1`) into a word
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address before it reaches `psram_controller` — so only **21**
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word-address bits are actually driven today. Wire all 22 chip
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address balls, but the chip's topmost line (A21) stays unused/tied
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low until `ADDR_WIDTH` is widened to 23 to use the chip's full
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8 MB instead of today's 4 MiB. Free headroom, not a defect.
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**Fallback: ISSI IS61WV6416DBLL / IS61WV102416BLL** (true async
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SRAM, not pseudo-SRAM) — electrically drop-in on the same
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`ce_n/oe_n/we_n/lb_n/ub_n` signals, no internal refresh (so `zz_n`
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can just be tied inactive), faster than needed (~10 ns), useful
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if the ISSI PSRAM specifically is out of stock. Smaller density
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(1–16 Mbit depending on exact part) — fine for this
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project's current memory footprint (weights/biases/activations for
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the networks exercised so far are well under 1 MB).
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Real part numbers, not yet ordered — verify current stock/pricing
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before BOM lock.
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---
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## 4. Clock
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`basic-ecp5-pcb` uses a fixed **16 MHz** MEMS oscillator
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(SiTime SiT2001B family) — no crystal driver on the ECP5, the clock
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input must come from an oscillator IC into a `PCLK` pad.
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**Recommendation: keep 16 MHz**, same SiT2001B family (or
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SiT1602/SiT8008, same vendor, also in stock). Rationale, not just
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"reuse what worked":
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- No PLL exists anywhere in this project's RTL yet — `CLK_FREQ_MHZ`
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is a **timing parameter**, not a clock generator. Whatever
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oscillator is fitted drives `clk` directly.
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- Every Fmax measured so far for the *full* integrated system
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(`spi_neuron_top`, Phase 5) sits at 39.5–45 MHz across a
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seed sweep (`docs/FPGA-NeuralNetwork-Engine.md` §15 "Phase 7 — Optimization") —
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confirmed structural, not placement luck. 16 MHz sits well
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under that with real margin.
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- **`CLK_FREQ_MHZ` must be set to match whatever oscillator is
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actually fitted** (16, if this recommendation is taken) — it feeds
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the PSRAM access-timing formulas directly (§3); using the RTL's
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default of 80 with a 16 MHz real clock would under-time the
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PSRAM by 5×.
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A higher oscillator (e.g. 25 or 32 MHz) is possible with margin
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to spare, but revisit once the Phase 7 timing-closure work
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(`docs/FPGA-NeuralNetwork-Engine.md`) lands rather than guessing a
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number now.
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---
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## 5. Power
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Reuse `basic-ecp5-pcb`'s proven three-rail tree as-is (same device
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family, same rail requirements regardless of package):
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| Rail | Value | Part | Load | Status |
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|---|---|---|---|---|
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| Core | 1.1 V | TLV62568 (buck) | ≥600 mA | Confirmed in production, DigiKey/Mouser listed |
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| I/O | 3.3 V | TLV62568 (buck) | 1 A (all banks + PSRAM + PMODs share this) | Confirmed in production |
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| Auxiliary | 2.5 V | TLV73325 (LDO) | 10 mA | Confirmed in production |
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Decoupling: one cap per I/O bank minimum, per Lattice's ECP5
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Hardware Checklist (referenced by `basic-ecp5-pcb`, not re-derived
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here).
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---
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## 6. Configuration (bitstream load)
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Reuse `basic-ecp5-pcb`'s SPI-FLASH-boot approach:
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- **W25Q128JV** SPI NOR flash (16 MB) — confirmed in production,
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multiple package options (WSON, SOIC) currently listed.
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- ECP5 reads its bitstream from this flash at power-on (`sysCONFIG`
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SPI master mode); no external programmer needed for normal
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power-up, only for the initial flash write.
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**Lessons reused from `basic-ecp5-pcb`'s errata (do not re-discover
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these the hard way):**
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- Config-mode select pins should tie directly to GND, not through a
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10 k resistor — the ECP5 test point is ~1 V, too close to
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the 3.3 V bank's input threshold through a resistor divider.
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- Not every SPI flash that claims QSPI actually has a usable QE
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(quad-enable) bit in practice — `basic-ecp5-pcb` hit this with an
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IS25LP016D and switched to the W25Q12x family instead. Stick with
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W25Q128JV rather than substituting on price alone.
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- **The dedicated config-SPI clock pin cannot be reused as a general
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input** post-configuration without extra board-level workaround
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(`basic-ecp5-pcb` needed a bodge wire to let a Raspberry Pi talk
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SPI to the FPGA over the *same* physical pin used for flash boot).
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**This project's application SPI** (`spi_neuron_top`'s
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`sclk`/`mosi`/`miso`/`cs_n`, the host-facing protocol in
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`docs/FPGA-NeuralNetwork-Engine.md` §8.1) **must land on separate,
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ordinary I/O pins — never the config-SPI pins** — precisely to
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avoid needing that same workaround.
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---
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## 7. Signal map (draft — not yet a real LPF)
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No `.lpf` pin constraints exist for this device/package combination
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yet (all `.lpf` files in `synth/` are currently empty — nextpnr has
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been auto-placing I/O for every synthesis run so far, fine for
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Fmax/resource benchmarking, **not** sufficient for a real board).
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Before schematic capture, someone needs to:
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1. Pick actual CABGA381 ball numbers for each signal below from the
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pinout table referenced in §2 (bank-aware: keep the PSRAM data/
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address bus in one or two adjacent banks to ease layout and
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timing).
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2. Write a real `.lpf` with those assignments and re-run
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`nextpnr-ecp5` with it (current benchmark runs deliberately
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skipped this — see `tools/fpga_benchmark.py`).
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3. Confirm bank voltage compatibility (all banks are 3.3 V I/O
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in this design, per §5 — fine for both the PSRAM candidates in §3
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and standard SPI-level signaling).
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| Signal group | Port(s) | Count | Target bank (TBD) |
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|---|---|---|---|
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| PSRAM address | `psram_a[21:0]` | 22 | one bank |
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| PSRAM data | `psram_dq[15:0]` | 16 | same or adjacent bank |
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| PSRAM control | `psram_ce_n/oe_n/we_n/lb_n/ub_n/zz_n` | 6 | same bank as above |
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| Application SPI | `sclk/mosi/miso/cs_n` | 4 | any bank, NOT the config-SPI bank (§6) |
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| Clock/reset | `clk`, `rst` | 2 | `clk` must land on a `PCLK`-capable pad |
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| Config SPI | to onboard flash | 4 | dedicated config bank (bank "40" balls, §2) |
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| JTAG (debug) | TCK/TMS/TDI/TDO | 4 | dedicated JTAG balls |
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---
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## 8. Bill of materials (draft)
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| Ref | Part | Function | Availability |
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|---|---|---|---|
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| U1 | LFE5U-45F-8BG381C | FPGA | Already the project's confirmed target (see main docs, price/stock table) |
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| U2 | ISSI IS66WVE4M16EBLL-70BLI | Parallel PSRAM, 64Mb, 70ns | Verified listed, DigiKey/Mouser |
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| U3, U4 | TLV62568 | Buck converter, core + IO rails | Confirmed in production |
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| U5 | TLV73325 | LDO, 2.5V aux rail | Confirmed in production |
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| U6 | W25Q128JV | SPI NOR flash, config | Confirmed in production, multiple packages |
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| Y1 | SiT2001B, 16 MHz | System clock oscillator | Confirmed in production |
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Not yet specified: exact package/footprint per part, decoupling cap
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values, JTAG header, PSRAM address-bus trim if a smaller/cheaper
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density than 4M×16 turns out to be sufficient once real network
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sizes are decided.
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---
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## 9. Open items before schematic capture
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- [ ] Decide real PSRAM density needed (drives whether `ADDR_WIDTH`
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stays 22 or can shrink, and whether the fallback true-SRAM
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part in §3 is sufficient instead of the pseudo-SRAM)
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- [ ] Real `.lpf` pin assignment (§7) and a synthesis run against it
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(current benchmark results all use auto-placed I/O)
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- [ ] Confirm PSRAM/SPI signal integrity at whatever clock is
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actually fitted (§4) — no signal integrity analysis done yet
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- [ ] JTAG header footprint choice
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- [ ] KiCad (or other) schematic capture — none exists yet for this
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device/package combination
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@@ -919,24 +919,51 @@ neither Phase 4's nor Phase 5's single P2/P8 runs establish that.
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**Candidate directions (not implemented, need a decision before
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touching the validated core further):**
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**Placement-seed sweep (2026-09-02) — resolved: it's structural, not
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noise.** Re-ran `nextpnr-ecp5` on the already-synthesized Phase 5
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netlists (`top.json` reused, only placement re-seeded — no re-synth)
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at `--seed 1/2/3` for both P8 and P2:
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| Build | seed (default) | seed 1 | seed 2 | seed 3 | spread |
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|---|---|---|---|---|---|
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| P8 | 40.57 MHz | 39.70 MHz | 39.54 MHz | 40.00 MHz | 1.03 MHz (2.6%) |
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| P2 | 42.54 MHz | 42.82 MHz | 42.72 MHz | 45.01 MHz | 2.47 MHz (5.8%) |
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Both builds land in a tight band regardless of seed — nothing close
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to the P2/P4/P8 same-tier benchmark's own non-monotonic swings (that
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benchmark's design uses <2% of the device, so its placer has enormous
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freedom; `spi_neuron_top`'s fuller design does not). **This confirms
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a real structural bottleneck, not a lucky/unlucky placement** — a
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seed sweep or floorplan constraint will not close a ~2x gap to
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80 MHz by itself; an RTL change is needed.
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**Candidate directions (not implemented, need a decision before
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touching the validated core further):**
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- Move `x_mem`/`w_mem` onto `DP16KD` block RAM (0% used) instead of
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LUT fabric — likely the highest-leverage single change, since it
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is directly implicated in the Phase 5 critical path and currently
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wastes a free, purpose-built resource.
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- Add a pipeline register between the final MAC accumulation and the
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activation/saturate stage in `neuron_parallel.v`, trading +1 cycle
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of per-neuron latency (negligible next to the existing
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N_INPUTS/PARALLEL group-count cycles) for a shorter combinational
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path. No existing testbench hardcodes an exact cycle count for
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neuron completion (`wait(done)`/polling patterns throughout), so
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this should be low regression-risk — but it is still a change to
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the explicitly "validated, don't touch" datapath (`mac8`/`mac_unit`
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/`neuron_parallel`), so deserves an explicit go-ahead rather than
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being done opportunistically.
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- A `nextpnr` seed/effort sweep to check how much of the shortfall is
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placement variance (see P4's own 75.01/76.41 MHz two-number report
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in the same run, or P2/P4/P8's non-monotonic Fmax in the
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same-tier benchmark) vs. a structural bottleneck.
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LUT fabric — the leading candidate. The critical path runs through
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what looks like `w_mem`'s *write*-address decode (`neuron_memory`
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loads one byte per cycle into a variable index during
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`STATE_READ_X`/`STATE_READ_W`, which needs a full-width mux/demux
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in LUT fabric to steer that byte to the right register) feeding
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forward into the accumulator's input path — not the arithmetic
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itself. A block-RAM read/write port replaces that scattered
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LUT-based decode with a single hard macro. This is a genuine
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redesign, not a drop-in swap: `x_bus`/`w_bus` are currently
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exposed to `neuron_parallel` as one fully-parallel N_INPUTS-wide
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combinational bus (built by unrolling every `x_mem`/`w_mem`
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element every cycle); block RAM has a registered, address-in/
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data-out-next-cycle read port, so `neuron_parallel`'s group
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processing would need to become RAM-latency-aware instead of
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assuming the whole bus is already valid. Real potential upside,
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real design effort — needs a go-ahead, not something to do
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opportunistically.
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- A pipeline register between MAC accumulation and the
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activation/saturate stage (this session's original guess) does
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**not** target the actual Phase 5 bottleneck — that finding was
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Phase 4's critical path (the saturation comparator), and the path
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moved once Phase 5's logic was wired in (see above). Keeping this
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noted for Phase 4-only builds; not a fix for the current problem.
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## Phase 8 — Optional Hardware Training
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Reference in New Issue
Block a user