fix: ERR-0029 sdram_unified_backend weight-cache hit-index critical path

Replace the serial "last-match-wins" priority-scan hit-index encoder
with a flat one-hot compare + single-level priority encode, breaking
the serially-dependent PFUMX/OFX cascade real P&R showed dominating
the N_SLOTS=8 @ 64MHz critical path (55.84MHz worst, 4/8 seeds PASS).

Real nextpnr-ecp5 re-verification (32-run matrix, 4 configs x 8 seeds):
N_SLOTS=8 @ 64MHz improves to 5/8 PASS (worst 60.12MHz, up from
55.84MHz). N_SLOTS=4 @ 64MHz stays 8/8 PASS but with reduced worst-case
margin (WNS +0.605ns, down from +2.143ns) as the critical path
relocates to a different, previously-second-worst path in the same
module -- a real, disclosed trade-off, not hidden. 80MHz remains NO-GO
at both processor counts (re-confirmed on the fixed RTL).

Bit-exact, zero functional regression: isolated
tb_sdram_unified_backend.v (40/40) and full D-Stress N=4/N=8 (both
256/256 neurons bit-exact vs golden model).

See errors.log ERR-0029 and decisions.log DEC-0040 for full root-cause
writeup and MEMORY_UPGRADE_64MB_N8.md section 10 for the complete
measured data set and AS4C32M16SB-7BIN pinout tables.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/logs/decisions.log

@@ -2230,3 +2230,48 @@ P&R re-run, all seeds failing -- consistent with this project's own
 prior documented conclusion (ecp5_pll_sys_clk.v's own header: "64MHz
 was chosen... the highest frequency at which ALL measured seeds close
 timing with real margin").
+
+DEC-0040 -- N_SLOTS=8 @ 64MHz weight-cache hit-index optimization
+(ERR-0029): accepted a measured, disclosed N_SLOTS=4 margin reduction
+in exchange for a measured N_SLOTS=8 pass-rate improvement
+
+DATE: 2026-09-07
+CONTEXT: user-mandated root-cause investigation and optimization of
+DEC-0039's own remaining open item (N_SLOTS=8 @ 64MHz not fully
+timing-closed), under an explicit constraint set: N_SLOTS=4 must stay
+8/8 PASS and not "regress into a hardware concern," N_SLOTS=8 must
+measurably improve (by the real routed critical path, not synthesis
+LUT counts), full regression must stay bit-exact, and the complete
+8-seed matrix must be re-run and reported honestly either way.
+DECISION: applied ERR-0029's fix (sdram_unified_backend.v's weight-
+cache hit-index: serial priority-scan -> flat one-hot compare + single-
+level priority encode). Re-ran the full real nextpnr-ecp5 32-run matrix
+(4 configs x 8 seeds) post-fix:
+  N_SLOTS=4 @ 64MHz: 8/8 PASS (unchanged pass count), worst-case WNS
+    fell from +2.143ns to +0.605ns (worst seed Fmax 74.17->66.58MHz).
+    Real cause: the critical path relocated off the (shortened) hit-
+    index chain onto a different, previously-second-worst path in the
+    same module, which this seed set happens to route less favorably.
+  N_SLOTS=8 @ 64MHz: pass count improved 4/8 -> 5/8, worst-case Fmax
+    55.84->60.12MHz, worst WNS -2.284ns->-1.009ns.
+  N_SLOTS=4/8 @ 80MHz: unchanged, still 0/8 both -- NO-GO confirmed
+    again on the fixed RTL.
+ACCEPTED, not rejected: N_SLOTS=4 @ 64MHz remains a real 8/8 PASS
+(all seeds have positive WNS -- no seed fails), which is this project's
+own stated acceptance bar; the margin reduction is disclosed here and
+in errors.log ERR-0029, not hidden. N_SLOTS=8 is a genuine, measured
+improvement toward closure but is explicitly NOT declared fully closed
+(3/8 seeds still fail, now via a still-different critical path -- a
+further iteration, e.g. constraining nextpnr's placement region for
+u_sdram_backend or exploring more seeds, remains a real OPEN item, not
+attempted here).
+Full regression re-verified after this fix: isolated
+tb_sdram_unified_backend.v (40/40, bit-exact), full D-Stress N_SLOTS=4
+(49927 cycles, 256/256 neurons bit-exact vs golden) and N_SLOTS=8
+(49909 cycles, 256/256 neurons bit-exact vs golden) -- zero functional
+regression at either processor count.
+STATUS: N_SLOTS=4 @ 64MHz remains the frozen production baseline (8/8
+PASS, real positive margin on every seed). N_SLOTS=8 @ 64MHz OPEN,
+improved but not closed (5/8 PASS). 80MHz NO-GO at either N_SLOTS,
+reconfirmed on the fixed RTL. File changed: hardware/v2/nms/rtl/
+sdram_unified_backend.v.