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docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

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Adds hardware/v2/docs/PRE_PCB_VERIFICATION.md as the single
authoritative pre-schematic verification record: RTL/ERR-0025/
regression re-verification, clock/reset, synthesis/P&R re-audit,
setup/hold timing status, the real SDRAM datasheet-parameter audit
table (Alliance Memory AS4C4M16SA-6TIN Table 17), SPI host bridge
protocol documentation, FPGA power/pinout tables, first-board bring-up
and benchmark status, and cross-domain consistency audit.

Freezes the FPGA configuration flash: Winbond W25Q32JVSSIQ (32Mbit,
SOIC-8, 2.7-3.6V, standard SPI, ECP5 Master-SPI-boot compatible) --
this was the one section-11 item the governing mandate required not
be left OPEN.

Marks CHIP_READINESS.md/OPEN_ITEMS.md/PINOUT.md/CLOCK_ARCHITECTURE.md/
POWER_ARCHITECTURE.md/SCHEMATIC_READINESS.md as superseded (they
predate the SPI host bridge, PLL, and this session's SDRAM datasheet
audit) with pointers to the new consolidated document, rather than
rewriting each individually.

Updates the V2 LaTeX datasheet's status/roadmap chapter to reflect the
SDRAM datasheet audit and configuration-flash decisions, rebuilds the
PDF (clean compile, 16 pages).

Classification: PRE-PCB VERIFIED. Schematic and PCB implementation
remain user-owned and not started.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-06 18:32:40 +02:00
co-authored by Claude Sonnet 5
parent 8890b0abc2
commit eb0b0f9170
10 changed files with 650 additions and 13 deletions
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hardware/v2/docs/POWER_ARCHITECTURE.md
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# FPGA-Neural V2 — POWER ARCHITECTURE
## Status: OPEN — component/regulator selection not made this round
**SUPERSEDED.** See `PRE_PCB_VERIFICATION.md` \S11-\S12 for the
current per-bank voltage table (PASS) and current/power budget
status (still OPEN, same real reasons as below). Left in place for
its own detailed real-value derivation.
## Status (HISTORICAL framing, current status is in PRE_PCB_VERIFICATION.md): OPEN — component/regulator selection not made this round
Per the governing spec's own "NON inventare valori" rule, this
document states what is REALLY known (device-level voltage