docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

Adds hardware/v2/docs/PRE_PCB_VERIFICATION.md as the single
authoritative pre-schematic verification record: RTL/ERR-0025/
regression re-verification, clock/reset, synthesis/P&R re-audit,
setup/hold timing status, the real SDRAM datasheet-parameter audit
table (Alliance Memory AS4C4M16SA-6TIN Table 17), SPI host bridge
protocol documentation, FPGA power/pinout tables, first-board bring-up
and benchmark status, and cross-domain consistency audit.

Freezes the FPGA configuration flash: Winbond W25Q32JVSSIQ (32Mbit,
SOIC-8, 2.7-3.6V, standard SPI, ECP5 Master-SPI-boot compatible) --
this was the one section-11 item the governing mandate required not
be left OPEN.

Marks CHIP_READINESS.md/OPEN_ITEMS.md/PINOUT.md/CLOCK_ARCHITECTURE.md/
POWER_ARCHITECTURE.md/SCHEMATIC_READINESS.md as superseded (they
predate the SPI host bridge, PLL, and this session's SDRAM datasheet
audit) with pointers to the new consolidated document, rather than
rewriting each individually.

Updates the V2 LaTeX datasheet's status/roadmap chapter to reflect the
SDRAM datasheet audit and configuration-flash decisions, rebuilds the
PDF (clean compile, 16 pages).

Classification: PRE-PCB VERIFIED. Schematic and PCB implementation
remain user-owned and not started.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/CLOCK_ARCHITECTURE.md

@@ -1,6 +1,12 @@
 # FPGA-Neural V2 — CLOCK ARCHITECTURE
 
-## Status: CRITICAL — real, unresolved oscillator/clock-input mismatch
+**SUPERSEDED.** This document predates the real EHXPLLL PLL
+(`ecp5_pll_sys_clk.v`) that resolves the mismatch described below. See
+`PRE_PCB_VERIFICATION.md` \S3 for the current, verified clock/reset
+status (PASS). Left in place as a historical record of the
+architectural decision that led to adding the PLL.
+
+## Status (HISTORICAL): CRITICAL — real, unresolved oscillator/clock-input mismatch
 
 ## What the RTL actually assumes