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docs+synth: post-fix Fmax measurement (EXP-0051) - honest result, N=8 regressed

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Fresh 8-seed sweep after DEC-0043's arbiter/mux fix:
- N=4: worst 82.43MHz (was 81.20MHz), mean 89.48MHz (was 91.05MHz) - a wash.
- N=8: worst 77.36MHz (was 80.97MHz), mean 80.71MHz (was 84.62MHz) - a real,
  measured regression, though still 8/8 PASS at 64MHz with +21% margin.

P&R is a stochastic heuristic search; removing logic from one path can shift
the placer onto a different, coincidentally worse-mapped critical path for
this specific seed set. Not a functional regression - both configs remain
closed. Keeping the fix regardless: it's bit-exact and removes a known-bad
pattern that gets worse as N_SLOTS grows toward 16, even though it didn't
pay off in Fmax at today's N=8. Full numbers and interpretation in
timing.log.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
michele
2026-09-15 23:24:25 +00:00
co-authored by Claude Sonnet 5
parent 6a46dc857f
commit e809b71806
23 changed files with 897078 additions and 869658 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed0.log
+218 -232
View File
@@ -1,13 +1,13 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: Total LUT4s: 7262/43848 16%
Info: logic LUTs: 4612/43848 10%
Info: carry LUTs: 1480/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Total DFFs: 6529/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
@@ -36,11 +36,11 @@ Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
@@ -79,13 +79,13 @@ Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: 2373 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Checksum: 0xa739669a
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
@@ -113,295 +113,281 @@ Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_FF: 6529/ 43848 14%
Info: TRELLIS_COMB: 7712/ 43848 17%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 664680.
Info: at initial placer iter 0, wirelen = 4133
Info: at initial placer iter 1, wirelen = 3182
Info: at initial placer iter 2, wirelen = 3156
Info: at initial placer iter 3, wirelen = 3396
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3086, spread = 111145, legal = 129244; time = 0.60s
Info: at iteration #2, type ALL: wirelen solved = 12402, spread = 85214, legal = 103100; time = 0.49s
Info: at iteration #3, type ALL: wirelen solved = 20047, spread = 77846, legal = 92001; time = 0.41s
Info: at iteration #4, type ALL: wirelen solved = 24325, spread = 71204, legal = 88132; time = 0.43s
Info: at iteration #5, type ALL: wirelen solved = 26567, spread = 69032, legal = 86727; time = 0.44s
Info: at iteration #6, type ALL: wirelen solved = 28109, spread = 69033, legal = 82585; time = 0.39s
Info: at iteration #7, type ALL: wirelen solved = 30841, spread = 67648, legal = 81646; time = 0.42s
Info: at iteration #8, type ALL: wirelen solved = 31193, spread = 66517, legal = 82404; time = 0.42s
Info: at iteration #9, type ALL: wirelen solved = 32060, spread = 65855, legal = 81233; time = 0.36s
Info: at iteration #10, type ALL: wirelen solved = 32211, spread = 68190, legal = 82078; time = 0.33s
Info: at iteration #11, type ALL: wirelen solved = 34272, spread = 68133, legal = 82417; time = 0.35s
Info: at iteration #12, type ALL: wirelen solved = 34894, spread = 68739, legal = 80890; time = 0.38s
Info: at iteration #13, type ALL: wirelen solved = 35680, spread = 67838, legal = 84257; time = 0.42s
Info: at iteration #14, type ALL: wirelen solved = 35537, spread = 67735, legal = 82031; time = 0.33s
Info: at iteration #15, type ALL: wirelen solved = 35984, spread = 67845, legal = 81553; time = 0.43s
Info: at iteration #16, type ALL: wirelen solved = 36390, spread = 68149, legal = 83055; time = 0.39s
Info: at iteration #17, type ALL: wirelen solved = 37027, spread = 68348, legal = 81915; time = 0.33s
Info: HeAP Placer Time: 9.86s
Info: of which solving equations: 4.87s
Info: of which spreading cells: 0.77s
Info: of which strict legalisation: 2.12s
Info: Creating initial analytic placement for 8052 cells, random placement wirelen = 663057.
Info: at initial placer iter 0, wirelen = 3706
Info: at initial placer iter 1, wirelen = 3323
Info: at initial placer iter 2, wirelen = 3076
Info: at initial placer iter 3, wirelen = 3195
Info: Running main analytical placer, max placement attempts per cell = 26342911.
Info: at iteration #1, type ALL: wirelen solved = 3124, spread = 114145, legal = 129690; time = 0.55s
Info: at iteration #2, type ALL: wirelen solved = 12744, spread = 81692, legal = 98901; time = 0.56s
Info: at iteration #3, type ALL: wirelen solved = 19390, spread = 78167, legal = 95014; time = 0.52s
Info: at iteration #4, type ALL: wirelen solved = 23219, spread = 70571, legal = 89652; time = 0.50s
Info: at iteration #5, type ALL: wirelen solved = 26859, spread = 67652, legal = 85696; time = 0.44s
Info: at iteration #6, type ALL: wirelen solved = 27953, spread = 66511, legal = 83204; time = 0.41s
Info: at iteration #7, type ALL: wirelen solved = 29297, spread = 65432, legal = 82519; time = 0.45s
Info: at iteration #8, type ALL: wirelen solved = 30058, spread = 66180, legal = 82029; time = 0.44s
Info: at iteration #9, type ALL: wirelen solved = 31303, spread = 66739, legal = 81492; time = 0.40s
Info: at iteration #10, type ALL: wirelen solved = 31892, spread = 66418, legal = 82031; time = 0.45s
Info: at iteration #11, type ALL: wirelen solved = 32685, spread = 66642, legal = 83038; time = 0.44s
Info: at iteration #12, type ALL: wirelen solved = 33251, spread = 68185, legal = 82959; time = 0.37s
Info: at iteration #13, type ALL: wirelen solved = 35020, spread = 67543, legal = 80638; time = 0.39s
Info: at iteration #14, type ALL: wirelen solved = 35576, spread = 70154, legal = 83490; time = 0.38s
Info: at iteration #15, type ALL: wirelen solved = 37833, spread = 70888, legal = 83298; time = 0.45s
Info: at iteration #16, type ALL: wirelen solved = 38282, spread = 70327, legal = 84325; time = 0.44s
Info: at iteration #17, type ALL: wirelen solved = 38652, spread = 70263, legal = 83038; time = 0.41s
Info: at iteration #18, type ALL: wirelen solved = 38855, spread = 70196, legal = 84036; time = 0.40s
Info: HeAP Placer Time: 11.28s
Info: of which solving equations: 5.41s
Info: of which spreading cells: 0.83s
Info: of which strict legalisation: 2.62s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1092, wirelen = 80890
Info: at iteration #5: temp = 0.000000, timing cost = 1360, wirelen = 74943
Info: at iteration #10: temp = 0.000000, timing cost = 865, wirelen = 72983
Info: at iteration #15: temp = 0.000000, timing cost = 848, wirelen = 72519
Info: at iteration #20: temp = 0.000000, timing cost = 840, wirelen = 72349
Info: at iteration #25: temp = 0.000000, timing cost = 838, wirelen = 72261
Info: at iteration #28: temp = 0.000000, timing cost = 947, wirelen = 72239
Info: SA placement time 25.66s
Info: at iteration #1: temp = 0.000000, timing cost = 887, wirelen = 80638
Info: at iteration #5: temp = 0.000000, timing cost = 1092, wirelen = 74293
Info: at iteration #10: temp = 0.000000, timing cost = 383, wirelen = 72440
Info: at iteration #15: temp = 0.000000, timing cost = 509, wirelen = 71900
Info: at iteration #18: temp = 0.000000, timing cost = 446, wirelen = 71782
Info: SA placement time 18.23s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 72.23 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 66.12 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.62 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.93 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.20 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.76 ns
Info: Slack histogram:
Info: legend: * represents 38 endpoint(s)
Info: + represents [1,38) endpoint(s)
Info: [ 1780, 2444) |+
Info: [ 2444, 3108) |
Info: [ 3108, 3772) |*+
Info: [ 3772, 4436) |****+
Info: [ 4436, 5100) |***+
Info: [ 5100, 5764) |******+
Info: [ 5764, 6428) |********+
Info: [ 6428, 7092) |********+
Info: [ 7092, 7756) |***************+
Info: [ 7756, 8420) |******************+
Info: [ 8420, 9084) |***********************+
Info: [ 9084, 9748) |*************************************+
Info: [ 9748, 10412) |********************************************+
Info: [ 10412, 11076) |************************************+
Info: [ 11076, 11740) |***********************************+
Info: [ 11740, 12404) |*****************************************+
Info: [ 12404, 13068) |************************************************************
Info: [ 13068, 13732) |****************************************************+
Info: [ 13732, 14396) |*****************************************************+
Info: [ 14396, 15060) |********************************************+
Info: Checksum: 0xc812ecb1
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 501, 1229) |+
Info: [ 1229, 1957) |+
Info: [ 1957, 2685) |+
Info: [ 2685, 3413) |*+
Info: [ 3413, 4141) |*+
Info: [ 4141, 4869) |*******+
Info: [ 4869, 5597) |*******+
Info: [ 5597, 6325) |******+
Info: [ 6325, 7053) |********+
Info: [ 7053, 7781) |**********+
Info: [ 7781, 8509) |*************************+
Info: [ 8509, 9237) |*************************************************+
Info: [ 9237, 9965) |***********************************************+
Info: [ 9965, 10693) |*************************************************+
Info: [ 10693, 11421) |********************************************+
Info: [ 11421, 12149) |*****************************************+
Info: [ 12149, 12877) |********************************************************+
Info: [ 12877, 13605) |*******************************************************+
Info: [ 13605, 14333) |************************************************************
Info: [ 14333, 15061) |*********************************************************+
Info: Checksum: 0x41fb2d21
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39389 arcs.
Info: Routing 41131 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 485 514 | 485 514 | 39053| 1.68 1.68|
Info: 2000 | 781 1218 | 296 704 | 38581| 1.21 2.89|
Info: 3000 | 1110 1889 | 329 671 | 38084| 0.94 3.83|
Info: 4000 | 1176 2823 | 66 934 | 37200| 0.54 4.37|
Info: 5000 | 1337 3662 | 161 839 | 36525| 0.77 5.13|
Info: 6000 | 1499 4500 | 162 838 | 35834| 0.76 5.89|
Info: 7000 | 1609 5390 | 110 890 | 35059| 0.48 6.37|
Info: 8000 | 1713 6286 | 104 896 | 34343| 0.54 6.92|
Info: 9000 | 1827 7172 | 114 886 | 33705| 0.60 7.51|
Info: 10000 | 1950 8049 | 123 877 | 32990| 0.51 8.03|
Info: 11000 | 2083 8916 | 133 867 | 32198| 0.56 8.59|
Info: 12000 | 2206 9793 | 123 877 | 31494| 0.74 9.33|
Info: 13000 | 2315 10684 | 109 891 | 30877| 0.76 10.09|
Info: 14000 | 2466 11533 | 151 849 | 30109| 0.41 10.50|
Info: 15000 | 2630 12369 | 164 836 | 29407| 0.45 10.95|
Info: 16000 | 2770 13229 | 140 860 | 28669| 0.35 11.30|
Info: 17000 | 2921 14078 | 151 849 | 27973| 0.44 11.74|
Info: 18000 | 3087 14912 | 166 834 | 27356| 0.80 12.54|
Info: 19000 | 3260 15739 | 173 827 | 26748| 0.73 13.27|
Info: 20000 | 3507 16492 | 247 753 | 26069| 0.43 13.70|
Info: 21000 | 3761 17238 | 254 746 | 25409| 0.70 14.40|
Info: 22000 | 3984 18015 | 223 777 | 24750| 0.44 14.84|
Info: 23000 | 4201 18798 | 217 783 | 24192| 0.50 15.34|
Info: 24000 | 4415 19582 | 214 784 | 23607| 0.51 15.85|
Info: 25000 | 4717 20279 | 302 697 | 23015| 0.41 16.26|
Info: 26000 | 5074 20914 | 357 635 | 22464| 0.51 16.77|
Info: 27000 | 5306 21660 | 232 746 | 21802| 0.46 17.24|
Info: 28000 | 5530 22393 | 224 733 | 21125| 0.50 17.74|
Info: 29000 | 5776 23095 | 246 702 | 20474| 0.54 18.28|
Info: 30000 | 6001 23819 | 225 724 | 19879| 0.45 18.73|
Info: 31000 | 6221 24551 | 220 732 | 19277| 0.46 19.19|
Info: 32000 | 6468 25232 | 247 681 | 18624| 0.54 19.73|
Info: 33000 | 6694 25961 | 226 729 | 17968| 0.70 20.43|
Info: 34000 | 6893 26690 | 199 729 | 17250| 0.51 20.94|
Info: 35000 | 7168 27398 | 275 708 | 16740| 0.68 21.62|
Info: 36000 | 7394 28150 | 226 752 | 16268| 0.58 22.20|
Info: 37000 | 7658 28855 | 264 705 | 15733| 0.64 22.85|
Info: 38000 | 7881 29593 | 223 738 | 15023| 0.62 23.46|
Info: 39000 | 8231 30237 | 350 644 | 14769| 2.80 26.26|
Info: 40000 | 8472 30962 | 241 725 | 14195| 0.64 26.90|
Info: 41000 | 8703 31655 | 231 693 | 13645| 0.74 27.64|
Info: 42000 | 8891 32416 | 188 761 | 13111| 0.77 28.41|
Info: 43000 | 9142 33137 | 251 721 | 12546| 0.64 29.06|
Info: 44000 | 9361 33874 | 219 737 | 12137| 0.64 29.69|
Info: 45000 | 9618 34588 | 257 714 | 11824| 0.79 30.48|
Info: 46000 | 9792 35377 | 174 789 | 11370| 0.84 31.32|
Info: 47000 | 10022 36101 | 230 724 | 10797| 0.59 31.91|
Info: 48000 | 10264 36852 | 242 751 | 10556| 1.06 32.96|
Info: 49000 | 10467 37595 | 203 743 | 9998| 0.80 33.76|
Info: 50000 | 10568 38425 | 101 830 | 9147| 0.42 34.18|
Info: 51000 | 10745 39225 | 177 800 | 8795| 0.85 35.03|
Info: 52000 | 11022 39947 | 277 722 | 8474| 1.26 36.28|
Info: 53000 | 11135 40746 | 113 799 | 7634| 0.31 36.60|
Info: 54000 | 11249 41556 | 114 810 | 6812| 0.39 36.99|
Info: 55000 | 11583 42222 | 334 666 | 6561| 1.05 38.04|
Info: 56000 | 11892 42906 | 309 684 | 6204| 1.39 39.43|
Info: 57000 | 12095 43697 | 203 791 | 5692| 0.72 40.15|
Info: 58000 | 12242 44550 | 147 853 | 5350| 0.57 40.72|
Info: 59000 | 12542 45243 | 300 693 | 4975| 0.81 41.52|
Info: 60000 | 12994 45791 | 452 548 | 4807| 1.39 42.91|
Info: 61000 | 13390 46395 | 396 604 | 4700| 1.26 44.18|
Info: 62000 | 13750 47035 | 360 640 | 4481| 1.16 45.34|
Info: 63000 | 13960 47823 | 210 788 | 3854| 0.55 45.89|
Info: 64000 | 14241 48542 | 281 719 | 3416| 0.83 46.72|
Info: 65000 | 14637 49146 | 396 604 | 3265| 1.71 48.44|
Info: 66000 | 14967 49816 | 330 670 | 3164| 1.51 49.94|
Info: 67000 | 15464 50319 | 497 503 | 2977| 1.76 51.71|
Info: 68000 | 15812 50971 | 348 652 | 2515| 0.98 52.69|
Info: 69000 | 16047 51719 | 235 748 | 1870| 0.60 53.28|
Info: 70000 | 16254 52401 | 207 682 | 1255| 1.19 54.47|
Info: 71000 | 16583 53018 | 329 617 | 945| 1.31 55.78|
Info: 72000 | 16844 53694 | 261 676 | 560| 1.21 56.99|
Info: 72686 | 16927 54202 | 83 508 | 0| 0.53 57.52|
Info: 1000 | 369 630 | 369 630 | 40654| 1.44 1.44|
Info: 2000 | 609 1390 | 240 760 | 40090| 1.06 2.50|
Info: 3000 | 726 2273 | 117 883 | 39304| 0.71 3.21|
Info: 4000 | 806 3193 | 80 920 | 38507| 0.55 3.76|
Info: 5000 | 920 4079 | 114 886 | 37682| 0.50 4.26|
Info: 6000 | 991 5008 | 71 929 | 36807| 0.44 4.70|
Info: 7000 | 1077 5922 | 86 914 | 35945| 0.68 5.38|
Info: 8000 | 1157 6842 | 80 920 | 35039| 0.42 5.81|
Info: 9000 | 1232 7767 | 75 925 | 34151| 0.49 6.30|
Info: 10000 | 1320 8679 | 88 912 | 33277| 0.43 6.73|
Info: 11000 | 1379 9620 | 59 941 | 32422| 0.38 7.11|
Info: 12000 | 1487 10512 | 108 892 | 31547| 0.43 7.53|
Info: 13000 | 1614 11385 | 127 873 | 30788| 0.45 7.98|
Info: 14000 | 1736 12263 | 122 878 | 29979| 0.50 8.48|
Info: 15000 | 1858 13141 | 122 878 | 29163| 0.41 8.88|
Info: 16000 | 2018 13981 | 160 840 | 28553| 0.39 9.28|
Info: 17000 | 2172 14827 | 154 846 | 27750| 0.38 9.65|
Info: 18000 | 2264 15735 | 92 908 | 26927| 0.37 10.03|
Info: 19000 | 2394 16605 | 130 870 | 26180| 0.45 10.47|
Info: 20000 | 2513 17484 | 119 879 | 25386| 0.49 10.97|
Info: 21000 | 2685 18310 | 172 826 | 24597| 0.48 11.45|
Info: 22000 | 2854 19140 | 169 830 | 23799| 0.74 12.19|
Info: 23000 | 3037 19955 | 183 815 | 23081| 0.52 12.71|
Info: 24000 | 3242 20739 | 205 784 | 22351| 0.49 13.20|
Info: 25000 | 3452 21507 | 210 768 | 21655| 0.45 13.65|
Info: 26000 | 3623 22296 | 171 789 | 20923| 0.40 14.05|
Info: 27000 | 3748 23098 | 125 802 | 20099| 0.36 14.41|
Info: 28000 | 3874 23852 | 126 754 | 19323| 0.38 14.79|
Info: 29000 | 4029 24628 | 155 776 | 18603| 0.42 15.22|
Info: 30000 | 4206 25400 | 177 772 | 17887| 0.37 15.59|
Info: 31000 | 4405 26157 | 199 757 | 17234| 0.53 16.12|
Info: 32000 | 4550 26941 | 145 784 | 16442| 0.41 16.53|
Info: 33000 | 4733 27680 | 183 739 | 15692| 0.51 17.03|
Info: 34000 | 4830 28508 | 97 828 | 14830| 0.51 17.55|
Info: 35000 | 4974 29267 | 144 759 | 14002| 0.51 18.06|
Info: 36000 | 5121 30070 | 147 803 | 13252| 0.62 18.68|
Info: 37000 | 5276 30852 | 155 782 | 12481| 0.53 19.21|
Info: 38000 | 5418 31657 | 142 805 | 11685| 0.55 19.76|
Info: 39000 | 5585 32432 | 167 775 | 10932| 0.53 20.29|
Info: 40000 | 5782 33190 | 197 758 | 10382| 0.63 20.92|
Info: 41000 | 5881 34022 | 99 832 | 9533| 0.33 21.25|
Info: 42000 | 6035 34803 | 154 781 | 8768| 0.35 21.60|
Info: 43000 | 6261 35560 | 226 757 | 8323| 0.98 22.57|
Info: 44000 | 6398 36369 | 137 809 | 7555| 0.60 23.17|
Info: 45000 | 6582 37126 | 184 757 | 6855| 0.63 23.80|
Info: 46000 | 6907 37799 | 325 673 | 6494| 1.01 24.81|
Info: 47000 | 7057 38581 | 150 782 | 5799| 0.69 25.50|
Info: 48000 | 7199 39433 | 142 852 | 4978| 0.48 25.98|
Info: 49000 | 7563 40069 | 364 636 | 4631| 1.05 27.03|
Info: 50000 | 7764 40864 | 201 795 | 3970| 0.66 27.69|
Info: 51000 | 7960 41668 | 196 804 | 3385| 0.70 28.38|
Info: 52000 | 8369 42259 | 409 591 | 3109| 1.52 29.90|
Info: 53000 | 8777 42851 | 408 592 | 2889| 1.44 31.35|
Info: 54000 | 9045 43583 | 268 732 | 2315| 0.73 32.08|
Info: 55000 | 9217 44352 | 172 769 | 1753| 0.69 32.77|
Info: 56000 | 9370 45051 | 153 699 | 1041| 0.72 33.49|
Info: 57000 | 9601 45723 | 231 672 | 525| 1.08 34.57|
Info: 57683 | 9709 46204 | 108 481 | 0| 0.60 35.17|
Info: Routing complete.
Info: Router1 time 57.52s
Info: Checksum: 0x95485497
Info: Router1 time 35.17s
Info: Checksum: 0x409be511
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q.Q
Info: routing 1.02 1.42 Net u_arbiter_wide.m_addr[1] (24,4) -> (23,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_1.B
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.60 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_1.F
Info: routing 0.51 2.11 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D[0] (23,8) -> (22,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.A
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_7.Q
Info: routing 0.85 1.24 Net u_arbiter_wide.m_addr[7] (24,11) -> (25,9)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D_LUT4_Z.B
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.29 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.F
Info: routing 0.66 2.94 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (22,8) -> (22,7)
Info: logic 0.18 1.42 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D_LUT4_Z.F
Info: routing 0.45 1.88 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D[1] (25,9) -> (25,9)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.06 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1.F
Info: routing 0.60 2.65 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (25,9) -> (25,9)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.12 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 3.58 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (22,7) -> (22,7)
Info: logic 0.18 2.83 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.56 3.39 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (25,9) -> (24,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.76 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.34 4.10 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (22,7) -> (21,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 3.57 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.45 4.03 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (24,8) -> (24,8)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.28 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.76 5.04 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (21,7) -> (14,7)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 4.21 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.22 5.43 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (24,8) -> (12,11)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.22 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.65 5.87 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (14,7) -> (15,5)
Info: logic 0.18 5.61 Source u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.01 6.62 Net u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (12,11) -> (19,8)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.05 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.17 6.22 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (15,5) -> (15,5)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: logic 0.18 6.80 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.57 7.37 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (19,8) -> (16,4)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.40 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.35 6.76 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (15,5) -> (15,5)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: logic 0.18 7.55 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.34 7.90 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (16,4) -> (16,4)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.94 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 2.81 9.75 Net u_host_arb.m_wr_LUT4_C_Z[3] (15,5) -> (5,45)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: logic 0.18 8.08 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 2.02 10.10 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (16,4) -> (5,25)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.93 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 2.09 12.02 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (5,45) -> (5,7)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.D
Info: logic 0.18 10.28 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.86 12.13 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (5,25) -> (5,54)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 12.20 Source u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.F
Info: routing 0.12 12.32 Net u_sdram_backend.state_TRELLIS_FF_Q_3_DI (5,7) -> (5,7)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: setup 0.00 12.32 Source u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: 2.38 ns logic, 9.94 ns routing
Info: setup 0.00 12.13 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q.CE
Info: 2.19 ns logic, 9.94 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 0.77 0.77 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,14)
Info: Sink ext_rst_n_LUT4_D.D
Info: source 0.00 0.00 Source sdram_dq[2]$tr_io.O
Info: routing 2.90 2.90 Net sdram_dq[2]$TRELLIS_IO_IN (0,29) -> (15,8)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 0.95 Source ext_rst_n_LUT4_D.F
Info: routing 2.72 3.67 Net ext_rst_n_LUT4_D_Z (2,14) -> (17,40)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 3.96 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 3.49 ns routing
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.08 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.56 3.64 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D[2] (15,8) -> (14,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_114_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.83 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_114_DI_LUT4_Z.F
Info: routing 0.12 3.94 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_114_DI (14,7) -> (14,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_114.DI
Info: setup 0.00 3.94 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_114.DI
Info: 0.36 ns logic, 3.58 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 1.22 1.61 Net u_spi_bridge.byte_idx[2] (20,33) -> (19,29)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.D
Info: routing 0.77 1.16 Net u_spi_bridge.byte_idx[2] (22,48) -> (21,45)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.79 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.34 2.13 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (19,29) -> (19,29)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 1.34 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.48 1.82 Net u_dataflow_core.reg_result_addr_TRELLIS_FF_Q_CE_LUT4_Z_C[0] (21,45) -> (21,45)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.31 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 2.01 4.32 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (19,29) -> (14,56)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: logic 0.18 2.00 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.F
Info: routing 1.24 3.24 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (21,45) -> (16,52)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.50 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.80 5.30 Net spi_miso_LUT4_Z_B[2] (14,56) -> (15,57)
Info: logic 0.18 3.42 Source spi_miso_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.71 4.14 Net spi_miso_LUT4_Z_B[2] (16,52) -> (16,53)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.48 Source spi_miso_LUT4_Z.F
Info: routing 1.53 7.01 Net spi_miso$TRELLIS_IO_OUT (15,57) -> (0,62)
Info: logic 0.18 4.32 Source spi_miso_LUT4_Z.F
Info: routing 1.77 6.08 Net spi_miso$TRELLIS_IO_OUT (16,53) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.89 ns routing
Info: 1.12 ns logic, 4.97 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 81.20 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 82.43 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.96 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.01 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.94 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.08 ns
Info: Slack histogram:
Info: legend: * represents 40 endpoint(s)
Info: + represents [1,40) endpoint(s)
Info: [ 3309, 3890) |+
Info: [ 3890, 4471) |+
Info: [ 4471, 5052) |+
Info: [ 5052, 5633) |+
Info: [ 5633, 6214) |*+
Info: [ 6214, 6795) |******+
Info: [ 6795, 7376) |********+
Info: [ 7376, 7957) |******+
Info: [ 7957, 8538) |*********+
Info: [ 8538, 9119) |************+
Info: [ 9119, 9700) |****************+
Info: [ 9700, 10281) |**************************+
Info: [ 10281, 10862) |********************************+
Info: [ 10862, 11443) |*****************************************+
Info: [ 11443, 12024) |****************************************+
Info: [ 12024, 12605) |****************************************+
Info: [ 12605, 13186) |********************************************************+
Info: [ 13186, 13767) |*****************************************************+
Info: [ 13767, 14348) |************************************************************
Info: [ 14348, 14929) |**************************************************+
Info: legend: * represents 44 endpoint(s)
Info: + represents [1,44) endpoint(s)
Info: [ 3493, 4065) |+
Info: [ 4065, 4637) |+
Info: [ 4637, 5209) |+
Info: [ 5209, 5781) |+
Info: [ 5781, 6353) |***+
Info: [ 6353, 6925) |****+
Info: [ 6925, 7497) |*****+
Info: [ 7497, 8069) |*****+
Info: [ 8069, 8641) |********+
Info: [ 8641, 9213) |*********+
Info: [ 9213, 9785) |****************+
Info: [ 9785, 10357) |*********************+
Info: [ 10357, 10929) |********************************+
Info: [ 10929, 11501) |*****************************************+
Info: [ 11501, 12073) |********************************************+
Info: [ 12073, 12645) |****************************************+
Info: [ 12645, 13217) |*****************************************+
Info: [ 13217, 13789) |***********************************************+
Info: [ 13789, 14361) |************************************************************
Info: [ 14361, 14933) |********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed1.log
+239 -226
View File
@@ -1,13 +1,13 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: Total LUT4s: 7262/43848 16%
Info: logic LUTs: 4612/43848 10%
Info: carry LUTs: 1480/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Total DFFs: 6529/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
@@ -36,11 +36,11 @@ Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
@@ -79,13 +79,13 @@ Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: 2373 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Checksum: 0xa739669a
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
@@ -113,288 +113,301 @@ Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_FF: 6529/ 43848 14%
Info: TRELLIS_COMB: 7712/ 43848 17%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 655670.
Info: at initial placer iter 0, wirelen = 3827
Info: at initial placer iter 1, wirelen = 3206
Info: at initial placer iter 2, wirelen = 3155
Info: at initial placer iter 3, wirelen = 3232
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3130, spread = 109014, legal = 126494; time = 0.52s
Info: at iteration #2, type ALL: wirelen solved = 13231, spread = 79811, legal = 97134; time = 0.48s
Info: at iteration #3, type ALL: wirelen solved = 18697, spread = 72512, legal = 87983; time = 0.49s
Info: at iteration #4, type ALL: wirelen solved = 23287, spread = 70058, legal = 86103; time = 0.43s
Info: at iteration #5, type ALL: wirelen solved = 26264, spread = 67123, legal = 84736; time = 0.46s
Info: at iteration #6, type ALL: wirelen solved = 27184, spread = 65554, legal = 81619; time = 0.49s
Info: at iteration #7, type ALL: wirelen solved = 28331, spread = 64778, legal = 81607; time = 0.41s
Info: at iteration #8, type ALL: wirelen solved = 28958, spread = 64602, legal = 80938; time = 0.40s
Info: at iteration #9, type ALL: wirelen solved = 29749, spread = 64076, legal = 81736; time = 0.37s
Info: at iteration #10, type ALL: wirelen solved = 30280, spread = 63693, legal = 79295; time = 0.35s
Info: at iteration #11, type ALL: wirelen solved = 30964, spread = 63529, legal = 80035; time = 0.37s
Info: at iteration #12, type ALL: wirelen solved = 31577, spread = 63732, legal = 80122; time = 0.42s
Info: at iteration #13, type ALL: wirelen solved = 32309, spread = 64165, legal = 81845; time = 0.39s
Info: at iteration #14, type ALL: wirelen solved = 33191, spread = 63991, legal = 80333; time = 0.39s
Info: at iteration #15, type ALL: wirelen solved = 33371, spread = 64423, legal = 79749; time = 0.37s
Info: HeAP Placer Time: 9.08s
Info: of which solving equations: 4.34s
Info: of which spreading cells: 0.63s
Info: of which strict legalisation: 2.18s
Info: Creating initial analytic placement for 8052 cells, random placement wirelen = 660684.
Info: at initial placer iter 0, wirelen = 3803
Info: at initial placer iter 1, wirelen = 3378
Info: at initial placer iter 2, wirelen = 3113
Info: at initial placer iter 3, wirelen = 2949
Info: Running main analytical placer, max placement attempts per cell = 26342911.
Info: at iteration #1, type ALL: wirelen solved = 2909, spread = 112770, legal = 127780; time = 0.50s
Info: at iteration #2, type ALL: wirelen solved = 12968, spread = 86263, legal = 103294; time = 0.45s
Info: at iteration #3, type ALL: wirelen solved = 20172, spread = 81550, legal = 93219; time = 0.42s
Info: at iteration #4, type ALL: wirelen solved = 25808, spread = 75490, legal = 93566; time = 0.43s
Info: at iteration #5, type ALL: wirelen solved = 29057, spread = 72435, legal = 87627; time = 0.44s
Info: at iteration #6, type ALL: wirelen solved = 30759, spread = 70172, legal = 86980; time = 0.42s
Info: at iteration #7, type ALL: wirelen solved = 31353, spread = 69534, legal = 87567; time = 0.50s
Info: at iteration #8, type ALL: wirelen solved = 32609, spread = 72493, legal = 86483; time = 0.46s
Info: at iteration #9, type ALL: wirelen solved = 34652, spread = 70890, legal = 88630; time = 0.48s
Info: at iteration #10, type ALL: wirelen solved = 34993, spread = 69972, legal = 87146; time = 0.45s
Info: at iteration #11, type ALL: wirelen solved = 34856, spread = 69841, legal = 86852; time = 0.51s
Info: at iteration #12, type ALL: wirelen solved = 35830, spread = 69956, legal = 88366; time = 0.46s
Info: at iteration #13, type ALL: wirelen solved = 36096, spread = 70176, legal = 85158; time = 0.45s
Info: at iteration #14, type ALL: wirelen solved = 37098, spread = 70021, legal = 83868; time = 0.37s
Info: at iteration #15, type ALL: wirelen solved = 37476, spread = 69858, legal = 83933; time = 0.49s
Info: at iteration #16, type ALL: wirelen solved = 37708, spread = 69862, legal = 82898; time = 0.48s
Info: at iteration #17, type ALL: wirelen solved = 38081, spread = 70354, legal = 86125; time = 0.49s
Info: at iteration #18, type ALL: wirelen solved = 38876, spread = 70999, legal = 84933; time = 0.42s
Info: at iteration #19, type ALL: wirelen solved = 39078, spread = 71607, legal = 85847; time = 0.37s
Info: at iteration #20, type ALL: wirelen solved = 39781, spread = 71148, legal = 85953; time = 0.45s
Info: at iteration #21, type ALL: wirelen solved = 40375, spread = 72313, legal = 87197; time = 0.39s
Info: HeAP Placer Time: 12.79s
Info: of which solving equations: 5.92s
Info: of which spreading cells: 0.99s
Info: of which strict legalisation: 3.15s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1848, wirelen = 79295
Info: at iteration #5: temp = 0.000000, timing cost = 1158, wirelen = 72990
Info: at iteration #10: temp = 0.000000, timing cost = 1636, wirelen = 71066
Info: at iteration #15: temp = 0.000000, timing cost = 1651, wirelen = 70413
Info: at iteration #20: temp = 0.000000, timing cost = 1556, wirelen = 70115
Info: at iteration #25: temp = 0.000000, timing cost = 1596, wirelen = 69993
Info: at iteration #30: temp = 0.000000, timing cost = 1545, wirelen = 69963
Info: at iteration #31: temp = 0.000000, timing cost = 1560, wirelen = 69952
Info: SA placement time 29.80s
Info: at iteration #1: temp = 0.000000, timing cost = 1265, wirelen = 82898
Info: at iteration #5: temp = 0.000000, timing cost = 927, wirelen = 76655
Info: at iteration #10: temp = 0.000000, timing cost = 1851, wirelen = 74803
Info: at iteration #15: temp = 0.000000, timing cost = 1888, wirelen = 74184
Info: at iteration #20: temp = 0.000000, timing cost = 1728, wirelen = 73925
Info: at iteration #25: temp = 0.000000, timing cost = 1588, wirelen = 73831
Info: at iteration #25: temp = 0.000000, timing cost = 1586, wirelen = 73831
Info: SA placement time 24.23s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 81.02 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 77.99 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 5.07 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.63 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.89 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.01 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 3282, 3871) |*+
Info: [ 3871, 4460) |**+
Info: [ 4460, 5049) |****+
Info: [ 5049, 5638) |*****+
Info: [ 5638, 6227) |*******+
Info: [ 6227, 6816) |*******+
Info: [ 6816, 7405) |********+
Info: [ 7405, 7994) |************+
Info: [ 7994, 8583) |****************************+
Info: [ 8583, 9172) |**************************************+
Info: [ 9172, 9761) |**********************************+
Info: [ 9761, 10350) |********************************************+
Info: [ 10350, 10939) |**************************************+
Info: [ 10939, 11528) |***************************+
Info: [ 11528, 12117) |***************************+
Info: [ 12117, 12706) |*****************************************+
Info: [ 12706, 13295) |*******************************************************+
Info: [ 13295, 13884) |************************************************************
Info: [ 13884, 14473) |**********************************************+
Info: [ 14473, 15062) |********************************************+
Info: Checksum: 0x9d313277
Info: legend: * represents 31 endpoint(s)
Info: + represents [1,31) endpoint(s)
Info: [ 2803, 3416) |+
Info: [ 3416, 4029) |**+
Info: [ 4029, 4642) |*****+
Info: [ 4642, 5255) |*******+
Info: [ 5255, 5868) |******+
Info: [ 5868, 6481) |*******+
Info: [ 6481, 7094) |*********+
Info: [ 7094, 7707) |*********+
Info: [ 7707, 8320) |********************+
Info: [ 8320, 8933) |****************************************+
Info: [ 8933, 9546) |**************************************+
Info: [ 9546, 10159) |**********************************************+
Info: [ 10159, 10772) |****************************************************+
Info: [ 10772, 11385) |*********************************************+
Info: [ 11385, 11998) |*************************************+
Info: [ 11998, 12611) |*********************************************+
Info: [ 12611, 13224) |*****************************************************+
Info: [ 13224, 13837) |************************************************************
Info: [ 13837, 14450) |**********************************************************+
Info: [ 14450, 15063) |**************************************************+
Info: Checksum: 0x08288d0d
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39258 arcs.
Info: Routing 40964 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 693 306 | 693 306 | 39096| 1.46 1.46|
Info: 2000 | 1126 873 | 433 567 | 39076| 1.53 2.99|
Info: 3000 | 1530 1469 | 404 596 | 38869| 1.26 4.25|
Info: 4000 | 2003 1996 | 473 527 | 38635| 1.30 5.54|
Info: 5000 | 2497 2502 | 494 506 | 38323| 0.91 6.46|
Info: 6000 | 2713 3286 | 216 784 | 37633| 0.88 7.34|
Info: 7000 | 2846 4153 | 133 867 | 36825| 0.52 7.86|
Info: 8000 | 2993 5006 | 147 853 | 36050| 0.44 8.31|
Info: 9000 | 3085 5914 | 92 908 | 35184| 0.67 8.97|
Info: 10000 | 3210 6789 | 125 875 | 34448| 0.63 9.61|
Info: 11000 | 3365 7634 | 155 845 | 33777| 0.54 10.15|
Info: 12000 | 3488 8511 | 123 877 | 32921| 0.45 10.60|
Info: 13000 | 3604 9395 | 116 884 | 32117| 0.61 11.21|
Info: 14000 | 3753 10246 | 149 851 | 31414| 0.43 11.65|
Info: 15000 | 3859 11140 | 106 894 | 30625| 0.52 12.16|
Info: 16000 | 3988 12011 | 129 871 | 29811| 0.50 12.66|
Info: 17000 | 4095 12904 | 107 893 | 28950| 0.46 13.12|
Info: 18000 | 4245 13754 | 150 850 | 28148| 0.42 13.54|
Info: 19000 | 4404 14595 | 159 841 | 27427| 0.53 14.07|
Info: 20000 | 4564 15435 | 160 840 | 26641| 0.47 14.54|
Info: 21000 | 4759 16240 | 195 805 | 25996| 0.53 15.06|
Info: 22000 | 4950 17049 | 191 809 | 25381| 0.61 15.68|
Info: 23000 | 5146 17853 | 196 804 | 24686| 0.46 16.13|
Info: 24000 | 5365 18634 | 219 781 | 24022| 0.56 16.69|
Info: 25000 | 5569 19430 | 204 796 | 23322| 0.57 17.26|
Info: 26000 | 5849 20129 | 280 699 | 22848| 1.00 18.25|
Info: 27000 | 6046 20912 | 197 783 | 22131| 0.48 18.74|
Info: 28000 | 6296 21636 | 250 724 | 21735| 0.42 19.16|
Info: 29000 | 6526 22357 | 230 721 | 21082| 0.46 19.61|
Info: 30000 | 6821 23023 | 295 666 | 20691| 0.79 20.41|
Info: 31000 | 7079 23727 | 258 704 | 20077| 0.46 20.87|
Info: 32000 | 7357 24421 | 278 694 | 19443| 0.47 21.34|
Info: 33000 | 7631 25119 | 274 698 | 18810| 0.58 21.93|
Info: 34000 | 7858 25850 | 227 731 | 18131| 0.46 22.39|
Info: 35000 | 8109 26568 | 251 718 | 17565| 0.62 23.01|
Info: 36000 | 8335 27283 | 226 715 | 16860| 0.58 23.58|
Info: 37000 | 8595 27983 | 260 700 | 16322| 0.66 24.24|
Info: 38000 | 8823 28692 | 228 709 | 15646| 0.55 24.79|
Info: 39000 | 9053 29430 | 230 738 | 14965| 0.70 25.49|
Info: 40000 | 9280 30155 | 227 725 | 14422| 0.51 26.00|
Info: 41000 | 9440 30940 | 160 785 | 13686| 0.70 26.70|
Info: 42000 | 9608 31707 | 168 767 | 12934| 0.42 27.12|
Info: 43000 | 9801 32456 | 193 749 | 12413| 0.58 27.70|
Info: 44000 | 10006 33208 | 205 752 | 11792| 0.76 28.46|
Info: 45000 | 10231 33961 | 225 753 | 11237| 0.63 29.09|
Info: 46000 | 10445 34688 | 214 727 | 10562| 0.63 29.72|
Info: 47000 | 10748 35366 | 303 678 | 10280| 1.19 30.91|
Info: 48000 | 10906 36162 | 158 796 | 9566| 0.64 31.55|
Info: 49000 | 11138 36866 | 232 704 | 9099| 0.81 32.35|
Info: 50000 | 11379 37605 | 241 739 | 8636| 1.15 33.50|
Info: 51000 | 11614 38353 | 235 748 | 8095| 0.74 34.25|
Info: 52000 | 11760 39156 | 146 803 | 7362| 0.42 34.66|
Info: 53000 | 11955 39884 | 195 728 | 6759| 0.56 35.22|
Info: 54000 | 12264 40569 | 309 685 | 6419| 1.09 36.31|
Info: 55000 | 12519 41299 | 255 730 | 6110| 1.07 37.38|
Info: 56000 | 12652 42139 | 133 840 | 5354| 0.35 37.73|
Info: 57000 | 12880 42905 | 228 766 | 4884| 0.78 38.51|
Info: 58000 | 13308 43477 | 428 572 | 4732| 1.40 39.91|
Info: 59000 | 13659 44126 | 351 649 | 4477| 1.03 40.94|
Info: 60000 | 13934 44849 | 275 723 | 4173| 1.05 41.99|
Info: 61000 | 14150 45633 | 216 784 | 3535| 0.54 42.54|
Info: 62000 | 14543 46240 | 393 607 | 3185| 1.17 43.71|
Info: 63000 | 14992 46791 | 449 551 | 2965| 1.31 45.01|
Info: 64000 | 15372 47411 | 380 620 | 2691| 1.33 46.34|
Info: 65000 | 15705 48078 | 333 667 | 2320| 0.83 47.17|
Info: 66000 | 15884 48850 | 179 772 | 1640| 0.62 47.79|
Info: 67000 | 16167 49509 | 283 659 | 1310| 1.04 48.83|
Info: 68000 | 16364 50216 | 197 707 | 835| 0.77 49.60|
Info: 69000 | 16564 50946 | 200 730 | 461| 0.74 50.34|
Info: 69905 | 16847 51501 | 283 555 | 0| 1.00 51.34|
Info: 1000 | 672 327 | 672 327 | 40792| 1.42 1.42|
Info: 2000 | 1140 859 | 468 532 | 40542| 1.49 2.90|
Info: 3000 | 1679 1320 | 539 461 | 40359| 1.30 4.21|
Info: 4000 | 2150 1849 | 471 529 | 39999| 1.27 5.47|
Info: 5000 | 2376 2623 | 226 774 | 39456| 0.92 6.39|
Info: 6000 | 2538 3461 | 162 838 | 38751| 0.67 7.07|
Info: 7000 | 2677 4322 | 139 861 | 37948| 0.62 7.69|
Info: 8000 | 2793 5206 | 116 884 | 37186| 0.86 8.56|
Info: 9000 | 2904 6095 | 111 889 | 36344| 0.50 9.05|
Info: 10000 | 3014 6985 | 110 890 | 35491| 0.48 9.53|
Info: 11000 | 3143 7856 | 129 871 | 34685| 0.47 10.01|
Info: 12000 | 3305 8694 | 162 838 | 33891| 0.52 10.52|
Info: 13000 | 3437 9562 | 132 868 | 33046| 0.46 10.99|
Info: 14000 | 3581 10418 | 144 856 | 32366| 0.58 11.57|
Info: 15000 | 3741 11258 | 160 840 | 31795| 0.98 12.55|
Info: 16000 | 3880 12119 | 139 861 | 31037| 0.39 12.94|
Info: 17000 | 4021 12978 | 141 859 | 30282| 0.42 13.36|
Info: 18000 | 4147 13852 | 126 874 | 29477| 0.45 13.81|
Info: 19000 | 4354 14645 | 207 793 | 28900| 0.53 14.34|
Info: 20000 | 4545 15454 | 191 809 | 28184| 0.52 14.85|
Info: 21000 | 4686 16313 | 141 859 | 27412| 0.44 15.30|
Info: 22000 | 4895 17104 | 209 791 | 26782| 0.47 15.77|
Info: 23000 | 5214 17785 | 319 681 | 26234| 0.46 16.22|
Info: 24000 | 5474 18525 | 260 740 | 25746| 0.66 16.88|
Info: 25000 | 5637 19362 | 163 837 | 24972| 0.41 17.29|
Info: 26000 | 5804 20194 | 167 832 | 24323| 0.66 17.95|
Info: 27000 | 6012 20984 | 208 790 | 23640| 0.45 18.40|
Info: 28000 | 6204 21778 | 192 794 | 22996| 0.48 18.88|
Info: 29000 | 6536 22436 | 332 658 | 22462| 0.44 19.32|
Info: 30000 | 6878 23082 | 342 646 | 21921| 0.48 19.80|
Info: 31000 | 7138 23783 | 260 701 | 21274| 0.46 20.26|
Info: 32000 | 7361 24495 | 223 712 | 20581| 0.54 20.80|
Info: 33000 | 7601 25221 | 240 726 | 20458| 0.49 21.29|
Info: 34000 | 7850 25903 | 249 682 | 19894| 0.52 21.81|
Info: 35000 | 8088 26590 | 238 687 | 19256| 0.57 22.38|
Info: 36000 | 8300 27333 | 212 743 | 18809| 0.56 22.93|
Info: 37000 | 8524 28058 | 224 725 | 18345| 0.55 23.48|
Info: 38000 | 8724 28833 | 200 775 | 17947| 0.72 24.20|
Info: 39000 | 8969 29578 | 245 745 | 17560| 0.68 24.88|
Info: 40000 | 9170 30343 | 201 765 | 16923| 0.58 25.47|
Info: 41000 | 9360 31092 | 190 749 | 16219| 0.53 26.00|
Info: 42000 | 9564 31850 | 204 758 | 15651| 0.67 26.68|
Info: 43000 | 9776 32610 | 212 760 | 15113| 0.68 27.35|
Info: 44000 | 9946 33424 | 170 814 | 14860| 0.90 28.25|
Info: 45000 | 10125 34168 | 179 744 | 14197| 0.58 28.83|
Info: 46000 | 10321 34890 | 196 722 | 13542| 0.70 29.52|
Info: 47000 | 10473 35683 | 152 793 | 12808| 0.55 30.07|
Info: 48000 | 10668 36421 | 195 738 | 12230| 0.85 30.92|
Info: 49000 | 10834 37213 | 166 792 | 11591| 0.82 31.73|
Info: 50000 | 11009 37977 | 175 764 | 10869| 0.69 32.42|
Info: 51000 | 11230 38743 | 221 766 | 10293| 1.03 33.45|
Info: 52000 | 11451 39506 | 221 763 | 10060| 1.06 34.51|
Info: 53000 | 11632 40302 | 181 796 | 9466| 0.68 35.19|
Info: 54000 | 11793 41064 | 161 762 | 8854| 0.48 35.67|
Info: 55000 | 12119 41734 | 326 670 | 8725| 1.12 36.79|
Info: 56000 | 12370 42483 | 251 749 | 8403| 1.26 38.06|
Info: 57000 | 12528 43259 | 158 776 | 7698| 0.49 38.55|
Info: 58000 | 12691 44022 | 163 763 | 6972| 0.56 39.11|
Info: 59000 | 13010 44675 | 319 653 | 6657| 1.03 40.15|
Info: 60000 | 13370 45312 | 360 637 | 6455| 1.05 41.20|
Info: 61000 | 13665 45994 | 295 682 | 6122| 1.37 42.56|
Info: 62000 | 13871 46775 | 206 781 | 5541| 0.86 43.42|
Info: 63000 | 14119 47513 | 248 738 | 4989| 0.91 44.33|
Info: 64000 | 14506 48126 | 387 613 | 4752| 1.87 46.20|
Info: 65000 | 14911 48721 | 405 595 | 4453| 1.50 47.70|
Info: 66000 | 15127 49501 | 216 780 | 3927| 0.92 48.63|
Info: 67000 | 15342 50286 | 215 785 | 3349| 0.75 49.38|
Info: 68000 | 15771 50857 | 429 571 | 3148| 2.04 51.42|
Info: 69000 | 16160 51468 | 389 611 | 3336| 1.64 53.06|
Info: 70000 | 16428 52200 | 268 732 | 3121| 1.28 54.34|
Info: 71000 | 16882 52746 | 454 546 | 2925| 2.08 56.42|
Info: 72000 | 17201 53427 | 319 681 | 2755| 1.17 57.59|
Info: 73000 | 17462 54166 | 261 739 | 2489| 0.91 58.50|
Info: 74000 | 17828 54800 | 366 634 | 2121| 0.97 59.47|
Info: 75000 | 18070 55479 | 242 679 | 1625| 1.16 60.63|
Info: 76000 | 18239 56171 | 169 692 | 894| 0.95 61.58|
Info: 77000 | 18423 56852 | 184 681 | 225| 0.98 62.56|
Info: 77272 | 18462 57040 | 39 188 | 0| 0.33 62.89|
Info: Routing complete.
Info: Router1 time 51.34s
Info: Checksum: 0xfd994332
Info: Router1 time 62.89s
Info: Checksum: 0xbaacf4e1
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_23.Q
Info: routing 0.78 1.17 Net u_arbiter_wide.m_addr[24] (25,2) -> (24,5)
Info: Sink u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.A
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_25.Q
Info: routing 1.02 1.41 Net u_arbiter_wide.m_addr[25] (25,8) -> (24,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D_LUT4_Z_1.A
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.36 Source u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.F
Info: routing 0.60 1.96 Net u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z_D[3] (24,5) -> (24,5)
Info: Sink u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z.D
Info: logic 0.18 1.59 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D_LUT4_Z_1.F
Info: routing 0.64 2.23 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D[2] (24,7) -> (22,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.14 Source u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_Z.F
Info: routing 0.64 2.78 Net u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z[3] (24,5) -> (23,5)
Info: Sink u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D.D
Info: logic 0.18 2.41 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1.F
Info: routing 0.45 2.87 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (22,7) -> (22,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.96 Source u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D.F
Info: routing 0.45 3.41 Net u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z[3] (23,5) -> (23,5)
Info: Sink u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D.D
Info: logic 0.18 3.05 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 3.50 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (22,7) -> (22,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.59 Source u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.63 4.22 Net u_sdram_backend.w_cache_valid[1]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z[3] (23,5) -> (25,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1.D
Info: logic 0.18 3.68 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.60 4.28 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (22,7) -> (22,4)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.41 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_1.F
Info: routing 0.90 5.30 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[1] (25,5) -> (15,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.B
Info: logic 0.18 4.45 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.97 5.43 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (22,4) -> (18,7)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.48 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.34 5.83 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (15,7) -> (15,7)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: logic 0.18 5.61 Source u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.49 6.09 Net u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (18,7) -> (18,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.27 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.56 6.83 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (18,7) -> (16,5)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.01 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.34 6.35 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (15,7) -> (15,7)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: logic 0.18 7.01 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.03 7.05 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (16,5) -> (16,5)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.53 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 1.52 8.05 Net u_host_arb.m_wr_LUT4_C_Z[3] (15,7) -> (6,17)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: logic 0.18 7.23 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 1.86 9.09 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (16,5) -> (5,29)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.23 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 1.89 10.12 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (6,17) -> (10,44)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_5.CE
Info: logic 0.18 9.27 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.46 10.73 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (5,29) -> (3,55)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_10.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 10.12 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_5.CE
Info: 2.02 ns logic, 8.10 ns routing
Info: setup 0.00 10.73 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_10.CE
Info: 2.19 ns logic, 8.53 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 3.06 3.06 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (12,2)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.B
Info: source 0.00 0.00 Source sdram_dq[0]$tr_io.O
Info: routing 2.42 2.42 Net sdram_dq[0]$TRELLIS_IO_IN (0,26) -> (11,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.24 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.63 3.88 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D[2] (12,2) -> (14,2)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.D
Info: logic 0.18 2.60 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.53 3.12 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D[2] (11,9) -> (11,11)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.05 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.F
Info: routing 0.12 4.17 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI (14,2) -> (14,2)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: setup 0.00 4.17 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: 0.36 ns logic, 3.81 ns routing
Info: logic 0.18 3.30 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI_LUT4_Z.F
Info: routing 0.12 3.42 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI (11,11) -> (11,11)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112.DI
Info: setup 0.00 3.42 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112.DI
Info: 0.36 ns logic, 3.06 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 0.94 1.33 Net u_spi_bridge.byte_idx[3] (24,42) -> (23,38)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.C
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_4.Q
Info: routing 0.86 1.25 Net u_dataflow_core.reg_result_addr_TRELLIS_FF_Q_CE_LUT4_Z_D[0] (18,49) -> (18,48)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.51 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.62 2.14 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (23,38) -> (23,38)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 1.43 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.F
Info: routing 1.46 2.89 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (18,48) -> (13,56)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.32 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.42 3.73 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (23,38) -> (16,45)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.91 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.50 4.41 Net spi_miso_LUT4_Z_B[2] (16,45) -> (17,45)
Info: logic 0.18 3.08 Source spi_miso_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.51 3.59 Net spi_miso_LUT4_Z_B[2] (13,56) -> (13,57)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.59 Source spi_miso_LUT4_Z.F
Info: routing 2.20 6.80 Net spi_miso$TRELLIS_IO_OUT (17,45) -> (0,62)
Info: logic 0.18 3.77 Source spi_miso_LUT4_Z.F
Info: routing 1.49 5.25 Net spi_miso$TRELLIS_IO_OUT (13,57) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.68 ns routing
Info: 0.94 ns logic, 4.32 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 98.82 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 93.23 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.17 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.80 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.42 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 5.25 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 5506, 5977) |+
Info: [ 5977, 6448) |+
Info: [ 6448, 6919) |****+
Info: [ 6919, 7390) |******+
Info: [ 7390, 7861) |********+
Info: [ 7861, 8332) |*******+
Info: [ 8332, 8803) |********+
Info: [ 8803, 9274) |************+
Info: [ 9274, 9745) |****************+
Info: [ 9745, 10216) |******************************+
Info: [ 10216, 10687) |*********************************+
Info: [ 10687, 11158) |*********************************+
Info: [ 11158, 11629) |*************************************+
Info: [ 11629, 12100) |******************************************+
Info: [ 12100, 12571) |*****************************+
Info: [ 12571, 13042) |***************************+
Info: [ 13042, 13513) |******************************************+
Info: [ 13513, 13984) |************************************************************
Info: [ 13984, 14455) |************************************************************
Info: [ 14455, 14926) |*****************************************+
Info: [ 4899, 5401) |+
Info: [ 5401, 5903) |*+
Info: [ 5903, 6405) |**+
Info: [ 6405, 6907) |****+
Info: [ 6907, 7409) |*******+
Info: [ 7409, 7911) |*******+
Info: [ 7911, 8413) |*********+
Info: [ 8413, 8915) |*******+
Info: [ 8915, 9417) |**********+
Info: [ 9417, 9919) |*********************+
Info: [ 9919, 10421) |*******************************+
Info: [ 10421, 10923) |*********************************+
Info: [ 10923, 11425) |******************************************+
Info: [ 11425, 11927) |**************************************************+
Info: [ 11927, 12429) |*************************************************+
Info: [ 12429, 12931) |*************************************+
Info: [ 12931, 13433) |*****************************************+
Info: [ 13433, 13935) |**********************************************+
Info: [ 13935, 14437) |************************************************************
Info: [ 14437, 14939) |*********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed2.log
+224 -235
View File
@@ -1,13 +1,13 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: Total LUT4s: 7262/43848 16%
Info: logic LUTs: 4612/43848 10%
Info: carry LUTs: 1480/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Total DFFs: 6529/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
@@ -36,11 +36,11 @@ Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
@@ -79,13 +79,13 @@ Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: 2373 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Checksum: 0xa739669a
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
@@ -113,298 +113,287 @@ Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_FF: 6529/ 43848 14%
Info: TRELLIS_COMB: 7712/ 43848 17%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 655030.
Info: at initial placer iter 0, wirelen = 3962
Info: at initial placer iter 1, wirelen = 3211
Info: at initial placer iter 2, wirelen = 3093
Info: at initial placer iter 3, wirelen = 2985
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 2941, spread = 115246, legal = 127776; time = 0.49s
Info: at iteration #2, type ALL: wirelen solved = 13107, spread = 84959, legal = 96142; time = 0.43s
Info: at iteration #3, type ALL: wirelen solved = 19618, spread = 74146, legal = 85837; time = 0.43s
Info: at iteration #4, type ALL: wirelen solved = 25379, spread = 70995, legal = 85148; time = 0.41s
Info: at iteration #5, type ALL: wirelen solved = 26790, spread = 69359, legal = 85551; time = 0.43s
Info: at iteration #6, type ALL: wirelen solved = 29110, spread = 66873, legal = 82846; time = 0.38s
Info: at iteration #7, type ALL: wirelen solved = 29658, spread = 66046, legal = 81698; time = 0.37s
Info: at iteration #8, type ALL: wirelen solved = 30830, spread = 69832, legal = 82932; time = 0.41s
Info: at iteration #9, type ALL: wirelen solved = 33846, spread = 69400, legal = 86531; time = 0.41s
Info: at iteration #10, type ALL: wirelen solved = 34265, spread = 68266, legal = 83836; time = 0.36s
Info: at iteration #11, type ALL: wirelen solved = 34380, spread = 67939, legal = 81038; time = 0.37s
Info: at iteration #12, type ALL: wirelen solved = 34715, spread = 68037, legal = 84566; time = 0.43s
Info: at iteration #13, type ALL: wirelen solved = 35337, spread = 68443, legal = 83899; time = 0.40s
Info: at iteration #14, type ALL: wirelen solved = 35790, spread = 68542, legal = 83721; time = 0.40s
Info: at iteration #15, type ALL: wirelen solved = 36382, spread = 68588, legal = 83108; time = 0.42s
Info: at iteration #16, type ALL: wirelen solved = 36751, spread = 68704, legal = 83352; time = 0.44s
Info: HeAP Placer Time: 9.44s
Info: of which solving equations: 4.82s
Info: of which spreading cells: 0.70s
Info: of which strict legalisation: 1.96s
Info: Creating initial analytic placement for 8052 cells, random placement wirelen = 656364.
Info: at initial placer iter 0, wirelen = 4067
Info: at initial placer iter 1, wirelen = 3249
Info: at initial placer iter 2, wirelen = 3044
Info: at initial placer iter 3, wirelen = 2994
Info: Running main analytical placer, max placement attempts per cell = 26342911.
Info: at iteration #1, type ALL: wirelen solved = 3134, spread = 116470, legal = 130535; time = 0.59s
Info: at iteration #2, type ALL: wirelen solved = 13401, spread = 88179, legal = 104882; time = 0.57s
Info: at iteration #3, type ALL: wirelen solved = 20516, spread = 77182, legal = 92611; time = 0.48s
Info: at iteration #4, type ALL: wirelen solved = 24741, spread = 74710, legal = 90138; time = 0.50s
Info: at iteration #5, type ALL: wirelen solved = 28917, spread = 69970, legal = 83614; time = 0.46s
Info: at iteration #6, type ALL: wirelen solved = 29993, spread = 70266, legal = 87100; time = 0.55s
Info: at iteration #7, type ALL: wirelen solved = 31523, spread = 71175, legal = 86281; time = 0.44s
Info: at iteration #8, type ALL: wirelen solved = 32373, spread = 73181, legal = 86603; time = 0.46s
Info: at iteration #9, type ALL: wirelen solved = 34940, spread = 70908, legal = 87087; time = 0.47s
Info: at iteration #10, type ALL: wirelen solved = 35132, spread = 72407, legal = 84422; time = 0.50s
Info: HeAP Placer Time: 7.50s
Info: of which solving equations: 4.05s
Info: of which spreading cells: 0.47s
Info: of which strict legalisation: 1.60s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1922, wirelen = 81038
Info: at iteration #5: temp = 0.000000, timing cost = 1579, wirelen = 75036
Info: at iteration #10: temp = 0.000000, timing cost = 1188, wirelen = 72869
Info: at iteration #15: temp = 0.000000, timing cost = 1208, wirelen = 72253
Info: at iteration #20: temp = 0.000000, timing cost = 1201, wirelen = 72048
Info: at iteration #22: temp = 0.000000, timing cost = 1197, wirelen = 72025
Info: SA placement time 20.66s
Info: at iteration #1: temp = 0.000000, timing cost = 958, wirelen = 83614
Info: at iteration #5: temp = 0.000000, timing cost = 1843, wirelen = 76142
Info: at iteration #10: temp = 0.000000, timing cost = 1135, wirelen = 73875
Info: at iteration #15: temp = 0.000000, timing cost = 1338, wirelen = 73266
Info: at iteration #20: temp = 0.000000, timing cost = 1324, wirelen = 72981
Info: at iteration #25: temp = 0.000000, timing cost = 1390, wirelen = 72843
Info: at iteration #30: temp = 0.000000, timing cost = 1389, wirelen = 72771
Info: at iteration #35: temp = 0.000000, timing cost = 1385, wirelen = 72718
Info: at iteration #35: temp = 0.000000, timing cost = 1383, wirelen = 72722
Info: SA placement time 38.56s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 74.68 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 79.57 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.45 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.00 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.58 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.70 ns
Info: Slack histogram:
Info: legend: * represents 33 endpoint(s)
Info: + represents [1,33) endpoint(s)
Info: [ 2234, 2875) |*+
Info: [ 2875, 3516) |**+
Info: [ 3516, 4157) |****+
Info: [ 4157, 4798) |*****+
Info: [ 4798, 5439) |********+
Info: [ 5439, 6080) |**********+
Info: [ 6080, 6721) |***************+
Info: [ 6721, 7362) |******************************+
Info: [ 7362, 8003) |********************************************+
Info: [ 8003, 8644) |******************************************+
Info: [ 8644, 9285) |******************************+
Info: [ 9285, 9926) |*******************************+
Info: [ 9926, 10567) |*******************************+
Info: [ 10567, 11208) |****************+
Info: [ 11208, 11849) |********************+
Info: [ 11849, 12490) |***************************************+
Info: [ 12490, 13131) |***********************************************************+
Info: [ 13131, 13772) |************************************************************
Info: [ 13772, 14413) |********************************************************+
Info: [ 14413, 15054) |**************************************************+
Info: Checksum: 0x5a66600d
Info: [ 3057, 3657) |+
Info: [ 3657, 4257) |+
Info: [ 4257, 4857) |******+
Info: [ 4857, 5457) |********+
Info: [ 5457, 6057) |*****+
Info: [ 6057, 6657) |******+
Info: [ 6657, 7257) |***********+
Info: [ 7257, 7857) |***********+
Info: [ 7857, 8457) |******************+
Info: [ 8457, 9057) |***************************************+
Info: [ 9057, 9657) |*******************************************+
Info: [ 9657, 10257) |****************************************************+
Info: [ 10257, 10857) |*****************************************+
Info: [ 10857, 11457) |***********************************+
Info: [ 11457, 12057) |********************************+
Info: [ 12057, 12657) |*****************************************+
Info: [ 12657, 13257) |****************************************************+
Info: [ 13257, 13857) |************************************************************
Info: [ 13857, 14457) |******************************************************+
Info: [ 14457, 15057) |**********************************************+
Info: Checksum: 0x816cfa98
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39414 arcs.
Info: Routing 40941 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 472 527 | 472 527 | 39020| 1.60 1.60|
Info: 2000 | 816 1183 | 344 656 | 38680| 1.14 2.74|
Info: 3000 | 1193 1806 | 377 623 | 38340| 1.33 4.07|
Info: 4000 | 1480 2519 | 287 713 | 37758| 1.01 5.09|
Info: 5000 | 1586 3413 | 106 894 | 36962| 0.64 5.72|
Info: 6000 | 1789 4210 | 203 797 | 36346| 0.65 6.38|
Info: 7000 | 1967 5032 | 178 822 | 35636| 0.73 7.11|
Info: 8000 | 2102 5897 | 135 865 | 34933| 0.90 8.01|
Info: 9000 | 2276 6723 | 174 826 | 34305| 1.32 9.33|
Info: 10000 | 2484 7515 | 208 792 | 33752| 1.32 10.65|
Info: 11000 | 2585 8414 | 101 899 | 32938| 0.58 11.23|
Info: 12000 | 2668 9331 | 83 917 | 32078| 0.46 11.68|
Info: 13000 | 2759 10240 | 91 909 | 31331| 0.37 12.06|
Info: 14000 | 2925 11074 | 166 834 | 30639| 0.51 12.56|
Info: 15000 | 3075 11924 | 150 850 | 29844| 0.45 13.02|
Info: 16000 | 3214 12785 | 139 861 | 29113| 0.49 13.51|
Info: 17000 | 3407 13592 | 193 807 | 28571| 0.45 13.96|
Info: 18000 | 3600 14399 | 193 807 | 27864| 0.41 14.37|
Info: 19000 | 3796 15203 | 196 804 | 27189| 0.47 14.85|
Info: 20000 | 3965 16034 | 169 831 | 26462| 0.53 15.38|
Info: 21000 | 4285 16714 | 320 680 | 25902| 0.45 15.83|
Info: 22000 | 4500 17499 | 215 785 | 25266| 0.49 16.32|
Info: 23000 | 4739 18260 | 239 761 | 24593| 0.40 16.72|
Info: 24000 | 4900 19099 | 161 839 | 23861| 0.53 17.25|
Info: 25000 | 5120 19878 | 220 779 | 23220| 0.44 17.69|
Info: 26000 | 5391 20604 | 271 726 | 23108| 0.92 18.62|
Info: 27000 | 5613 21382 | 222 778 | 22637| 0.97 19.59|
Info: 28000 | 5918 22061 | 305 679 | 22032| 0.42 20.00|
Info: 29000 | 6279 22682 | 361 621 | 21494| 0.41 20.41|
Info: 30000 | 6616 23312 | 337 630 | 20996| 0.49 20.90|
Info: 31000 | 6867 24028 | 251 716 | 20333| 0.47 21.37|
Info: 32000 | 7108 24738 | 241 710 | 19668| 0.44 21.82|
Info: 33000 | 7319 25472 | 211 734 | 19078| 0.49 22.31|
Info: 34000 | 7506 26222 | 187 750 | 18420| 0.45 22.76|
Info: 35000 | 7750 26950 | 244 728 | 17852| 0.58 23.33|
Info: 36000 | 7989 27677 | 239 727 | 17193| 0.59 23.92|
Info: 37000 | 8220 28393 | 231 716 | 16526| 0.52 24.44|
Info: 38000 | 8439 29114 | 219 721 | 16127| 0.61 25.04|
Info: 39000 | 8655 29856 | 216 742 | 15598| 0.74 25.78|
Info: 40000 | 8889 30587 | 234 731 | 14946| 0.55 26.33|
Info: 41000 | 9113 31322 | 224 735 | 14417| 0.56 26.89|
Info: 42000 | 9334 32059 | 221 737 | 13933| 0.66 27.55|
Info: 43000 | 9529 32824 | 195 765 | 13291| 0.60 28.16|
Info: 44000 | 9765 33513 | 236 689 | 12874| 0.85 29.01|
Info: 45000 | 9925 34321 | 160 808 | 12537| 0.78 29.79|
Info: 46000 | 10088 35128 | 163 807 | 11838| 0.55 30.34|
Info: 47000 | 10287 35867 | 199 739 | 11396| 0.72 31.06|
Info: 48000 | 10584 36558 | 297 691 | 10878| 0.73 31.79|
Info: 49000 | 10821 37310 | 237 752 | 10450| 0.90 32.70|
Info: 50000 | 10997 38053 | 176 743 | 9769| 0.53 33.23|
Info: 51000 | 11183 38835 | 186 782 | 9151| 0.49 33.71|
Info: 52000 | 11422 39557 | 239 722 | 8636| 0.82 34.53|
Info: 53000 | 11536 40376 | 114 819 | 7820| 0.56 35.09|
Info: 54000 | 11756 41092 | 220 716 | 7223| 0.68 35.77|
Info: 55000 | 11960 41872 | 204 780 | 6897| 0.79 36.57|
Info: 56000 | 12280 42550 | 320 678 | 6511| 1.03 37.59|
Info: 57000 | 12697 43133 | 417 583 | 6460| 1.44 39.04|
Info: 58000 | 12926 43891 | 229 758 | 6066| 0.86 39.90|
Info: 59000 | 13069 44724 | 143 833 | 5349| 0.50 40.40|
Info: 60000 | 13371 45420 | 302 696 | 4936| 0.91 41.31|
Info: 61000 | 13757 46034 | 386 614 | 4648| 1.39 42.69|
Info: 62000 | 14117 46666 | 360 632 | 4350| 1.26 43.95|
Info: 63000 | 14294 47489 | 177 823 | 3578| 0.35 44.30|
Info: 64000 | 14644 48139 | 350 650 | 3364| 1.35 45.65|
Info: 65000 | 15073 48710 | 429 571 | 3197| 1.69 47.34|
Info: 66000 | 15446 49337 | 373 627 | 2989| 1.55 48.90|
Info: 67000 | 15824 49959 | 378 622 | 2565| 1.10 49.99|
Info: 68000 | 16106 50677 | 282 718 | 2142| 0.75 50.74|
Info: 69000 | 16308 51423 | 202 746 | 1541| 0.82 51.56|
Info: 70000 | 16527 52084 | 219 661 | 923| 0.85 52.41|
Info: 71000 | 16911 52662 | 384 578 | 746| 1.39 53.80|
Info: 72000 | 17253 53254 | 342 592 | 397| 1.09 54.89|
Info: 72770 | 17468 53745 | 215 491 | 0| 0.90 55.80|
Info: 1000 | 642 357 | 642 357 | 40730| 1.60 1.60|
Info: 2000 | 1261 738 | 619 381 | 40550| 1.15 2.74|
Info: 3000 | 1590 1409 | 329 671 | 40076| 0.96 3.70|
Info: 4000 | 1908 2091 | 318 682 | 39589| 1.04 4.74|
Info: 5000 | 2118 2881 | 210 790 | 38887| 0.85 5.59|
Info: 6000 | 2225 3774 | 107 893 | 38090| 0.70 6.29|
Info: 7000 | 2330 4669 | 105 895 | 37231| 0.38 6.67|
Info: 8000 | 2429 5570 | 99 901 | 36471| 0.59 7.26|
Info: 9000 | 2510 6489 | 81 919 | 35681| 0.35 7.61|
Info: 10000 | 2592 7407 | 82 918 | 34830| 0.40 8.01|
Info: 11000 | 2700 8299 | 108 892 | 33980| 0.33 8.34|
Info: 12000 | 2845 9154 | 145 855 | 33259| 0.46 8.80|
Info: 13000 | 2988 10011 | 143 857 | 32497| 0.65 9.45|
Info: 14000 | 3148 10851 | 160 840 | 31814| 0.67 10.11|
Info: 15000 | 3315 11684 | 167 833 | 31141| 0.49 10.61|
Info: 16000 | 3499 12500 | 184 816 | 30704| 0.45 11.05|
Info: 17000 | 3637 13362 | 138 862 | 30036| 0.69 11.74|
Info: 18000 | 3811 14188 | 174 826 | 29537| 0.44 12.18|
Info: 19000 | 3989 15010 | 178 822 | 28891| 0.46 12.64|
Info: 20000 | 4184 15815 | 195 805 | 28288| 0.44 13.08|
Info: 21000 | 4371 16628 | 187 813 | 27657| 0.45 13.53|
Info: 22000 | 4644 17355 | 273 727 | 27061| 0.50 14.03|
Info: 23000 | 4969 18030 | 325 675 | 26531| 0.47 14.51|
Info: 24000 | 5174 18825 | 205 795 | 25858| 0.49 15.00|
Info: 25000 | 5410 19589 | 236 764 | 25367| 0.65 15.65|
Info: 26000 | 5657 20342 | 247 753 | 24818| 0.49 16.15|
Info: 27000 | 5878 21121 | 221 779 | 24288| 0.88 17.02|
Info: 28000 | 6111 21887 | 233 766 | 23772| 0.56 17.59|
Info: 29000 | 6463 22532 | 352 645 | 23274| 0.54 18.12|
Info: 30000 | 6804 23189 | 341 657 | 22797| 0.49 18.61|
Info: 31000 | 7140 23840 | 336 651 | 22306| 0.64 19.25|
Info: 32000 | 7404 24555 | 264 715 | 21751| 0.59 19.85|
Info: 33000 | 7618 25305 | 214 750 | 21150| 0.61 20.46|
Info: 34000 | 7773 26093 | 155 788 | 20518| 0.49 20.95|
Info: 35000 | 8015 26791 | 242 698 | 19854| 0.56 21.51|
Info: 36000 | 8247 27492 | 232 701 | 19262| 0.61 22.12|
Info: 37000 | 8498 28183 | 251 691 | 18652| 0.57 22.69|
Info: 38000 | 8722 28876 | 224 693 | 18022| 0.53 23.22|
Info: 39000 | 8956 29578 | 234 702 | 17374| 0.66 23.88|
Info: 40000 | 9167 30313 | 211 735 | 16770| 0.59 24.46|
Info: 41000 | 9425 31007 | 258 694 | 16149| 0.70 25.16|
Info: 42000 | 9666 31723 | 241 716 | 15689| 1.04 26.20|
Info: 43000 | 9862 32478 | 196 755 | 15039| 0.57 26.77|
Info: 44000 | 10058 33224 | 196 746 | 14330| 0.51 27.28|
Info: 45000 | 10218 33980 | 160 756 | 13694| 0.60 27.88|
Info: 46000 | 10409 34739 | 191 759 | 13017| 0.62 28.50|
Info: 47000 | 10637 35473 | 228 734 | 12505| 0.64 29.14|
Info: 48000 | 10800 36271 | 163 798 | 11949| 0.76 29.91|
Info: 49000 | 11029 36987 | 229 716 | 11316| 0.85 30.76|
Info: 50000 | 11234 37766 | 205 779 | 10752| 0.78 31.53|
Info: 51000 | 11500 38446 | 266 680 | 10288| 0.83 32.37|
Info: 52000 | 11704 39228 | 204 782 | 9884| 1.06 33.43|
Info: 53000 | 11803 40055 | 99 827 | 9005| 0.33 33.76|
Info: 54000 | 12023 40799 | 220 744 | 8532| 0.80 34.56|
Info: 55000 | 12363 41459 | 340 660 | 8260| 1.29 35.85|
Info: 56000 | 12502 42249 | 139 790 | 7619| 0.63 36.48|
Info: 57000 | 12643 43053 | 141 804 | 6799| 0.39 36.87|
Info: 58000 | 12962 43733 | 319 680 | 6553| 1.13 38.00|
Info: 59000 | 13269 44426 | 307 693 | 6404| 1.45 39.46|
Info: 60000 | 13633 45062 | 364 636 | 6223| 1.56 41.02|
Info: 61000 | 13860 45778 | 227 716 | 5825| 0.86 41.87|
Info: 62000 | 14024 46604 | 164 826 | 5072| 0.61 42.49|
Info: 63000 | 14307 47321 | 283 717 | 4730| 0.91 43.39|
Info: 64000 | 14709 47919 | 402 598 | 4466| 1.65 45.04|
Info: 65000 | 14968 48660 | 259 741 | 3931| 1.08 46.13|
Info: 66000 | 15196 49432 | 228 772 | 3466| 0.79 46.91|
Info: 67000 | 15615 50013 | 419 581 | 3277| 1.38 48.30|
Info: 68000 | 16039 50589 | 424 576 | 3108| 1.58 49.88|
Info: 69000 | 16473 51155 | 434 566 | 2885| 1.63 51.50|
Info: 70000 | 16785 51843 | 312 688 | 2580| 1.14 52.64|
Info: 71000 | 17185 52443 | 400 600 | 2477| 1.51 54.15|
Info: 72000 | 17409 53193 | 224 750 | 1883| 0.75 54.90|
Info: 73000 | 17613 53869 | 204 676 | 1259| 0.97 55.88|
Info: 74000 | 17783 54573 | 170 704 | 646| 0.76 56.64|
Info: 74781 | 17853 55158 | 70 585 | 0| 0.58 57.22|
Info: Routing complete.
Info: Router1 time 55.80s
Info: Checksum: 0x935e25cb
Info: Router1 time 57.22s
Info: Checksum: 0x33ee714a
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_18.Q
Info: routing 0.70 1.09 Net u_arbiter_wide.m_addr[19] (18,6) -> (20,6)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z_D_LUT4_Z.A
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.27 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z_D_LUT4_Z.F
Info: routing 0.74 2.01 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z_D[2] (20,6) -> (20,9)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z.D
Info: clk-to-q 0.40 0.40 Source u_sdram_backend.w_cache_addr[3]_TRELLIS_FF_Q_13.Q
Info: routing 0.73 1.12 Net u_sdram_backend.w_cache_addr[3][13] (25,4) -> (26,6)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D_LUT4_Z_1.D
Info: logic 0.18 1.30 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D_LUT4_Z_1.F
Info: routing 0.64 1.95 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D[2] (26,6) -> (24,6)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.19 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z.F
Info: routing 0.45 2.64 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z[0] (20,9) -> (20,9)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.A
Info: logic 0.18 2.13 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1.F
Info: routing 0.60 2.72 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (24,6) -> (24,6)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.82 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.F
Info: routing 0.32 3.14 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z[3] (20,9) -> (20,9)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.D
Info: logic 0.18 2.90 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 3.36 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (24,6) -> (24,6)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.33 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.68 4.01 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[3] (20,9) -> (20,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: logic 0.18 3.54 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.39 3.93 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (24,6) -> (24,4)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.19 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.88 5.07 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[1] (20,7) -> (13,7)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: logic 0.18 4.11 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.26 5.37 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (24,4) -> (17,9)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.25 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.50 5.75 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (13,7) -> (13,7)
Info: logic 0.18 5.55 Source u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.82 6.37 Net u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (17,9) -> (19,6)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.93 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.60 6.53 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (13,7) -> (13,3)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: logic 0.18 6.55 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.38 6.93 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (19,6) -> (19,6)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.71 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.03 6.75 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (13,3) -> (13,3)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: logic 0.18 7.11 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.17 7.28 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (19,6) -> (19,6)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.93 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 2.28 9.20 Net u_host_arb.m_wr_LUT4_C_Z[3] (13,3) -> (4,33)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: logic 0.18 7.46 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 1.59 9.05 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (19,6) -> (5,21)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.39 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 1.65 11.03 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (4,33) -> (7,8)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.D
Info: logic 0.18 9.23 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.87 11.10 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (5,21) -> (4,50)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_15.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.21 Source u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.F
Info: routing 0.12 11.33 Net u_sdram_backend.state_TRELLIS_FF_Q_3_DI (7,8) -> (7,8)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: setup 0.00 11.33 Source u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: 2.38 ns logic, 8.96 ns routing
Info: setup 0.00 11.10 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_15.CE
Info: 2.19 ns logic, 8.91 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 2.79 2.79 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (13,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.B
Info: source 0.00 0.00 Source sdram_dq[0]$tr_io.O
Info: routing 2.96 2.96 Net sdram_dq[0]$TRELLIS_IO_IN (0,26) -> (14,3)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_32_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 2.97 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.67 3.63 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D[2] (13,9) -> (12,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z.D
Info: logic 0.18 3.14 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_32_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.65 3.79 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_32_DI_LUT4_Z_D[2] (14,3) -> (14,5)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_32_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.82 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z.F
Info: routing 0.12 3.93 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI (12,9) -> (12,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51.DI
Info: setup 0.00 3.93 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51.DI
Info: 0.36 ns logic, 3.57 ns routing
Info: logic 0.18 3.97 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_32_DI_LUT4_Z.F
Info: routing 0.12 4.09 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_32_DI (14,5) -> (14,5)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_32.DI
Info: setup 0.00 4.09 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_32.DI
Info: 0.36 ns logic, 3.73 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 1.28 1.67 Net u_spi_bridge.byte_idx[2] (21,56) -> (21,41)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.D
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_4.Q
Info: routing 0.87 1.26 Net u_dataflow_core.reg_result_addr_TRELLIS_FF_Q_CE_LUT4_Z_D[0] (20,42) -> (20,41)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.85 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.84 2.69 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (21,41) -> (20,45)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 1.45 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.F
Info: routing 1.36 2.81 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (20,41) -> (16,52)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.87 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.14 4.01 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (20,45) -> (12,57)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.19 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.62 4.80 Net spi_miso_LUT4_Z_B[2] (12,57) -> (12,57)
Info: logic 0.18 2.99 Source spi_miso_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.50 3.48 Net spi_miso_LUT4_Z_B[2] (16,52) -> (17,52)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.99 Source spi_miso_LUT4_Z.F
Info: routing 1.46 6.45 Net spi_miso$TRELLIS_IO_OUT (12,57) -> (0,62)
Info: logic 0.18 3.66 Source spi_miso_LUT4_Z.F
Info: routing 1.77 5.44 Net spi_miso$TRELLIS_IO_OUT (17,52) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.33 ns routing
Info: 0.94 ns logic, 4.50 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 88.25 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 90.08 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.93 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.45 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.09 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 5.44 ns
Info: Slack histogram:
Info: legend: * represents 38 endpoint(s)
Info: + represents [1,38) endpoint(s)
Info: [ 4294, 4826) |+
Info: [ 4826, 5358) |+
Info: [ 5358, 5890) |+
Info: [ 5890, 6422) |***+
Info: [ 6422, 6954) |*****+
Info: [ 6954, 7486) |**********+
Info: [ 7486, 8018) |********+
Info: [ 8018, 8550) |************+
Info: [ 8550, 9082) |************+
Info: [ 9082, 9614) |************************+
Info: [ 9614, 10146) |*******************************************+
Info: [ 10146, 10678) |*****************************************+
Info: [ 10678, 11210) |************************************+
Info: [ 11210, 11742) |****************************+
Info: [ 11742, 12274) |********************************+
Info: [ 12274, 12806) |********************************+
Info: [ 12806, 13338) |*****************************************+
Info: [ 13338, 13870) |*****************************************************+
Info: [ 13870, 14402) |************************************************************
Info: [ 14402, 14934) |*************************************************+
Info: legend: * represents 39 endpoint(s)
Info: + represents [1,39) endpoint(s)
Info: [ 4524, 5044) |+
Info: [ 5044, 5564) |+
Info: [ 5564, 6084) |+
Info: [ 6084, 6604) |**+
Info: [ 6604, 7124) |*****+
Info: [ 7124, 7644) |*****+
Info: [ 7644, 8164) |********+
Info: [ 8164, 8684) |***********+
Info: [ 8684, 9204) |***********+
Info: [ 9204, 9724) |***********+
Info: [ 9724, 10244) |**********************+
Info: [ 10244, 10764) |**************************************+
Info: [ 10764, 11284) |*********************************************+
Info: [ 11284, 11804) |*******************************************+
Info: [ 11804, 12324) |**********************************************+
Info: [ 12324, 12844) |***********************************+
Info: [ 12844, 13364) |***************************************+
Info: [ 13364, 13884) |***************************************************+
Info: [ 13884, 14404) |************************************************************
Info: [ 14404, 14924) |*********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed3.log
+241 -222
View File
@@ -1,13 +1,13 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: Total LUT4s: 7262/43848 16%
Info: logic LUTs: 4612/43848 10%
Info: carry LUTs: 1480/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Total DFFs: 6529/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
@@ -36,11 +36,11 @@ Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
@@ -79,13 +79,13 @@ Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: 2373 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Checksum: 0xa739669a
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
@@ -113,286 +113,305 @@ Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_FF: 6529/ 43848 14%
Info: TRELLIS_COMB: 7712/ 43848 17%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 664743.
Info: at initial placer iter 0, wirelen = 3679
Info: at initial placer iter 1, wirelen = 3262
Info: at initial placer iter 2, wirelen = 3061
Info: at initial placer iter 3, wirelen = 3146
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3007, spread = 111430, legal = 128172; time = 0.51s
Info: at iteration #2, type ALL: wirelen solved = 12169, spread = 80051, legal = 94988; time = 0.46s
Info: at iteration #3, type ALL: wirelen solved = 18837, spread = 71939, legal = 88497; time = 0.44s
Info: at iteration #4, type ALL: wirelen solved = 22992, spread = 69314, legal = 85813; time = 0.46s
Info: at iteration #5, type ALL: wirelen solved = 26132, spread = 66108, legal = 81806; time = 0.39s
Info: at iteration #6, type ALL: wirelen solved = 27501, spread = 66274, legal = 80141; time = 0.37s
Info: at iteration #7, type ALL: wirelen solved = 29268, spread = 65007, legal = 82054; time = 0.50s
Info: at iteration #8, type ALL: wirelen solved = 29608, spread = 64907, legal = 82065; time = 0.50s
Info: at iteration #9, type ALL: wirelen solved = 30207, spread = 64649, legal = 80874; time = 0.42s
Info: at iteration #10, type ALL: wirelen solved = 30969, spread = 64440, legal = 79251; time = 0.38s
Info: at iteration #11, type ALL: wirelen solved = 31424, spread = 65098, legal = 78914; time = 0.39s
Info: at iteration #12, type ALL: wirelen solved = 32740, spread = 66049, legal = 80698; time = 0.38s
Info: at iteration #13, type ALL: wirelen solved = 33705, spread = 64898, legal = 79207; time = 0.41s
Info: at iteration #14, type ALL: wirelen solved = 34833, spread = 66931, legal = 80217; time = 0.37s
Info: at iteration #15, type ALL: wirelen solved = 35608, spread = 67387, legal = 80401; time = 0.37s
Info: at iteration #16, type ALL: wirelen solved = 36304, spread = 66987, legal = 78361; time = 0.37s
Info: at iteration #17, type ALL: wirelen solved = 36488, spread = 67341, legal = 78026; time = 0.38s
Info: at iteration #18, type ALL: wirelen solved = 36913, spread = 66941, legal = 81760; time = 0.37s
Info: at iteration #19, type ALL: wirelen solved = 37228, spread = 67336, legal = 79815; time = 0.50s
Info: at iteration #20, type ALL: wirelen solved = 37541, spread = 67771, legal = 78911; time = 0.32s
Info: at iteration #21, type ALL: wirelen solved = 37898, spread = 67671, legal = 79244; time = 0.41s
Info: at iteration #22, type ALL: wirelen solved = 38263, spread = 68210, legal = 80382; time = 0.39s
Info: HeAP Placer Time: 12.71s
Info: of which solving equations: 6.11s
Info: Creating initial analytic placement for 8052 cells, random placement wirelen = 658771.
Info: at initial placer iter 0, wirelen = 3777
Info: at initial placer iter 1, wirelen = 3418
Info: at initial placer iter 2, wirelen = 3191
Info: at initial placer iter 3, wirelen = 3246
Info: Running main analytical placer, max placement attempts per cell = 26342911.
Info: at iteration #1, type ALL: wirelen solved = 3286, spread = 121415, legal = 135557; time = 0.57s
Info: at iteration #2, type ALL: wirelen solved = 12836, spread = 85667, legal = 101785; time = 0.56s
Info: at iteration #3, type ALL: wirelen solved = 19556, spread = 76735, legal = 94213; time = 0.54s
Info: at iteration #4, type ALL: wirelen solved = 23735, spread = 71218, legal = 88978; time = 0.56s
Info: at iteration #5, type ALL: wirelen solved = 27278, spread = 68771, legal = 85471; time = 0.52s
Info: at iteration #6, type ALL: wirelen solved = 28843, spread = 68525, legal = 86291; time = 0.49s
Info: at iteration #7, type ALL: wirelen solved = 30830, spread = 68147, legal = 85543; time = 0.54s
Info: at iteration #8, type ALL: wirelen solved = 31830, spread = 68536, legal = 87500; time = 0.51s
Info: at iteration #9, type ALL: wirelen solved = 32948, spread = 68486, legal = 85985; time = 0.48s
Info: at iteration #10, type ALL: wirelen solved = 33856, spread = 67439, legal = 85265; time = 0.44s
Info: at iteration #11, type ALL: wirelen solved = 34000, spread = 70952, legal = 84813; time = 0.39s
Info: at iteration #12, type ALL: wirelen solved = 36242, spread = 71217, legal = 84052; time = 0.38s
Info: at iteration #13, type ALL: wirelen solved = 37105, spread = 70317, legal = 83135; time = 0.36s
Info: at iteration #14, type ALL: wirelen solved = 37208, spread = 70761, legal = 85228; time = 0.43s
Info: at iteration #15, type ALL: wirelen solved = 37721, spread = 70665, legal = 86140; time = 0.45s
Info: at iteration #16, type ALL: wirelen solved = 38058, spread = 70475, legal = 82322; time = 0.40s
Info: at iteration #17, type ALL: wirelen solved = 37921, spread = 70553, legal = 85027; time = 0.56s
Info: at iteration #18, type ALL: wirelen solved = 38474, spread = 71251, legal = 87239; time = 0.50s
Info: at iteration #19, type ALL: wirelen solved = 38897, spread = 70986, legal = 85756; time = 0.45s
Info: at iteration #20, type ALL: wirelen solved = 39130, spread = 72111, legal = 85799; time = 0.46s
Info: at iteration #21, type ALL: wirelen solved = 39740, spread = 72418, legal = 85467; time = 0.42s
Info: HeAP Placer Time: 13.42s
Info: of which solving equations: 6.37s
Info: of which spreading cells: 1.00s
Info: of which strict legalisation: 2.80s
Info: of which strict legalisation: 3.34s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1201, wirelen = 78026
Info: at iteration #5: temp = 0.000000, timing cost = 1601, wirelen = 73061
Info: at iteration #10: temp = 0.000000, timing cost = 972, wirelen = 71811
Info: at iteration #15: temp = 0.000000, timing cost = 975, wirelen = 71455
Info: at iteration #20: temp = 0.000000, timing cost = 1067, wirelen = 71329
Info: at iteration #20: temp = 0.000000, timing cost = 1065, wirelen = 71335
Info: SA placement time 17.35s
Info: at iteration #1: temp = 0.000000, timing cost = 1489, wirelen = 82322
Info: at iteration #5: temp = 0.000000, timing cost = 2175, wirelen = 76462
Info: at iteration #10: temp = 0.000000, timing cost = 1893, wirelen = 75060
Info: at iteration #15: temp = 0.000000, timing cost = 1853, wirelen = 74564
Info: at iteration #20: temp = 0.000000, timing cost = 1901, wirelen = 74270
Info: at iteration #25: temp = 0.000000, timing cost = 1885, wirelen = 74160
Info: at iteration #30: temp = 0.000000, timing cost = 1886, wirelen = 74070
Info: at iteration #35: temp = 0.000000, timing cost = 1875, wirelen = 74035
Info: at iteration #36: temp = 0.000000, timing cost = 1860, wirelen = 74034
Info: SA placement time 35.90s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 73.11 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 78.14 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.58 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.76 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.33 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.57 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 1947, 2603) |+
Info: [ 2603, 3259) |+
Info: [ 3259, 3915) |***+
Info: [ 3915, 4571) |*****+
Info: [ 4571, 5227) |*******+
Info: [ 5227, 5883) |*****+
Info: [ 5883, 6539) |*******+
Info: [ 6539, 7195) |**********+
Info: [ 7195, 7851) |********************+
Info: [ 7851, 8507) |*********************************+
Info: [ 8507, 9163) |*************************************************+
Info: [ 9163, 9819) |*****************************************+
Info: [ 9819, 10475) |*****************************************+
Info: [ 10475, 11131) |****************************+
Info: [ 11131, 11787) |***********************+
Info: [ 11787, 12443) |***************************************+
Info: [ 12443, 13099) |*****************************************************+
Info: [ 13099, 13755) |************************************************************
Info: [ 13755, 14411) |***************************************************+
Info: [ 14411, 15067) |**********************************************+
Info: Checksum: 0xe0d6d18e
Info: legend: * represents 30 endpoint(s)
Info: + represents [1,30) endpoint(s)
Info: [ 2828, 3440) |*+
Info: [ 3440, 4052) |***+
Info: [ 4052, 4664) |******+
Info: [ 4664, 5276) |****+
Info: [ 5276, 5888) |*****+
Info: [ 5888, 6500) |*******+
Info: [ 6500, 7112) |***********+
Info: [ 7112, 7724) |**************+
Info: [ 7724, 8336) |********************************+
Info: [ 8336, 8948) |****************************************+
Info: [ 8948, 9560) |*********************************************+
Info: [ 9560, 10172) |*****************************************+
Info: [ 10172, 10784) |******************************************************+
Info: [ 10784, 11396) |**************************************+
Info: [ 11396, 12008) |***************************************+
Info: [ 12008, 12620) |**************************************************+
Info: [ 12620, 13232) |************************************************************
Info: [ 13232, 13844) |*********************************************************+
Info: [ 13844, 14456) |***********************************************************+
Info: [ 14456, 15068) |***************************************************+
Info: Checksum: 0xbed01102
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39482 arcs.
Info: Routing 40955 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 475 524 | 475 524 | 39125| 1.34 1.34|
Info: 2000 | 722 1277 | 247 753 | 38672| 1.33 2.67|
Info: 3000 | 909 2090 | 187 813 | 37922| 0.75 3.41|
Info: 4000 | 982 3017 | 73 927 | 37234| 0.47 3.89|
Info: 5000 | 1097 3902 | 115 885 | 36648| 0.64 4.52|
Info: 6000 | 1211 4788 | 114 886 | 35815| 0.49 5.01|
Info: 7000 | 1391 5608 | 180 820 | 35108| 0.70 5.72|
Info: 8000 | 1541 6458 | 150 850 | 34406| 0.75 6.47|
Info: 9000 | 1581 7418 | 40 960 | 33451| 0.40 6.87|
Info: 10000 | 1704 8295 | 123 877 | 32615| 0.39 7.25|
Info: 11000 | 1838 9161 | 134 866 | 31902| 0.52 7.77|
Info: 12000 | 1956 10043 | 118 882 | 31113| 0.62 8.39|
Info: 13000 | 2068 10931 | 112 888 | 30292| 0.35 8.74|
Info: 14000 | 2206 11793 | 138 862 | 29480| 0.47 9.21|
Info: 15000 | 2399 12600 | 193 807 | 28749| 0.40 9.61|
Info: 16000 | 2543 13456 | 144 856 | 27958| 0.45 10.05|
Info: 17000 | 2705 14294 | 162 838 | 27295| 0.46 10.52|
Info: 18000 | 2823 15176 | 118 882 | 26505| 0.43 10.95|
Info: 19000 | 2984 16015 | 161 839 | 25795| 0.40 11.35|
Info: 20000 | 3149 16850 | 165 835 | 25050| 0.50 11.85|
Info: 21000 | 3312 17687 | 163 837 | 24308| 0.41 12.26|
Info: 22000 | 3505 18493 | 193 806 | 23601| 0.42 12.68|
Info: 23000 | 3780 19210 | 275 717 | 22955| 0.39 13.07|
Info: 24000 | 4142 19840 | 362 630 | 22361| 0.36 13.44|
Info: 25000 | 4422 20525 | 280 685 | 21677| 0.38 13.81|
Info: 26000 | 4696 21199 | 274 674 | 21018| 0.37 14.18|
Info: 27000 | 4916 21933 | 220 734 | 20283| 0.48 14.66|
Info: 28000 | 5067 22742 | 151 809 | 19486| 0.44 15.10|
Info: 29000 | 5264 23495 | 197 753 | 18729| 0.40 15.50|
Info: 30000 | 5474 24248 | 210 753 | 17993| 0.45 15.96|
Info: 31000 | 5681 24990 | 207 742 | 17268| 0.45 16.41|
Info: 32000 | 5870 25732 | 189 742 | 16621| 0.47 16.88|
Info: 33000 | 6073 26480 | 203 748 | 15878| 0.44 17.32|
Info: 34000 | 6231 27258 | 158 778 | 15065| 0.42 17.74|
Info: 35000 | 6378 28018 | 147 760 | 14267| 0.39 18.13|
Info: 36000 | 6547 28777 | 169 759 | 13638| 0.50 18.63|
Info: 37000 | 6700 29582 | 153 805 | 12871| 0.55 19.18|
Info: 38000 | 6851 30366 | 151 784 | 12095| 0.51 19.69|
Info: 39000 | 6991 31182 | 140 816 | 11360| 0.63 20.32|
Info: 40000 | 7146 31999 | 155 817 | 10690| 0.58 20.90|
Info: 41000 | 7291 32802 | 145 803 | 9936| 0.68 21.59|
Info: 42000 | 7399 33615 | 108 813 | 9129| 0.54 22.13|
Info: 43000 | 7603 34384 | 204 769 | 8496| 0.86 22.98|
Info: 44000 | 7706 35203 | 103 819 | 7648| 0.60 23.58|
Info: 45000 | 7857 36005 | 151 802 | 6999| 0.55 24.13|
Info: 46000 | 8064 36782 | 207 777 | 6560| 0.80 24.93|
Info: 47000 | 8352 37485 | 288 703 | 6177| 1.34 26.27|
Info: 48000 | 8479 38315 | 127 830 | 5402| 0.44 26.71|
Info: 49000 | 8698 39091 | 219 776 | 4783| 0.76 27.47|
Info: 50000 | 9063 39726 | 365 635 | 4454| 1.29 28.76|
Info: 51000 | 9260 40523 | 197 797 | 3759| 0.49 29.26|
Info: 52000 | 9516 41267 | 256 744 | 3263| 0.87 30.13|
Info: 53000 | 9876 41907 | 360 640 | 3232| 1.12 31.25|
Info: 54000 | 10242 42541 | 366 634 | 2954| 1.22 32.47|
Info: 55000 | 10565 43218 | 323 677 | 2546| 0.96 33.43|
Info: 56000 | 10848 43935 | 283 717 | 2187| 0.93 34.37|
Info: 57000 | 10999 44676 | 151 741 | 1408| 0.80 35.17|
Info: 58000 | 11353 45255 | 354 579 | 1035| 1.02 36.19|
Info: 59000 | 11530 45974 | 177 719 | 341| 0.70 36.88|
Info: 59458 | 11599 46302 | 69 328 | 0| 0.35 37.24|
Info: 1000 | 732 267 | 732 267 | 40844| 1.34 1.34|
Info: 2000 | 1196 803 | 464 536 | 40432| 1.06 2.40|
Info: 3000 | 1355 1644 | 159 841 | 39857| 1.16 3.56|
Info: 4000 | 1584 2415 | 229 771 | 39216| 0.74 4.30|
Info: 5000 | 1848 3151 | 264 736 | 38640| 0.79 5.09|
Info: 6000 | 2091 3908 | 243 757 | 38002| 0.70 5.79|
Info: 7000 | 2230 4769 | 139 861 | 37395| 0.46 6.25|
Info: 8000 | 2351 5648 | 121 879 | 36747| 0.54 6.79|
Info: 9000 | 2457 6542 | 106 894 | 35960| 0.33 7.12|
Info: 10000 | 2617 7382 | 160 840 | 35269| 0.50 7.62|
Info: 11000 | 2756 8243 | 139 861 | 34541| 0.64 8.26|
Info: 12000 | 2920 9079 | 164 836 | 33906| 0.42 8.68|
Info: 13000 | 3104 9895 | 184 816 | 33305| 0.37 9.05|
Info: 14000 | 3276 10723 | 172 828 | 32549| 0.41 9.46|
Info: 15000 | 3454 11545 | 178 822 | 31869| 0.48 9.94|
Info: 16000 | 3592 12407 | 138 862 | 31178| 0.40 10.34|
Info: 17000 | 3727 13272 | 135 865 | 30432| 0.42 10.76|
Info: 18000 | 3852 14147 | 125 875 | 29786| 0.40 11.16|
Info: 19000 | 4004 14995 | 152 848 | 29072| 1.00 12.16|
Info: 20000 | 4220 15779 | 216 784 | 28410| 0.44 12.60|
Info: 21000 | 4421 16578 | 201 799 | 27852| 0.51 13.10|
Info: 22000 | 4649 17350 | 228 772 | 27257| 0.50 13.60|
Info: 23000 | 4864 18135 | 215 785 | 26597| 0.53 14.13|
Info: 24000 | 5130 18869 | 266 734 | 25999| 0.52 14.65|
Info: 25000 | 5319 19680 | 189 811 | 25240| 0.50 15.15|
Info: 26000 | 5542 20457 | 223 777 | 24820| 0.39 15.54|
Info: 27000 | 5719 21280 | 177 823 | 24221| 0.53 16.08|
Info: 28000 | 5932 22063 | 213 783 | 23549| 0.51 16.59|
Info: 29000 | 6231 22744 | 299 681 | 22944| 0.41 17.00|
Info: 30000 | 6554 23409 | 323 665 | 22436| 0.48 17.48|
Info: 31000 | 6848 24086 | 294 677 | 21842| 0.47 17.94|
Info: 32000 | 7080 24826 | 232 740 | 21392| 0.51 18.46|
Info: 33000 | 7379 25499 | 299 673 | 20957| 0.83 19.28|
Info: 34000 | 7647 26180 | 268 681 | 20340| 0.43 19.71|
Info: 35000 | 7853 26915 | 206 735 | 19747| 0.46 20.17|
Info: 36000 | 8101 27608 | 248 693 | 19091| 0.46 20.64|
Info: 37000 | 8295 28350 | 194 742 | 18460| 0.52 21.15|
Info: 38000 | 8546 29063 | 251 713 | 17925| 0.54 21.69|
Info: 39000 | 8791 29776 | 245 713 | 17395| 0.60 22.29|
Info: 40000 | 8966 30555 | 175 779 | 16677| 0.58 22.88|
Info: 41000 | 9154 31286 | 188 731 | 16012| 0.50 23.38|
Info: 42000 | 9398 32006 | 244 720 | 15538| 0.76 24.14|
Info: 43000 | 9598 32777 | 200 771 | 14934| 0.63 24.77|
Info: 44000 | 9759 33546 | 161 769 | 14347| 0.57 25.35|
Info: 45000 | 9973 34288 | 214 742 | 13892| 0.79 26.14|
Info: 46000 | 10137 35074 | 164 786 | 13565| 0.54 26.68|
Info: 47000 | 10290 35875 | 153 801 | 12802| 0.63 27.31|
Info: 48000 | 10490 36612 | 200 737 | 12168| 0.71 28.02|
Info: 49000 | 10759 37331 | 269 719 | 11730| 1.82 29.84|
Info: 50000 | 10936 38118 | 177 787 | 11170| 0.59 30.43|
Info: 51000 | 11116 38889 | 180 771 | 10483| 0.60 31.03|
Info: 52000 | 11319 39652 | 203 763 | 10067| 1.01 32.03|
Info: 53000 | 11483 40443 | 164 791 | 9524| 0.64 32.67|
Info: 54000 | 11627 41216 | 144 773 | 8765| 0.60 33.27|
Info: 55000 | 11873 41967 | 246 751 | 8497| 0.98 34.25|
Info: 56000 | 12223 42601 | 350 634 | 8333| 1.15 35.40|
Info: 57000 | 12472 43308 | 249 707 | 7788| 1.05 36.45|
Info: 58000 | 12614 44106 | 142 798 | 7013| 0.36 36.82|
Info: 59000 | 12904 44787 | 290 681 | 6542| 0.86 37.67|
Info: 60000 | 13241 45441 | 337 654 | 6359| 1.59 39.26|
Info: 61000 | 13549 46130 | 308 689 | 6077| 1.11 40.37|
Info: 62000 | 13699 46937 | 150 807 | 5358| 0.51 40.88|
Info: 63000 | 13970 47660 | 271 723 | 4773| 0.90 41.78|
Info: 64000 | 14403 48227 | 433 567 | 4593| 1.41 43.19|
Info: 65000 | 14769 48861 | 366 634 | 4391| 1.27 44.46|
Info: 66000 | 14972 49656 | 203 795 | 3688| 0.51 44.97|
Info: 67000 | 15325 50303 | 353 647 | 3485| 1.05 46.02|
Info: 68000 | 15619 51009 | 294 706 | 3292| 1.55 47.56|
Info: 69000 | 16061 51567 | 442 558 | 3150| 1.60 49.16|
Info: 70000 | 16522 52106 | 461 539 | 2971| 1.96 51.12|
Info: 71000 | 16812 52816 | 290 710 | 2509| 0.89 52.01|
Info: 72000 | 17079 53544 | 267 728 | 1978| 0.70 52.71|
Info: 73000 | 17318 54171 | 239 627 | 1386| 1.01 53.72|
Info: 74000 | 17476 54876 | 158 705 | 625| 0.80 54.52|
Info: 74882 | 17608 55504 | 132 628 | 0| 0.87 55.40|
Info: Routing complete.
Info: Router1 time 37.24s
Info: Checksum: 0x4e49b5c8
Info: Router1 time 55.40s
Info: Checksum: 0x8398e6d7
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_director.job_out_slot_TRELLIS_FF_Q.Q
Info: routing 1.09 1.49 Net u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0[4] (23,40) -> (25,30)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z_LUT4_Z.D
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_25.Q
Info: routing 1.06 1.46 Net u_arbiter_wide.m_addr[25] (25,8) -> (24,5)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D_LUT4_Z_1.A
Info: Defined in:
Info: hardware/v2/rtl/neural_director.v:73.39-73.51
Info: logic 0.18 1.67 Source u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z_LUT4_Z.F
Info: routing 1.39 3.06 Net u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z[5] (25,30) -> (26,42)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.64 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D_LUT4_Z_1.F
Info: routing 0.64 2.28 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1_D[2] (24,5) -> (22,5)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 3.25 Source u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0_L6MUX21_SD_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: routing 1.22 4.47 Net u_dataflow_core.u_dep_mgr.node_producer_ids[15]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z_C[4] (26,42) -> (22,33)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.M
Info: logic 0.18 2.46 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_1.F
Info: routing 0.51 2.97 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (22,5) -> (21,5)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 4.66 Source u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.27 4.93 Net u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_C0[4] (22,33) -> (22,33)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_BLUT_LUT4_Z.M
Info: logic 0.18 3.15 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.44 3.59 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (21,5) -> (22,5)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 5.12 Source u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.75 5.87 Net u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_C0[4] (22,33) -> (23,36)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.M
Info: logic 0.18 3.77 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.45 4.22 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (22,5) -> (22,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.07 Source u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info: routing 0.47 6.54 Net u_dataflow_core.u_dep_mgr.node_resolved[0]_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_D_Z[5] (23,36) -> (23,37)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[14]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: logic 0.18 4.40 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.23 4.63 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (22,5) -> (22,7)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 6.73 Source u_dataflow_core.u_dep_mgr.node_state[14]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_D_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.89 7.62 Net u_dataflow_core.u_dep_mgr.node_state[14]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_D_Z[5] (23,37) -> (24,41)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: logic 0.18 4.81 Source u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.55 5.36 Net u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (22,7) -> (22,6)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 7.82 Source u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 7.82 Net u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1 (24,41) -> (24,41)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: logic 0.18 5.54 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.83 6.37 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (22,6) -> (17,4)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
Info: logic 0.18 8.00 Source u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_4_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.82 8.82 Net u_dataflow_core.u_dep_mgr.node_state[10]_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_Z[5] (24,41) -> (25,45)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.55 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.46 7.01 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (17,4) -> (17,4)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 9.01 Source u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.70 9.71 Net u_dataflow_core.u_dep_mgr.node_resolved[11]_TRELLIS_FF_Q_2_DI_LUT4_Z_C_LUT4_D_Z_LUT4_Z_1_D_LUT4_D_1_Z[4] (25,45) -> (24,47)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.M
Info: logic 0.18 7.19 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 1.73 8.92 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (17,4) -> (7,20)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 9.90 Source u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.92 10.82 Net u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q_DI (24,47) -> (23,42)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q.M
Info: setup 0.00 10.82 Source u_dataflow_core.u_dep_mgr.node_state[9]_TRELLIS_FF_Q.M
Info: 2.30 ns logic, 8.52 ns routing
Info: logic 0.18 9.10 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.98 11.08 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (7,20) -> (7,59)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_7.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 11.08 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_7.CE
Info: 2.19 ns logic, 8.89 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 3.12 3.12 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (13,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.B
Info: source 0.00 0.00 Source sdram_dq[1]$tr_io.O
Info: routing 3.06 3.06 Net sdram_dq[1]$TRELLIS_IO_IN (0,29) -> (13,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_97_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.30 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.69 3.99 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D[2] (13,7) -> (13,6)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z.D
Info: logic 0.18 3.24 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_97_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.34 3.58 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_97_DI_LUT4_Z_D[2] (13,7) -> (10,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.17 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z.F
Info: routing 0.12 4.28 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI (13,6) -> (13,6)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51.DI
Info: setup 0.00 4.28 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51.DI
Info: 0.36 ns logic, 3.92 ns routing
Info: logic 0.18 3.76 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33_DI_LUT4_Z.F
Info: routing 0.12 3.88 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33_DI (10,7) -> (10,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33.DI
Info: setup 0.00 3.88 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33.DI
Info: 0.36 ns logic, 3.52 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 1.03 1.43 Net u_spi_bridge.byte_idx[3] (19,52) -> (21,48)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.C
Info: routing 0.96 1.35 Net u_spi_bridge.byte_idx[3] (19,50) -> (17,47)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.61 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.17 1.78 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (21,48) -> (21,48)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 1.53 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.17 1.71 Net u_dataflow_core.reg_result_addr_TRELLIS_FF_Q_CE_LUT4_Z_C[0] (17,47) -> (17,47)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.96 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.81 2.77 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (21,48) -> (16,48)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: logic 0.18 1.89 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.F
Info: routing 1.18 3.07 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (17,47) -> (13,57)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.95 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 1.14 4.09 Net spi_miso_LUT4_Z_B[2] (16,48) -> (16,54)
Info: logic 0.18 3.25 Source spi_miso_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.51 3.76 Net spi_miso_LUT4_Z_B[2] (13,57) -> (14,57)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.28 Source spi_miso_LUT4_Z.F
Info: routing 1.86 6.14 Net spi_miso$TRELLIS_IO_OUT (16,54) -> (0,62)
Info: logic 0.18 3.93 Source spi_miso_LUT4_Z.F
Info: routing 1.50 5.43 Net spi_miso$TRELLIS_IO_OUT (14,57) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.02 ns routing
Info: 1.12 ns logic, 4.32 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 92.43 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 90.22 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.28 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.14 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.88 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 5.43 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 4806, 5312) |+
Info: [ 5312, 5818) |**+
Info: [ 5818, 6324) |**+
Info: [ 6324, 6830) |**+
Info: [ 6830, 7336) |******+
Info: [ 7336, 7842) |*********+
Info: [ 7842, 8348) |**********+
Info: [ 8348, 8854) |**********+
Info: [ 8854, 9360) |***********+
Info: [ 9360, 9866) |********************+
Info: [ 9866, 10372) |******************************+
Info: [ 10372, 10878) |*************************************************+
Info: [ 10878, 11384) |************************************+
Info: [ 11384, 11890) |******************************************+
Info: [ 11890, 12396) |***********************************+
Info: [ 12396, 12902) |******************************+
Info: [ 12902, 13408) |*****************************************+
Info: [ 13408, 13914) |*****************************************************+
Info: [ 13914, 14420) |************************************************************
Info: [ 14420, 14926) |***********************************************+
Info: [ 4541, 5060) |+
Info: [ 5060, 5579) |+
Info: [ 5579, 6098) |+
Info: [ 6098, 6617) |**+
Info: [ 6617, 7136) |****+
Info: [ 7136, 7655) |******+
Info: [ 7655, 8174) |*********+
Info: [ 8174, 8693) |**********+
Info: [ 8693, 9212) |*************+
Info: [ 9212, 9731) |**************+
Info: [ 9731, 10250) |**************************+
Info: [ 10250, 10769) |***********************************+
Info: [ 10769, 11288) |****************************************+
Info: [ 11288, 11807) |******************************************+
Info: [ 11807, 12326) |************************************************+
Info: [ 12326, 12845) |***********************************************+
Info: [ 12845, 13364) |**********************************************+
Info: [ 13364, 13883) |**********************************************+
Info: [ 13883, 14402) |************************************************************
Info: [ 14402, 14921) |**********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed4.log
+229 -231
View File
@@ -1,13 +1,13 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: Total LUT4s: 7262/43848 16%
Info: logic LUTs: 4612/43848 10%
Info: carry LUTs: 1480/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Total DFFs: 6529/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
@@ -36,11 +36,11 @@ Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
@@ -79,13 +79,13 @@ Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: 2373 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Checksum: 0xa739669a
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
@@ -113,292 +113,290 @@ Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_FF: 6529/ 43848 14%
Info: TRELLIS_COMB: 7712/ 43848 17%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 665354.
Info: at initial placer iter 0, wirelen = 3823
Info: at initial placer iter 1, wirelen = 3248
Info: at initial placer iter 2, wirelen = 3043
Info: at initial placer iter 3, wirelen = 3116
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3008, spread = 111060, legal = 126956; time = 0.50s
Info: at iteration #2, type ALL: wirelen solved = 12675, spread = 81942, legal = 97252; time = 0.45s
Info: at iteration #3, type ALL: wirelen solved = 19570, spread = 72038, legal = 88404; time = 0.50s
Info: at iteration #4, type ALL: wirelen solved = 23775, spread = 68858, legal = 84735; time = 0.47s
Info: at iteration #5, type ALL: wirelen solved = 26419, spread = 67156, legal = 83186; time = 0.47s
Info: at iteration #6, type ALL: wirelen solved = 27305, spread = 66515, legal = 81140; time = 0.40s
Info: at iteration #7, type ALL: wirelen solved = 28670, spread = 65617, legal = 81992; time = 0.40s
Info: at iteration #8, type ALL: wirelen solved = 29818, spread = 65582, legal = 82545; time = 0.36s
Info: at iteration #9, type ALL: wirelen solved = 30687, spread = 67127, legal = 79744; time = 0.34s
Info: at iteration #10, type ALL: wirelen solved = 32928, spread = 69762, legal = 81597; time = 0.39s
Info: at iteration #11, type ALL: wirelen solved = 35460, spread = 69492, legal = 83803; time = 0.40s
Info: at iteration #12, type ALL: wirelen solved = 36065, spread = 68501, legal = 82712; time = 0.40s
Info: at iteration #13, type ALL: wirelen solved = 36458, spread = 67718, legal = 83242; time = 0.37s
Info: at iteration #14, type ALL: wirelen solved = 36273, spread = 69530, legal = 79474; time = 0.36s
Info: at iteration #15, type ALL: wirelen solved = 37214, spread = 68862, legal = 84101; time = 0.42s
Info: at iteration #16, type ALL: wirelen solved = 37355, spread = 69275, legal = 82613; time = 0.35s
Info: at iteration #17, type ALL: wirelen solved = 37816, spread = 69305, legal = 84580; time = 0.41s
Info: at iteration #18, type ALL: wirelen solved = 38288, spread = 69360, legal = 82286; time = 0.35s
Info: at iteration #19, type ALL: wirelen solved = 38706, spread = 69484, legal = 81801; time = 0.36s
Info: HeAP Placer Time: 10.99s
Info: of which solving equations: 5.30s
Info: of which spreading cells: 0.85s
Info: of which strict legalisation: 2.38s
Info: Creating initial analytic placement for 8052 cells, random placement wirelen = 664291.
Info: at initial placer iter 0, wirelen = 4033
Info: at initial placer iter 1, wirelen = 3250
Info: at initial placer iter 2, wirelen = 3048
Info: at initial placer iter 3, wirelen = 3166
Info: Running main analytical placer, max placement attempts per cell = 26342911.
Info: at iteration #1, type ALL: wirelen solved = 3126, spread = 114429, legal = 129666; time = 0.52s
Info: at iteration #2, type ALL: wirelen solved = 12598, spread = 84846, legal = 99848; time = 0.52s
Info: at iteration #3, type ALL: wirelen solved = 19494, spread = 76536, legal = 94218; time = 0.51s
Info: at iteration #4, type ALL: wirelen solved = 24326, spread = 71576, legal = 89317; time = 0.43s
Info: at iteration #5, type ALL: wirelen solved = 26999, spread = 71686, legal = 85905; time = 0.42s
Info: at iteration #6, type ALL: wirelen solved = 29667, spread = 70348, legal = 87842; time = 0.44s
Info: at iteration #7, type ALL: wirelen solved = 30078, spread = 69820, legal = 87229; time = 0.44s
Info: at iteration #8, type ALL: wirelen solved = 31328, spread = 69060, legal = 83991; time = 0.41s
Info: at iteration #9, type ALL: wirelen solved = 32034, spread = 71455, legal = 83994; time = 0.44s
Info: at iteration #10, type ALL: wirelen solved = 34435, spread = 70945, legal = 84894; time = 0.46s
Info: at iteration #11, type ALL: wirelen solved = 35386, spread = 69852, legal = 86031; time = 0.45s
Info: at iteration #12, type ALL: wirelen solved = 35307, spread = 70334, legal = 87785; time = 0.43s
Info: at iteration #13, type ALL: wirelen solved = 35861, spread = 69445, legal = 84524; time = 0.41s
Info: HeAP Placer Time: 8.62s
Info: of which solving equations: 4.16s
Info: of which spreading cells: 0.61s
Info: of which strict legalisation: 2.04s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1383, wirelen = 79474
Info: at iteration #5: temp = 0.000000, timing cost = 1522, wirelen = 73788
Info: at iteration #10: temp = 0.000000, timing cost = 1422, wirelen = 72608
Info: at iteration #15: temp = 0.000000, timing cost = 1479, wirelen = 72135
Info: at iteration #20: temp = 0.000000, timing cost = 1634, wirelen = 71921
Info: at iteration #21: temp = 0.000000, timing cost = 1631, wirelen = 71893
Info: SA placement time 20.23s
Info: at iteration #1: temp = 0.000000, timing cost = 1600, wirelen = 83991
Info: at iteration #5: temp = 0.000000, timing cost = 1413, wirelen = 76445
Info: at iteration #10: temp = 0.000000, timing cost = 1106, wirelen = 74194
Info: at iteration #15: temp = 0.000000, timing cost = 1042, wirelen = 73456
Info: at iteration #20: temp = 0.000000, timing cost = 1145, wirelen = 73200
Info: at iteration #25: temp = 0.000000, timing cost = 989, wirelen = 73042
Info: at iteration #27: temp = 0.000000, timing cost = 982, wirelen = 73003
Info: SA placement time 27.42s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 79.25 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 76.14 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.81 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.99 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.58 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.57 ns
Info: Slack histogram:
Info: legend: * represents 33 endpoint(s)
Info: + represents [1,33) endpoint(s)
Info: [ 3007, 3610) |+
Info: [ 3610, 4213) |*+
Info: [ 4213, 4816) |***+
Info: [ 4816, 5419) |***+
Info: [ 5419, 6022) |*********+
Info: [ 6022, 6625) |**********+
Info: [ 6625, 7228) |*************+
Info: [ 7228, 7831) |***************+
Info: [ 7831, 8434) |**************************+
Info: [ 8434, 9037) |*******************************+
Info: [ 9037, 9640) |****************************************+
Info: [ 9640, 10243) |****************************************+
Info: [ 10243, 10846) |************************************+
Info: [ 10846, 11449) |************************************+
Info: [ 11449, 12052) |************************************+
Info: [ 12052, 12655) |******************************************+
Info: [ 12655, 13258) |************************************************************
Info: [ 13258, 13861) |****************************************************+
Info: [ 13861, 14464) |************************************************+
Info: [ 14464, 15067) |*************************************************+
Info: Checksum: 0xe06743c5
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 2492, 3120) |+
Info: [ 3120, 3748) |+
Info: [ 3748, 4376) |*+
Info: [ 4376, 5004) |*****+
Info: [ 5004, 5632) |*********+
Info: [ 5632, 6260) |*****+
Info: [ 6260, 6888) |*********+
Info: [ 6888, 7516) |**********+
Info: [ 7516, 8144) |**************+
Info: [ 8144, 8772) |****************************+
Info: [ 8772, 9400) |**************************************+
Info: [ 9400, 10028) |****************************************+
Info: [ 10028, 10656) |************************************************+
Info: [ 10656, 11284) |*************************************+
Info: [ 11284, 11912) |***********************************+
Info: [ 11912, 12540) |************************************+
Info: [ 12540, 13168) |**************************************************+
Info: [ 13168, 13796) |************************************************************
Info: [ 13796, 14424) |***********************************************************+
Info: [ 14424, 15052) |******************************************+
Info: Checksum: 0x07add481
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39441 arcs.
Info: Routing 40958 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 676 323 | 676 323 | 39282| 1.49 1.49|
Info: 2000 | 1126 873 | 450 550 | 39060| 1.37 2.86|
Info: 3000 | 1511 1488 | 385 615 | 38714| 1.13 3.99|
Info: 4000 | 1885 2114 | 374 626 | 38225| 1.00 4.99|
Info: 5000 | 2079 2920 | 194 806 | 37596| 0.74 5.73|
Info: 6000 | 2184 3815 | 105 895 | 36840| 0.51 6.24|
Info: 7000 | 2332 4667 | 148 852 | 36099| 0.81 7.05|
Info: 8000 | 2437 5562 | 105 895 | 35333| 0.54 7.59|
Info: 9000 | 2701 6298 | 264 736 | 34815| 1.01 8.60|
Info: 10000 | 2778 7221 | 77 923 | 34057| 0.41 9.02|
Info: 11000 | 2855 8144 | 77 923 | 33275| 0.43 9.45|
Info: 12000 | 2949 9050 | 94 906 | 32438| 0.54 9.98|
Info: 13000 | 3070 9929 | 121 879 | 31697| 0.48 10.47|
Info: 14000 | 3211 10788 | 141 859 | 30954| 0.64 11.11|
Info: 15000 | 3360 11639 | 149 851 | 30400| 0.47 11.58|
Info: 16000 | 3536 12463 | 176 824 | 29903| 0.54 12.12|
Info: 17000 | 3726 13273 | 190 810 | 29571| 0.40 12.53|
Info: 18000 | 3938 14061 | 212 788 | 29030| 2.03 14.56|
Info: 19000 | 4167 14832 | 229 771 | 28586| 1.10 15.66|
Info: 20000 | 4385 15614 | 218 782 | 28245| 0.49 16.15|
Info: 21000 | 4505 16494 | 120 880 | 27650| 0.37 16.51|
Info: 22000 | 4692 17307 | 187 813 | 27027| 0.42 16.93|
Info: 23000 | 4903 18096 | 211 789 | 26326| 0.56 17.48|
Info: 24000 | 5120 18879 | 217 783 | 25650| 0.49 17.97|
Info: 25000 | 5360 19639 | 240 760 | 25204| 0.43 18.40|
Info: 26000 | 5594 20405 | 234 766 | 24656| 0.53 18.93|
Info: 27000 | 5852 21147 | 258 742 | 24240| 0.58 19.51|
Info: 28000 | 6125 21874 | 273 727 | 23601| 0.38 19.89|
Info: 29000 | 6385 22614 | 260 740 | 23124| 0.61 20.50|
Info: 30000 | 6623 23375 | 238 761 | 22613| 0.53 21.04|
Info: 31000 | 6886 24079 | 263 704 | 22013| 0.46 21.49|
Info: 32000 | 7122 24795 | 236 716 | 21446| 0.49 21.99|
Info: 33000 | 7384 25480 | 262 685 | 20889| 0.42 22.40|
Info: 34000 | 7765 26058 | 381 578 | 20345| 0.48 22.89|
Info: 35000 | 8066 26720 | 301 662 | 19777| 0.44 23.33|
Info: 36000 | 8408 27360 | 342 640 | 19215| 0.45 23.78|
Info: 37000 | 8690 28020 | 282 660 | 18647| 0.55 24.33|
Info: 38000 | 8954 28721 | 264 701 | 18130| 0.57 24.90|
Info: 39000 | 9242 29417 | 288 696 | 17691| 0.98 25.89|
Info: 40000 | 9473 30145 | 231 728 | 17056| 0.48 26.37|
Info: 41000 | 9669 30897 | 196 752 | 16415| 0.51 26.88|
Info: 42000 | 9875 31654 | 206 757 | 15717| 0.50 27.38|
Info: 43000 | 10101 32375 | 226 721 | 15079| 0.49 27.87|
Info: 44000 | 10350 33109 | 249 734 | 14691| 0.77 28.64|
Info: 45000 | 10579 33866 | 229 757 | 14177| 1.02 29.66|
Info: 46000 | 10783 34598 | 204 732 | 13466| 0.61 30.27|
Info: 47000 | 10950 35341 | 167 743 | 12751| 0.60 30.87|
Info: 48000 | 11140 36084 | 190 743 | 12138| 0.52 31.40|
Info: 49000 | 11375 36809 | 235 725 | 11602| 0.79 32.19|
Info: 50000 | 11582 37579 | 207 770 | 10998| 0.88 33.07|
Info: 51000 | 11775 38339 | 193 760 | 10391| 0.72 33.79|
Info: 52000 | 12010 39097 | 235 758 | 9850| 0.79 34.58|
Info: 53000 | 12138 39881 | 128 784 | 9101| 0.46 35.04|
Info: 54000 | 12344 40663 | 206 782 | 8585| 0.93 35.97|
Info: 55000 | 12509 41421 | 165 758 | 7931| 0.49 36.46|
Info: 56000 | 12707 42206 | 198 785 | 7494| 0.76 37.22|
Info: 57000 | 12851 42968 | 144 762 | 6840| 0.43 37.65|
Info: 58000 | 13134 43683 | 283 715 | 6364| 1.25 38.91|
Info: 59000 | 13312 44482 | 178 799 | 5848| 0.67 39.58|
Info: 60000 | 13418 45365 | 106 883 | 5004| 0.32 39.90|
Info: 61000 | 13777 46006 | 359 641 | 4782| 1.29 41.18|
Info: 62000 | 14145 46638 | 368 632 | 4731| 1.35 42.53|
Info: 63000 | 14471 47312 | 326 674 | 4552| 1.00 43.53|
Info: 64000 | 14701 48082 | 230 770 | 3918| 0.63 44.16|
Info: 65000 | 14960 48823 | 259 741 | 3346| 0.87 45.03|
Info: 66000 | 15337 49446 | 377 623 | 3164| 1.21 46.24|
Info: 67000 | 15664 50119 | 327 673 | 3011| 1.25 47.49|
Info: 68000 | 15914 50869 | 250 750 | 2436| 0.70 48.19|
Info: 69000 | 16133 51625 | 219 756 | 1787| 0.58 48.77|
Info: 70000 | 16253 52376 | 120 751 | 1005| 0.67 49.44|
Info: 71000 | 16343 53135 | 90 759 | 144| 0.69 50.13|
Info: 71146 | 16346 53243 | 3 108 | 0| 0.16 50.29|
Info: 1000 | 534 465 | 534 465 | 40639| 1.74 1.74|
Info: 2000 | 890 1109 | 356 644 | 40261| 1.32 3.06|
Info: 3000 | 1159 1840 | 269 731 | 39633| 0.81 3.87|
Info: 4000 | 1374 2625 | 215 785 | 38895| 0.67 4.54|
Info: 5000 | 1508 3491 | 134 866 | 38166| 0.57 5.10|
Info: 6000 | 1663 4336 | 155 845 | 37506| 0.61 5.71|
Info: 7000 | 1785 5214 | 122 878 | 36743| 0.62 6.33|
Info: 8000 | 1908 6091 | 123 877 | 35957| 0.53 6.86|
Info: 9000 | 2044 6955 | 136 864 | 35162| 0.43 7.30|
Info: 10000 | 2148 7851 | 104 896 | 34462| 0.41 7.71|
Info: 11000 | 2301 8698 | 153 847 | 33758| 0.48 8.19|
Info: 12000 | 2422 9577 | 121 879 | 32960| 0.56 8.74|
Info: 13000 | 2519 10480 | 97 903 | 32146| 0.42 9.16|
Info: 14000 | 2647 11352 | 128 872 | 31378| 0.50 9.66|
Info: 15000 | 2768 12231 | 121 879 | 30894| 0.50 10.16|
Info: 16000 | 2893 13106 | 125 875 | 30052| 0.43 10.59|
Info: 17000 | 3076 13923 | 183 817 | 29291| 0.42 11.01|
Info: 18000 | 3261 14738 | 185 815 | 28692| 0.47 11.48|
Info: 19000 | 3397 15602 | 136 864 | 27892| 0.43 11.92|
Info: 20000 | 3607 16392 | 210 790 | 27165| 0.43 12.35|
Info: 21000 | 3821 17178 | 214 786 | 26460| 0.39 12.74|
Info: 22000 | 4095 17904 | 274 726 | 25800| 0.44 13.18|
Info: 23000 | 4274 18725 | 179 821 | 25139| 0.46 13.64|
Info: 24000 | 4447 19552 | 173 827 | 24496| 0.48 14.12|
Info: 25000 | 4620 20377 | 173 825 | 23759| 0.43 14.55|
Info: 26000 | 4773 21221 | 153 844 | 23405| 0.46 15.01|
Info: 27000 | 5099 21891 | 326 670 | 22913| 0.48 15.49|
Info: 28000 | 5383 22593 | 284 702 | 22265| 0.41 15.90|
Info: 29000 | 5695 23275 | 312 682 | 21741| 0.53 16.43|
Info: 30000 | 5949 23995 | 254 720 | 21111| 0.49 16.92|
Info: 31000 | 6193 24689 | 244 694 | 20500| 0.53 17.45|
Info: 32000 | 6341 25442 | 148 753 | 19810| 0.40 17.85|
Info: 33000 | 6516 26174 | 175 732 | 19176| 0.47 18.32|
Info: 34000 | 6691 26929 | 175 755 | 18518| 0.45 18.77|
Info: 35000 | 6887 27688 | 196 759 | 17837| 0.48 19.24|
Info: 36000 | 7101 28422 | 214 734 | 17316| 0.44 19.69|
Info: 37000 | 7368 29116 | 267 694 | 16817| 0.73 20.41|
Info: 38000 | 7601 29836 | 233 720 | 16230| 0.61 21.02|
Info: 39000 | 7774 30610 | 173 774 | 15592| 0.55 21.57|
Info: 40000 | 7953 31373 | 179 763 | 14842| 0.53 22.10|
Info: 41000 | 8143 32127 | 190 754 | 14121| 0.47 22.56|
Info: 42000 | 8344 32876 | 201 749 | 13561| 0.53 23.09|
Info: 43000 | 8511 33643 | 167 767 | 12834| 0.74 23.83|
Info: 44000 | 8695 34407 | 184 764 | 12343| 0.62 24.46|
Info: 45000 | 8853 35207 | 158 800 | 11863| 0.78 25.24|
Info: 46000 | 9015 35982 | 162 775 | 11280| 0.71 25.95|
Info: 47000 | 9186 36775 | 171 793 | 10575| 0.51 26.46|
Info: 48000 | 9450 37498 | 264 723 | 10187| 1.02 27.48|
Info: 49000 | 9714 38222 | 264 724 | 9864| 0.99 28.47|
Info: 50000 | 9851 39033 | 137 811 | 9135| 0.43 28.90|
Info: 51000 | 10074 39770 | 223 737 | 8655| 0.85 29.75|
Info: 52000 | 10325 40509 | 251 739 | 8326| 1.12 30.87|
Info: 53000 | 10570 41244 | 245 735 | 7834| 0.94 31.80|
Info: 54000 | 10754 42010 | 184 766 | 7252| 0.58 32.38|
Info: 55000 | 10962 42739 | 208 729 | 6810| 0.75 33.13|
Info: 56000 | 11238 43458 | 276 719 | 6427| 1.08 34.21|
Info: 57000 | 11607 44089 | 369 631 | 6298| 1.40 35.61|
Info: 58000 | 11850 44810 | 243 721 | 5837| 1.16 36.77|
Info: 59000 | 11964 45668 | 114 858 | 4984| 0.30 37.07|
Info: 60000 | 12313 46319 | 349 651 | 4846| 1.20 38.27|
Info: 61000 | 12687 46945 | 374 626 | 4597| 1.28 39.55|
Info: 62000 | 13000 47632 | 313 687 | 4462| 1.28 40.83|
Info: 63000 | 13162 48466 | 162 834 | 3684| 0.54 41.37|
Info: 64000 | 13457 49171 | 295 705 | 3331| 0.88 42.25|
Info: 65000 | 13860 49768 | 403 597 | 3180| 1.46 43.70|
Info: 66000 | 14283 50345 | 423 577 | 2949| 1.83 45.53|
Info: 67000 | 14641 50987 | 358 642 | 2656| 1.36 46.89|
Info: 68000 | 14901 51727 | 260 740 | 2289| 2.66 49.55|
Info: 69000 | 15078 52440 | 177 713 | 1522| 0.72 50.27|
Info: 70000 | 15380 53048 | 302 608 | 1082| 1.12 51.39|
Info: 71000 | 15562 53760 | 182 712 | 496| 0.77 52.16|
Info: 71687 | 15670 54247 | 108 487 | 0| 0.57 52.73|
Info: Routing complete.
Info: Router1 time 50.29s
Info: Checksum: 0x9bf9af99
Info: Router1 time 52.73s
Info: Checksum: 0xa6319bc1
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q.Q
Info: routing 0.90 1.29 Net u_arbiter_wide.m_addr[1] (15,4) -> (15,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_1.B
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.47 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_1.F
Info: routing 0.60 2.07 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D[0] (15,7) -> (15,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.A
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_7.Q
Info: routing 0.75 1.14 Net u_arbiter_wide.m_addr[7] (24,7) -> (23,5)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.25 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.F
Info: routing 0.53 2.78 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (15,7) -> (14,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: logic 0.18 1.33 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z.F
Info: routing 0.78 2.11 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[4] (23,5) -> (25,2)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.96 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 3.42 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (14,7) -> (14,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: logic 0.19 2.30 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.68 2.98 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0[4] (25,2) -> (25,5)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.60 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.60 4.20 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (14,7) -> (14,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.19 3.17 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.52 3.69 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[0] (25,5) -> (24,6)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.38 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.85 5.23 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (14,7) -> (12,8)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 3.87 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.56 4.42 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (24,6) -> (22,7)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.41 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.36 5.77 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (12,8) -> (12,8)
Info: logic 0.18 4.60 Source u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.03 4.64 Net u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (22,7) -> (22,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.95 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.47 6.42 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (12,8) -> (13,12)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: logic 0.18 4.82 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.62 5.43 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (22,7) -> (19,5)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 6.60 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.36 6.97 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (13,12) -> (13,12)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: logic 0.18 5.61 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.03 5.65 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (19,5) -> (19,5)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.15 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 1.02 8.17 Net u_host_arb.m_wr_LUT4_C_Z[3] (13,12) -> (5,18)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: logic 0.18 5.83 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 2.21 8.04 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (19,5) -> (4,26)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.35 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 2.26 10.61 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (5,18) -> (5,57)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_8.CE
Info: logic 0.18 8.22 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.81 10.03 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (4,26) -> (15,7)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_2_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 10.61 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_8.CE
Info: 2.19 ns logic, 8.42 ns routing
Info: logic 0.18 10.21 Source u_sdram_backend.state_TRELLIS_FF_Q_2_DI_LUT4_Z.F
Info: routing 0.12 10.33 Net u_sdram_backend.state_TRELLIS_FF_Q_2_DI (15,7) -> (15,7)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_2.DI
Info: setup 0.00 10.33 Source u_sdram_backend.state_TRELLIS_FF_Q_2.DI
Info: 2.22 ns logic, 8.10 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[0]$tr_io.O
Info: routing 3.36 3.36 Net sdram_dq[0]$TRELLIS_IO_IN (0,26) -> (12,6)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D_LUT4_Z.B
Info: source 0.00 0.00 Source sdram_dq[2]$tr_io.O
Info: routing 3.10 3.10 Net sdram_dq[2]$TRELLIS_IO_IN (0,29) -> (11,6)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_98_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.54 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.72 4.26 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_48_DI_LUT4_Z_D[2] (12,6) -> (13,5)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI_LUT4_Z.D
Info: logic 0.18 3.28 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_98_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.42 3.70 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_98_DI_LUT4_Z_D[2] (11,6) -> (13,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_34_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.44 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI_LUT4_Z.F
Info: routing 0.12 4.56 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112_DI (13,5) -> (13,5)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112.DI
Info: setup 0.00 4.56 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_112.DI
Info: 0.36 ns logic, 4.20 ns routing
Info: logic 0.18 3.88 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_34_DI_LUT4_Z.F
Info: routing 0.12 4.00 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_34_DI (13,7) -> (13,7)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_34.DI
Info: setup 0.00 4.00 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_34.DI
Info: 0.36 ns logic, 3.64 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q.Q
Info: routing 1.55 1.94 Net u_spi_bridge.byte_idx[0] (21,47) -> (21,26)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 0.68 1.07 Net u_spi_bridge.byte_idx[3] (21,45) -> (19,45)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.12 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 2.09 4.21 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (21,26) -> (15,56)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: logic 0.18 1.25 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.34 1.59 Net u_dataflow_core.reg_result_addr_TRELLIS_FF_Q_CE_LUT4_Z_C[0] (19,45) -> (19,45)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.39 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.44 4.83 Net spi_miso_LUT4_Z_B[2] (15,56) -> (16,56)
Info: logic 0.18 1.77 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.F
Info: routing 1.24 3.01 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (19,45) -> (14,52)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.19 Source spi_miso_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.67 3.86 Net spi_miso_LUT4_Z_B[2] (14,52) -> (15,53)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.01 Source spi_miso_LUT4_Z.F
Info: routing 1.48 6.49 Net spi_miso$TRELLIS_IO_OUT (16,56) -> (0,62)
Info: logic 0.18 4.04 Source spi_miso_LUT4_Z.F
Info: routing 1.71 5.75 Net spi_miso$TRELLIS_IO_OUT (15,53) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 0.94 ns logic, 5.56 ns routing
Info: 1.12 ns logic, 4.64 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 94.22 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 96.84 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.56 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.49 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.00 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 5.75 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 5012, 5508) |+
Info: [ 5508, 6004) |*+
Info: [ 6004, 6500) |***+
Info: [ 6500, 6996) |****+
Info: [ 6996, 7492) |******+
Info: [ 7492, 7988) |*******+
Info: [ 7988, 8484) |***********+
Info: [ 8484, 8980) |*************+
Info: [ 8980, 9476) |***************+
Info: [ 9476, 9972) |*************************+
Info: [ 9972, 10468) |*******************************+
Info: [ 10468, 10964) |***************************************+
Info: [ 10964, 11460) |**************************************+
Info: [ 11460, 11956) |************************************+
Info: [ 11956, 12452) |**************************************+
Info: [ 12452, 12948) |**************************************************+
Info: [ 12948, 13444) |**********************************************+
Info: [ 13444, 13940) |*******************************************************+
Info: [ 13940, 14436) |************************************************************
Info: [ 14436, 14932) |*************************************************+
Info: legend: * represents 39 endpoint(s)
Info: + represents [1,39) endpoint(s)
Info: [ 5299, 5781) |+
Info: [ 5781, 6263) |+
Info: [ 6263, 6745) |*+
Info: [ 6745, 7227) |***+
Info: [ 7227, 7709) |*****+
Info: [ 7709, 8191) |*********+
Info: [ 8191, 8673) |**********+
Info: [ 8673, 9155) |*********+
Info: [ 9155, 9637) |*********+
Info: [ 9637, 10119) |*********************+
Info: [ 10119, 10601) |*************************+
Info: [ 10601, 11083) |*********************************+
Info: [ 11083, 11565) |**************************************+
Info: [ 11565, 12047) |**********************************************+
Info: [ 12047, 12529) |*****************************************+
Info: [ 12529, 13011) |*************************************+
Info: [ 13011, 13493) |*************************************+
Info: [ 13493, 13975) |***********************************************+
Info: [ 13975, 14457) |************************************************************
Info: [ 14457, 14939) |*************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed5.log
+223 -216
View File
@@ -1,13 +1,13 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: Total LUT4s: 7262/43848 16%
Info: logic LUTs: 4612/43848 10%
Info: carry LUTs: 1480/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Total DFFs: 6529/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
@@ -36,11 +36,11 @@ Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
@@ -79,13 +79,13 @@ Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: 2373 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Checksum: 0xa739669a
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
@@ -113,279 +113,286 @@ Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_FF: 6529/ 43848 14%
Info: TRELLIS_COMB: 7712/ 43848 17%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 652028.
Info: at initial placer iter 0, wirelen = 3714
Info: at initial placer iter 1, wirelen = 3306
Info: at initial placer iter 2, wirelen = 3140
Info: at initial placer iter 3, wirelen = 3093
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3292, spread = 111450, legal = 125640; time = 0.48s
Info: at iteration #2, type ALL: wirelen solved = 12489, spread = 84015, legal = 97642; time = 0.43s
Info: at iteration #3, type ALL: wirelen solved = 20103, spread = 72651, legal = 86958; time = 0.47s
Info: at iteration #4, type ALL: wirelen solved = 23708, spread = 70133, legal = 87621; time = 0.50s
Info: at iteration #5, type ALL: wirelen solved = 25645, spread = 67729, legal = 84477; time = 0.41s
Info: at iteration #6, type ALL: wirelen solved = 26619, spread = 66406, legal = 80494; time = 0.41s
Info: at iteration #7, type ALL: wirelen solved = 27537, spread = 65375, legal = 81688; time = 0.40s
Info: at iteration #8, type ALL: wirelen solved = 28365, spread = 65612, legal = 80930; time = 0.43s
Info: at iteration #9, type ALL: wirelen solved = 29553, spread = 67858, legal = 81892; time = 0.43s
Info: at iteration #10, type ALL: wirelen solved = 31925, spread = 69560, legal = 80742; time = 0.40s
Info: at iteration #11, type ALL: wirelen solved = 33586, spread = 69204, legal = 77791; time = 0.35s
Info: at iteration #12, type ALL: wirelen solved = 34385, spread = 68629, legal = 81183; time = 0.35s
Info: at iteration #13, type ALL: wirelen solved = 34445, spread = 68383, legal = 81209; time = 0.41s
Info: at iteration #14, type ALL: wirelen solved = 34771, spread = 68801, legal = 83592; time = 0.38s
Info: at iteration #15, type ALL: wirelen solved = 35340, spread = 68411, legal = 81890; time = 0.39s
Info: at iteration #16, type ALL: wirelen solved = 35627, spread = 68678, legal = 82269; time = 0.37s
Info: HeAP Placer Time: 9.46s
Info: of which solving equations: 4.74s
Info: of which spreading cells: 0.71s
Info: of which strict legalisation: 1.94s
Info: Creating initial analytic placement for 8052 cells, random placement wirelen = 650829.
Info: at initial placer iter 0, wirelen = 3724
Info: at initial placer iter 1, wirelen = 3154
Info: at initial placer iter 2, wirelen = 3233
Info: at initial placer iter 3, wirelen = 3116
Info: Running main analytical placer, max placement attempts per cell = 26342911.
Info: at iteration #1, type ALL: wirelen solved = 2928, spread = 112498, legal = 127470; time = 0.53s
Info: at iteration #2, type ALL: wirelen solved = 12770, spread = 87356, legal = 100367; time = 0.47s
Info: at iteration #3, type ALL: wirelen solved = 20239, spread = 75632, legal = 94332; time = 0.53s
Info: at iteration #4, type ALL: wirelen solved = 24607, spread = 69502, legal = 85195; time = 0.43s
Info: at iteration #5, type ALL: wirelen solved = 26546, spread = 69714, legal = 84164; time = 0.44s
Info: at iteration #6, type ALL: wirelen solved = 28692, spread = 67268, legal = 82992; time = 0.40s
Info: at iteration #7, type ALL: wirelen solved = 29271, spread = 66515, legal = 84126; time = 0.41s
Info: at iteration #8, type ALL: wirelen solved = 29639, spread = 66244, legal = 81867; time = 0.40s
Info: at iteration #9, type ALL: wirelen solved = 30934, spread = 66120, legal = 82532; time = 0.42s
Info: at iteration #10, type ALL: wirelen solved = 31449, spread = 65887, legal = 82784; time = 0.42s
Info: at iteration #11, type ALL: wirelen solved = 32345, spread = 64512, legal = 77822; time = 0.43s
Info: at iteration #12, type ALL: wirelen solved = 32153, spread = 64786, legal = 80975; time = 0.40s
Info: at iteration #13, type ALL: wirelen solved = 32927, spread = 64999, legal = 80402; time = 0.41s
Info: at iteration #14, type ALL: wirelen solved = 33177, spread = 65476, legal = 80776; time = 0.50s
Info: at iteration #15, type ALL: wirelen solved = 34189, spread = 65852, legal = 79796; time = 0.38s
Info: at iteration #16, type ALL: wirelen solved = 34826, spread = 65663, legal = 83271; time = 0.46s
Info: HeAP Placer Time: 10.09s
Info: of which solving equations: 4.80s
Info: of which spreading cells: 0.73s
Info: of which strict legalisation: 2.45s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1442, wirelen = 77791
Info: at iteration #5: temp = 0.000000, timing cost = 1356, wirelen = 72049
Info: at iteration #10: temp = 0.000000, timing cost = 885, wirelen = 70691
Info: at iteration #15: temp = 0.000000, timing cost = 849, wirelen = 70380
Info: at iteration #20: temp = 0.000000, timing cost = 841, wirelen = 70180
Info: at iteration #25: temp = 0.000000, timing cost = 830, wirelen = 70040
Info: at iteration #28: temp = 0.000000, timing cost = 831, wirelen = 70005
Info: SA placement time 25.76s
Info: at iteration #1: temp = 0.000000, timing cost = 954, wirelen = 77822
Info: at iteration #5: temp = 0.000000, timing cost = 923, wirelen = 71847
Info: at iteration #10: temp = 0.000000, timing cost = 686, wirelen = 69877
Info: at iteration #15: temp = 0.000000, timing cost = 589, wirelen = 69316
Info: at iteration #18: temp = 0.000000, timing cost = 1092, wirelen = 69144
Info: SA placement time 18.65s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 70.83 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 74.81 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.51 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 9.18 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.64 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.69 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 1507, 2185) |+
Info: [ 2185, 2863) |+
Info: [ 2863, 3541) |+
Info: [ 3541, 4219) |*****+
Info: [ 4219, 4897) |******+
Info: [ 4897, 5575) |*********+
Info: [ 5575, 6253) |*********+
Info: [ 6253, 6931) |**********+
Info: [ 6931, 7609) |************************+
Info: [ 7609, 8287) |*********************************+
Info: [ 8287, 8965) |**********************************************+
Info: [ 8965, 9643) |***********************************+
Info: [ 9643, 10321) |********************************+
Info: [ 10321, 10999) |**************************+
Info: [ 10999, 11677) |********************+
Info: [ 11677, 12355) |*********************************+
Info: [ 12355, 13033) |**************************************************+
Info: [ 13033, 13711) |************************************************************
Info: [ 13711, 14389) |***************************************************+
Info: [ 14389, 15067) |*********************************************+
Info: Checksum: 0x6abd595c
Info: legend: * represents 34 endpoint(s)
Info: + represents [1,34) endpoint(s)
Info: [ 2257, 2897) |+
Info: [ 2897, 3537) |+
Info: [ 3537, 4177) |+
Info: [ 4177, 4817) |**+
Info: [ 4817, 5457) |***+
Info: [ 5457, 6097) |******+
Info: [ 6097, 6737) |*********+
Info: [ 6737, 7377) |********+
Info: [ 7377, 8017) |**********+
Info: [ 8017, 8657) |*******************+
Info: [ 8657, 9297) |********************************+
Info: [ 9297, 9937) |***********************************+
Info: [ 9937, 10577) |********************************************+
Info: [ 10577, 11217) |**************************************************+
Info: [ 11217, 11857) |***********************************************************+
Info: [ 11857, 12497) |**************************************************+
Info: [ 12497, 13137) |************************************************************
Info: [ 13137, 13777) |***********************************************************+
Info: [ 13777, 14417) |*************************************************+
Info: [ 14417, 15057) |************************************************+
Info: Checksum: 0x48a90575
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39479 arcs.
Info: Routing 41064 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 429 570 | 429 570 | 39015| 1.55 1.55|
Info: 2000 | 669 1330 | 240 760 | 38340| 0.80 2.34|
Info: 3000 | 831 2168 | 162 838 | 37558| 0.68 3.03|
Info: 4000 | 893 3106 | 62 938 | 36667| 0.47 3.49|
Info: 5000 | 1062 3937 | 169 831 | 35993| 0.59 4.09|
Info: 6000 | 1203 4796 | 141 859 | 35298| 0.70 4.79|
Info: 7000 | 1345 5654 | 142 858 | 34742| 0.71 5.50|
Info: 8000 | 1472 6527 | 127 873 | 34045| 0.56 6.06|
Info: 9000 | 1529 7470 | 57 943 | 33150| 0.50 6.56|
Info: 10000 | 1713 8286 | 184 816 | 32501| 0.96 7.52|
Info: 11000 | 1836 9163 | 123 877 | 31778| 0.60 8.12|
Info: 12000 | 1927 10072 | 91 909 | 30912| 0.43 8.55|
Info: 13000 | 2047 10952 | 120 880 | 30118| 0.67 9.21|
Info: 14000 | 2131 11868 | 84 916 | 29309| 0.49 9.71|
Info: 15000 | 2242 12757 | 111 889 | 28541| 0.51 10.22|
Info: 16000 | 2364 13635 | 122 878 | 27815| 0.42 10.64|
Info: 17000 | 2559 14440 | 195 805 | 27340| 0.64 11.28|
Info: 18000 | 2703 15296 | 144 856 | 26614| 0.55 11.83|
Info: 19000 | 2865 16134 | 162 838 | 25917| 0.40 12.23|
Info: 20000 | 3093 16906 | 228 772 | 25233| 0.43 12.66|
Info: 21000 | 3250 17749 | 157 843 | 24488| 0.38 13.04|
Info: 22000 | 3477 18521 | 227 772 | 23824| 0.56 13.60|
Info: 23000 | 3815 19182 | 338 661 | 23284| 0.46 14.07|
Info: 24000 | 4083 19914 | 268 732 | 22679| 0.54 14.61|
Info: 25000 | 4321 20658 | 238 744 | 22133| 0.44 15.05|
Info: 26000 | 4526 21439 | 205 781 | 21537| 0.55 15.60|
Info: 27000 | 4793 22128 | 267 689 | 20913| 0.41 16.01|
Info: 28000 | 4993 22879 | 200 751 | 20252| 0.43 16.44|
Info: 29000 | 5230 23583 | 237 704 | 19585| 0.43 16.88|
Info: 30000 | 5462 24273 | 232 690 | 18922| 0.39 17.27|
Info: 31000 | 5650 25027 | 188 754 | 18180| 0.51 17.79|
Info: 32000 | 5857 25778 | 207 751 | 17507| 0.49 18.28|
Info: 33000 | 6077 26542 | 220 764 | 16957| 1.36 19.64|
Info: 34000 | 6221 27321 | 144 779 | 16181| 0.47 20.11|
Info: 35000 | 6452 28043 | 231 722 | 15568| 0.54 20.65|
Info: 36000 | 6660 28800 | 208 757 | 14916| 0.56 21.22|
Info: 37000 | 6835 29553 | 175 753 | 14124| 0.45 21.67|
Info: 38000 | 7054 30316 | 219 763 | 13755| 1.23 22.89|
Info: 39000 | 7214 31082 | 160 766 | 13058| 0.45 23.34|
Info: 40000 | 7376 31865 | 162 783 | 12331| 0.49 23.83|
Info: 41000 | 7535 32660 | 159 795 | 11698| 0.66 24.49|
Info: 42000 | 7694 33464 | 159 804 | 10992| 0.57 25.06|
Info: 43000 | 7880 34263 | 186 799 | 10401| 0.94 25.99|
Info: 44000 | 7997 35066 | 117 803 | 9572| 0.39 26.38|
Info: 45000 | 8106 35897 | 109 831 | 8731| 0.49 26.87|
Info: 46000 | 8298 36670 | 192 773 | 8115| 0.75 27.62|
Info: 47000 | 8393 37482 | 95 812 | 7300| 0.33 27.95|
Info: 48000 | 8583 38265 | 190 783 | 6595| 0.68 28.63|
Info: 49000 | 8763 39037 | 180 772 | 6140| 0.78 29.41|
Info: 50000 | 8892 39896 | 129 859 | 5496| 0.44 29.85|
Info: 51000 | 9112 40675 | 220 779 | 4978| 0.83 30.68|
Info: 52000 | 9505 41282 | 393 607 | 4735| 1.29 31.98|
Info: 53000 | 9726 42057 | 221 775 | 4223| 0.76 32.73|
Info: 54000 | 9900 42883 | 174 826 | 3445| 0.50 33.23|
Info: 55000 | 10291 43492 | 391 609 | 3223| 1.43 34.66|
Info: 56000 | 10686 44097 | 395 605 | 2953| 1.21 35.86|
Info: 57000 | 10891 44892 | 205 795 | 2346| 0.60 36.47|
Info: 58000 | 11041 45676 | 150 784 | 1590| 0.57 37.04|
Info: 59000 | 11157 46403 | 116 727 | 796| 0.60 37.63|
Info: 60000 | 11364 47119 | 207 716 | 308| 1.25 38.89|
Info: 60407 | 11397 47453 | 33 334 | 0| 0.28 39.16|
Info: 1000 | 499 500 | 499 500 | 40705| 1.82 1.82|
Info: 2000 | 905 1094 | 406 594 | 40273| 1.07 2.90|
Info: 3000 | 1199 1800 | 294 706 | 39822| 1.27 4.17|
Info: 4000 | 1381 2618 | 182 818 | 39297| 0.99 5.15|
Info: 5000 | 1541 3458 | 160 840 | 38602| 0.93 6.08|
Info: 6000 | 1635 4364 | 94 906 | 37752| 0.64 6.71|
Info: 7000 | 1754 5245 | 119 881 | 36971| 0.69 7.41|
Info: 8000 | 1847 6152 | 93 907 | 36112| 0.52 7.92|
Info: 9000 | 1934 7065 | 87 913 | 35234| 0.34 8.27|
Info: 10000 | 2052 7947 | 118 882 | 34416| 0.34 8.61|
Info: 11000 | 2136 8863 | 84 916 | 33550| 0.32 8.92|
Info: 12000 | 2203 9796 | 67 933 | 32634| 0.33 9.25|
Info: 13000 | 2304 10695 | 101 899 | 31838| 0.34 9.59|
Info: 14000 | 2421 11578 | 117 883 | 31007| 0.40 9.99|
Info: 15000 | 2568 12431 | 147 853 | 30257| 0.68 10.67|
Info: 16000 | 2720 13279 | 152 848 | 29450| 0.43 11.10|
Info: 17000 | 2890 14109 | 170 830 | 28708| 0.45 11.56|
Info: 18000 | 3034 14965 | 144 856 | 27905| 0.40 11.96|
Info: 19000 | 3202 15797 | 168 832 | 27103| 0.43 12.40|
Info: 20000 | 3436 16563 | 234 766 | 26441| 0.49 12.89|
Info: 21000 | 3586 17413 | 150 850 | 25667| 0.46 13.35|
Info: 22000 | 3749 18250 | 163 837 | 24896| 0.49 13.84|
Info: 23000 | 3980 19016 | 231 766 | 24183| 0.49 14.33|
Info: 24000 | 4273 19722 | 293 706 | 23559| 0.59 14.92|
Info: 25000 | 4522 20473 | 249 751 | 22917| 0.59 15.51|
Info: 26000 | 4777 21210 | 255 737 | 22302| 0.53 16.04|
Info: 27000 | 5028 21927 | 251 717 | 21662| 0.53 16.57|
Info: 28000 | 5248 22651 | 220 724 | 20990| 0.44 17.01|
Info: 29000 | 5444 23385 | 196 734 | 20284| 0.45 17.46|
Info: 30000 | 5628 24125 | 184 740 | 19547| 0.41 17.87|
Info: 31000 | 5804 24853 | 176 728 | 18783| 0.47 18.34|
Info: 32000 | 6012 25587 | 208 734 | 18040| 0.51 18.86|
Info: 33000 | 6252 26303 | 240 716 | 17446| 0.49 19.35|
Info: 34000 | 6440 27037 | 188 734 | 16743| 0.56 19.92|
Info: 35000 | 6626 27801 | 186 764 | 16006| 0.51 20.43|
Info: 36000 | 6873 28540 | 247 739 | 15499| 0.60 21.03|
Info: 37000 | 7077 29270 | 204 730 | 14825| 0.58 21.61|
Info: 38000 | 7240 30011 | 163 741 | 14051| 0.46 22.07|
Info: 39000 | 7389 30798 | 149 787 | 13251| 0.47 22.55|
Info: 40000 | 7522 31602 | 133 804 | 12466| 0.41 22.96|
Info: 41000 | 7748 32331 | 226 729 | 11922| 0.94 23.90|
Info: 42000 | 7904 33115 | 156 784 | 11283| 0.49 24.40|
Info: 43000 | 8075 33917 | 171 802 | 10580| 0.70 25.10|
Info: 44000 | 8333 34635 | 258 718 | 10269| 1.19 26.28|
Info: 45000 | 8474 35465 | 141 830 | 9502| 0.50 26.78|
Info: 46000 | 8624 36249 | 150 784 | 8735| 0.66 27.44|
Info: 47000 | 8855 36974 | 231 725 | 8067| 0.86 28.30|
Info: 48000 | 8965 37774 | 110 800 | 7265| 0.39 28.69|
Info: 49000 | 9124 38563 | 159 789 | 6509| 0.66 29.35|
Info: 50000 | 9443 39244 | 319 681 | 6206| 1.63 30.99|
Info: 51000 | 9590 40056 | 147 812 | 5516| 0.44 31.42|
Info: 52000 | 9778 40858 | 188 802 | 4954| 0.65 32.08|
Info: 53000 | 10150 41486 | 372 628 | 4587| 1.25 33.32|
Info: 54000 | 10372 42256 | 222 770 | 4194| 0.71 34.03|
Info: 55000 | 10591 43037 | 219 781 | 3565| 0.55 34.58|
Info: 56000 | 11014 43614 | 423 577 | 3285| 1.34 35.92|
Info: 57000 | 11412 44216 | 398 602 | 3035| 1.19 37.11|
Info: 58000 | 11761 44867 | 349 651 | 2664| 1.12 38.23|
Info: 59000 | 11970 45634 | 209 767 | 1944| 0.53 38.76|
Info: 60000 | 12152 46333 | 182 699 | 1326| 0.77 39.53|
Info: 61000 | 12297 47041 | 145 708 | 558| 0.74 40.26|
Info: 61770 | 12418 47582 | 121 541 | 0| 0.51 40.78|
Info: Routing complete.
Info: Router1 time 39.16s
Info: Checksum: 0x2fb02924
Info: Router1 time 40.78s
Info: Checksum: 0x3354add9
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_4.Q
Info: routing 0.79 1.18 Net u_arbiter_wide.m_addr[5] (17,11) -> (17,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_2.B
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_9.Q
Info: routing 0.85 1.25 Net u_arbiter_wide.m_addr[9] (18,4) -> (17,3)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.36 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z_2.F
Info: routing 0.60 1.96 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z_D[1] (17,7) -> (17,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.B
Info: logic 0.18 1.43 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_Z_D_LUT4_Z.F
Info: routing 0.45 1.88 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_Z_D[2] (17,3) -> (17,3)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.14 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_Z.F
Info: routing 0.52 2.66 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[3] (17,7) -> (17,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.D
Info: logic 0.18 2.06 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_Z.F
Info: routing 0.68 2.74 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z[3] (17,3) -> (18,4)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.85 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 3.30 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (17,8) -> (17,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: logic 0.18 2.92 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D.F
Info: routing 0.38 3.30 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z[3] (18,4) -> (18,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.48 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.45 3.93 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (17,8) -> (17,8)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 3.48 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.45 3.93 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z[3] (18,5) -> (18,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.11 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.18 5.29 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (17,8) -> (13,16)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 4.11 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 1.30 5.41 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[0] (18,5) -> (14,15)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.47 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.00 6.47 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (13,16) -> (14,9)
Info: logic 0.18 5.59 Source u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.57 6.16 Net u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (14,15) -> (16,11)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.65 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.78 7.43 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (14,9) -> (15,13)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: logic 0.18 6.34 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.03 6.38 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (16,11) -> (16,11)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 7.61 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.17 7.79 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (15,13) -> (15,13)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: logic 0.18 6.56 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.34 6.89 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (16,11) -> (16,11)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.97 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 1.11 9.07 Net u_host_arb.m_wr_LUT4_C_Z[3] (15,13) -> (6,21)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: logic 0.18 7.07 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 2.07 9.15 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (16,11) -> (7,38)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.25 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 2.25 11.50 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (6,21) -> (3,54)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q.CE
Info: logic 0.18 9.33 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.54 10.86 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (7,38) -> (15,23)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_2_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 11.50 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q.CE
Info: 2.19 ns logic, 9.31 ns routing
Info: logic 0.18 11.04 Source u_sdram_backend.state_TRELLIS_FF_Q_2_DI_LUT4_Z.F
Info: routing 0.12 11.16 Net u_sdram_backend.state_TRELLIS_FF_Q_2_DI (15,23) -> (15,23)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_2.DI
Info: setup 0.00 11.16 Source u_sdram_backend.state_TRELLIS_FF_Q_2.DI
Info: 2.38 ns logic, 8.79 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 2.71 2.71 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (11,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.B
Info: source 0.00 0.00 Source sdram_dq[1]$tr_io.O
Info: routing 3.15 3.15 Net sdram_dq[1]$TRELLIS_IO_IN (0,29) -> (13,5)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_97_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 2.89 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.69 3.58 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_51_DI_LUT4_Z_D[2] (11,9) -> (12,8)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115_DI_LUT4_Z.D
Info: logic 0.18 3.33 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_97_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.92 4.26 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_97_DI_LUT4_Z_D[2] (13,5) -> (15,8)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.76 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115_DI_LUT4_Z.F
Info: routing 0.12 3.88 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115_DI (12,8) -> (12,8)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115.DI
Info: setup 0.00 3.88 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_115.DI
Info: 0.36 ns logic, 3.52 ns routing
Info: logic 0.18 4.44 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33_DI_LUT4_Z.F
Info: routing 0.12 4.55 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33_DI (15,8) -> (15,8)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33.DI
Info: setup 0.00 4.55 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_33.DI
Info: 0.36 ns logic, 4.20 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q.Q
Info: routing 1.42 1.81 Net u_spi_bridge.byte_idx[0] (22,51) -> (22,30)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 0.66 1.05 Net u_spi_bridge.byte_idx[3] (25,39) -> (26,39)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.99 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.88 3.87 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (22,30) -> (15,57)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: logic 0.18 1.24 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.56 1.79 Net u_dataflow_core.reg_result_addr_TRELLIS_FF_Q_CE_LUT4_Z_C[0] (26,39) -> (24,39)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.05 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.80 4.85 Net spi_miso_LUT4_Z_B[2] (15,57) -> (18,57)
Info: logic 0.18 1.97 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.F
Info: routing 1.00 2.97 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (24,39) -> (18,44)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.15 Source spi_miso_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.62 3.77 Net spi_miso_LUT4_Z_B[2] (18,44) -> (19,44)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.03 Source spi_miso_LUT4_Z.F
Info: routing 1.65 6.68 Net spi_miso$TRELLIS_IO_OUT (18,57) -> (0,62)
Info: logic 0.18 3.95 Source spi_miso_LUT4_Z.F
Info: routing 2.38 6.33 Net spi_miso$TRELLIS_IO_OUT (19,44) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 0.94 ns logic, 5.74 ns routing
Info: 1.12 ns logic, 5.22 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 86.95 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 89.59 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.88 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.68 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.55 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.33 ns
Info: Slack histogram:
Info: legend: * represents 38 endpoint(s)
Info: + represents [1,38) endpoint(s)
Info: [ 4124, 4665) |+
Info: [ 4665, 5206) |+
Info: [ 5206, 5747) |*+
Info: [ 5747, 6288) |**+
Info: [ 6288, 6829) |*****+
Info: [ 6829, 7370) |********+
Info: [ 7370, 7911) |*****+
Info: [ 7911, 8452) |***********+
Info: [ 8452, 8993) |****************+
Info: [ 8993, 9534) |********************+
Info: [ 9534, 10075) |***********************************+
Info: [ 10075, 10616) |**************************************+
Info: [ 10616, 11157) |***************************************+
Info: [ 11157, 11698) |******************************+
Info: [ 11698, 12239) |**********************************+
Info: [ 12239, 12780) |******************************+
Info: [ 12780, 13321) |*************************************************+
Info: [ 13321, 13862) |*******************************************************+
Info: [ 13862, 14403) |************************************************************
Info: [ 14403, 14944) |************************************************+
Info: legend: * represents 39 endpoint(s)
Info: + represents [1,39) endpoint(s)
Info: [ 4463, 4986) |+
Info: [ 4986, 5509) |+
Info: [ 5509, 6032) |+
Info: [ 6032, 6555) |+
Info: [ 6555, 7078) |****+
Info: [ 7078, 7601) |*******+
Info: [ 7601, 8124) |********+
Info: [ 8124, 8647) |*******+
Info: [ 8647, 9170) |************+
Info: [ 9170, 9693) |***************+
Info: [ 9693, 10216) |*******************+
Info: [ 10216, 10739) |******************+
Info: [ 10739, 11262) |***********************************+
Info: [ 11262, 11785) |************************************+
Info: [ 11785, 12308) |********************************************+
Info: [ 12308, 12831) |***********************************************************+
Info: [ 12831, 13354) |*****************************************************+
Info: [ 13354, 13877) |****************************************************+
Info: [ 13877, 14400) |************************************************************
Info: [ 14400, 14923) |**********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed6.log
+225 -231
View File
@@ -1,13 +1,13 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: Total LUT4s: 7262/43848 16%
Info: logic LUTs: 4612/43848 10%
Info: carry LUTs: 1480/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Total DFFs: 6529/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
@@ -36,11 +36,11 @@ Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
@@ -79,13 +79,13 @@ Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: 2373 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Checksum: 0xa739669a
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
@@ -113,290 +113,284 @@ Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_FF: 6529/ 43848 14%
Info: TRELLIS_COMB: 7712/ 43848 17%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 653149.
Info: at initial placer iter 0, wirelen = 3728
Info: at initial placer iter 1, wirelen = 3229
Info: at initial placer iter 2, wirelen = 3142
Info: at initial placer iter 3, wirelen = 3088
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3089, spread = 113935, legal = 130601; time = 0.47s
Info: at iteration #2, type ALL: wirelen solved = 12854, spread = 81908, legal = 97493; time = 0.43s
Info: at iteration #3, type ALL: wirelen solved = 19569, spread = 71889, legal = 90858; time = 0.52s
Info: at iteration #4, type ALL: wirelen solved = 24226, spread = 66935, legal = 82654; time = 0.39s
Info: at iteration #5, type ALL: wirelen solved = 25768, spread = 66254, legal = 83971; time = 0.48s
Info: at iteration #6, type ALL: wirelen solved = 26901, spread = 65525, legal = 82834; time = 0.42s
Info: at iteration #7, type ALL: wirelen solved = 27650, spread = 65492, legal = 82841; time = 0.44s
Info: at iteration #8, type ALL: wirelen solved = 28809, spread = 65793, legal = 81456; time = 0.39s
Info: at iteration #9, type ALL: wirelen solved = 29996, spread = 66330, legal = 80505; time = 0.38s
Info: at iteration #10, type ALL: wirelen solved = 31755, spread = 67387, legal = 80671; time = 0.42s
Info: at iteration #11, type ALL: wirelen solved = 33379, spread = 65525, legal = 81860; time = 0.41s
Info: at iteration #12, type ALL: wirelen solved = 33278, spread = 70894, legal = 81378; time = 0.37s
Info: at iteration #13, type ALL: wirelen solved = 36236, spread = 69967, legal = 82289; time = 0.40s
Info: at iteration #14, type ALL: wirelen solved = 36398, spread = 69855, legal = 79257; time = 0.38s
Info: at iteration #15, type ALL: wirelen solved = 36668, spread = 69679, legal = 79976; time = 0.37s
Info: at iteration #16, type ALL: wirelen solved = 36947, spread = 69358, legal = 81699; time = 0.42s
Info: at iteration #17, type ALL: wirelen solved = 37359, spread = 69559, legal = 80854; time = 0.45s
Info: at iteration #18, type ALL: wirelen solved = 37512, spread = 69640, legal = 79462; time = 0.42s
Info: at iteration #19, type ALL: wirelen solved = 37966, spread = 69563, legal = 81375; time = 0.36s
Info: HeAP Placer Time: 11.22s
Info: of which solving equations: 5.26s
Info: of which spreading cells: 0.86s
Info: of which strict legalisation: 2.52s
Info: Creating initial analytic placement for 8052 cells, random placement wirelen = 663954.
Info: at initial placer iter 0, wirelen = 3749
Info: at initial placer iter 1, wirelen = 3173
Info: at initial placer iter 2, wirelen = 3164
Info: at initial placer iter 3, wirelen = 3136
Info: Running main analytical placer, max placement attempts per cell = 26342911.
Info: at iteration #1, type ALL: wirelen solved = 2963, spread = 111636, legal = 128684; time = 0.50s
Info: at iteration #2, type ALL: wirelen solved = 12440, spread = 83755, legal = 101490; time = 0.44s
Info: at iteration #3, type ALL: wirelen solved = 19745, spread = 76361, legal = 93335; time = 0.46s
Info: at iteration #4, type ALL: wirelen solved = 24452, spread = 71046, legal = 91524; time = 0.49s
Info: at iteration #5, type ALL: wirelen solved = 26878, spread = 68386, legal = 85066; time = 0.45s
Info: at iteration #6, type ALL: wirelen solved = 28574, spread = 68128, legal = 82982; time = 0.38s
Info: at iteration #7, type ALL: wirelen solved = 30414, spread = 67496, legal = 82022; time = 0.48s
Info: at iteration #8, type ALL: wirelen solved = 30778, spread = 73178, legal = 82578; time = 0.43s
Info: at iteration #9, type ALL: wirelen solved = 34697, spread = 72000, legal = 84818; time = 0.46s
Info: at iteration #10, type ALL: wirelen solved = 34678, spread = 71929, legal = 86759; time = 0.43s
Info: at iteration #11, type ALL: wirelen solved = 35754, spread = 71018, legal = 84953; time = 0.40s
Info: at iteration #12, type ALL: wirelen solved = 35664, spread = 71787, legal = 85437; time = 0.38s
Info: HeAP Placer Time: 7.78s
Info: of which solving equations: 3.97s
Info: of which spreading cells: 0.55s
Info: of which strict legalisation: 1.71s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1040, wirelen = 79257
Info: at iteration #5: temp = 0.000000, timing cost = 1417, wirelen = 73531
Info: at iteration #10: temp = 0.000000, timing cost = 1327, wirelen = 72227
Info: at iteration #15: temp = 0.000000, timing cost = 1293, wirelen = 71777
Info: at iteration #20: temp = 0.000000, timing cost = 1276, wirelen = 71618
Info: at iteration #20: temp = 0.000000, timing cost = 1274, wirelen = 71620
Info: SA placement time 18.65s
Info: at iteration #1: temp = 0.000000, timing cost = 898, wirelen = 82022
Info: at iteration #5: temp = 0.000000, timing cost = 918, wirelen = 75863
Info: at iteration #10: temp = 0.000000, timing cost = 487, wirelen = 73239
Info: at iteration #15: temp = 0.000000, timing cost = 393, wirelen = 72618
Info: at iteration #20: temp = 0.000000, timing cost = 504, wirelen = 72360
Info: at iteration #25: temp = 0.000000, timing cost = 405, wirelen = 72257
Info: at iteration #28: temp = 0.000000, timing cost = 504, wirelen = 72219
Info: SA placement time 28.31s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 75.51 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 66.80 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.87 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.56 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.58 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.33 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 2382, 3016) |+
Info: [ 3016, 3650) |**+
Info: [ 3650, 4284) |*+
Info: [ 4284, 4918) |*****+
Info: [ 4918, 5552) |******+
Info: [ 5552, 6186) |******+
Info: [ 6186, 6820) |**********+
Info: [ 6820, 7454) |****************+
Info: [ 7454, 8088) |**********************+
Info: [ 8088, 8722) |*********************************+
Info: [ 8722, 9356) |****************************************+
Info: [ 9356, 9990) |***************************************+
Info: [ 9990, 10624) |*******************************+
Info: [ 10624, 11258) |*********************************+
Info: [ 11258, 11892) |************************************+
Info: [ 11892, 12526) |*****************************************+
Info: [ 12526, 13160) |************************************************************
Info: [ 13160, 13794) |**************************************************+
Info: [ 13794, 14428) |************************************************+
Info: [ 14428, 15062) |***********************************************+
Info: Checksum: 0x47624ea3
Info: legend: * represents 38 endpoint(s)
Info: + represents [1,38) endpoint(s)
Info: [ 656, 1376) |+
Info: [ 1376, 2096) |+
Info: [ 2096, 2816) |*+
Info: [ 2816, 3536) |+
Info: [ 3536, 4256) |*+
Info: [ 4256, 4976) |****+
Info: [ 4976, 5696) |*******+
Info: [ 5696, 6416) |*******+
Info: [ 6416, 7136) |********+
Info: [ 7136, 7856) |********+
Info: [ 7856, 8576) |**************+
Info: [ 8576, 9296) |*******************************+
Info: [ 9296, 10016) |**************************************+
Info: [ 10016, 10736) |***********************************************+
Info: [ 10736, 11456) |****************************************************+
Info: [ 11456, 12176) |*********************************************+
Info: [ 12176, 12896) |************************************************************
Info: [ 12896, 13616) |********************************************************+
Info: [ 13616, 14336) |*****************************************************+
Info: [ 14336, 15056) |******************************************************+
Info: Checksum: 0xcb1a3c0f
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39492 arcs.
Info: Routing 40919 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 467 532 | 467 532 | 39202| 1.40 1.40|
Info: 2000 | 912 1087 | 445 555 | 38943| 1.33 2.74|
Info: 3000 | 1149 1850 | 237 763 | 38329| 0.91 3.65|
Info: 4000 | 1446 2553 | 297 703 | 37724| 0.89 4.53|
Info: 5000 | 1551 3448 | 105 895 | 37030| 0.69 5.22|
Info: 6000 | 1710 4289 | 159 841 | 36379| 0.73 5.96|
Info: 7000 | 1854 5145 | 144 856 | 35862| 0.70 6.65|
Info: 8000 | 1972 6027 | 118 882 | 35082| 0.52 7.17|
Info: 9000 | 2075 6924 | 103 897 | 34229| 0.54 7.71|
Info: 10000 | 2163 7836 | 88 912 | 33479| 0.36 8.07|
Info: 11000 | 2284 8715 | 121 879 | 32836| 0.52 8.59|
Info: 12000 | 2390 9609 | 106 894 | 32100| 0.56 9.15|
Info: 13000 | 2526 10473 | 136 864 | 31477| 0.72 9.87|
Info: 14000 | 2646 11353 | 120 880 | 30686| 0.41 10.28|
Info: 15000 | 2764 12235 | 118 882 | 30078| 0.44 10.72|
Info: 16000 | 2915 13084 | 151 849 | 29314| 0.47 11.19|
Info: 17000 | 3034 13965 | 119 881 | 28507| 0.56 11.75|
Info: 18000 | 3185 14814 | 151 849 | 27768| 0.50 12.25|
Info: 19000 | 3353 15646 | 168 832 | 27312| 0.63 12.88|
Info: 20000 | 3565 16434 | 212 788 | 26725| 0.46 13.34|
Info: 21000 | 3774 17225 | 209 791 | 26155| 0.61 13.95|
Info: 22000 | 3928 18071 | 154 846 | 25470| 0.53 14.48|
Info: 23000 | 4104 18895 | 176 824 | 24798| 0.48 14.96|
Info: 24000 | 4337 19662 | 233 767 | 24245| 0.72 15.67|
Info: 25000 | 4569 20430 | 232 768 | 23629| 0.49 16.17|
Info: 26000 | 4811 21187 | 242 757 | 23075| 0.82 16.99|
Info: 27000 | 5024 21958 | 213 771 | 22355| 0.52 17.51|
Info: 28000 | 5280 22686 | 256 728 | 21901| 0.55 18.07|
Info: 29000 | 5530 23402 | 250 716 | 21449| 0.48 18.55|
Info: 30000 | 5780 24108 | 250 706 | 20761| 0.45 19.01|
Info: 31000 | 6041 24804 | 261 696 | 20236| 0.78 19.78|
Info: 32000 | 6299 25513 | 258 709 | 19727| 0.53 20.31|
Info: 33000 | 6597 26187 | 298 674 | 19150| 0.52 20.83|
Info: 34000 | 6927 26803 | 330 616 | 18571| 0.46 21.29|
Info: 35000 | 7155 27502 | 228 699 | 17936| 0.44 21.73|
Info: 36000 | 7399 28230 | 244 728 | 17291| 0.52 22.26|
Info: 37000 | 7579 28990 | 180 760 | 16650| 0.64 22.90|
Info: 38000 | 7786 29760 | 207 770 | 15898| 0.42 23.31|
Info: 39000 | 8018 30521 | 232 761 | 15658| 1.05 24.37|
Info: 40000 | 8220 31287 | 202 766 | 14959| 0.51 24.88|
Info: 41000 | 8411 32019 | 191 732 | 14324| 0.61 25.49|
Info: 42000 | 8626 32766 | 215 747 | 13722| 0.60 26.10|
Info: 43000 | 8825 33534 | 199 768 | 13078| 0.67 26.77|
Info: 44000 | 9046 34235 | 221 701 | 12430| 0.59 27.36|
Info: 45000 | 9239 34980 | 193 745 | 11787| 0.74 28.10|
Info: 46000 | 9457 35714 | 218 734 | 11155| 0.75 28.85|
Info: 47000 | 9693 36455 | 236 741 | 10723| 0.78 29.63|
Info: 48000 | 10007 37129 | 314 674 | 10394| 0.98 30.61|
Info: 49000 | 10136 37934 | 129 805 | 9605| 0.45 31.06|
Info: 50000 | 10290 38747 | 154 813 | 9031| 0.60 31.66|
Info: 51000 | 10515 39501 | 225 754 | 8493| 1.09 32.76|
Info: 52000 | 10707 40244 | 192 743 | 7805| 0.44 33.20|
Info: 53000 | 10840 41026 | 133 782 | 7092| 0.42 33.63|
Info: 54000 | 11004 41840 | 164 814 | 6474| 0.71 34.33|
Info: 55000 | 11253 42558 | 249 718 | 5947| 0.98 35.32|
Info: 56000 | 11376 43409 | 123 851 | 5136| 0.38 35.69|
Info: 57000 | 11651 44134 | 275 725 | 4795| 1.14 36.83|
Info: 58000 | 11906 44877 | 255 743 | 4203| 1.01 37.84|
Info: 59000 | 12103 45680 | 197 803 | 3515| 0.58 38.42|
Info: 60000 | 12435 46348 | 332 668 | 3210| 1.31 39.73|
Info: 61000 | 12778 47005 | 343 657 | 3020| 1.85 41.59|
Info: 62000 | 13090 47693 | 312 688 | 2495| 1.01 42.60|
Info: 63000 | 13246 48493 | 156 800 | 1722| 0.55 43.14|
Info: 64000 | 13425 49225 | 179 732 | 1333| 1.26 44.41|
Info: 65000 | 13645 49922 | 220 697 | 715| 0.97 45.37|
Info: 66000 | 13895 50593 | 250 671 | 238| 1.27 46.65|
Info: 66629 | 14073 50999 | 178 406 | 0| 0.72 47.36|
Info: 1000 | 428 571 | 428 571 | 40518| 2.06 2.06|
Info: 2000 | 745 1254 | 317 683 | 40011| 1.10 3.16|
Info: 3000 | 975 2024 | 230 770 | 39367| 0.84 4.01|
Info: 4000 | 1008 2991 | 33 967 | 38410| 0.68 4.68|
Info: 5000 | 1093 3906 | 85 915 | 37557| 0.41 5.09|
Info: 6000 | 1192 4807 | 99 901 | 36737| 0.42 5.51|
Info: 7000 | 1288 5711 | 96 904 | 35855| 0.33 5.84|
Info: 8000 | 1396 6603 | 108 892 | 35101| 0.45 6.29|
Info: 9000 | 1467 7532 | 71 929 | 34257| 0.36 6.65|
Info: 10000 | 1562 8437 | 95 905 | 33373| 0.32 6.97|
Info: 11000 | 1640 9359 | 78 922 | 32493| 0.36 7.33|
Info: 12000 | 1739 10260 | 99 901 | 31632| 0.36 7.69|
Info: 13000 | 1826 11173 | 87 913 | 30755| 0.53 8.22|
Info: 14000 | 1894 12105 | 68 932 | 29833| 0.36 8.58|
Info: 15000 | 2052 12947 | 158 842 | 29022| 0.35 8.93|
Info: 16000 | 2258 13741 | 206 794 | 28283| 0.36 9.30|
Info: 17000 | 2348 14651 | 90 910 | 27481| 0.38 9.68|
Info: 18000 | 2447 15552 | 99 901 | 26669| 0.39 10.07|
Info: 19000 | 2586 16411 | 139 859 | 25847| 0.42 10.49|
Info: 20000 | 2795 17201 | 209 790 | 25134| 0.42 10.91|
Info: 21000 | 2997 17997 | 202 796 | 24435| 0.47 11.38|
Info: 22000 | 3175 18818 | 178 821 | 23705| 0.45 11.83|
Info: 23000 | 3321 19667 | 146 849 | 22957| 0.44 12.27|
Info: 24000 | 3494 20477 | 173 810 | 22228| 0.54 12.81|
Info: 25000 | 3665 21272 | 171 795 | 21515| 0.46 13.27|
Info: 26000 | 3811 22059 | 146 787 | 20710| 0.60 13.87|
Info: 27000 | 3955 22824 | 144 765 | 19915| 0.42 14.28|
Info: 28000 | 4140 23571 | 185 747 | 19272| 0.49 14.77|
Info: 29000 | 4342 24310 | 202 739 | 18551| 0.54 15.31|
Info: 30000 | 4546 25033 | 204 723 | 17828| 0.42 15.74|
Info: 31000 | 4763 25755 | 217 722 | 17176| 0.50 16.24|
Info: 32000 | 4984 26493 | 221 738 | 16547| 0.63 16.86|
Info: 33000 | 5149 27272 | 165 779 | 15799| 0.52 17.39|
Info: 34000 | 5313 28046 | 164 774 | 15024| 0.55 17.94|
Info: 35000 | 5447 28839 | 134 793 | 14336| 0.51 18.45|
Info: 36000 | 5579 29664 | 132 825 | 13564| 0.66 19.11|
Info: 37000 | 5712 30456 | 133 792 | 12781| 0.46 19.57|
Info: 38000 | 5866 31235 | 154 779 | 12016| 0.50 20.07|
Info: 39000 | 6018 32026 | 152 791 | 11321| 0.67 20.75|
Info: 40000 | 6196 32794 | 178 768 | 10640| 0.63 21.38|
Info: 41000 | 6437 33505 | 241 711 | 10309| 1.21 22.59|
Info: 42000 | 6578 34314 | 141 809 | 9501| 0.42 23.00|
Info: 43000 | 6738 35104 | 160 790 | 8749| 0.57 23.57|
Info: 44000 | 6968 35829 | 230 725 | 8162| 0.93 24.51|
Info: 45000 | 7133 36610 | 165 781 | 7592| 0.60 25.11|
Info: 46000 | 7272 37416 | 139 806 | 6803| 0.48 25.59|
Info: 47000 | 7637 38043 | 365 627 | 6448| 1.33 26.92|
Info: 48000 | 8008 38672 | 371 629 | 6203| 1.23 28.15|
Info: 49000 | 8183 39457 | 175 785 | 5530| 1.14 29.28|
Info: 50000 | 8451 40182 | 268 725 | 4911| 0.75 30.03|
Info: 51000 | 8833 40800 | 382 618 | 4685| 1.47 31.50|
Info: 52000 | 9212 41421 | 379 621 | 4508| 1.75 33.25|
Info: 53000 | 9475 42153 | 263 732 | 4025| 0.70 33.94|
Info: 54000 | 9705 42923 | 230 770 | 3458| 0.99 34.93|
Info: 55000 | 10163 43465 | 458 542 | 3278| 1.68 36.61|
Info: 56000 | 10592 44036 | 429 571 | 3079| 1.51 38.11|
Info: 57000 | 10937 44691 | 345 655 | 2614| 1.02 39.13|
Info: 58000 | 11175 45448 | 238 757 | 1990| 0.60 39.73|
Info: 59000 | 11417 46115 | 242 667 | 1557| 1.06 40.78|
Info: 60000 | 11663 46776 | 246 661 | 1062| 1.04 41.82|
Info: 61000 | 11904 47434 | 241 658 | 533| 0.96 42.77|
Info: 61746 | 12017 47959 | 113 525 | 0| 0.68 43.46|
Info: Routing complete.
Info: Router1 time 47.36s
Info: Checksum: 0xc68b6218
Info: Router1 time 43.46s
Info: Checksum: 0x7f607a18
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.u_director.job_out_slot_TRELLIS_FF_Q.Q
Info: routing 0.92 1.32 Net u_dataflow_core.u_dep_mgr.node_producer_ids[1]_LUT4_C_Z_PFUMX_Z_C0[4] (26,39) -> (24,27)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[12]_LUT4_C_Z_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_LUT4_Z.D
Info: Defined in:
Info: hardware/v2/rtl/neural_director.v:73.39-73.51
Info: logic 0.18 1.50 Source u_dataflow_core.u_dep_mgr.node_state[12]_LUT4_C_Z_PFUMX_Z_1_C0_L6MUX21_Z_1_SD_LUT4_Z.F
Info: routing 1.25 2.74 Net u_dataflow_core.u_dep_mgr.node_state[12]_LUT4_C_Z_PFUMX_Z_1_C0_L6MUX21_Z_1_SD[4] (24,27) -> (26,40)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[27]_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_16.Q
Info: routing 1.12 1.51 Net u_arbiter_wide.m_addr[16] (30,4) -> (25,6)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_ALUT_LUT4_Z.B
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.94 Source u_dataflow_core.u_dep_mgr.node_producer_ids[27]_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 1.42 4.36 Net u_dataflow_core.u_dep_mgr.node_producer_ids[15]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_PFUMX_Z_C0_PFUMX_Z_BLUT_LUT4_Z_C[3] (26,40) -> (26,55)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.53 Source u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C.F
Info: routing 0.32 4.86 Net u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z[3] (26,55) -> (26,55)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.04 Source u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D.F
Info: routing 0.00 5.04 Net u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z (26,55) -> (26,55)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1
Info: logic 0.18 1.69 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_ALUT_LUT4_Z.F
Info: routing 0.00 1.69 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_ALUT (25,6) -> (25,6)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
Info: logic 0.13 5.16 Source u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
Info: routing 0.63 5.80 Net u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] (26,55) -> (26,56)
Info: Sink u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_D.A
Info: logic 0.13 1.82 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_BLUT_LUT4_Z.OFX
Info: routing 0.47 2.29 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z[2] (25,6) -> (27,6)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.98 Source u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_D.F
Info: routing 1.25 7.23 Net u_dataflow_core.u_dep_mgr.node_producer_ids[31]_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_D_Z[4] (26,56) -> (26,40)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: logic 0.18 2.46 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D.F
Info: routing 0.45 2.92 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z[3] (27,6) -> (27,6)
Info: Sink u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 7.42 Source u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.48 7.90 Net u_dataflow_core.u_dep_mgr.node_state[13]_TRELLIS_FF_Q_CE_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z[5] (26,40) -> (25,40)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A.M
Info: logic 0.18 3.10 Source u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.57 3.66 Net u_sdram_backend.w_cache_valid[3]_PFUMX_C0_Z_LUT4_D_Z_LUT4_D_Z[3] (27,6) -> (26,4)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 8.09 Source u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A.OFX
Info: routing 0.00 8.09 Net u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z (25,40) -> (25,40)
Info: Sink u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
Info: logic 0.18 8.27 Source u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.99 9.26 Net u_dataflow_core.u_dep_mgr.node_state[4]_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_D1_Z[2] (25,40) -> (27,35)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info: logic 0.18 3.85 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.74 5.58 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (26,4) -> (11,14)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.44 Source u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.69 10.13 Net u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_LSR (27,35) -> (27,31)
Info: Sink u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_2.LSR
Info: setup 0.29 10.42 Source u_dataflow_core.u_dep_mgr.node_resolved[6]_TRELLIS_FF_Q_2.LSR
Info: 2.47 ns logic, 7.95 ns routing
Info: logic 0.18 5.76 Source u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.22 6.98 Net u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (11,14) -> (16,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.16 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.17 7.33 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (16,7) -> (16,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 7.51 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.34 7.85 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (16,7) -> (16,7)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.03 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 2.17 10.20 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (16,7) -> (4,33)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.38 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.35 11.73 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (4,33) -> (5,13)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_2_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.91 Source u_sdram_backend.state_TRELLIS_FF_Q_2_DI_LUT4_Z.F
Info: routing 0.12 12.03 Net u_sdram_backend.state_TRELLIS_FF_Q_2_DI (5,13) -> (5,13)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_2.DI
Info: setup 0.00 12.03 Source u_sdram_backend.state_TRELLIS_FF_Q_2.DI
Info: 2.32 ns logic, 9.71 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 3.28 3.28 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (12,9)
Info: routing 3.43 3.43 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (14,8)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.46 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.78 4.24 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D[2] (12,9) -> (12,9)
Info: logic 0.18 3.61 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.51 4.12 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z_D[2] (14,8) -> (14,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.43 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.F
Info: routing 0.12 4.54 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI (12,9) -> (12,9)
Info: logic 0.18 4.30 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI_LUT4_Z.F
Info: routing 0.12 4.42 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35_DI (14,9) -> (14,9)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: setup 0.00 4.54 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: 0.36 ns logic, 4.18 ns routing
Info: setup 0.00 4.42 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_35.DI
Info: 0.36 ns logic, 4.06 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 0.91 1.31 Net u_spi_bridge.byte_idx[3] (21,33) -> (21,32)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.C
Info: routing 0.86 1.26 Net u_spi_bridge.byte_idx[3] (22,43) -> (20,42)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.49 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.47 1.96 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (21,32) -> (21,32)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 1.44 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.63 2.07 Net u_dataflow_core.reg_result_addr_TRELLIS_FF_Q_CE_LUT4_Z_C[0] (20,42) -> (20,42)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.14 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.87 4.01 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (21,32) -> (14,57)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: logic 0.18 2.24 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.F
Info: routing 1.46 3.71 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (20,42) -> (16,50)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.19 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.67 4.86 Net spi_miso_LUT4_Z_B[2] (14,57) -> (17,57)
Info: logic 0.18 3.89 Source spi_miso_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.31 4.20 Net spi_miso_LUT4_Z_B[2] (16,50) -> (16,50)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.03 Source spi_miso_LUT4_Z.F
Info: routing 1.60 6.64 Net spi_miso$TRELLIS_IO_OUT (17,57) -> (0,62)
Info: logic 0.18 4.38 Source spi_miso_LUT4_Z.F
Info: routing 1.74 6.12 Net spi_miso$TRELLIS_IO_OUT (16,50) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.52 ns routing
Info: 1.12 ns logic, 5.00 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 96.01 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 83.14 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.54 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.64 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.42 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.12 ns
Info: Slack histogram:
Info: legend: * represents 33 endpoint(s)
Info: + represents [1,33) endpoint(s)
Info: [ 5209, 5695) |+
Info: [ 5695, 6181) |**+
Info: [ 6181, 6667) |****+
Info: [ 6667, 7153) |*****+
Info: [ 7153, 7639) |********+
Info: [ 7639, 8125) |********+
Info: [ 8125, 8611) |********+
Info: [ 8611, 9097) |************+
Info: [ 9097, 9583) |*****************+
Info: [ 9583, 10069) |*************************+
Info: [ 10069, 10555) |************************************+
Info: [ 10555, 11041) |********************************************+
Info: [ 11041, 11527) |*********************************************+
Info: [ 11527, 12013) |*************************************+
Info: [ 12013, 12499) |********************************************+
Info: [ 12499, 12985) |**********************************************+
Info: [ 12985, 13471) |*******************************************************+
Info: [ 13471, 13957) |********************************************************+
Info: [ 13957, 14443) |************************************************************
Info: [ 14443, 14929) |*************************************************+
Info: legend: * represents 41 endpoint(s)
Info: + represents [1,41) endpoint(s)
Info: [ 3597, 4164) |+
Info: [ 4164, 4731) |
Info: [ 4731, 5298) |+
Info: [ 5298, 5865) |*+
Info: [ 5865, 6432) |***+
Info: [ 6432, 6999) |***+
Info: [ 6999, 7566) |*****+
Info: [ 7566, 8133) |*******+
Info: [ 8133, 8700) |**********+
Info: [ 8700, 9267) |*********+
Info: [ 9267, 9834) |***********+
Info: [ 9834, 10401) |*********************+
Info: [ 10401, 10968) |*****************************+
Info: [ 10968, 11535) |****************************************+
Info: [ 11535, 12102) |***********************************************+
Info: [ 12102, 12669) |******************************************************+
Info: [ 12669, 13236) |*******************************************************+
Info: [ 13236, 13803) |*****************************************************+
Info: [ 13803, 14370) |************************************************************
Info: [ 14370, 14937) |************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/nextpnr_seed7.log
+230 -215
View File
@@ -1,13 +1,13 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6905/43848 15%
Info: logic LUTs: 4251/43848 9%
Info: carry LUTs: 1484/43848 3%
Info: Total LUT4s: 7262/43848 16%
Info: logic LUTs: 4612/43848 10%
Info: carry LUTs: 1480/43848 3%
Info: RAM LUTs: 780/ 5481 14%
Info: RAMW LUTs: 390/10962 3%
Info: Total DFFs: 6527/43848 14%
Info: Total DFFs: 6529/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
@@ -36,11 +36,11 @@ Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
@@ -79,13 +79,13 @@ Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2367 FFs paired with LUTs.
Info: 2373 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x53454a1f
Info: Checksum: 0xa739669a
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
@@ -113,282 +113,297 @@ Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6527/ 43848 14%
Info: TRELLIS_COMB: 7363/ 43848 16%
Info: TRELLIS_FF: 6529/ 43848 14%
Info: TRELLIS_COMB: 7712/ 43848 17%
Info: TRELLIS_RAMW: 195/ 5481 3%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 8044 cells, random placement wirelen = 659893.
Info: at initial placer iter 0, wirelen = 3804
Info: at initial placer iter 1, wirelen = 3418
Info: at initial placer iter 2, wirelen = 3166
Info: at initial placer iter 3, wirelen = 3156
Info: Running main analytical placer, max placement attempts per cell = 25084444.
Info: at iteration #1, type ALL: wirelen solved = 3096, spread = 111406, legal = 125486; time = 0.53s
Info: at iteration #2, type ALL: wirelen solved = 12698, spread = 81233, legal = 97847; time = 0.52s
Info: at iteration #3, type ALL: wirelen solved = 19122, spread = 72009, legal = 88536; time = 0.50s
Info: at iteration #4, type ALL: wirelen solved = 22864, spread = 67327, legal = 85354; time = 0.44s
Info: at iteration #5, type ALL: wirelen solved = 24628, spread = 65589, legal = 80927; time = 0.39s
Info: at iteration #6, type ALL: wirelen solved = 25853, spread = 65011, legal = 81238; time = 0.46s
Info: at iteration #7, type ALL: wirelen solved = 27382, spread = 63244, legal = 79647; time = 0.46s
Info: at iteration #8, type ALL: wirelen solved = 28170, spread = 63034, legal = 79694; time = 0.40s
Info: at iteration #9, type ALL: wirelen solved = 28883, spread = 63060, legal = 80527; time = 0.41s
Info: at iteration #10, type ALL: wirelen solved = 29696, spread = 62909, legal = 81324; time = 0.44s
Info: at iteration #11, type ALL: wirelen solved = 30752, spread = 62896, legal = 80283; time = 0.43s
Info: at iteration #12, type ALL: wirelen solved = 31448, spread = 62563, legal = 81569; time = 0.43s
Info: HeAP Placer Time: 7.93s
Info: of which solving equations: 3.95s
Info: of which spreading cells: 0.52s
Info: of which strict legalisation: 1.85s
Info: Creating initial analytic placement for 8052 cells, random placement wirelen = 655402.
Info: at initial placer iter 0, wirelen = 4352
Info: at initial placer iter 1, wirelen = 3373
Info: at initial placer iter 2, wirelen = 3272
Info: at initial placer iter 3, wirelen = 3106
Info: Running main analytical placer, max placement attempts per cell = 26342911.
Info: at iteration #1, type ALL: wirelen solved = 2986, spread = 116509, legal = 129027; time = 0.49s
Info: at iteration #2, type ALL: wirelen solved = 13026, spread = 90128, legal = 101117; time = 0.44s
Info: at iteration #3, type ALL: wirelen solved = 20231, spread = 78566, legal = 93711; time = 0.41s
Info: at iteration #4, type ALL: wirelen solved = 24652, spread = 77002, legal = 91892; time = 0.45s
Info: at iteration #5, type ALL: wirelen solved = 28863, spread = 71958, legal = 87641; time = 0.53s
Info: at iteration #6, type ALL: wirelen solved = 30241, spread = 70980, legal = 86437; time = 0.46s
Info: at iteration #7, type ALL: wirelen solved = 31453, spread = 69695, legal = 88889; time = 0.54s
Info: at iteration #8, type ALL: wirelen solved = 32839, spread = 68983, legal = 86183; time = 0.55s
Info: at iteration #9, type ALL: wirelen solved = 33202, spread = 72479, legal = 89122; time = 0.44s
Info: at iteration #10, type ALL: wirelen solved = 36157, spread = 72704, legal = 88127; time = 0.43s
Info: at iteration #11, type ALL: wirelen solved = 36930, spread = 71849, legal = 86177; time = 0.38s
Info: at iteration #12, type ALL: wirelen solved = 36975, spread = 71521, legal = 87196; time = 0.43s
Info: at iteration #13, type ALL: wirelen solved = 37233, spread = 71600, legal = 86927; time = 0.38s
Info: at iteration #14, type ALL: wirelen solved = 37650, spread = 71699, legal = 86881; time = 0.46s
Info: at iteration #15, type ALL: wirelen solved = 38503, spread = 71597, legal = 85590; time = 0.45s
Info: at iteration #16, type ALL: wirelen solved = 38948, spread = 73112, legal = 85701; time = 0.36s
Info: at iteration #17, type ALL: wirelen solved = 39571, spread = 73293, legal = 86189; time = 0.39s
Info: at iteration #18, type ALL: wirelen solved = 39846, spread = 73423, legal = 86090; time = 0.41s
Info: at iteration #19, type ALL: wirelen solved = 40442, spread = 74377, legal = 86387; time = 0.38s
Info: at iteration #20, type ALL: wirelen solved = 41251, spread = 74674, legal = 88958; time = 0.42s
Info: HeAP Placer Time: 12.20s
Info: of which solving equations: 5.70s
Info: of which spreading cells: 0.97s
Info: of which strict legalisation: 2.81s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1276, wirelen = 79647
Info: at iteration #5: temp = 0.000000, timing cost = 1232, wirelen = 73781
Info: at iteration #10: temp = 0.000000, timing cost = 1417, wirelen = 71986
Info: at iteration #15: temp = 0.000000, timing cost = 1243, wirelen = 71482
Info: at iteration #20: temp = 0.000000, timing cost = 1359, wirelen = 71286
Info: at iteration #25: temp = 0.000000, timing cost = 1211, wirelen = 71193
Info: at iteration #28: temp = 0.000000, timing cost = 1385, wirelen = 71165
Info: SA placement time 25.66s
Info: at iteration #1: temp = 0.000000, timing cost = 1321, wirelen = 85590
Info: at iteration #5: temp = 0.000000, timing cost = 601, wirelen = 78831
Info: at iteration #10: temp = 0.000000, timing cost = 647, wirelen = 76440
Info: at iteration #15: temp = 0.000000, timing cost = 632, wirelen = 75732
Info: at iteration #20: temp = 0.000000, timing cost = 638, wirelen = 75524
Info: at iteration #25: temp = 0.000000, timing cost = 656, wirelen = 75439
Info: at iteration #26: temp = 0.000000, timing cost = 636, wirelen = 75427
Info: SA placement time 25.43s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 75.96 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 70.62 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.45 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.99 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.27 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.39 ns
Info: Slack histogram:
Info: legend: * represents 37 endpoint(s)
Info: + represents [1,37) endpoint(s)
Info: [ 2460, 3090) |+
Info: [ 3090, 3720) |*+
Info: [ 3720, 4350) |*+
Info: [ 4350, 4980) |****+
Info: [ 4980, 5610) |*****+
Info: [ 5610, 6240) |*********+
Info: [ 6240, 6870) |********+
Info: [ 6870, 7500) |********+
Info: [ 7500, 8130) |*******************+
Info: [ 8130, 8760) |**************************+
Info: [ 8760, 9390) |***********************************+
Info: [ 9390, 10020) |****************************************+
Info: [ 10020, 10650) |**************************************+
Info: [ 10650, 11280) |********************************+
Info: [ 11280, 11910) |****************************+
Info: [ 11910, 12540) |***********************************+
Info: [ 12540, 13170) |*******************************************************+
Info: [ 13170, 13800) |************************************************************
Info: [ 13800, 14430) |********************************************+
Info: [ 14430, 15060) |*********************************************+
Info: Checksum: 0xb2c62bb6
Info: [ 1464, 2144) |+
Info: [ 2144, 2824) |+
Info: [ 2824, 3504) |*+
Info: [ 3504, 4184) |**+
Info: [ 4184, 4864) |****+
Info: [ 4864, 5544) |*****+
Info: [ 5544, 6224) |******+
Info: [ 6224, 6904) |*******+
Info: [ 6904, 7584) |**********+
Info: [ 7584, 8264) |*****************+
Info: [ 8264, 8944) |*******************************+
Info: [ 8944, 9624) |***********************************+
Info: [ 9624, 10304) |*********************************************+
Info: [ 10304, 10984) |**************************************************+
Info: [ 10984, 11664) |*****************************************+
Info: [ 11664, 12344) |****************************************+
Info: [ 12344, 13024) |*******************************************+
Info: [ 13024, 13704) |**********************************************************+
Info: [ 13704, 14384) |************************************************************
Info: [ 14384, 15064) |***************************************+
Info: Checksum: 0xafbfcd91
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 39305 arcs.
Info: Routing 41089 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 648 351 | 648 351 | 39084| 1.56 1.56|
Info: 2000 | 1167 832 | 519 481 | 38773| 1.32 2.89|
Info: 3000 | 1508 1491 | 341 659 | 38348| 1.39 4.28|
Info: 4000 | 1776 2223 | 268 732 | 37825| 1.24 5.52|
Info: 5000 | 1933 3066 | 157 843 | 37141| 0.57 6.09|
Info: 6000 | 2046 3953 | 113 887 | 36364| 0.53 6.61|
Info: 7000 | 2154 4845 | 108 892 | 35523| 0.37 6.98|
Info: 8000 | 2242 5757 | 88 912 | 34666| 0.46 7.45|
Info: 9000 | 2353 6646 | 111 889 | 33869| 0.37 7.82|
Info: 10000 | 2467 7532 | 114 886 | 33075| 0.48 8.30|
Info: 11000 | 2565 8434 | 98 902 | 32276| 0.38 8.68|
Info: 12000 | 2635 9364 | 70 930 | 31392| 0.43 9.11|
Info: 13000 | 2740 10259 | 105 895 | 30571| 0.34 9.45|
Info: 14000 | 2870 11129 | 130 870 | 29863| 0.39 9.85|
Info: 15000 | 3002 11997 | 132 868 | 29118| 0.50 10.35|
Info: 16000 | 3156 12843 | 154 846 | 28398| 0.37 10.71|
Info: 17000 | 3277 13722 | 121 879 | 27645| 0.39 11.10|
Info: 18000 | 3533 14466 | 256 744 | 27197| 1.65 12.74|
Info: 19000 | 3640 15359 | 107 893 | 26361| 0.38 13.13|
Info: 20000 | 3782 16217 | 142 858 | 25694| 0.35 13.48|
Info: 21000 | 4023 16976 | 241 759 | 25023| 0.44 13.92|
Info: 22000 | 4192 17807 | 169 831 | 24385| 0.39 14.31|
Info: 23000 | 4368 18628 | 176 821 | 23684| 0.48 14.79|
Info: 24000 | 4641 19348 | 273 720 | 23194| 0.56 15.35|
Info: 25000 | 4875 20098 | 234 750 | 22651| 0.35 15.71|
Info: 26000 | 5157 20794 | 282 696 | 22122| 0.46 16.17|
Info: 27000 | 5477 21431 | 320 637 | 21521| 0.46 16.63|
Info: 28000 | 5754 22117 | 277 686 | 20895| 0.38 17.00|
Info: 29000 | 5986 22841 | 232 724 | 20214| 0.42 17.42|
Info: 30000 | 6241 23555 | 255 714 | 19612| 0.49 17.92|
Info: 31000 | 6507 24270 | 266 715 | 19013| 0.44 18.36|
Info: 32000 | 6746 25011 | 239 741 | 18362| 0.58 18.93|
Info: 33000 | 7019 25697 | 273 686 | 17785| 0.53 19.47|
Info: 34000 | 7256 26401 | 237 704 | 17265| 0.54 20.01|
Info: 35000 | 7496 27097 | 240 696 | 16642| 0.60 20.61|
Info: 36000 | 7752 27808 | 256 711 | 16088| 0.74 21.35|
Info: 37000 | 7982 28527 | 230 719 | 15452| 0.53 21.87|
Info: 38000 | 8191 29261 | 209 734 | 14842| 0.65 22.52|
Info: 39000 | 8350 30037 | 159 776 | 14120| 0.57 23.09|
Info: 40000 | 8514 30839 | 164 802 | 13616| 0.66 23.75|
Info: 41000 | 8687 31639 | 173 800 | 13031| 0.57 24.32|
Info: 42000 | 8841 32408 | 154 769 | 12413| 0.59 24.90|
Info: 43000 | 8993 33207 | 152 799 | 11666| 0.66 25.56|
Info: 44000 | 9216 33950 | 223 743 | 11003| 0.60 26.17|
Info: 45000 | 9495 34651 | 279 701 | 10555| 1.06 27.23|
Info: 46000 | 9683 35402 | 188 751 | 9884| 0.59 27.82|
Info: 47000 | 9832 36197 | 149 795 | 9127| 0.47 28.29|
Info: 48000 | 10182 36823 | 350 626 | 8676| 1.01 29.30|
Info: 49000 | 10313 37608 | 131 785 | 7869| 0.31 29.61|
Info: 50000 | 10454 38412 | 141 804 | 7160| 0.41 30.02|
Info: 51000 | 10638 39205 | 184 793 | 6485| 0.71 30.73|
Info: 52000 | 10861 39962 | 223 757 | 5850| 0.81 31.54|
Info: 53000 | 10995 40790 | 134 828 | 5111| 0.40 31.94|
Info: 54000 | 11420 41365 | 425 575 | 4836| 1.02 32.97|
Info: 55000 | 11741 42044 | 321 679 | 4570| 1.09 34.05|
Info: 56000 | 12032 42751 | 291 707 | 4094| 1.12 35.18|
Info: 57000 | 12275 43508 | 243 757 | 3475| 0.74 35.91|
Info: 58000 | 12694 44089 | 419 581 | 3248| 1.32 37.23|
Info: 59000 | 13098 44685 | 404 596 | 3240| 1.57 38.80|
Info: 60000 | 13504 45279 | 406 594 | 3019| 1.44 40.24|
Info: 61000 | 13859 45924 | 355 645 | 2674| 0.97 41.21|
Info: 62000 | 14148 46635 | 289 711 | 2496| 0.98 42.19|
Info: 63000 | 14432 47348 | 284 713 | 1948| 0.61 42.80|
Info: 64000 | 14664 48081 | 232 733 | 1743| 0.77 43.57|
Info: 65000 | 14811 48801 | 147 720 | 992| 0.66 44.23|
Info: 66000 | 15036 49482 | 225 681 | 476| 0.97 45.20|
Info: 66865 | 15175 50133 | 139 651 | 0| 0.67 45.87|
Info: 1000 | 486 513 | 486 513 | 40727| 1.66 1.66|
Info: 2000 | 776 1223 | 290 710 | 40169| 0.93 2.58|
Info: 3000 | 954 2045 | 178 822 | 39483| 0.69 3.27|
Info: 4000 | 1088 2911 | 134 866 | 38704| 0.71 3.99|
Info: 5000 | 1260 3739 | 172 828 | 37971| 0.62 4.61|
Info: 6000 | 1333 4666 | 73 927 | 37056| 0.45 5.06|
Info: 7000 | 1384 5615 | 51 949 | 36148| 0.40 5.46|
Info: 8000 | 1463 6536 | 79 921 | 35287| 0.44 5.89|
Info: 9000 | 1560 7439 | 97 903 | 34438| 0.41 6.30|
Info: 10000 | 1632 8367 | 72 928 | 33536| 0.36 6.66|
Info: 11000 | 1725 9274 | 93 907 | 32742| 0.39 7.06|
Info: 12000 | 1832 10167 | 107 893 | 31942| 0.46 7.52|
Info: 13000 | 1932 11067 | 100 900 | 31125| 0.39 7.90|
Info: 14000 | 2082 11917 | 150 850 | 30415| 0.38 8.29|
Info: 15000 | 2238 12761 | 156 844 | 29652| 0.55 8.84|
Info: 16000 | 2372 13627 | 134 866 | 28891| 0.45 9.29|
Info: 17000 | 2520 14479 | 148 852 | 28180| 0.44 9.72|
Info: 18000 | 2691 15308 | 171 829 | 27424| 0.35 10.07|
Info: 19000 | 2839 16160 | 148 852 | 26676| 0.53 10.61|
Info: 20000 | 3006 16993 | 167 833 | 26084| 0.57 11.18|
Info: 21000 | 3178 17821 | 172 828 | 25449| 0.71 11.89|
Info: 22000 | 3413 18585 | 235 764 | 25193| 0.71 12.60|
Info: 23000 | 3694 19301 | 281 716 | 24609| 0.47 13.07|
Info: 24000 | 3956 20036 | 262 735 | 23944| 0.46 13.53|
Info: 25000 | 4167 20820 | 211 784 | 23265| 0.50 14.03|
Info: 26000 | 4334 21641 | 167 821 | 22649| 0.47 14.50|
Info: 27000 | 4497 22459 | 163 818 | 21894| 0.45 14.95|
Info: 28000 | 4712 23194 | 215 735 | 21372| 0.65 15.60|
Info: 29000 | 4924 23917 | 212 723 | 20676| 0.51 16.11|
Info: 30000 | 5160 24606 | 236 689 | 19988| 0.43 16.54|
Info: 31000 | 5357 25333 | 197 727 | 19300| 0.48 17.02|
Info: 32000 | 5579 26040 | 222 707 | 18698| 0.55 17.56|
Info: 33000 | 5765 26799 | 186 759 | 17973| 0.45 18.01|
Info: 34000 | 5957 27532 | 192 733 | 17314| 0.53 18.55|
Info: 35000 | 6172 28287 | 215 755 | 16862| 0.72 19.27|
Info: 36000 | 6386 29045 | 214 758 | 16391| 0.53 19.80|
Info: 37000 | 6587 29807 | 201 762 | 15677| 0.50 20.30|
Info: 38000 | 6793 30580 | 206 773 | 15101| 0.58 20.89|
Info: 39000 | 6953 31367 | 160 787 | 14451| 0.49 21.37|
Info: 40000 | 7092 32171 | 139 804 | 13672| 0.44 21.81|
Info: 41000 | 7278 32924 | 186 753 | 13052| 0.67 22.48|
Info: 42000 | 7482 33667 | 204 743 | 12515| 0.67 23.15|
Info: 43000 | 7686 34393 | 204 726 | 11951| 0.76 23.91|
Info: 44000 | 7846 35200 | 160 807 | 11286| 0.86 24.77|
Info: 45000 | 7997 35985 | 151 785 | 10546| 0.74 25.51|
Info: 46000 | 8174 36780 | 177 795 | 9861| 0.91 26.41|
Info: 47000 | 8271 37623 | 97 843 | 9076| 0.33 26.74|
Info: 48000 | 8538 38333 | 267 710 | 8555| 0.72 27.46|
Info: 49000 | 8875 38992 | 337 659 | 8352| 1.17 28.63|
Info: 50000 | 9275 39583 | 400 591 | 8057| 1.30 29.92|
Info: 51000 | 9383 40349 | 108 766 | 7195| 0.33 30.25|
Info: 52000 | 9563 41111 | 180 762 | 6501| 0.65 30.90|
Info: 53000 | 9900 41774 | 337 663 | 6317| 1.15 32.05|
Info: 54000 | 10135 42505 | 235 731 | 5757| 0.83 32.88|
Info: 55000 | 10359 43281 | 224 776 | 5256| 0.71 33.59|
Info: 56000 | 10668 43963 | 309 682 | 4849| 1.14 34.73|
Info: 57000 | 11128 44503 | 460 540 | 4675| 1.39 36.13|
Info: 58000 | 11391 45237 | 263 734 | 4119| 0.91 37.03|
Info: 59000 | 11585 46043 | 194 806 | 3464| 0.55 37.58|
Info: 60000 | 11965 46663 | 380 620 | 3171| 1.27 38.85|
Info: 61000 | 12399 47229 | 434 566 | 3071| 1.39 40.24|
Info: 62000 | 12822 47806 | 423 577 | 2776| 1.42 41.67|
Info: 63000 | 13089 48539 | 267 733 | 2199| 0.63 42.30|
Info: 64000 | 13326 49243 | 237 704 | 1668| 0.88 43.18|
Info: 65000 | 13506 49934 | 180 691 | 1026| 0.71 43.89|
Info: 66000 | 13693 50646 | 187 712 | 555| 0.89 44.78|
Info: 66688 | 13787 51131 | 94 485 | 0| 0.42 45.20|
Info: Routing complete.
Info: Router1 time 45.87s
Info: Checksum: 0xc233a902
Info: Router1 time 45.20s
Info: Checksum: 0xe13af220
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_sdram_backend.w_cache_addr[2]_TRELLIS_FF_Q_19.Q
Info: routing 0.87 1.26 Net u_sdram_backend.w_cache_addr[2][19] (24,3) -> (24,3)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z_2.D
Info: logic 0.18 1.44 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z_D_LUT4_Z_2.F
Info: routing 0.60 2.04 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z_D[1] (24,3) -> (24,3)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z.B
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_8.Q
Info: routing 0.67 1.06 Net u_arbiter_wide.m_addr[8] (26,7) -> (26,6)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.24 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_D_LUT4_Z.F
Info: routing 0.37 1.61 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_D[3] (26,6) -> (26,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.22 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z.F
Info: routing 0.85 3.07 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2_D[3] (24,3) -> (23,2)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2.D
Info: logic 0.18 1.79 Source u_sdram_backend.w_cache_valid[2]_LUT4_B.F
Info: routing 0.54 2.32 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z[2] (26,5) -> (26,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.25 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z_2.F
Info: routing 0.60 3.85 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[2] (23,2) -> (23,2)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.C
Info: logic 0.18 2.50 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D.F
Info: routing 0.16 2.66 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z[3] (26,5) -> (26,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.03 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 1.28 5.32 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[1] (23,2) -> (13,6)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: logic 0.18 2.84 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.76 3.60 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z[3] (26,5) -> (25,3)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.50 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.80 6.30 Net u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_PFUMX_BLUT_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (13,6) -> (18,5)
Info: logic 0.18 3.78 Source u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 1.28 5.06 Net u_sdram_backend.w_cache_valid[2]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[0] (25,3) -> (13,11)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.24 Source u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.06 6.30 Net u_sdram_backend.w_cache_valid[0]_LUT4_B_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (13,11) -> (21,6)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.48 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.48 6.95 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (18,5) -> (18,5)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.C
Info: logic 0.18 6.47 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.03 6.51 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (21,6) -> (21,6)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 7.13 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.34 7.47 Net u_host_arb.m_wr_LUT4_C_Z_LUT4_Z_C[0] (18,5) -> (18,5)
Info: Sink u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.C
Info: logic 0.18 6.69 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.82 7.51 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (21,6) -> (10,6)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.65 Source u_host_arb.m_wr_LUT4_C_Z_LUT4_Z.F
Info: routing 1.81 9.46 Net u_host_arb.m_wr_LUT4_C_Z[3] (18,5) -> (7,21)
Info: Sink u_sdram_backend.ar_req_pending_LUT4_B.D
Info: logic 0.18 7.69 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 1.65 9.34 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (10,6) -> (10,35)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.64 Source u_sdram_backend.ar_req_pending_LUT4_B.F
Info: routing 1.11 10.75 Net u_sdram_backend.ar_req_pending_LUT4_B_Z[3] (7,21) -> (10,4)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.D
Info: logic 0.18 9.52 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.26 10.78 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (10,35) -> (11,21)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_2_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.93 Source u_sdram_backend.state_TRELLIS_FF_Q_3_DI_LUT4_Z.F
Info: routing 0.12 11.04 Net u_sdram_backend.state_TRELLIS_FF_Q_3_DI (10,4) -> (10,4)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: setup 0.00 11.04 Source u_sdram_backend.state_TRELLIS_FF_Q_3.DI
Info: 2.19 ns logic, 8.85 ns routing
Info: logic 0.18 10.96 Source u_sdram_backend.state_TRELLIS_FF_Q_2_DI_LUT4_Z.F
Info: routing 0.12 11.07 Net u_sdram_backend.state_TRELLIS_FF_Q_2_DI (11,21) -> (11,21)
Info: Sink u_sdram_backend.state_TRELLIS_FF_Q_2.DI
Info: setup 0.00 11.07 Source u_sdram_backend.state_TRELLIS_FF_Q_2.DI
Info: 2.38 ns logic, 8.70 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[2]$tr_io.O
Info: routing 3.35 3.35 Net sdram_dq[2]$TRELLIS_IO_IN (0,29) -> (15,4)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D_LUT4_Z.C
Info: routing 3.02 3.02 Net sdram_dq[2]$TRELLIS_IO_IN (0,29) -> (14,15)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.53 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.63 4.16 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D[2] (15,4) -> (17,4)
Info: logic 0.18 3.20 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.33 3.53 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z_D[2] (14,15) -> (14,15)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.34 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z.F
Info: routing 0.12 4.46 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI (17,4) -> (17,4)
Info: logic 0.18 3.71 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI_LUT4_Z.F
Info: routing 0.12 3.83 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50_DI (14,15) -> (14,15)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50.DI
Info: setup 0.00 4.46 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50.DI
Info: 0.36 ns logic, 4.10 ns routing
Info: setup 0.00 3.83 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_50.DI
Info: 0.36 ns logic, 3.46 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 0.99 1.39 Net u_spi_bridge.byte_idx[3] (25,33) -> (25,26)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.C
Info: routing 0.85 1.25 Net u_spi_bridge.byte_idx[3] (19,50) -> (18,49)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.57 Source u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C_LUT4_Z.F
Info: routing 0.65 2.22 Net u_spi_bridge.state_TRELLIS_FF_Q_2_DI_LUT4_Z_B_LUT4_Z_C[3] (25,26) -> (24,26)
Info: Sink u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: logic 0.18 1.43 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.48 1.90 Net u_dataflow_core.reg_result_addr_TRELLIS_FF_Q_CE_LUT4_Z_C[0] (18,49) -> (18,49)
Info: Sink u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.40 Source u_spi_bridge.state_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_B_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 2.01 4.41 Net spi_miso_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_C0_PFUMX_Z_C0[3] (24,26) -> (16,45)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z.D
Info: logic 0.18 2.08 Source u_spi_bridge.rx_valid_LUT4_D_Z_LUT4_Z_D_LUT4_Z_D_LUT4_D.F
Info: routing 1.11 3.19 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (18,49) -> (13,53)
Info: Sink spi_miso_LUT4_Z_C_LUT4_Z_1.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.59 Source spi_miso_LUT4_Z_C_LUT4_Z.F
Info: routing 0.50 5.09 Net spi_miso_LUT4_Z_B[2] (16,45) -> (17,45)
Info: logic 0.18 3.37 Source spi_miso_LUT4_Z_C_LUT4_Z_1.F
Info: routing 0.47 3.84 Net spi_miso_LUT4_Z_B[2] (13,53) -> (14,57)
Info: Sink spi_miso_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.27 Source spi_miso_LUT4_Z.F
Info: routing 2.06 7.33 Net spi_miso$TRELLIS_IO_OUT (17,45) -> (0,62)
Info: logic 0.18 4.02 Source spi_miso_LUT4_Z.F
Info: routing 1.56 5.59 Net spi_miso$TRELLIS_IO_OUT (14,57) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 6.21 ns routing
Info: 1.12 ns logic, 4.47 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 90.55 MHz (PASS at 64.00 MHz)
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 90.29 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.46 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.33 ns
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 3.83 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 5.59 ns
Info: Slack histogram:
Info: legend: * represents 42 endpoint(s)
Info: + represents [1,42) endpoint(s)
Info: [ 4581, 5098) |+
Info: [ 5098, 5615) |+
Info: [ 5615, 6132) |**+
Info: [ 6132, 6649) |**+
Info: [ 6649, 7166) |******+
Info: [ 7166, 7683) |******+
Info: [ 7683, 8200) |*******+
Info: [ 8200, 8717) |*******+
Info: [ 8717, 9234) |***********+
Info: [ 9234, 9751) |***************+
Info: [ 9751, 10268) |*********************+
Info: [ 10268, 10785) |**********************************+
Info: [ 10785, 11302) |**************************************+
Info: [ 11302, 11819) |***********************************+
Info: [ 11819, 12336) |***********************************+
Info: [ 12336, 12853) |*****************************+
Info: [ 12853, 13370) |***************************************+
Info: [ 13370, 13887) |************************************************************
Info: [ 13887, 14404) |*************************************************+
Info: [ 14404, 14921) |******************************************+
Info: legend: * represents 38 endpoint(s)
Info: + represents [1,38) endpoint(s)
Info: [ 4550, 5069) |+
Info: [ 5069, 5588) |+
Info: [ 5588, 6107) |+
Info: [ 6107, 6626) |***+
Info: [ 6626, 7145) |*****+
Info: [ 7145, 7664) |********+
Info: [ 7664, 8183) |*******+
Info: [ 8183, 8702) |********+
Info: [ 8702, 9221) |***********+
Info: [ 9221, 9740) |*****************+
Info: [ 9740, 10259) |***************************+
Info: [ 10259, 10778) |************************************+
Info: [ 10778, 11297) |****************************************+
Info: [ 11297, 11816) |************************************************+
Info: [ 11816, 12335) |*****************************************+
Info: [ 12335, 12854) |***************************************+
Info: [ 12854, 13373) |****************************************+
Info: [ 13373, 13892) |***********************************************+
Info: [ 13892, 14411) |************************************************************
Info: [ 14411, 14930) |*********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n4/top.config
+181676 -177276
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hardware/v2/nms/synthesis/nms_multiproc_n4/top.json
+177047 -155418
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hardware/v2/nms/synthesis/nms_multiproc_n4/yosys.log
+12014 -11785
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