diff --git a/hardware/v2/logs/experiments.log b/hardware/v2/logs/experiments.log
index 1839c2a..1916821 100644
--- a/hardware/v2/logs/experiments.log
+++ b/hardware/v2/logs/experiments.log
@@ -5168,3 +5168,37 @@ displacement, no duplicated controller logic) over a second
 independent channel. User confirmed target: N=8 real cores; N=16 to
 be built and tested specifically to document where/how it breaks
 (real data for the analysis document, not a real deployment target).
+
+EXP-0082 -- real P&R confirms EXP-0081's denser packing is timing-safe,
+margin actually improved (2026-09-20)
+
+RESULT: route_design 100%, 0 errors. WNS = +0.068ns (UP from EXP-0079's
++0.030ns, not down -- confirms the "register the select bit at request
+time, off the critical path" design genuinely avoided introducing a
+new critical path). WHS unchanged +0.048ns, 0 failing endpoints.
+5437 LUTs (+58 vs EXP-0079's 5379, the real cost of the small mux/
+sel_lat addition), 16 DSP48E1 unchanged.
+
+DECISION: EXP-0081's denser activation packing is confirmed both
+functionally correct (3-level verification) AND real-timing-safe (P&R
+margin improved, not degraded). This is the current final real
+signoff for the N=2, 16-bit-DDR3 configuration.
+
+next_action (per user direction, same session): (1) user to re-run
+the real MIG Customize IP wizard for TWO real, wizard-validated
+changes at once -- Data Width 16->32 (physical 32-bit DDR3 channel,
+user's own decision after the dual-channel-vs-wide-channel analysis)
+and Input Clock Period tightened toward 2500ps/400MHz (DDR3-1600's
+real rated max) -- both correctly require the real wizard's own JEDEC/
+PLL calculator, not a hand-edited config (same reasoning as the
+speed-grade change, EXP-0074, but for parameters this project has not
+attempted to hand-edit); (2) build a real "DDRManager" -- an evolved,
+complete intelligent memory coordinator using orchestrator-level
+reservations to prefetch/anticipate DDR3 accesses ahead of demand,
+starting with the single-slot look-ahead prototype EXP-0080's own
+analysis recommended before attempting the full multi-slot scheduler;
+(3) real N-core scaling tests at N=2/4/8/16 once (1) and (2) are in
+place -- user's own explicit framing: N=8 is the realistic target,
+N=16 is being built specifically to document where/how it breaks
+(real data for the analysis, not assumed to be a viable deployment
+point).