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perf(v2): word-level burst reads - 2.24-2.37x real wall-clock speedup (DEC-0015)

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Implements optimization #1 from the final benchmark campaign's own
recommendation: exploit psram_controller.v's already-implemented
page-mode support (confirmed present by direct inspection) by
fetching multiple bytes per real backend transaction instead of one
at a time.

Root cause addressed: int8_memory_access.v (the byte-level backend
prefetch_engine.v originally sat on) already converts every 8-bit
logical request into a full 16-bit PSRAM word access internally
(mem_addr <= addr >> 1), discarding half of every word it already
paid for. prefetch_engine.v/memory_manager.v now speak
memory_interface.v's own 16-bit word protocol directly, bypassing
int8_memory_access.v entirely - which remains untouched, still frozen
V1 (§1/§34); V2 simply reuses the lower layer of the same frozen
chain instead of the byte-splitting layer on top of it, the same
"reuse what fits" precedent slot_mem_arbiter.v already set.
slot_mem_arbiter.v and neural_multiprocessor.v widened to match
(lb_n/ub_n added, master port wired directly to memory_interface.v).

Real, measured results: M4's own single-job testbench shows 49-56%
fewer cycles (166->84, 446->204, 728->322, all still bit-exact). The
full final-benchmark campaign (24/24 workload/config combinations)
re-verified bit-exact with D-Stress's real wall-clock time (cycles /
real POST-P&R Fmax) improving 2.24-2.37x across every N_SLOTS tested,
against a small real Fmax cost (unchanged at N=1, -6.2% at N=2, -1.2%
at N=4).

tb_neural_multiprocessor.v (M8) and tb_benchmark_suite.v (final
campaign) needed zero changes - both treat neural_multiprocessor.v as
a black box. Only tb_memory_manager.v (M4, rewired to skip
int8_memory_access.v) and tb_dataflow_core.v (M7, behavioral model
widened to word-level) needed updates.

The "real parallel scaling is flat beyond N_SLOTS=2" finding (DEC-0014)
still holds - this optimization made the shared PSRAM port more
efficient per transaction, not multi-ported - so N_SLOTS=2 remains
the recommended default.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0015)/
experiments (EXP-0015)/development.log.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 20:35:19 +02:00
co-authored by Claude Sonnet 5
parent 3cdaeaee35
commit e4a5540b6e
14 changed files with 489 additions and 168 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/sim/tb_dataflow_core.v
+40 -19
View File
@@ -21,13 +21,17 @@
// node1 (x=1,w=1,8in -> acc=8) --+
//
// Verified with Verilator (decisions.log DEC-0004). Each slot gets
// its own independent behavioral memory (sim_byte_mem, same as
// its own independent behavioral memory (sim_word_mem, same as
// tb_neural_director.v/tb_memory_manager.v's own scope decisions --
// DEC-0006/DEC-0007: shared-PSRAM arbitration across slots is
// explicitly M8's job, not exercised here).
//
// WORD-level (16-bit, + lb_n/ub_n) post-M10 (decisions.log DEC-0015),
// matching memory_manager.v's own backend port width after the
// burst-read rewrite (see prefetch_engine.v/memory_manager.v headers).
// ============================================================
module sim_byte_mem #(
module sim_word_mem #(
parameter ADDR_WIDTH = 23,
parameter DEPTH = 4096
)(
@@ -35,24 +39,28 @@ module sim_byte_mem #(
input wire rst,
input wire req,
input wire wr,
input wire [ADDR_WIDTH-1:0] addr,
input wire signed [7:0] wdata,
output reg signed [7:0] rdata,
input wire [ADDR_WIDTH-1:0] addr, // WORD address
input wire [15:0] wdata,
input wire lb_n, ub_n,
output reg [15:0] rdata,
output reg ready
);
reg signed [7:0] mem [0:DEPTH-1];
reg [15:0] mem [0:DEPTH-1];
reg [1:0] state;
reg [ADDR_WIDTH-1:0] addr_reg;
localparam ST_IDLE = 0, ST_WAIT = 1;
always @(posedge clk) begin
if (rst) begin
state <= ST_IDLE; ready <= 1'b0; rdata <= 8'sd0;
state <= ST_IDLE; ready <= 1'b0; rdata <= 16'h0000;
end else begin
ready <= 1'b0;
case (state)
ST_IDLE: if (req) begin
addr_reg <= addr;
if (wr) mem[addr] <= wdata;
if (wr) begin
if (!lb_n) mem[addr][7:0] <= wdata[7:0];
if (!ub_n) mem[addr][15:8] <= wdata[15:8];
end
state <= ST_WAIT;
end
ST_WAIT: begin
@@ -90,7 +98,8 @@ module tb;
wire [N_SLOTS-1:0] slot_mem_req, slot_mem_wr;
wire [ADDR_WIDTH*N_SLOTS-1:0] slot_mem_addr;
wire signed [8*N_SLOTS-1:0] slot_mem_wdata, slot_mem_rdata;
wire [16*N_SLOTS-1:0] slot_mem_wdata, slot_mem_rdata;
wire [N_SLOTS-1:0] slot_mem_lb_n, slot_mem_ub_n;
wire [N_SLOTS-1:0] slot_mem_ready;
dataflow_core #(
@@ -103,37 +112,49 @@ module tb;
.reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles),
.reg_result_addr(reg_result_addr),
.slot_mem_req(slot_mem_req), .slot_mem_wr(slot_mem_wr), .slot_mem_addr(slot_mem_addr),
.slot_mem_wdata(slot_mem_wdata), .slot_mem_rdata(slot_mem_rdata), .slot_mem_ready(slot_mem_ready)
.slot_mem_wdata(slot_mem_wdata), .slot_mem_lb_n(slot_mem_lb_n), .slot_mem_ub_n(slot_mem_ub_n),
.slot_mem_rdata(slot_mem_rdata), .slot_mem_ready(slot_mem_ready)
);
genvar g;
generate
for (g = 0; g < N_SLOTS; g = g + 1) begin : GEN_MEM
sim_byte_mem #(.ADDR_WIDTH(ADDR_WIDTH), .DEPTH(4096)) u_mem (
sim_word_mem #(.ADDR_WIDTH(ADDR_WIDTH), .DEPTH(4096)) u_mem (
.clk(clk), .rst(rst),
.req(slot_mem_req[g]), .wr(slot_mem_wr[g]),
.addr(slot_mem_addr[g*ADDR_WIDTH +: ADDR_WIDTH]),
.wdata(slot_mem_wdata[g*8 +: 8]),
.rdata(slot_mem_rdata[g*8 +: 8]), .ready(slot_mem_ready[g])
.wdata(slot_mem_wdata[g*16 +: 16]),
.lb_n(slot_mem_lb_n[g]), .ub_n(slot_mem_ub_n[g]),
.rdata(slot_mem_rdata[g*16 +: 16]), .ready(slot_mem_ready[g])
);
end
endgenerate
task automatic poke(input integer slot, input [ADDR_WIDTH-1:0] addr, input [7:0] val);
// poke/peek stay BYTE-addressed at the testbench level (matching
// every other testbench's own convention) -- converted to
// word-address + byte-lane internally, same as psram_model.v's
// own real convention.
task automatic poke(input integer slot, input [ADDR_WIDTH-1:0] byte_addr, input [7:0] val);
reg [ADDR_WIDTH-2:0] word_addr;
begin
word_addr = byte_addr[ADDR_WIDTH-1:1];
case (slot)
0: tb.GEN_MEM[0].u_mem.mem[addr] = val;
1: tb.GEN_MEM[1].u_mem.mem[addr] = val;
0: if (byte_addr[0]==1'b0) tb.GEN_MEM[0].u_mem.mem[word_addr][7:0] = val;
else tb.GEN_MEM[0].u_mem.mem[word_addr][15:8] = val;
1: if (byte_addr[0]==1'b0) tb.GEN_MEM[1].u_mem.mem[word_addr][7:0] = val;
else tb.GEN_MEM[1].u_mem.mem[word_addr][15:8] = val;
default: ;
endcase
end
endtask
function automatic signed [7:0] peek(input integer slot, input [ADDR_WIDTH-1:0] addr);
function automatic signed [7:0] peek(input integer slot, input [ADDR_WIDTH-1:0] byte_addr);
reg [ADDR_WIDTH-2:0] word_addr;
begin
word_addr = byte_addr[ADDR_WIDTH-1:1];
case (slot)
0: peek = tb.GEN_MEM[0].u_mem.mem[addr];
1: peek = tb.GEN_MEM[1].u_mem.mem[addr];
0: peek = (byte_addr[0]==1'b0) ? tb.GEN_MEM[0].u_mem.mem[word_addr][7:0] : tb.GEN_MEM[0].u_mem.mem[word_addr][15:8];
1: peek = (byte_addr[0]==1'b0) ? tb.GEN_MEM[1].u_mem.mem[word_addr][7:0] : tb.GEN_MEM[1].u_mem.mem[word_addr][15:8];
default: peek = 8'sdx;
endcase
end
hardware/v2/sim/tb_memory_manager.v
+14 -24
View File
@@ -50,11 +50,14 @@ module tb;
wire mm_result_valid, mm_result_ready;
wire signed [DATA_WIDTH-1:0] mm_result_data;
// ---- memory_manager <-> int8_memory_access (Memory Backend Interface) ----
// ---- memory_manager <-> memory_interface (word-level Memory
// Backend Interface, post-M10 DEC-0015 -- int8_memory_access is no
// longer in this datapath, see memory_manager.v's own header) ----
wire mem_req, mem_wr;
wire [ADDR_WIDTH-1:0] mem_addr;
wire signed [7:0] mem_wdata;
wire signed [7:0] mem_rdata;
wire [ADDR_WIDTH-1:0] mem_addr; // WORD address
wire [15:0] mem_wdata;
wire mem_lb_n, mem_ub_n;
wire [15:0] mem_rdata;
wire mem_ready;
memory_manager #(
@@ -67,6 +70,7 @@ module tb;
.input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last),
.result_valid(mm_result_valid), .result_ready(mm_result_ready), .result_data(mm_result_data),
.mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr), .mem_wdata(mem_wdata),
.mem_lb_n(mem_lb_n), .mem_ub_n(mem_ub_n),
.mem_rdata(mem_rdata), .mem_ready(mem_ready)
);
@@ -105,23 +109,9 @@ module tb;
else if (job_valid_np && job_ready_np) job_valid_np <= 1'b0;
end
// ---- REAL, unmodified V1 backend chain ----
wire if_mem_req, if_mem_wr;
wire [ADDR_WIDTH-1:0] if_mem_addr;
wire [PSRAM_DATA_WIDTH-1:0] if_mem_wdata;
wire if_mem_lb_n, if_mem_ub_n;
wire [PSRAM_DATA_WIDTH-1:0] if_mem_rdata;
wire if_mem_ready;
int8_memory_access #(.ADDR_WIDTH(ADDR_WIDTH)) u_int8 (
.clk(clk), .rst(rst),
.req(mem_req), .wr(mem_wr), .addr(mem_addr), .wdata(mem_wdata),
.rdata(mem_rdata), .ready(mem_ready),
.mem_req(if_mem_req), .mem_wr(if_mem_wr), .mem_addr(if_mem_addr), .mem_wdata(if_mem_wdata),
.mem_lb_n(if_mem_lb_n), .mem_ub_n(if_mem_ub_n),
.mem_rdata(if_mem_rdata), .mem_ready(if_mem_ready)
);
// ---- REAL, unmodified V1 backend chain (memory_interface ->
// psram_controller; int8_memory_access no longer in this datapath,
// see memory_manager.v's own header, DEC-0015) ----
wire pc_mem_req, pc_mem_wr;
wire [ADDR_WIDTH-1:0] pc_mem_addr;
wire [PSRAM_DATA_WIDTH-1:0] pc_mem_wdata;
@@ -131,9 +121,9 @@ module tb;
memory_interface #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(PSRAM_DATA_WIDTH)) u_memif (
.clk(clk), .rst(rst),
.req(if_mem_req), .wr(if_mem_wr), .addr(if_mem_addr), .wdata(if_mem_wdata),
.lb_n(if_mem_lb_n), .ub_n(if_mem_ub_n),
.rdata(if_mem_rdata), .ready(if_mem_ready),
.req(mem_req), .wr(mem_wr), .addr(mem_addr), .wdata(mem_wdata),
.lb_n(mem_lb_n), .ub_n(mem_ub_n),
.rdata(mem_rdata), .ready(mem_ready),
.mem_req(pc_mem_req), .mem_wr(pc_mem_wr), .mem_addr(pc_mem_addr), .mem_wdata(pc_mem_wdata),
.mem_lb_n(pc_mem_lb_n), .mem_ub_n(pc_mem_ub_n),
.mem_rdata(pc_mem_rdata), .mem_ready(pc_mem_ready)