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perf(v2): word-level burst reads - 2.24-2.37x real wall-clock speedup (DEC-0015)

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Implements optimization #1 from the final benchmark campaign's own
recommendation: exploit psram_controller.v's already-implemented
page-mode support (confirmed present by direct inspection) by
fetching multiple bytes per real backend transaction instead of one
at a time.

Root cause addressed: int8_memory_access.v (the byte-level backend
prefetch_engine.v originally sat on) already converts every 8-bit
logical request into a full 16-bit PSRAM word access internally
(mem_addr <= addr >> 1), discarding half of every word it already
paid for. prefetch_engine.v/memory_manager.v now speak
memory_interface.v's own 16-bit word protocol directly, bypassing
int8_memory_access.v entirely - which remains untouched, still frozen
V1 (§1/§34); V2 simply reuses the lower layer of the same frozen
chain instead of the byte-splitting layer on top of it, the same
"reuse what fits" precedent slot_mem_arbiter.v already set.
slot_mem_arbiter.v and neural_multiprocessor.v widened to match
(lb_n/ub_n added, master port wired directly to memory_interface.v).

Real, measured results: M4's own single-job testbench shows 49-56%
fewer cycles (166->84, 446->204, 728->322, all still bit-exact). The
full final-benchmark campaign (24/24 workload/config combinations)
re-verified bit-exact with D-Stress's real wall-clock time (cycles /
real POST-P&R Fmax) improving 2.24-2.37x across every N_SLOTS tested,
against a small real Fmax cost (unchanged at N=1, -6.2% at N=2, -1.2%
at N=4).

tb_neural_multiprocessor.v (M8) and tb_benchmark_suite.v (final
campaign) needed zero changes - both treat neural_multiprocessor.v as
a black box. Only tb_memory_manager.v (M4, rewired to skip
int8_memory_access.v) and tb_dataflow_core.v (M7, behavioral model
widened to word-level) needed updates.

The "real parallel scaling is flat beyond N_SLOTS=2" finding (DEC-0014)
still holds - this optimization made the shared PSRAM port more
efficient per transaction, not multi-ported - so N_SLOTS=2 remains
the recommended default.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0015)/
experiments (EXP-0015)/development.log.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 20:35:19 +02:00
co-authored by Claude Sonnet 5
parent 3cdaeaee35
commit e4a5540b6e
14 changed files with 489 additions and 168 deletions
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hardware/v2/logs/experiments.log
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@@ -551,3 +551,36 @@ next_action: none mandated by the roadmap (this campaign was
characterization before deciding N_SLOTS and writing the V2
datasheet). Full report: hardware/v2/docs/benchmarks/final-
benchmark.md.
[2026-09-05] EXP-0015 -- word-level burst-read implementation (user-
requested optimization #1, following final-benchmark.md's own
recommendation: exploit psram_controller.v's already-implemented
page-mode support by fetching multiple bytes per real transaction
instead of one at a time)
test: prefetch_engine.v/memory_manager.v rewritten to speak
memory_interface.v's 16-bit word protocol directly (bypassing
int8_memory_access.v, still frozen/unmodified -- just no longer
instantiated in this datapath); slot_mem_arbiter.v/dataflow_core.v/
neural_multiprocessor.v widened to match. Re-verified: M4's own
testbench (updated to skip int8_memory_access), M7's own testbench
(sim_byte_mem -> sim_word_mem), M8's own testbench (UNCHANGED,
black-box), and the full final benchmark campaign (UNCHANGED,
black-box) at N_SLOTS=1/2/4/8.
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL:
SIMULATED: M4 3/3 PASS, cycles reduced 49-56% (166->84, 446->204,
728->322). M7 4/4 PASS. M8 4/4 PASS, cycles 684->337. Final
campaign 24/24 PASS bit-exact, D-Stress cycles reduced from
780298/736402/736823/738751 to 348682/307602/307346/307874
(N=1/2/4/8) -- roughly 2.2-2.4x fewer real cycles.
SYNTHESIZED + POST-P&R (real, full system incl. real PSRAM pins):
N=1 152.44 MHz (was 152.46), N=2 133.58 MHz (was 142.45, -6.2%),
N=4 112.07 MHz (was 113.38, -1.2%) -- small real Fmax cost.
Combined real wall-clock speedup (cycles / real Fmax): 2.24-2.37x
across N_SLOTS=1/2/4.
errors: none found (clean implementation, no regressions).
decision: see decisions.log DEC-0015.
next_action: user-requested optimization #2 -- a shared on-chip cache
for the activation (X) vector, so N independent neurons sharing one
input vector (the dense-layer shape used throughout this benchmark
suite) fetch it from PSRAM ONCE instead of once per neuron.