perf(v2): word-level burst reads - 2.24-2.37x real wall-clock speedup (DEC-0015)

Implements optimization #1 from the final benchmark campaign's own recommendation: exploit psram_controller.v's already-implemented page-mode support (confirmed present by direct inspection) by fetching multiple bytes per real backend transaction instead of one at a time. Root cause addressed: int8_memory_access.v (the byte-level backend prefetch_engine.v originally sat on) already converts every 8-bit logical request into a full 16-bit PSRAM word access internally (mem_addr <= addr >> 1), discarding half of every word it already paid for. prefetch_engine.v/memory_manager.v now speak memory_interface.v's own 16-bit word protocol directly, bypassing int8_memory_access.v entirely - which remains untouched, still frozen V1 (§1/§34); V2 simply reuses the lower layer of the same frozen chain instead of the byte-splitting layer on top of it, the same "reuse what fits" precedent slot_mem_arbiter.v already set. slot_mem_arbiter.v and neural_multiprocessor.v widened to match (lb_n/ub_n added, master port wired directly to memory_interface.v). Real, measured results: M4's own single-job testbench shows 49-56% fewer cycles (166->84, 446->204, 728->322, all still bit-exact). The full final-benchmark campaign (24/24 workload/config combinations) re-verified bit-exact with D-Stress's real wall-clock time (cycles / real POST-P&R Fmax) improving 2.24-2.37x across every N_SLOTS tested, against a small real Fmax cost (unchanged at N=1, -6.2% at N=2, -1.2% at N=4). tb_neural_multiprocessor.v (M8) and tb_benchmark_suite.v (final campaign) needed zero changes - both treat neural_multiprocessor.v as a black box. Only tb_memory_manager.v (M4, rewired to skip int8_memory_access.v) and tb_dataflow_core.v (M7, behavioral model widened to word-level) needed updates. The "real parallel scaling is flat beyond N_SLOTS=2" finding (DEC-0014) still holds - this optimization made the shared PSRAM port more efficient per transaction, not multi-ported - so N_SLOTS=2 remains the recommended default. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0015)/ experiments (EXP-0015)/development.log. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-05 20:35:19 +02:00
parent 3cdaeaee35
commit e4a5540b6e
14 changed files with 489 additions and 168 deletions
@@ -311,3 +311,23 @@ decision: vedi decisions.log DEC-0014 -- N_SLOTS=2 raccomandato come
  tetto DSP mafisico, non come raccomandazione d'uso generale).
 next_action: datasheet V2 in stile professionale (richiesta utente),
  ora sbloccato dalla decisione su N_SLOTS.
+
+[2026-09-05] Ottimizzazione #1 -- burst read a livello di parola
+(word-level), su richiesta esplicita dell'utente
+reason: dopo la campagna di benchmark finale, l'utente ha chiesto
+  concretamente di implementare la raccomandazione #1 (sfruttare il
+  page-mode gia' presente nel controller PSRAM leggendo piu' byte in
+  una sola transazione, non uno alla volta).
+result: prefetch_engine.v/memory_manager.v riscritti per parlare
+  direttamente il protocollo a 16 bit di memory_interface.v (bypassando
+  int8_memory_access.v, che resta comunque congelato e non modificato
+  -- semplicemente non piu' istanziato in questo percorso dati).
+  Risultato reale misurato: -49/-54/-56% cicli su job singoli (M4),
+  2.24-2.37x speedup reale in wall-clock sull'intera campagna finale
+  (24/24 ancora bit-exact), a fronte di un costo Fmax reale piccolo
+  (-6.2% a N_SLOTS=2, -1.2% a N_SLOTS=4, invariato a N_SLOTS=1).
+errors: nessuno (implementazione pulita, nessuna regressione).
+decision: vedi decisions.log DEC-0015.
+next_action: ottimizzazione #2 -- cache condivisa on-chip per il
+  vettore di attivazione (X), per eliminare le letture ridondanti tra
+  neuroni che condividono lo stesso input di layer.