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perf(v2): word-level burst reads - 2.24-2.37x real wall-clock speedup (DEC-0015)

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Implements optimization #1 from the final benchmark campaign's own
recommendation: exploit psram_controller.v's already-implemented
page-mode support (confirmed present by direct inspection) by
fetching multiple bytes per real backend transaction instead of one
at a time.

Root cause addressed: int8_memory_access.v (the byte-level backend
prefetch_engine.v originally sat on) already converts every 8-bit
logical request into a full 16-bit PSRAM word access internally
(mem_addr <= addr >> 1), discarding half of every word it already
paid for. prefetch_engine.v/memory_manager.v now speak
memory_interface.v's own 16-bit word protocol directly, bypassing
int8_memory_access.v entirely - which remains untouched, still frozen
V1 (§1/§34); V2 simply reuses the lower layer of the same frozen
chain instead of the byte-splitting layer on top of it, the same
"reuse what fits" precedent slot_mem_arbiter.v already set.
slot_mem_arbiter.v and neural_multiprocessor.v widened to match
(lb_n/ub_n added, master port wired directly to memory_interface.v).

Real, measured results: M4's own single-job testbench shows 49-56%
fewer cycles (166->84, 446->204, 728->322, all still bit-exact). The
full final-benchmark campaign (24/24 workload/config combinations)
re-verified bit-exact with D-Stress's real wall-clock time (cycles /
real POST-P&R Fmax) improving 2.24-2.37x across every N_SLOTS tested,
against a small real Fmax cost (unchanged at N=1, -6.2% at N=2, -1.2%
at N=4).

tb_neural_multiprocessor.v (M8) and tb_benchmark_suite.v (final
campaign) needed zero changes - both treat neural_multiprocessor.v as
a black box. Only tb_memory_manager.v (M4, rewired to skip
int8_memory_access.v) and tb_dataflow_core.v (M7, behavioral model
widened to word-level) needed updates.

The "real parallel scaling is flat beyond N_SLOTS=2" finding (DEC-0014)
still holds - this optimization made the shared PSRAM port more
efficient per transaction, not multi-ported - so N_SLOTS=2 remains
the recommended default.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0015)/
experiments (EXP-0015)/development.log.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 20:35:19 +02:00
co-authored by Claude Sonnet 5
parent 3cdaeaee35
commit e4a5540b6e
14 changed files with 489 additions and 168 deletions
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@@ -275,3 +275,39 @@ bit-exact against a software golden model, zero errors, zero
timeouts, zero deadlocks (after fixing the 3 issues in errors.log
ERR-0009). No node lost, no node duplicated, correct multi-hop
dependency wake-up verified (workload F's 2-hop diamond+fan-in graph).
[2026-09-05] EXP-0015 -- word-level burst-read rewrite (DEC-0015),
real before/after comparison (user-requested optimization #1,
following the final-benchmark.md report's own recommendation)
M4 standalone (tb_memory_manager.v, real V1 PSRAM chain, single job):
| Job (n_tiles) | cycles BEFORE | cycles AFTER | reduction |
|-----------------|-----------------|----------------|-------------|
| 1 tile | 166 | 84 | -49.4% |
| 3 tiles | 446 | 204 | -54.3% |
| 5 tiles | 728 | 322 | -55.8% |
All still bit-exact.
Full campaign (tb_benchmark_suite.v, same 6 workloads as EXP-0014),
D-Stress (256 neurons, the largest/most representative workload),
real cycles and real wall-clock (cycles / real POST-P&R Fmax):
| N_SLOTS | Fmax BEFORE | Fmax AFTER | cycles BEFORE | cycles AFTER | wall-clock BEFORE | wall-clock AFTER | real speedup |
|-----------|---------------|--------------|------------------|-----------------|----------------------|---------------------|----------------|
| 1 | 152.46 MHz | 152.44 MHz | 780298 | 348682 | 5118.1 us | 2287.3 us | 2.24x |
| 2 | 142.45 MHz | 133.58 MHz | 736402 | 307602 | 5169.5 us | 2302.8 us | 2.24x |
| 4 | 113.38 MHz | 112.07 MHz | 736823 | 307346 | 6498.7 us | 2742.4 us | 2.37x |
Real PSRAM port utilization also rose (e.g. N=2, D-Stress: 91.0% ->
89.1% -- essentially unchanged fraction, but of a MUCH smaller total
cycle count, meaning the port is doing genuinely useful work a larger
fraction of the time it IS busy, not idling on redundant round-trips).
All 24/24 workload/config combinations (6 workloads x N_SLOTS=1/2/4/8)
re-verified bit-exact after the rewrite. The "real parallel scaling is
flat beyond N_SLOTS=2" finding from EXP-0014 STILL holds (D-Stress
cycles at N=2/4/8 remain within ~0.2% of each other: 307602/307346/
307874) -- this optimization made the shared PSRAM port more
EFFICIENT per transaction, it did not remove the fact that there is
still only one physical port, so DEC-0014's N_SLOTS=2 recommendation
is unaffected and reconfirmed with the new, faster numbers.