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b/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.tex deleted file mode 100644 index 8ec4845..0000000 --- a/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.tex +++ /dev/null @@ -1,120 +0,0 @@ -% ====================================================================== -% FPGA-Neural V2 -- INT8 Neural Network Engine, single-SDRAM architecture -% Datasheet / Technical reference manual -% Repository: github.com/manvalan/FPGA-Neural -% Ported from the V1 LaTeX datasheet (hardware/v1/docs/DatasheetLatex/): -% same preamble, macros, typography, and title-page/features-page -% structure -- content rewritten for the V2 architecture throughout. -% ====================================================================== -\documentclass[11pt,a4paper,openany]{report} - -\newcommand{\datasheetrev}{B0} -\newcommand{\datasheetdate}{September 2026} - -\input{preamble} - -\begin{document} -\sloppy - -% ====================================================================== -% TITLE PAGE -% ====================================================================== -\begin{titlepage} -\thispagestyle{empty} -\begin{tikzpicture}[remember picture,overlay] - \fill[fnDark] (current page.north west) rectangle - ([yshift=-4.3cm]current page.north east); - \fill[fnTeal] ([yshift=-4.3cm]current page.north west) rectangle - ([yshift=-4.55cm]current page.north east); - \node[anchor=north west,text=white,font=\Huge\bfseries] - at ([xshift=2.2cm,yshift=-1.15cm]current page.north west) - {FPGA\,--\,Neural V2}; - \node[anchor=north west,text=fnLight,font=\large] - at ([xshift=2.25cm,yshift=-2.15cm]current page.north west) - {INT8 Neural Multiprocessor, unified single-SDRAM architecture}; - \node[anchor=north west,text=fnLight2,font=\normalsize] - at ([xshift=2.25cm,yshift=-2.85cm]current page.north west) - {Parametric N-processor hardware accelerator -- Datasheet and reference manual}; - \node[anchor=north east,text=white,font=\ttfamily\small] - at ([xshift=-2.2cm,yshift=-3.55cm]current page.north east) - {Rev.~\datasheetrev~~\textbullet~~\datasheetdate}; -\end{tikzpicture} - -\vspace*{5.0cm} - -% --- compact block diagram on the title page --- -\begin{center} -\begin{tikzpicture}[node distance=7mm and 12mm] - \node[fnblockD,minimum width=30mm] (host) {HOST\\{\scriptsize MCU / PC (SPI master)}}; - \node[fnblockT,right=18mm of host,minimum width=34mm] (fpga) - {FPGA\\{\scriptsize Neural Multiprocessor, N=4}}; - \node[fnblock,right=18mm of fpga,minimum width=26mm] (ram) - {SDRAM\\{\scriptsize 8\,MB, unified}}; - \draw[fnbus] (host) -- node[fnlbl,above]{SPI Mode 0} (fpga); - \draw[fnbus] (fpga) -- node[fnlbl,above]{16-bit, single chip} (ram); - \node[below=1mm of fpga,font=\scriptsize\itshape,text=fnGrey] - {weights + activations + results, ONE physical memory}; -\end{tikzpicture} -\end{center} - -\vfill -\begin{center} -\begin{tikzpicture} -\node[draw=fnRule,rounded corners=3pt,inner sep=10pt,fill=fnLight,text width=15.5cm]{ -\footnotesize -\textbf{\color{fnDark}Reference target device:} Lattice ECP5 \code{LFE5U-45F-8BG381} -(speed grade $-8$, CABGA381, 72$\times$MULT18X18D, $\approx$44k LUT).\\[2pt] -\textbf{\color{fnDark}Baseline configuration:} INT8/INT32, \code{N\_PROCESSORS}=4, -\code{P\_IN}=8, single external SDRAM Alliance Memory \code{AS4C4M16SA-6TIN} -(weights + activations + results, unified). No PSRAM anywhere in the V2 -physical path.\\[2pt] -\textbf{\color{fnDark}Clock:} 16\,MHz board oscillator $\rightarrow$ real -ECP5 \code{EHXPLLL} $\rightarrow$ 64\,MHz system clock, timing-closed -across 8 real place-and-route seeds (worst 68.51\,MHz, best 74.17\,MHz).\\[2pt] -\textbf{\color{fnDark}Host:} real SPI protocol engine -(\code{spi\_host\_bridge.v}) -- WRITE\_JOB / WRITE\_MEM / READ\_MEM / -STATUS / RESET.\\[2pt] -\textbf{\color{fnDark}Status:} RTL verified in simulation (Verilator, -bit-exact), real synthesis (Yosys) and real place-and-route -(nextpnr-ecp5). No fabricated hardware exists -- see \S\ref{ch:status} -for the precise, itemized readiness state. Document describing the -project as of \datasheetdate. -}; -\end{tikzpicture} -\end{center} -\vspace{0.6cm} -{\footnotesize\color{fnGrey}\raggedright -Project author: Michele Bigi \textbullet{} MIKILAB / manvalan.\\ -This datasheet documents the RTL code, documentation and benchmarks -present in the repository \texttt{github.com/manvalan/FPGA-Neural}, -ported from the V1 datasheet's own LaTeX structure (same preamble and -macros, content rewritten for V2).\par} -\end{titlepage} - -% ====================================================================== -% "FEATURES" PAGE (datasheet style) -% ====================================================================== -\input{chapters/00-features} - -% ====================================================================== -% TABLE OF CONTENTS -% ====================================================================== -\newpage -\pagenumbering{roman} -{\color{fnDark}\tableofcontents} -\newpage -\pagenumbering{arabic} - -% ====================================================================== -% CHAPTERS -% ====================================================================== -\include{chapters/01-overview} -\include{chapters/02-architecture} -\include{chapters/03-clock-reset} -\include{chapters/04-host-interface} -\include{chapters/05-pinout-timing} -\include{chapters/06-power-configuration} -\include{chapters/07-benchmarks} -\include{chapters/08-status-roadmap} - -\end{document} diff --git a/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.toc b/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.toc deleted file mode 100644 index 976e1c8..0000000 --- a/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.toc +++ /dev/null @@ -1,30 +0,0 @@ -\babel@toc {english}{}\relax -\contentsline {chapter}{\numberline {1}Overview}{1}{chapter.1}% -\contentsline {section}{\numberline {1.1}Document scope and status labels}{1}{section.1.1}% -\contentsline {section}{\numberline {1.2}Frozen reference configuration}{1}{section.1.2}% -\contentsline {chapter}{\numberline {2}Architecture}{2}{chapter.2}% -\contentsline {section}{\numberline {2.1}Compute: Neural Multiprocessor}{2}{section.2.1}% -\contentsline {section}{\numberline {2.2}Unified single-SDRAM memory}{2}{section.2.2}% -\contentsline {section}{\numberline {2.3}Read-timing discipline (ERR-0025)}{3}{section.2.3}% -\contentsline {chapter}{\numberline {3}Clock and reset architecture}{4}{chapter.3}% -\contentsline {section}{\numberline {3.1}Clock generation}{4}{section.3.1}% -\contentsline {section}{\numberline {3.2}Reset architecture}{4}{section.3.2}% -\contentsline {chapter}{\numberline {4}Host interface (SPI)}{5}{chapter.4}% -\contentsline {section}{\numberline {4.1}Opcodes}{5}{section.4.1}% -\contentsline {section}{\numberline {4.2}Verification}{5}{section.4.2}% -\contentsline {chapter}{\numberline {5}Pinout, place-and-route, and timing}{6}{chapter.5}% -\contentsline {section}{\numberline {5.1}Final pinout}{6}{section.5.1}% -\contentsline {section}{\numberline {5.2}Synthesis (real, this revision)}{6}{section.5.2}% -\contentsline {section}{\numberline {5.3}Place and route: 8-seed timing table}{6}{section.5.3}% -\contentsline {chapter}{\numberline {6}Power, SDRAM electrical, and configuration}{8}{chapter.6}% -\contentsline {section}{\numberline {6.1}Power architecture -- status: OPEN}{8}{section.6.1}% -\contentsline {section}{\numberline {6.2}SDRAM electrical / timing sign-off -- status: PARTIAL}{8}{section.6.2}% -\contentsline {section}{\numberline {6.3}Configuration -- status: OPEN}{8}{section.6.3}% -\contentsline {chapter}{\numberline {7}Benchmarks}{9}{chapter.7}% -\contentsline {section}{\numberline {7.1}Internal benchmark: D-Stress workload}{9}{section.7.1}% -\contentsline {section}{\numberline {7.2}Host-interface pacing benchmark}{9}{section.7.2}% -\contentsline {section}{\numberline {7.3}Software reference comparison}{9}{section.7.3}% -\contentsline {chapter}{\numberline {8}Chip readiness and roadmap}{11}{chapter.8}% -\contentsline {section}{\numberline {8.1}Precise readiness checklist}{11}{section.8.1}% -\contentsline {section}{\numberline {8.2}Final answer}{11}{section.8.2}% -\contentsline {section}{\numberline {8.3}Roadmap}{11}{section.8.3}% diff --git a/hardware/v2/docs/DatasheetLatex/chapters/00-features.tex b/hardware/v2/docs/DatasheetLatex/chapters/00-features.tex deleted file mode 100644 index f8daead..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/00-features.tex +++ /dev/null @@ -1,123 +0,0 @@ -\thispagestyle{plain} -\noindent -\begin{tikzpicture} -\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt, - minimum width=\textwidth,anchor=west] - {\large\bfseries FPGA-Neural V2 --- General description and features}; -\end{tikzpicture} - -\vspace{6pt} -\noindent -{\small FPGA-Neural V2 is a \textbf{parametric hardware neural -multiprocessor} built around \code{N\_PROCESSORS} independent INT8 MAC -engines dispatched by a real dependency-graph scheduler -(Dependency Manager $\to$ Neural Director $\to$ per-slot Memory -Manager), streaming weight/activation tiles from, and writing results -to, a \textbf{single external SDRAM chip} -- no PSRAM, no second -memory device anywhere in the V2 physical path. Job registration is -via a real SPI host protocol engine; the host never participates in -the compute datapath.} - -\vspace{8pt} -\begin{multicols}{2} -{\color{fnDark}\large\bfseries Features}\\[2pt] -{\footnotesize -\begin{itemize}[leftmargin=1.1em] -\item \textbf{INT8 $\times$ INT8 $\to$ INT32} datapath per processor, - \code{P\_IN}=8-wide parallel MAC, balanced adder tree. -\item \textbf{N\_PROCESSORS} independent Neural Processors (frozen - reference: N=4; N=2 also fully validated; N=8 is a future - evolution). -\item \textbf{Unified single-SDRAM memory}: weights, activations, AND - results all share ONE physical Alliance Memory - \code{AS4C4M16SA-6TIN} (8\,MB, 16-bit), through one - \code{sdram\_unified\_backend} arbitrating a read-only, - cached weight (W) port and a read/write, byte-maskable - activation+result (AR) port. -\item Real dependency-graph scheduling: the Dependency Manager tracks - per-node WAITING/READY/DISPATCHED state and producer/consumer - wake-up; the Neural Director allocates the first free processor - slot. -\item \textbf{Real SPI host protocol engine} - (\code{spi\_host\_bridge.v}): \code{WRITE\_JOB} (job - registration), \code{WRITE\_MEM}/\code{READ\_MEM} (raw SDRAM - access), \code{STATUS}, \code{RESET}. -\item \textbf{Real ECP5 clock generation}: 16\,MHz oscillator - $\to$ \code{EHXPLLL} (real Project Trellis \code{ecppll} - parameters) $\to$ 64\,MHz system clock. -\item Real reset architecture (\code{reset\_sync.v}): asynchronous - assertion, synchronous deassertion, gated by external POR and - PLL lock. -\item Verified in \textbf{simulation} (Verilator, bit-exact) and real - synthesis + place-and-route (Yosys + nextpnr-ecp5). -\end{itemize}} - -\columnbreak - -{\color{fnDark}\large\bfseries Applications}\\[2pt] -{\footnotesize -\begin{itemize}[leftmargin=1.1em] -\item Deterministic low-latency inference as an SPI peripheral of a - microcontroller or SoC host. -\item Reusable dependency-graph compute fabric, not a single fixed - network topology. -\item Edge AI on compact, INT8-quantized dense/DAG-structured - networks. -\item Off-loading neural workload from a constrained host CPU to - dedicated hardware with predictable, measured throughput. -\end{itemize}} - -\vspace{4pt} -{\color{fnDark}\large\bfseries Target \& toolchain}\\[2pt] -{\footnotesize -\begin{itemize}[leftmargin=1.1em] -\item FPGA: Lattice ECP5 \code{LFE5U-45F-8BG381} ($-8$, CABGA381). -\item Synthesis: Yosys; place\&route: nextpnr-ecp5. -\item Simulation: Verilator (trusted per this project's own DEC-0004 - protocol) and Icarus Verilog (cross-checked). -\item SDRAM: Alliance Memory \code{AS4C4M16SA-6TIN} (4M$\times$16, 8\,MB). -\end{itemize}} -\end{multicols} - -\vspace{2pt} -% --- key parameter table --- -\noindent -{\small\color{fnDark}\bfseries Key parameters (frozen V2 reference configuration)} -\vspace{2pt} - -\noindent -\begin{tabularx}{\textwidth}{L{3.4cm}L{3.8cm}Y} -\toprule -\rowh \thd{Quantity} & \thd{Value} & \thd{Notes} \\ -\midrule -Data precision & INT8 (signed) & \code{DATA\_WIDTH}=8 \\ -\rowa Accumulator & INT32 (signed) & \code{ACC\_WIDTH}=32 \\ -Processors & 4 (N=2 also validated) & \code{N\_PROCESSORS} \\ -\rowa MAC width per processor & 8 & \code{P\_IN}=8 \\ -Activation & ReLU + INT8 saturate & fixed, matches golden model \\ -\rowa External memory & 1 $\times$ SDRAM, 8\,MB & \code{AS4C4M16SA-6TIN}, unified \\ -System clock & 64\,MHz (real P\&R, 8/8 seeds PASS) & 16\,MHz osc.\ $\to$ EHXPLLL \\ -\rowa Bit-exact regression & 256/256, N=2 and N=4 & Verilator, D-Stress workload \\ -Host interface & real SPI (4 pins) & \code{spi\_host\_bridge.v} \\ -\bottomrule -\end{tabularx} - -\vspace{8pt} -\noindent -{\small\color{fnDark}\bfseries System block diagram} -\begin{center} -\begin{tikzpicture}[node distance=6mm and 10mm,font=\footnotesize] - \node[fnblockD,minimum width=26mm,minimum height=13mm] (host){HOST\\{\scriptsize SPI master}}; - \node[fnblockT,right=16mm of host,minimum width=56mm,minimum height=24mm] (eng){}; - \node[anchor=north,font=\footnotesize\bfseries,text=fnDark] at (eng.north){FPGA -- Neural Multiprocessor (N=4)}; - \node[fnreg,fill=white] (spi) at ([yshift=-3mm]eng.center){\code{spi\_host\_bridge} + Dependency Manager}; - \node[fnreg,fill=white,below=2.5mm of spi] (mm){Neural Director $\to$ 4$\times$ Memory Manager $\to$ Neural Processor}; - \node[fnreg,fill=white,above=2.5mm of spi] (be){\code{sdram\_unified\_backend} (W + AR arbitration)}; - \node[fnblock,right=16mm of eng,minimum width=24mm,minimum height=13mm] (ram){SDRAM 8\,MB\\{\scriptsize unified: W+A+R}}; - \draw[fnbus] (host) -- node[fnlbl,above]{SPI} (eng.west|-host); - \draw[fnbus] (eng.east|-ram) -- node[fnlbl,above]{16-bit} (ram); -\end{tikzpicture} -\end{center} -\begin{center}\footnotesize\itshape\color{fnGrey} -Weights, activations and results all share the single physical SDRAM; -the host only registers jobs and reads back results over SPI.\end{center} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/01-overview.aux b/hardware/v2/docs/DatasheetLatex/chapters/01-overview.aux deleted file mode 100644 index 030c6ca..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/01-overview.aux +++ /dev/null @@ -1,53 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\gdef \LT@ii {\LT@entry - {1}{125.81102pt}\LT@entry - {1}{346.50493pt}} -\@writefile{toc}{\contentsline {chapter}{\numberline {1}Overview}{1}{chapter.1}\protected@file@percent } -\@writefile{lof}{\addvspace {10\p@ }} -\@writefile{lot}{\addvspace {10\p@ }} -\@writefile{toc}{\contentsline {section}{\numberline {1.1}Document scope and status labels}{1}{section.1.1}\protected@file@percent } -\newlabel{sec:status-labels}{{1.1}{1}{Document scope and status labels}{section.1.1}{}} -\@writefile{toc}{\contentsline {section}{\numberline {1.2}Frozen reference configuration}{1}{section.1.2}\protected@file@percent } -\@setckpt{chapters/01-overview}{ -\setcounter{page}{2} -\setcounter{equation}{0} -\setcounter{enumi}{3} -\setcounter{enumii}{0} -\setcounter{enumiii}{0} -\setcounter{enumiv}{0} -\setcounter{footnote}{0} -\setcounter{mpfootnote}{0} -\setcounter{part}{0} -\setcounter{chapter}{1} -\setcounter{section}{2} -\setcounter{subsection}{0} -\setcounter{subsubsection}{0} -\setcounter{paragraph}{0} -\setcounter{subparagraph}{0} -\setcounter{figure}{0} -\setcounter{table}{1} -\setcounter{LT@tables}{2} -\setcounter{LT@chunks}{1} -\setcounter{parentequation}{0} -\setcounter{tcbbreakpart}{0} -\setcounter{tcblayer}{0} -\setcounter{tcolorbox@number}{0} -\setcounter{tcbrastercolumn}{1} -\setcounter{tcbrasterrow}{1} -\setcounter{tcbrasternum}{1} -\setcounter{tcbraster}{0} -\setcounter{lstnumber}{1} -\setcounter{tcblisting}{0} -\setcounter{caption@flags}{0} -\setcounter{continuedfloat}{0} -\setcounter{tikztiming@nrows}{0} -\setcounter{tikztimingrows}{0} -\setcounter{tikztimingtrans}{0} -\setcounter{tikztimingtranspos}{0} -\setcounter{section@level}{0} -\setcounter{Item}{3} -\setcounter{Hfootnote}{0} -\setcounter{bookmark@seq@number}{3} -\setcounter{lstlisting}{0} -} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/01-overview.tex b/hardware/v2/docs/DatasheetLatex/chapters/01-overview.tex deleted file mode 100644 index e21e20a..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/01-overview.tex +++ /dev/null @@ -1,64 +0,0 @@ -\chapter{Overview} - -FPGA-Neural V2 succeeds V1 with three architectural changes, all -frozen and verified in this revision: - -\begin{enumerate} -\item \textbf{Neural multiprocessor}: N\_PROCESSORS (4, frozen - reference) independent Neural Processors instead of V1's single - engine, scheduled by a real dependency-graph Dependency Manager and - Neural Director. -\item \textbf{Unified single-SDRAM memory}: one physical Alliance - Memory \code{AS4C4M16SA-6TIN} SDRAM serves weights, activations, - \emph{and} results. V1's PSRAM (\code{IS66WVE4M16EBLL-70BLI}) and - its controller are not part of V2's physical path at all. -\item \textbf{Real physical host interface}: a from-scratch SPI - protocol engine (\code{spi\_host\_bridge.v}) replaces the internal - 110-pin \code{reg\_*} testbench bus as the board-level top's own - physical interface. -\end{enumerate} - -V1 itself (\code{hardware/v1/**}) is untouched and remains the golden, -independently certified reference design; V2 shares no RTL file with -it. - -\section{Document scope and status labels} -\label{sec:status-labels} -This datasheet distinguishes explicitly between: -\begin{itemize} -\item \textbf{RTL verified} -- verified through RTL simulation only. -\item \textbf{Simulation verified} -- verified in simulation for the - specific configuration named. -\item \textbf{Synthesis verified} -- synthesizes cleanly for the - target FPGA (Yosys, real run, zero unintended latches or - multi-driver issues beyond a small, previously-reviewed benign set). -\item \textbf{P\&R verified} -- successfully placed, routed, and - timing-analyzed by nextpnr-ecp5 for a real, ball-assigned LPF. -\item \textbf{Hardware designed} -- schematic/PCB electrically - designed but not fabricated. -\item \textbf{Hardware validated} -- physically tested on fabricated - hardware. -\item \textbf{Silicon validated} -- the actual physical FPGA has been - programmed and tested. -\end{itemize} -As of \datasheetdate, V2 is \textbf{RTL verified}, \textbf{simulation -verified} (bit-exact), \textbf{synthesis verified}, and \textbf{P\&R -verified}. No item in this datasheet is presented as hardware- or -silicon-validated -- no fabricated V2 board exists. See -Chapter~\ref{ch:status} for the complete, itemized status. - -\section{Frozen reference configuration} -\begin{tabularx}{\textwidth}{L{4cm}Y} -\toprule -\rowh \thd{Parameter} & \thd{Value} \\ -\midrule -FPGA & Lattice \code{LFE5U-45F-8BG381}, speed grade $-8$, CABGA381 \\ -\rowa N\_PROCESSORS & 4 (frozen reference; N=2 also fully validated) \\ -P\_IN & 8 (MAC width per processor) \\ -\rowa ACC\_WIDTH & 32 \\ -External memory & 1 $\times$ SDRAM, Alliance Memory \code{AS4C4M16SA-6TIN}, 8\,MB \\ -\rowa Oscillator & 16\,MHz (board-level, external) \\ -System clock & 64\,MHz, generated by a real ECP5 \code{EHXPLLL} \\ -\rowa Host interface & real SPI (4 pins), \code{spi\_host\_bridge.v} \\ -\bottomrule -\end{tabularx} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/02-architecture.aux b/hardware/v2/docs/DatasheetLatex/chapters/02-architecture.aux deleted file mode 100644 index e7d7231..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/02-architecture.aux +++ /dev/null @@ -1,54 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\gdef \LT@iii {\LT@entry - {1}{103.04872pt}\LT@entry - {1}{103.04872pt}\LT@entry - {1}{266.2185pt}} -\@writefile{toc}{\contentsline {chapter}{\numberline {2}Architecture}{2}{chapter.2}\protected@file@percent } -\@writefile{lof}{\addvspace {10\p@ }} -\@writefile{lot}{\addvspace {10\p@ }} -\@writefile{toc}{\contentsline {section}{\numberline {2.1}Compute: Neural Multiprocessor}{2}{section.2.1}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {2.2}Unified single-SDRAM memory}{2}{section.2.2}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {2.3}Read-timing discipline (ERR-0025)}{3}{section.2.3}\protected@file@percent } -\@setckpt{chapters/02-architecture}{ -\setcounter{page}{4} -\setcounter{equation}{0} -\setcounter{enumi}{3} -\setcounter{enumii}{0} -\setcounter{enumiii}{0} -\setcounter{enumiv}{0} -\setcounter{footnote}{0} -\setcounter{mpfootnote}{0} -\setcounter{part}{0} -\setcounter{chapter}{2} -\setcounter{section}{3} -\setcounter{subsection}{0} -\setcounter{subsubsection}{0} -\setcounter{paragraph}{0} -\setcounter{subparagraph}{0} -\setcounter{figure}{0} -\setcounter{table}{1} -\setcounter{LT@tables}{3} -\setcounter{LT@chunks}{1} -\setcounter{parentequation}{0} -\setcounter{tcbbreakpart}{0} -\setcounter{tcblayer}{0} -\setcounter{tcolorbox@number}{0} -\setcounter{tcbrastercolumn}{1} -\setcounter{tcbrasterrow}{1} -\setcounter{tcbrasternum}{1} -\setcounter{tcbraster}{0} -\setcounter{lstnumber}{1} -\setcounter{tcblisting}{0} -\setcounter{caption@flags}{0} -\setcounter{continuedfloat}{0} -\setcounter{tikztiming@nrows}{0} -\setcounter{tikztimingrows}{0} -\setcounter{tikztimingtrans}{0} -\setcounter{tikztimingtranspos}{0} -\setcounter{section@level}{0} -\setcounter{Item}{3} -\setcounter{Hfootnote}{0} -\setcounter{bookmark@seq@number}{7} -\setcounter{lstlisting}{0} -} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/02-architecture.tex b/hardware/v2/docs/DatasheetLatex/chapters/02-architecture.tex deleted file mode 100644 index a170187..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/02-architecture.tex +++ /dev/null @@ -1,86 +0,0 @@ -\chapter{Architecture} - -\section{Compute: Neural Multiprocessor} -Each of the \code{N\_PROCESSORS} Neural Processors is an independent -INT8 datapath: \code{P\_IN}=8 parallel multipliers feeding a balanced -binary adder tree into a 32-bit accumulator, followed by ReLU and INT8 -saturation -- byte-for-byte identical to \code{neural\_processor.v}, -unmodified since before the V2 single-SDRAM freeze. Job dispatch is a -real dependency-graph pipeline: - -\begin{center} -\begin{tikzpicture}[node distance=5mm and 6mm,font=\scriptsize] - \node[fnreg] (host) {SPI host\\bridge}; - \node[fnreg,right=of host] (dm) {Dependency\\Manager}; - \node[fnreg,right=of dm] (dir) {Neural\\Director}; - \node[fnreg,below=of dir] (mm) {Memory Manager\\(per slot)}; - \node[fnreg,left=of mm] (np) {Neural\\Processor}; - \draw[fnarrow] (host) -- (dm); - \draw[fnarrow] (dm) -- (dir); - \draw[fnarrow] (dir) -- (mm); - \draw[fnarrow] (mm) -- (np); -\end{tikzpicture} -\end{center} - -The Dependency Manager holds a per-node table (state, required/ -resolved producer count, job descriptor fields) and hands READY nodes -to the Director one at a time (valid/ready, backpressure-safe). The -Director allocates the first free processor slot (first-free, not -load-balanced) and frees it the instant that slot's job completes. - -\section{Unified single-SDRAM memory} -\begin{center} -\begin{tikzpicture}[node distance=6mm and 10mm,font=\footnotesize] - \node[fnblockT,minimum width=50mm,minimum height=20mm] (fpga){}; - \node[anchor=north,font=\bfseries,text=fnDark] at (fpga.north){FPGA}; - \node[fnreg,fill=white] (np) at ([yshift=2mm]fpga.center){4$\times$ Neural Processor}; - \node[fnreg,fill=white,below=2mm of np] (be){Unified SDRAM Backend / Arbiter}; - \node[fnblock,right=16mm of fpga,minimum height=20mm] (ram){\code{AS4C4M16SA-6TIN}\\Weights\\Activations\\Results}; - \draw[fnbus] (fpga.east|-be) -- node[fnlbl,above]{16-bit SDRAM bus} (ram); -\end{tikzpicture} -\end{center} - -\code{sdram\_unified\_backend.v} owns exactly one \code{sdram\_ -controller.v} instance and presents two logical ports: -\begin{itemize} -\item \textbf{W} (weight fetch): 64-bit, read-only, a 4-entry - fully-associative ``other half'' cache (round-robin eviction -- - safe under any sizing, since an evicted-too-early entry only costs - an extra real fetch, never wrong data). -\item \textbf{AR} (activation fill + result write-back): 16-bit, - read/write, byte-maskable via real SDR SDRAM DQM semantics - (\code{lb\_n}/\code{ub\_n}). -\end{itemize} -Both ports are, in turn, each arbitrated across the N\_PROCESSORS -slots by a generic, reused \code{slot\_mem\_arbiter} (a proven, -pending-latch-based, single-owner-until-ready design used identically -throughout this project). - -\subsection*{Official V2 memory map} -\begin{tabularx}{\textwidth}{L{3.2cm}L{3.2cm}Y} -\toprule -\rowh \thd{Region} & \thd{Base address} & \thd{Notes} \\ -\midrule -Weights & \code{0x010000} & 1\,MB-aligned \\ -\rowa Activations & \code{0x200000} & 1\,MB-aligned \\ -Results & \code{0x300000} & 1\,MB-aligned \\ -\bottomrule -\end{tabularx} -All three regions are non-overlapping within the single 8\,MB -(\code{0x000000}--\code{0x7FFFFF}) SDRAM address space. Base addresses -are host-programmable per job (via \code{WRITE\_JOB}'s own -\code{x\_base}/\code{w\_base}/\code{result\_addr} fields), not hard-coded -in the datapath. - -\section{Read-timing discipline (ERR-0025)} -The shared weight and activation SRAMs (\code{nms\_weight\_packed.v}, -\code{nms\_activation\_replicated.v}) use \textbf{combinational} read -ports, matching the exact 1-cycle latency assumption of the per-slot -Memory Manager's own pipelined read-ahead consumer. An earlier, -registered-read implementation added one uncounted cycle of latency -that a busy, multi-tile job's own prefetch lead time always absorbed -invisibly, but that an uncontested single-tile job exposed on its -first (only) tile -- found and fixed via this revision's own -board-level SPI integration testing, with zero regression to the -existing bit-exact regression suite (identical cycle counts before and -after the fix). diff --git a/hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.aux b/hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.aux deleted file mode 100644 index f1de3f1..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.aux +++ /dev/null @@ -1,49 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\@writefile{toc}{\contentsline {chapter}{\numberline {3}Clock and reset architecture}{4}{chapter.3}\protected@file@percent } -\@writefile{lof}{\addvspace {10\p@ }} -\@writefile{lot}{\addvspace {10\p@ }} -\@writefile{toc}{\contentsline {section}{\numberline {3.1}Clock generation}{4}{section.3.1}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {3.2}Reset architecture}{4}{section.3.2}\protected@file@percent } -\@setckpt{chapters/03-clock-reset}{ -\setcounter{page}{5} -\setcounter{equation}{0} -\setcounter{enumi}{3} -\setcounter{enumii}{0} -\setcounter{enumiii}{0} -\setcounter{enumiv}{0} -\setcounter{footnote}{0} -\setcounter{mpfootnote}{0} -\setcounter{part}{0} -\setcounter{chapter}{3} -\setcounter{section}{2} -\setcounter{subsection}{0} -\setcounter{subsubsection}{0} -\setcounter{paragraph}{0} -\setcounter{subparagraph}{0} -\setcounter{figure}{0} -\setcounter{table}{0} -\setcounter{LT@tables}{3} -\setcounter{LT@chunks}{1} -\setcounter{parentequation}{0} -\setcounter{tcbbreakpart}{0} -\setcounter{tcblayer}{0} -\setcounter{tcolorbox@number}{0} -\setcounter{tcbrastercolumn}{1} -\setcounter{tcbrasterrow}{1} -\setcounter{tcbrasternum}{1} -\setcounter{tcbraster}{0} -\setcounter{lstnumber}{1} -\setcounter{tcblisting}{0} -\setcounter{caption@flags}{0} -\setcounter{continuedfloat}{0} -\setcounter{tikztiming@nrows}{0} -\setcounter{tikztimingrows}{0} -\setcounter{tikztimingtrans}{0} -\setcounter{tikztimingtranspos}{0} -\setcounter{section@level}{0} -\setcounter{Item}{3} -\setcounter{Hfootnote}{0} -\setcounter{bookmark@seq@number}{10} -\setcounter{lstlisting}{0} -} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.tex b/hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.tex deleted file mode 100644 index c79ea64..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.tex +++ /dev/null @@ -1,54 +0,0 @@ -\chapter{Clock and reset architecture} - -\section{Clock generation} -\begin{center} -\begin{tikzpicture}[node distance=8mm and 14mm,font=\footnotesize] - \node[fnblockD] (osc){16\,MHz\\oscillator}; - \node[fnblockT,right=of osc] (pll){ECP5 \code{EHXPLLL}}; - \node[fnblock,right=of pll] (sys){system clock\\64\,MHz}; - \draw[fnbus] (osc) -- (pll); - \draw[fnbus] (pll) -- (sys); -\end{tikzpicture} -\end{center} - -\code{ecp5\_pll\_sys\_clk.v} instantiates a real \code{EHXPLLL}, with -parameters generated by Project Trellis's own \code{ecppll} utility -(not hand-derived): \code{CLKI\_DIV}=1, \code{CLKFB\_DIV}=4, -\code{CLKOP\_DIV}=9, \code{FEEDBK\_PATH}=\code{CLKOP}, giving a real -VCO frequency of 576\,MHz (within the ECP5's documented 400--800\,MHz -range) and an exact, zero-error 64\,MHz output ($16 \times 4 / 1$, -divided by 9 at the VCO). 64\,MHz was chosen over 80\,MHz specifically -because it is the highest frequency at which \emph{all} measured P\&R -seeds close timing with real margin -- see Chapter~\ref{ch:pinout} for -the full 8-seed table. - -Simulation note: \code{EHXPLLL} has no open, licensable behavioral -model (Lattice ships it only inside encrypted simulation libraries). -\code{ecp5\_pll\_sys\_clk.v} therefore provides a declared, -simulation-only bypass under a \code{`SIM} define (\code{clk\_sys} -tied directly to \code{clk\_16mhz}, \code{locked} tied high) -- this is -not, and does not claim to be, a simulation of real PLL lock timing. - -\section{Reset architecture} -\begin{center} -\begin{tikzpicture}[node distance=8mm and 14mm,font=\footnotesize] - \node[fnblockD] (por){External POR\\/ supervisor}; - \node[fnblockT,right=of por] (rs){\code{reset\_sync.v}}; - \node[fnblock,right=of rs] (rst){\code{rst}\\(sync-deassert)}; - \node[fnblock,below=6mm of rs] (lock){PLL \code{locked}}; - \draw[fnbus] (por) -- (rs); - \draw[fnbus] (rs) -- (rst); - \draw[fnbus] (lock) -- (rs); -\end{tikzpicture} -\end{center} - -\code{reset\_sync.v} is a standard async-assert/sync-deassert bridge: -\code{rst} is asserted \emph{immediately} (combinationally) whenever -either the external POR (\code{ext\_rst\_n}, active-low) is asserted -\emph{or} the PLL has not yet reported lock, and is released only -after two flip-flops of the system clock following both conditions -clearing -- so no downstream synchronous logic (SDRAM controller, -compute datapath, SPI bridge) ever sees an asynchronous release edge. -This is a real, RTL-implemented mechanism, not a placeholder: it is -included, unmodified, in every synthesis and P\&R run reported in this -datasheet. diff --git a/hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.aux b/hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.aux deleted file mode 100644 index ee14fac..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.aux +++ /dev/null @@ -1,54 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\gdef \LT@iv {\LT@entry - {1}{68.9055pt}\LT@entry - {1}{103.04872pt}\LT@entry - {1}{300.36172pt}} -\@writefile{toc}{\contentsline {chapter}{\numberline {4}Host interface (SPI)}{5}{chapter.4}\protected@file@percent } -\@writefile{lof}{\addvspace {10\p@ }} -\@writefile{lot}{\addvspace {10\p@ }} -\@writefile{toc}{\contentsline {section}{\numberline {4.1}Opcodes}{5}{section.4.1}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {4.2}Verification}{5}{section.4.2}\protected@file@percent } -\newlabel{sec:host}{{4.2}{5}{Verification}{section.4.2}{}} -\@setckpt{chapters/04-host-interface}{ -\setcounter{page}{6} -\setcounter{equation}{0} -\setcounter{enumi}{3} -\setcounter{enumii}{0} -\setcounter{enumiii}{0} -\setcounter{enumiv}{0} -\setcounter{footnote}{0} -\setcounter{mpfootnote}{0} -\setcounter{part}{0} -\setcounter{chapter}{4} -\setcounter{section}{2} -\setcounter{subsection}{0} -\setcounter{subsubsection}{0} -\setcounter{paragraph}{0} -\setcounter{subparagraph}{0} -\setcounter{figure}{0} -\setcounter{table}{1} -\setcounter{LT@tables}{4} -\setcounter{LT@chunks}{1} -\setcounter{parentequation}{0} -\setcounter{tcbbreakpart}{0} -\setcounter{tcblayer}{0} -\setcounter{tcolorbox@number}{0} -\setcounter{tcbrastercolumn}{1} -\setcounter{tcbrasterrow}{1} -\setcounter{tcbrasternum}{1} -\setcounter{tcbraster}{0} -\setcounter{lstnumber}{1} -\setcounter{tcblisting}{0} -\setcounter{caption@flags}{0} -\setcounter{continuedfloat}{0} -\setcounter{tikztiming@nrows}{0} -\setcounter{tikztimingrows}{0} -\setcounter{tikztimingtrans}{0} -\setcounter{tikztimingtranspos}{0} -\setcounter{section@level}{0} -\setcounter{Item}{3} -\setcounter{Hfootnote}{0} -\setcounter{bookmark@seq@number}{13} -\setcounter{lstlisting}{0} -} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.tex b/hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.tex deleted file mode 100644 index 40655ab..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.tex +++ /dev/null @@ -1,47 +0,0 @@ -\chapter{Host interface (SPI)} - -\code{spi\_host\_bridge.v} is the real, physical host interface for -V2's board-level top (\code{fpga\_neural\_v2\_top.v}). It replaces the -internal 110-pin \code{reg\_*} bus (a simulation/testbench convenience -that must never be represented as a physical board interface) with 4 -real pins: \sig{spi\_sclk}, \sig{spi\_mosi}, \sig{spi\_miso}, -\sig{spi\_cs\_n}. Mode 0 (CPOL=0/CPHA=0), MSB-first, one opcode per -CS-low period. - -\section{Opcodes} -\begin{tabularx}{\textwidth}{L{2cm}L{3.2cm}Y} -\toprule -\rowh \thd{Opcode} & \thd{Name} & \thd{Function} \\ -\midrule -\op{0x10} & \op{WRITE\_JOB} & 15-byte payload: node id, required - dependency count, producer ids, \sig{x\_base}, \sig{w\_base}, - \sig{n\_tiles}, \sig{result\_addr}. Registers one Dependency Manager - job; \sig{reg\_valid} is held until the same-cycle - \sig{reg\_valid}\,\&\&\,\sig{reg\_ready} acceptance fires. \\ -\rowa \op{0x01} & \op{WRITE\_MEM} & word-addressed raw SDRAM write, - via a second, arbitrated AR port. \\ -\op{0x02} & \op{READ\_MEM} & word-addressed raw SDRAM read. \\ -\rowa \op{0x20} & \op{STATUS} & 1-byte status: job-busy, mem-busy, - sticky last-job-accepted. \\ -\op{0x0F} & \op{RESET} & pulses a soft-reset into the compute+memory - core (not the SPI bridge's own state, avoiding a self-reset hazard). \\ -\bottomrule -\end{tabularx} - -\section{Verification} -\label{sec:host} -The protocol engine is verified in two independent ways: -\begin{itemize} -\item \textbf{Isolated}: \code{tb\_spi\_host\_bridge.v}, 18/18 PASS -- - every opcode, including a real DQM-style byte-masked - \op{WRITE\_MEM}. -\item \textbf{End-to-end}: \code{tb\_fpga\_neural\_v2\_top\_smoke.v}, - 11/11 PASS -- a single job, two jobs back-to-back, two jobs across a - realistic $\sim$85\,\textmu s SPI-paced gap, and a parametric sweep - of inter-job gaps (100\,ns / 5\,000\,ns / 50\,000\,ns), all checked - bit-exact against a software golden model via a real SDRAM backdoor - readback. -\end{itemize} -Both regressions pass with \textbf{zero regression} to the existing -N=2/N=4 D-Stress bit-exact baseline (identical cycle counts before and -after every fix applied during this interface's own development). diff --git a/hardware/v2/docs/DatasheetLatex/chapters/05-pinout-timing.aux b/hardware/v2/docs/DatasheetLatex/chapters/05-pinout-timing.aux deleted file mode 100644 index 97cbc1a..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/05-pinout-timing.aux +++ /dev/null @@ -1,64 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\gdef \LT@v {\LT@entry - {1}{85.97733pt}\LT@entry - {1}{57.52458pt}\LT@entry - {1}{40.45274pt}\LT@entry - {1}{288.3613pt}} -\gdef \LT@vi {\LT@entry - {1}{108.73918pt}\LT@entry - {1}{363.57677pt}} -\@writefile{toc}{\contentsline {chapter}{\numberline {5}Pinout, place-and-route, and timing}{6}{chapter.5}\protected@file@percent } -\@writefile{lof}{\addvspace {10\p@ }} -\@writefile{lot}{\addvspace {10\p@ }} -\newlabel{ch:pinout}{{5}{6}{Pinout, place-and-route, and timing}{chapter.5}{}} -\@writefile{toc}{\contentsline {section}{\numberline {5.1}Final pinout}{6}{section.5.1}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {5.2}Synthesis (real, this revision)}{6}{section.5.2}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {5.3}Place and route: 8-seed timing table}{6}{section.5.3}\protected@file@percent } -\gdef \LT@vii {\LT@entry - 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-\section{Final pinout} -All 44 top-level signals of \code{fpga\_neural\_v2\_top.v} carry a -real ball assignment (\code{v2\_board\_top.lpf}), sourced from the -official Lattice pinout CSV (rev.\ 3.0) and confirmed by a real, -successful nextpnr-ecp5 P\&R run -- \textbf{no placeholders}. - -\begin{tabularx}{\textwidth}{L{2.6cm}L{1.6cm}L{1cm}Y} -\toprule -\rowh \thd{Signal} & \thd{Ball} & \thd{Bank} & \thd{Notes} \\ -\midrule -\sig{osc\_clk} & H5 & -- & reused from V1's own validated LPF \\ -\rowa \sig{ext\_rst\_n} & B4 & -- & reused from V1's own validated LPF \\ -\sig{spi\_sclk} & L3 & 6/7 & real, plain GPIO \\ -\rowa \sig{spi\_mosi} & M3 & 6/7 & real, plain GPIO \\ -\sig{spi\_miso} & L2 & 6/7 & real, plain GPIO \\ -\rowa \sig{spi\_cs\_n} & N2 & 6/7 & real, plain GPIO \\ -\sig{pll\_locked} & L1 & 6/7 & real, plain GPIO (bring-up/debug) \\ -\rowa \sig{sdram\_*} (37 signals) & see LPF & 6/7 & control/address/data/mask bus \\ -\bottomrule -\end{tabularx} - -All signals are assumed LVCMOS33, matching banks 6/7's own real VCCIO -range and the SDRAM device's own 3.3\,V requirement (not yet -independently cross-verified at the schematic/PCB level -- a -disclosed WARNING, not a blocker). - -\section{Synthesis (real, this revision)} -Yosys \code{synth\_ecp5}, target \code{fpga\_neural\_v2\_top}, real -run, zero CHECK-pass problems: - -\begin{tabularx}{\textwidth}{L{3.4cm}Y} -\toprule -\rowh \thd{Resource} & \thd{Count} \\ -\midrule -\code{TRELLIS\_FF} & 6\,322 \\ -\rowa \code{TRELLIS\_COMB} (LUT4 equiv.) & 7\,084 \\ -\code{MULT18X18D} & 32 (=\,4 processors $\times$ 8-wide MAC) \\ -\rowa \code{EHXPLLL} & 1 (real PLL, confirmed present) \\ -\code{DP16KD} & 0 (all small SRAMs synthesize to distributed RAM) \\ -\bottomrule -\end{tabularx} -38 unique warnings (43 total), all matching this project's own -previously-reviewed, benign baseline set (a known \code{genvar} -multi-driver artifact in \code{neural\_processor.v}, small-array-to- -register unrolling, and the real SDRAM \code{DQ} tristate bus) -- no -new warnings introduced by the SPI bridge, PLL, or reset synchronizer. - -\section{Place and route: 8-seed timing table} -Real nextpnr-ecp5 P\&R, same final top and LPF, 8 distinct seeds, -target 64\,MHz: - -\begin{tabularx}{\textwidth}{L{1.6cm}L{2.4cm}L{2cm}Y} -\toprule -\rowh \thd{Seed} & \thd{Fmax (MHz)} & \thd{Result} & \thd{Slack @ 64\,MHz} \\ -\midrule -1 & 73.17 & \PASS & +1.958\,ns \\ -\rowa 2 & 68.90 & \PASS & +1.111\,ns \\ -3 & 72.10 & \PASS & +1.755\,ns \\ -\rowa 4 & 68.51 & \PASS & +1.029\,ns (worst) \\ -5 & 69.29 & \PASS & +1.193\,ns \\ -\rowa 6 & 73.03 & \PASS & +1.931\,ns \\ -7 & 74.17 & \PASS & +2.143\,ns (best) \\ -\rowa 8 & 70.10 & \PASS & +1.360\,ns \\ -\bottomrule -\end{tabularx} -\textbf{8/8 seeds PASS at 64\,MHz} -- worst 68.51\,MHz, best -74.17\,MHz, mean 71.16\,MHz. Every seed also fits with real routing -margin: \code{TRELLIS\_IO}=44/245 (17\%), zero unrouted nets, zero -placement/routing errors, across all 8 runs. - -The critical path is routing-dominated (typ.\ 15--20\% logic / 80--85\% -routing) and alternates, seed to seed, between two comparably-tight -structures already documented in this project's own prior timing -investigations: \code{dependency\_manager.v}'s own wide priority-encoder -scan, and \code{sdram\_unified\_backend.v}'s own weight-cache -hit-index logic -- neither is a new defect introduced by this -revision. - -Hold timing was not separately reported by this toolchain's standard -summary output and was not independently analyzed this round (an -honest, disclosed OPEN item, not a fabricated PASS). diff --git a/hardware/v2/docs/DatasheetLatex/chapters/06-power-configuration.aux b/hardware/v2/docs/DatasheetLatex/chapters/06-power-configuration.aux deleted file mode 100644 index b541cc1..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/06-power-configuration.aux +++ /dev/null @@ -1,54 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\gdef \LT@viii {\LT@entry - {1}{85.97733pt}\LT@entry - {1}{74.59596pt}\LT@entry - {1}{311.74266pt}} -\@writefile{toc}{\contentsline {chapter}{\numberline {6}Power, SDRAM electrical, and configuration}{8}{chapter.6}\protected@file@percent } -\@writefile{lof}{\addvspace {10\p@ }} -\@writefile{lot}{\addvspace {10\p@ }} -\@writefile{toc}{\contentsline {section}{\numberline {6.1}Power architecture -- status: OPEN}{8}{section.6.1}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {6.2}SDRAM electrical / timing sign-off -- status: PARTIAL}{8}{section.6.2}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {6.3}Configuration -- status: OPEN}{8}{section.6.3}\protected@file@percent } -\@setckpt{chapters/06-power-configuration}{ -\setcounter{page}{9} -\setcounter{equation}{0} -\setcounter{enumi}{3} -\setcounter{enumii}{0} -\setcounter{enumiii}{0} -\setcounter{enumiv}{0} -\setcounter{footnote}{0} -\setcounter{mpfootnote}{0} -\setcounter{part}{0} -\setcounter{chapter}{6} -\setcounter{section}{3} -\setcounter{subsection}{0} -\setcounter{subsubsection}{0} -\setcounter{paragraph}{0} -\setcounter{subparagraph}{0} -\setcounter{figure}{0} -\setcounter{table}{1} -\setcounter{LT@tables}{8} -\setcounter{LT@chunks}{1} -\setcounter{parentequation}{0} -\setcounter{tcbbreakpart}{0} -\setcounter{tcblayer}{0} -\setcounter{tcolorbox@number}{0} -\setcounter{tcbrastercolumn}{1} -\setcounter{tcbrasterrow}{1} -\setcounter{tcbrasternum}{1} -\setcounter{tcbraster}{0} -\setcounter{lstnumber}{1} -\setcounter{tcblisting}{0} -\setcounter{caption@flags}{0} -\setcounter{continuedfloat}{0} -\setcounter{tikztiming@nrows}{0} -\setcounter{tikztimingrows}{0} -\setcounter{tikztimingtrans}{0} -\setcounter{tikztimingtranspos}{0} -\setcounter{section@level}{0} -\setcounter{Item}{3} -\setcounter{Hfootnote}{0} -\setcounter{bookmark@seq@number}{21} -\setcounter{lstlisting}{0} -} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/06-power-configuration.tex b/hardware/v2/docs/DatasheetLatex/chapters/06-power-configuration.tex deleted file mode 100644 index b9ce0b4..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/06-power-configuration.tex +++ /dev/null @@ -1,42 +0,0 @@ -\chapter{Power, SDRAM electrical, and configuration} - -\section{Power architecture -- status: OPEN} -Rail \emph{voltages} are real, DATASHEET VALUEs from the actual ECP5 -and \code{AS4C4M16SA-6TIN} datasheets; regulator selection, current -budget, and decoupling are \textbf{not} finalized in this revision. - -\begin{tabularx}{\textwidth}{L{2.6cm}L{2.2cm}Y} -\toprule -\rowh \thd{Rail} & \thd{Nominal} & \thd{Status} \\ -\midrule -VCC (core) & 1.1\,V & DATASHEET VALUE; regulator TBD \\ -\rowa VCCAUX & 2.5\,V & DATASHEET VALUE; regulator TBD \\ -VCCIO 6/7 (SDRAM) & 3.3\,V (assumed) & matches SDRAM's own LVCMOS33 need; not independently re-verified \\ -\rowa SDRAM VDD/VDDQ & 3.3\,V & DATASHEET VALUE (\code{AS4C4M16SA-6TIN}) \\ -\bottomrule -\end{tabularx} - -No real power-estimation tool was run against the actual synthesized -netlist this revision; a real, computed current budget therefore -remains an OPEN item, not an invented number. - -\section{SDRAM electrical / timing sign-off -- status: PARTIAL} -\code{AS4C4M16SA-6TIN} is a standard JEDEC SDR SDRAM; the controller -(\code{sdram\_controller.v}) implements a real power-up wait, mode -register set, and periodic AUTO REFRESH, verified functionally in -simulation (init/refresh/read/write/burst/masked-write, 40 real -refresh events per D-Stress run, zero corruption). A byte-for-byte -cross-check of the controller's own timing constants against the -device's real datasheet parameters (CAS latency, \sig{tRCD}, -\sig{tRP}, refresh interval, setup/hold) was \textbf{not} independently -re-performed this revision -- simulation-level correctness is -established; a dedicated datasheet-parameter audit remains an OPEN -item before board layout. - -\section{Configuration -- status: OPEN} -Standard ECP5 JTAG (\sig{TDI}/\sig{TDO}/\sig{TCK}/\sig{TMS}) and -configuration (\sig{PROGRAMN}/\sig{INITN}/\sig{DONE}/\sig{CCLK}) pins -are identified and standard (real balls listed in -\code{docs/pinouts.md}); JTAG remains available regardless of boot -mode. No configuration-flash part number has been selected, and no -SPI-flash-boot-vs-JTAG-only decision has been made this revision. diff --git a/hardware/v2/docs/DatasheetLatex/chapters/07-benchmarks.aux b/hardware/v2/docs/DatasheetLatex/chapters/07-benchmarks.aux deleted file mode 100644 index 7eeaccb..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/07-benchmarks.aux +++ /dev/null @@ -1,58 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\gdef \LT@ix {\LT@entry - {1}{68.9055pt}\LT@entry - {1}{80.28644pt}\LT@entry - {1}{80.28644pt}\LT@entry - {1}{242.83757pt}} -\gdef \LT@x {\LT@entry - {1}{137.19194pt}\LT@entry - {1}{335.12401pt}} -\@writefile{toc}{\contentsline {chapter}{\numberline {7}Benchmarks}{9}{chapter.7}\protected@file@percent } -\@writefile{lof}{\addvspace {10\p@ }} -\@writefile{lot}{\addvspace {10\p@ }} -\@writefile{toc}{\contentsline {section}{\numberline {7.1}Internal benchmark: D-Stress workload}{9}{section.7.1}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {7.2}Host-interface pacing benchmark}{9}{section.7.2}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {7.3}Software reference comparison}{9}{section.7.3}\protected@file@percent } -\@setckpt{chapters/07-benchmarks}{ -\setcounter{page}{11} -\setcounter{equation}{0} -\setcounter{enumi}{3} -\setcounter{enumii}{0} -\setcounter{enumiii}{0} -\setcounter{enumiv}{0} -\setcounter{footnote}{0} -\setcounter{mpfootnote}{0} -\setcounter{part}{0} -\setcounter{chapter}{7} -\setcounter{section}{3} -\setcounter{subsection}{0} -\setcounter{subsubsection}{0} -\setcounter{paragraph}{0} -\setcounter{subparagraph}{0} -\setcounter{figure}{0} -\setcounter{table}{2} -\setcounter{LT@tables}{10} -\setcounter{LT@chunks}{1} -\setcounter{parentequation}{0} -\setcounter{tcbbreakpart}{0} -\setcounter{tcblayer}{0} -\setcounter{tcolorbox@number}{0} -\setcounter{tcbrastercolumn}{1} -\setcounter{tcbrasterrow}{1} -\setcounter{tcbrasternum}{1} -\setcounter{tcbraster}{0} -\setcounter{lstnumber}{1} -\setcounter{tcblisting}{0} -\setcounter{caption@flags}{0} -\setcounter{continuedfloat}{0} -\setcounter{tikztiming@nrows}{0} -\setcounter{tikztimingrows}{0} -\setcounter{tikztimingtrans}{0} -\setcounter{tikztimingtranspos}{0} -\setcounter{section@level}{0} -\setcounter{Item}{3} -\setcounter{Hfootnote}{0} -\setcounter{bookmark@seq@number}{25} -\setcounter{lstlisting}{0} -} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/07-benchmarks.tex b/hardware/v2/docs/DatasheetLatex/chapters/07-benchmarks.tex deleted file mode 100644 index 4164dd8..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/07-benchmarks.tex +++ /dev/null @@ -1,67 +0,0 @@ -\chapter{Benchmarks} - -\section{Internal benchmark: D-Stress workload} -256 independent neurons, 128 inputs each (16 tiles of \code{P\_IN}=8), -one shared activation vector -- the project's own existing, reused -benchmark, run against the final, frozen RTL via Verilator. - -\begin{tabularx}{\textwidth}{L{2cm}L{2.4cm}L{2.4cm}Y} -\toprule -\rowh \thd{Config} & \thd{Cycles} & \thd{Correctness} & \thd{Latency @ 64\,MHz} \\ -\midrule -N=2 & 49\,788 & 256/256 \PASS & 777.9\,\textmu s \\ -\rowa N=4 & 49\,771 & 256/256 \PASS & 777.7\,\textmu s \\ -\bottomrule -\end{tabularx} - -Cycle counts are \textbf{simulation-verified} (Verilator, bit-exact) -and unchanged before/after the ERR-0025 read-timing fix. Latency at -64\,MHz is a \textbf{derived} figure (cycles~/~clock), not an -independently re-simulated wall-clock measurement, and is not a -measured-hardware number (no fabricated board exists). - -N=4 barely improves over N=2 on this specific workload -($49\,771$ vs.\ $49\,788$ cycles) because the workload is dominated by -shared-SDRAM and shared-activation-fill traffic, not by raw MAC -throughput -- consistent with this project's own prior STEP17/18 -memory-bound-vs-compute-bound findings, not a new anomaly. - -\section{Host-interface pacing benchmark} -The board-level SPI smoke test (\S\ref{sec:host}) exercises single-job, -back-to-back, and gap-swept (100\,ns/5\,000\,ns/50\,000\,ns/$\sim$85\,\textmu s) -dispatch patterns -- all 11/11 bit-exact -- establishing that realistic -host pacing does not, itself, change correctness (only the STEP19-era -registered-read bug did, and that is fixed). - -\section{Software reference comparison} -\textbf{No physical ESP32 (or other embedded MCU) hardware is -available in this environment.} A real ESP32 benchmark was -\emph{not} performed, and no ESP32 number is estimated or invented -here -- this is a disclosed OPEN item, not a claimed result. - -As an honest, clearly-labeled illustrative data point only, the -identical D-Stress arithmetic (256 neurons $\times$ 128 INT8 MACs, -ReLU + INT8 saturate) was compiled (\code{cc~-O2}) and run on the -\emph{development machine itself} (Apple M4, arm64 -- \textbf{not} -an embedded target): - -\begin{tabularx}{\textwidth}{L{4.4cm}Y} -\toprule -\rowh \thd{Metric} & \thd{Value} \\ -\midrule -Platform & Apple M4 (arm64), \code{cc -O2}, single-threaded scalar C \\ -\rowa Latency, full 256-neuron batch & 1.28\,\textmu s \\ -Throughput & $2.56\times10^{10}$ MAC/s \\ -\bottomrule -\end{tabularx} - -On this specific, tiny workload, a modern, auto-vectorizing, -multi-GHz superscalar CPU outperforms the current FPGA design's -\emph{simulated} cycle count in raw latency. This is reported -honestly rather than omitted: FPGA-Neural V2's real value proposition -is a deterministic, low-power, standalone SDRAM-attached accelerator -for hosts that do \emph{not} have this class of CPU (e.g.\ an -ESP32-class microcontroller) -- not a claim of outperforming a -desktop-class processor on this workload size. A real, meaningful -software baseline for THAT comparison requires the actual embedded -target hardware, which remains unavailable this revision. diff --git a/hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.aux b/hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.aux deleted file mode 100644 index 484b72c..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.aux +++ /dev/null @@ -1,54 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\gdef \LT@xi {\LT@entry - {1}{194.09746pt}\LT@entry - {1}{278.21849pt}} -\@writefile{toc}{\contentsline {chapter}{\numberline {8}Chip readiness and roadmap}{11}{chapter.8}\protected@file@percent } -\@writefile{lof}{\addvspace {10\p@ }} -\@writefile{lot}{\addvspace {10\p@ }} -\newlabel{ch:status}{{8}{11}{Chip readiness and roadmap}{chapter.8}{}} -\@writefile{toc}{\contentsline {section}{\numberline {8.1}Precise readiness checklist}{11}{section.8.1}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {8.2}Final answer}{11}{section.8.2}\protected@file@percent } -\@writefile{toc}{\contentsline {section}{\numberline {8.3}Roadmap}{11}{section.8.3}\protected@file@percent } -\@setckpt{chapters/08-status-roadmap}{ -\setcounter{page}{13} -\setcounter{equation}{0} -\setcounter{enumi}{3} -\setcounter{enumii}{0} -\setcounter{enumiii}{0} -\setcounter{enumiv}{0} -\setcounter{footnote}{0} -\setcounter{mpfootnote}{0} -\setcounter{part}{0} -\setcounter{chapter}{8} -\setcounter{section}{3} -\setcounter{subsection}{0} -\setcounter{subsubsection}{0} -\setcounter{paragraph}{0} -\setcounter{subparagraph}{0} -\setcounter{figure}{0} -\setcounter{table}{1} -\setcounter{LT@tables}{11} -\setcounter{LT@chunks}{1} -\setcounter{parentequation}{0} -\setcounter{tcbbreakpart}{0} -\setcounter{tcblayer}{0} -\setcounter{tcolorbox@number}{0} -\setcounter{tcbrastercolumn}{1} -\setcounter{tcbrasterrow}{1} -\setcounter{tcbrasternum}{1} -\setcounter{tcbraster}{0} -\setcounter{lstnumber}{1} -\setcounter{tcblisting}{0} -\setcounter{caption@flags}{0} -\setcounter{continuedfloat}{0} -\setcounter{tikztiming@nrows}{0} -\setcounter{tikztimingrows}{0} -\setcounter{tikztimingtrans}{0} -\setcounter{tikztimingtranspos}{0} -\setcounter{section@level}{0} -\setcounter{Item}{3} -\setcounter{Hfootnote}{0} -\setcounter{bookmark@seq@number}{29} -\setcounter{lstlisting}{0} -} diff --git a/hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.tex b/hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.tex deleted file mode 100644 index 13d11df..0000000 --- a/hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.tex +++ /dev/null @@ -1,57 +0,0 @@ -\chapter{Chip readiness and roadmap} -\label{ch:status} - -\section{Precise readiness checklist} -Per this project's own standing rule: no item below is checked unless -genuinely verified; no OPEN item is masked as a future enhancement. - -\begin{tabularx}{\textwidth}{L{6.4cm}Y} -\toprule -\rowh \thd{Item} & \thd{Status} \\ -\midrule -RTL frozen, zero V1 dependency & \OK \\ -\rowa Bit-exact regression (N=2, N=4) & \OK\ (256/256, Verilator) \\ -Real SPI host interface, end-to-end & \OK\ (11/11, zero regression) \\ -\rowa SDRAM validation (init/refresh/masked-write) & \OK \\ -Synthesis (final top, real Yosys run) & \OK\ (0 CHECK-pass problems) \\ -\rowa Place\&route (8 real seeds) & \OK\ (8/8 fit, routed, zero errors) \\ -Timing closure @ 64\,MHz & \OK\ (8/8 seeds PASS, worst 68.51\,MHz) \\ -\rowa Final pinout (44/44 top-level signals) & \OK\ (real balls, P\&R-confirmed) \\ -Hold-time analysis & OPEN (tool limitation, see PRE\_PCB\_VERIFICATION.md \S6) \\ -\rowa Power: rail voltages & OK (real datasheet values) \\ -Power: regulator selection / current budget & OPEN \\ -\rowa SDRAM datasheet-parameter cross-check & \OK\ (real AS4C4M16SA-6TIN Table 17 audit; found and fixed ERR-0026, tMRD unit mismatch) \\ -Configuration flash selection & \OK\ (Winbond \code{W25Q32JVSSIQ}, SOIC-8, frozen) \\ -\rowa Real KiCad schematic + ERC & NOT STARTED \\ -PCB layout & NOT STARTED \\ -\rowa BOM (sourced, purchasable parts) & NOT STARTED \\ -Physical board bring-up & NOT APPLICABLE (no board fabricated) \\ -\rowa Real embedded-target (ESP32) software baseline & NOT AVAILABLE (no hardware) \\ -\bottomrule -\end{tabularx} - -\section{Final answer} -\begin{center} -\Large\bfseries\color{fnRed}NOT SILICON READY -\end{center} -The RTL, simulation, synthesis, place-and-route, timing, and pinout -gates are all genuinely closed for the final board-level top. The -remaining, real, disclosed blockers are entirely in the physical -domain -- schematic capture, PCB layout, sourced BOM, and (necessarily) -physical fabrication and bring-up -- none of which were claimed -complete in this revision. - -\section{Roadmap} -\begin{itemize} -\item Real KiCad schematic capture + ERC. -\item PCB layout (BGA escape, SDRAM routing, power integrity). -\item Sourced, purchasable BOM (regulators, configuration flash, - connectors). -\item Real power current-budget estimate against the actual - synthesized netlist. -\item First physical board fabrication and the 15-step bring-up - procedure already documented in \code{FIRST\_POWER\_ON.md}. -\item A real embedded-target (ESP32-class) software baseline, once - hardware is available, to replace this revision's honestly-labeled - desktop-CPU illustrative comparison. -\end{itemize} diff --git a/hardware/v2/docs/DatasheetLatex/preamble.tex b/hardware/v2/docs/DatasheetLatex/preamble.tex deleted file mode 100644 index 0efcef3..0000000 --- a/hardware/v2/docs/DatasheetLatex/preamble.tex +++ /dev/null @@ -1,184 +0,0 @@ -% ====================================================================== -% FPGA-Neural Datasheet -- preamble / stile -% ====================================================================== -\usepackage[T1]{fontenc} -\usepackage[utf8]{inputenc} -\usepackage[english]{babel} -\usepackage{helvet} -\renewcommand{\familydefault}{\sfdefault} -\usepackage{courier} -\usepackage{microtype} - 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