feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v1/tools/netasm/frames.py

@@ -0,0 +1,131 @@
+"""
+SPI frame encoding matching rtl/spi_engine.v's opcode set (§5 of the
+spec). A "frame" is the exact sequence of bytes shifted over MOSI
+during one CS-low transaction -- opcode byte first, then whatever
+fixed-size payload that opcode expects. This module only builds
+byte sequences; it does not talk to real hardware.
+"""
+
+from __future__ import annotations
+
+from dataclasses import dataclass
+from typing import List
+
+OP_NOP = 0x00
+OP_WRITE_RAM = 0x01
+OP_READ_RAM = 0x02
+OP_RESET = 0x0F
+OP_SET_BASE = 0x10
+OP_SET_NET_TYPE = 0x11
+OP_START = 0x20
+OP_STATUS = 0x21
+OP_READ_OUTPUT = 0x22
+OP_RUN_NETWORK = 0x23
+OP_READ_CONFIG = 0x30
+
+SEL_X_BASE = 0x00
+SEL_W_BASE = 0x01
+SEL_BIAS_ADDR = 0x02
+SEL_TABLE_BASE = 0x03
+SEL_BUF_A_BASE = 0x04
+SEL_BUF_B_BASE = 0x05
+SEL_ACTIVATION = 0x06
+SEL_N_INPUTS = 0x07
+SEL_N_NEURONS = 0x08
+SEL_NUM_NEURONS_GRAPH = 0x09
+SEL_N_OUT = 0x0A
+
+NET_TYPE_DENSE = 0x01
+NET_TYPE_GRAPH = 0x02
+
+ACT_NONE = 0
+ACT_RELU = 1
+
+
+def _u24(v: int) -> bytes:
+    if not (0 <= v < (1 << 24)):
+        raise ValueError(f"address 0x{v:x} does not fit in 24 bits")
+    return bytes([(v >> 16) & 0xFF, (v >> 8) & 0xFF, v & 0xFF])
+
+
+def _u16(v: int) -> bytes:
+    if not (0 <= v < (1 << 16)):
+        raise ValueError(f"value 0x{v:x} does not fit in 16 bits")
+    return bytes([(v >> 8) & 0xFF, v & 0xFF])
+
+
+def _i8(v: int) -> int:
+    if not (-128 <= v <= 127):
+        raise ValueError(f"value {v} does not fit in a signed byte")
+    return v & 0xFF
+
+
+@dataclass
+class Frame:
+    label: str
+    data: bytes
+
+
+def reset() -> Frame:
+    return Frame("RESET", bytes([OP_RESET]))
+
+
+def set_net_type(net_type: int) -> Frame:
+    return Frame(f"SET_NET_TYPE({net_type:#04x})", bytes([OP_SET_NET_TYPE, net_type & 0xFF]))
+
+
+def set_base(sel: int, addr: int) -> Frame:
+    return Frame(
+        f"SET_BASE(sel={sel:#04x}, addr={addr:#08x})",
+        bytes([OP_SET_BASE, sel & 0xFF]) + _u24(addr),
+    )
+
+
+def write_ram(addr: int, data: bytes) -> Frame:
+    return Frame(
+        f"WRITE_RAM(addr={addr:#08x}, len={len(data)})",
+        bytes([OP_WRITE_RAM]) + _u24(addr) + _u16(len(data)) + bytes(data),
+    )
+
+
+def read_ram(addr: int, length: int) -> Frame:
+    return Frame(
+        f"READ_RAM(addr={addr:#08x}, len={length})",
+        bytes([OP_READ_RAM]) + _u24(addr) + _u16(length),
+    )
+
+
+def run_network(payload_byte: int = 0) -> Frame:
+    return Frame(f"RUN_NETWORK(payload={payload_byte:#04x})", bytes([OP_RUN_NETWORK, payload_byte & 0xFF]))
+
+
+def start() -> Frame:
+    return Frame("START", bytes([OP_START]))
+
+
+def status() -> Frame:
+    return Frame("STATUS", bytes([OP_STATUS, 0x00]))
+
+
+def read_config() -> Frame:
+    return Frame("READ_CONFIG", bytes([OP_READ_CONFIG] + [0x00] * 10))
+
+
+def dump_frames(frames: List[Frame], path: str) -> None:
+    """Length-prefixed binary dump: for each frame, a 2-byte
+    big-endian length followed by that many payload bytes. A simple
+    host driver replays this by, for each record, asserting CS,
+    shifting out the bytes, then deasserting CS."""
+    with open(path, "wb") as f:
+        for fr in frames:
+            n = len(fr.data)
+            f.write(bytes([(n >> 8) & 0xFF, n & 0xFF]))
+            f.write(fr.data)
+
+
+def frames_as_hex(frames: List[Frame]) -> str:
+    lines = []
+    for fr in frames:
+        hexbytes = " ".join(f"{b:02x}" for b in fr.data)
+        lines.append(f"{fr.label:40s} : {hexbytes}")
+    return "\n".join(lines)