feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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`timescale 1ns/1ps
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// ================================================================
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// SPI_SLAVE PHYSICAL LAYER TESTBENCH
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//
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// Bit-bangs a simulated SPI master (Mode 0, MSB-first) against
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// rtl/spi_slave.v and checks:
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// TEST 1: single-byte transaction (rx_byte/rx_valid, MISO readback)
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// TEST 2: multi-byte transaction within one CS-low period
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// TEST 3: back-to-back separate transactions (state resets cleanly)
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// TEST 4: a slower SPI clock (stresses nothing new, but confirms
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// the module isn't implicitly tied to one SCLK/clk ratio)
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// ================================================================
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module tb;
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localparam CLK_PERIOD = 12.5; // 80 MHz system clock
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reg clk;
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reg rst;
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD / 2.0) clk = ~clk;
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end
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reg sclk;
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reg mosi;
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wire miso;
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reg cs_n;
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wire [7:0] rx_byte;
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wire rx_valid;
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reg [7:0] tx_byte;
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wire tx_byte_req;
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wire cs_active;
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wire cs_start;
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wire cs_end;
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spi_slave dut (
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.clk(clk),
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.rst(rst),
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.sclk(sclk),
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.mosi(mosi),
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.miso(miso),
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.cs_n(cs_n),
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.rx_byte(rx_byte),
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.rx_valid(rx_valid),
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.tx_byte(tx_byte),
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.tx_byte_req(tx_byte_req),
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.cs_active(cs_active),
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.cs_start(cs_start),
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.cs_end(cs_end)
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);
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// ============================================================
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// tx_byte queue: serves tx_queue[tx_queue_idx] combinationally
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// at all times (spi_slave.v prefetches it via tx_byte_req).
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//
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// The index advances on `rx_valid`, NOT on `tx_byte_req`:
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// tx_byte_req fires one extra ("phantom") time after the last
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// byte of every transaction (see the contract note in
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// rtl/spi_slave.v), while rx_valid fires exactly once per REAL
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// byte transferred, in both directions (SPI is full-duplex) --
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// the correct signal to retire one queue entry.
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// ============================================================
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reg [7:0] tx_queue [0:7];
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integer tx_queue_len;
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integer tx_queue_idx;
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always @(posedge clk) begin
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if (rst) begin
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tx_queue_idx <= 0;
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end else if (rx_valid) begin
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if (tx_queue_idx < tx_queue_len)
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tx_queue_idx <= tx_queue_idx + 1;
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end
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end
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always @(*) begin
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tx_byte = (tx_queue_idx < tx_queue_len) ? tx_queue[tx_queue_idx] : 8'h00;
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end
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// ============================================================
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// rx capture: record every received byte in order
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// ============================================================
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reg [7:0] rx_log [0:7];
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integer rx_log_len;
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always @(posedge clk) begin
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if (rst) begin
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rx_log_len <= 0;
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end else if (rx_valid) begin
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rx_log[rx_log_len] <= rx_byte;
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rx_log_len <= rx_log_len + 1;
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end
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end
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// ============================================================
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// cs_start / cs_end pulse counters
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// ============================================================
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integer cs_start_count;
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integer cs_end_count;
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always @(posedge clk) begin
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if (rst) begin
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cs_start_count <= 0;
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cs_end_count <= 0;
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end else begin
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if (cs_start) cs_start_count <= cs_start_count + 1;
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if (cs_end) cs_end_count <= cs_end_count + 1;
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end
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end
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// ============================================================
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// SPI MASTER BFM (Mode 0, MSB-first, bit-banged)
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//
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// half_period is in ns; must stay large enough relative to
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// CLK_PERIOD for the 2-flop CDC synchronizer in spi_slave.v to
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// reliably catch every edge (>= ~3 system clocks per SCLK
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// half-period is a safe margin).
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// ============================================================
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reg [7:0] miso_capture [0:7];
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integer miso_capture_len;
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// clk-cycle-counted wait: every SPI edge in this BFM is placed a
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// fixed number of `clk` cycles apart, instead of a raw `#ns`
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// delay. This keeps the master deterministically phase-aligned
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// to the system clock, so the fixed CDC latency of spi_slave.v
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// (3-stage synchronizer + 1 cycle for edge detect, ~4 clk
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// cycles) always falls comfortably inside the margin instead of
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// drifting against it run to run.
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task clk_wait;
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input integer n;
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integer k;
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begin
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for (k = 0; k < n; k = k + 1)
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@(posedge clk);
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end
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endtask
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task spi_begin;
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input integer half_bit_cycles;
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begin
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cs_n = 1'b1;
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sclk = 1'b0;
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mosi = 1'b0;
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clk_wait(half_bit_cycles * 2);
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cs_n = 1'b0;
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clk_wait(half_bit_cycles * 2);
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end
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endtask
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task spi_end;
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input integer half_bit_cycles;
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begin
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clk_wait(half_bit_cycles * 2);
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cs_n = 1'b1;
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clk_wait(half_bit_cycles * 2);
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end
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endtask
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task spi_xfer_byte;
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input [7:0] tx;
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input integer half_bit_cycles;
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output [7:0] rx;
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integer i;
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reg [7:0] rx_acc;
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begin
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rx_acc = 8'h00;
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for (i = 7; i >= 0; i = i - 1) begin
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mosi = tx[i];
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clk_wait(half_bit_cycles);
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sclk = 1'b1; // rising edge: slave samples MOSI
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rx_acc[i] = miso; // master samples MISO (stable since the prior falling edge)
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clk_wait(half_bit_cycles);
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sclk = 1'b0; // falling edge: slave updates MISO
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clk_wait(half_bit_cycles);
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end
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rx = rx_acc;
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end
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endtask
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reg [7:0] rx_tmp;
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integer errors;
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integer errors_before;
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// ============================================================
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// MAIN
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// ============================================================
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initial begin
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$dumpfile("sim/spi_slave.vcd");
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$dumpvars(0, tb);
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rst = 1'b1;
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cs_n = 1'b1;
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sclk = 1'b0;
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mosi = 1'b0;
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errors = 0;
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tx_queue_len = 0;
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rx_log_len = 0;
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repeat (5) @(posedge clk);
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rst = 1'b0;
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repeat (5) @(posedge clk);
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$display("");
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$display("========================================");
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$display("SPI_SLAVE PHYSICAL LAYER TEST");
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$display("========================================");
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// --------------------------------------------------------
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// TEST 1: single-byte transaction
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// Master sends 0xA5, slave echoes back queued 0x3C.
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// --------------------------------------------------------
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errors_before = errors;
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tx_queue[0] = 8'h3C;
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tx_queue_len = 1;
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spi_begin(8);
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spi_xfer_byte(8'hA5, 8, rx_tmp);
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spi_end(8);
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@(posedge clk); @(posedge clk);
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$display("");
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$display("TEST 1: single byte");
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$display(" MOSI sent = 0xA5, slave rx_byte = 0x%02x (expect 0xA5)", rx_log[0]);
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$display(" MISO sent = 0x3C, master received = 0x%02x (expect 0x3C)", rx_tmp);
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$display(" cs_start pulses = %0d (expect 1), cs_end pulses = %0d (expect 1)",
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cs_start_count, cs_end_count);
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if (rx_log[0] !== 8'hA5) begin $display(" FAIL: rx_byte mismatch"); errors = errors + 1; end
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if (rx_tmp !== 8'h3C) begin $display(" FAIL: MISO readback mismatch"); errors = errors + 1; end
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if (cs_start_count !== 1) begin $display(" FAIL: cs_start count"); errors = errors + 1; end
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if (cs_end_count !== 1) begin $display(" FAIL: cs_end count"); errors = errors + 1; end
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if (errors == errors_before) $display(" PASS");
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// --------------------------------------------------------
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// TEST 2: multi-byte transaction, single CS-low period
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// Master sends 0x11, 0x22, 0x33, 0x44.
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// Slave echoes back 0xDE, 0xAD, 0xBE, 0xEF.
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// --------------------------------------------------------
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@(negedge clk); rst = 1'b1; @(negedge clk); rst = 1'b0; @(posedge clk);
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rx_log_len = 0; cs_start_count = 0; cs_end_count = 0;
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errors_before = errors;
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tx_queue[0] = 8'hDE;
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tx_queue[1] = 8'hAD;
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tx_queue[2] = 8'hBE;
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tx_queue[3] = 8'hEF;
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tx_queue_len = 4;
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spi_begin(8);
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spi_xfer_byte(8'h11, 8, rx_tmp); miso_capture[0] = rx_tmp;
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spi_xfer_byte(8'h22, 8, rx_tmp); miso_capture[1] = rx_tmp;
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spi_xfer_byte(8'h33, 8, rx_tmp); miso_capture[2] = rx_tmp;
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spi_xfer_byte(8'h44, 8, rx_tmp); miso_capture[3] = rx_tmp;
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spi_end(8);
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@(posedge clk); @(posedge clk);
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$display("");
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$display("TEST 2: multi-byte, one CS period");
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$display(" rx_log = %02x %02x %02x %02x (expect 11 22 33 44)",
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rx_log[0], rx_log[1], rx_log[2], rx_log[3]);
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$display(" miso = %02x %02x %02x %02x (expect de ad be ef)",
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miso_capture[0], miso_capture[1], miso_capture[2], miso_capture[3]);
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$display(" cs_start pulses = %0d (expect 1), cs_end pulses = %0d (expect 1)",
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cs_start_count, cs_end_count);
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if (rx_log[0] !== 8'h11 || rx_log[1] !== 8'h22 ||
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rx_log[2] !== 8'h33 || rx_log[3] !== 8'h44) begin
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$display(" FAIL: rx sequence mismatch");
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errors = errors + 1;
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end
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if (miso_capture[0] !== 8'hDE || miso_capture[1] !== 8'hAD ||
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miso_capture[2] !== 8'hBE || miso_capture[3] !== 8'hEF) begin
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$display(" FAIL: MISO sequence mismatch");
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errors = errors + 1;
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end
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if (cs_start_count !== 1) begin $display(" FAIL: cs_start count"); errors = errors + 1; end
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if (cs_end_count !== 1) begin $display(" FAIL: cs_end count"); errors = errors + 1; end
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if (errors == errors_before) $display(" PASS");
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// --------------------------------------------------------
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// TEST 3: back-to-back separate transactions
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// Two independent single-byte transactions; state must
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// reset cleanly between them (no leftover bit_count/shift).
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// --------------------------------------------------------
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@(negedge clk); rst = 1'b1; @(negedge clk); rst = 1'b0; @(posedge clk);
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rx_log_len = 0; cs_start_count = 0; cs_end_count = 0;
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errors_before = errors;
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tx_queue[0] = 8'h01;
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tx_queue_len = 1;
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spi_begin(8);
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spi_xfer_byte(8'h7E, 8, rx_tmp);
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spi_end(8);
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repeat (10) @(posedge clk);
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tx_queue[0] = 8'h02;
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tx_queue_len = 1;
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spi_begin(8);
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spi_xfer_byte(8'h81, 8, rx_tmp);
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spi_end(8);
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@(posedge clk); @(posedge clk);
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$display("");
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$display("TEST 3: back-to-back transactions");
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$display(" rx_log = %02x %02x (expect 7e 81)", rx_log[0], rx_log[1]);
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$display(" cs_start pulses = %0d (expect 2), cs_end pulses = %0d (expect 2)",
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cs_start_count, cs_end_count);
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if (rx_log[0] !== 8'h7E || rx_log[1] !== 8'h81) begin
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$display(" FAIL: rx sequence mismatch");
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errors = errors + 1;
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end
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if (cs_start_count !== 2) begin $display(" FAIL: cs_start count"); errors = errors + 1; end
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if (cs_end_count !== 2) begin $display(" FAIL: cs_end count"); errors = errors + 1; end
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if (errors == errors_before) $display(" PASS");
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// --------------------------------------------------------
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// TEST 4: slower SPI clock (larger half_period), same
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// single-byte check, confirms no hidden dependency on a
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// specific SCLK/clk ratio (as long as the CDC margin holds).
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// --------------------------------------------------------
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@(negedge clk); rst = 1'b1; @(negedge clk); rst = 1'b0; @(posedge clk);
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rx_log_len = 0; cs_start_count = 0; cs_end_count = 0;
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errors_before = errors;
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tx_queue[0] = 8'h5A;
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tx_queue_len = 1;
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spi_begin(20);
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spi_xfer_byte(8'h96, 20, rx_tmp);
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spi_end(20);
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@(posedge clk); @(posedge clk);
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$display("");
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$display("TEST 4: slower SCLK (200ns half-period)");
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$display(" rx_byte = 0x%02x (expect 0x96), MISO = 0x%02x (expect 0x5a)",
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rx_log[0], rx_tmp);
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if (rx_log[0] !== 8'h96) begin $display(" FAIL: rx_byte mismatch"); errors = errors + 1; end
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if (rx_tmp !== 8'h5A) begin $display(" FAIL: MISO readback mismatch"); errors = errors + 1; end
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if (errors == errors_before) $display(" PASS");
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$display("");
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$display("========================================");
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if (errors == 0)
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$display("SPI_SLAVE TEST PASSED");
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else
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$display("SPI_SLAVE TEST FAILED: %0d errors", errors);
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$display("========================================");
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$display("");
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$finish;
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end
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endmodule
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Block a user