feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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`timescale 1ns/1ps
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// ================================================================
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// PHASE 3 - NEURON_MEMORY MULTI-NEURON TEST
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//
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// neuron_memory.v originally only handled N_NEURONS=1. It now
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// loops over N_NEURONS, reading X once (shared) and re-reading W
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// and bias per neuron from memory (neuron-major layout, same
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// convention as layer.v's weights_bus/bias_bus), reusing a single
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// neuron_parallel instance. This bench validates that loop end to
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// end through the full memory stack (memory_interface + PSRAM
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// controller + PSRAM model), not just the RTL in isolation.
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//
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// N_NEURONS = 3, N_INPUTS = 32:
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// X shared, all inputs = 1
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// Neuron 0: W=1, bias=0 -> 32
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// Neuron 1: W=2, bias=0 -> 64
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// Neuron 2: W=-1, bias=0 -> -32 -> ReLU -> 0
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// ================================================================
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module tb;
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localparam ADDR_WIDTH = 23;
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localparam DATA_WIDTH = 16;
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localparam CLK_PERIOD = 12.5; // 80 MHz
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localparam N_NEURONS = 3;
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localparam N_INPUTS = 32;
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// ============================================================
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// CLOCK / RESET
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// ============================================================
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reg clk;
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reg rst;
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD / 2.0) clk = ~clk;
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end
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// ============================================================
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// NEURON MEMORY
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// ============================================================
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reg start;
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reg [ADDR_WIDTH-1:0] x_base;
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reg [ADDR_WIDTH-1:0] w_base;
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reg [ADDR_WIDTH-1:0] bias_addr;
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wire signed [DATA_WIDTH/2*N_NEURONS-1:0] y_bus;
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wire busy;
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wire done;
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// neuron_memory -> memory_interface
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wire neuron_mem_req;
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wire neuron_mem_wr;
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wire [ADDR_WIDTH-1:0] neuron_mem_addr;
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wire signed [7:0] neuron_mem_wdata;
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wire signed [7:0] neuron_mem_rdata;
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wire neuron_mem_ready;
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// ============================================================
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// TB PRELOAD MASTER
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//
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// Direct 16-bit master.
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// Used only before starting neuron_memory.
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// ============================================================
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reg tb_mem_req;
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reg tb_mem_wr;
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reg [ADDR_WIDTH-1:0] tb_mem_addr;
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reg [DATA_WIDTH-1:0] tb_mem_wdata;
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reg tb_mem_lb_n;
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reg tb_mem_ub_n;
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wire [DATA_WIDTH-1:0] tb_mem_rdata;
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wire tb_mem_ready;
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// ============================================================
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// SINGLE MASTER MUX
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//
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// 0 = TB preload master
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// 1 = neuron_memory master
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// ============================================================
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reg use_neuron_master;
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wire master_req;
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wire master_wr;
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wire [ADDR_WIDTH-1:0] master_addr;
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wire [DATA_WIDTH-1:0] master_wdata;
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wire master_lb_n;
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wire master_ub_n;
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// ============================================================
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// MEMORY INTERFACE
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// ============================================================
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wire [DATA_WIDTH-1:0] memory_rdata;
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wire memory_ready;
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wire memory_mem_req;
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wire memory_mem_wr;
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wire [ADDR_WIDTH-1:0] memory_mem_addr;
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wire [DATA_WIDTH-1:0] memory_mem_wdata;
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wire memory_mem_lb_n;
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wire memory_mem_ub_n;
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wire [DATA_WIDTH-1:0] psram_mem_rdata;
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wire psram_mem_ready;
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assign master_req =
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use_neuron_master ? neuron_mem_req : tb_mem_req;
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assign master_wr =
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use_neuron_master ? neuron_mem_wr : tb_mem_wr;
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assign master_addr =
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use_neuron_master ? (neuron_mem_addr >> 1) : tb_mem_addr;
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assign master_wdata =
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use_neuron_master
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? (neuron_mem_addr[0]
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? {neuron_mem_wdata, 8'h00}
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: {8'h00, neuron_mem_wdata})
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: tb_mem_wdata;
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assign master_lb_n =
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use_neuron_master
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? (neuron_mem_addr[0] ? 1'b1 : 1'b0)
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: tb_mem_lb_n;
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assign master_ub_n =
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use_neuron_master
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? (neuron_mem_addr[0] ? 1'b0 : 1'b1)
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: tb_mem_ub_n;
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// Return path
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assign tb_mem_rdata = memory_rdata;
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assign tb_mem_ready = memory_ready;
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assign neuron_mem_rdata =
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neuron_mem_addr[0]
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? memory_rdata[15:8]
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: memory_rdata[7:0];
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assign neuron_mem_ready = memory_ready;
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memory_interface #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH)
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) u_memory_if (
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.clk(clk),
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.rst(rst),
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.req(master_req),
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.wr(master_wr),
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.addr(master_addr),
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.wdata(master_wdata),
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.lb_n(master_lb_n),
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.ub_n(master_ub_n),
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.rdata(memory_rdata),
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.ready(memory_ready),
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.mem_req(memory_mem_req),
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.mem_wr(memory_mem_wr),
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.mem_addr(memory_mem_addr),
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.mem_wdata(memory_mem_wdata),
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.mem_lb_n(memory_mem_lb_n),
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.mem_ub_n(memory_mem_ub_n),
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.mem_rdata(psram_mem_rdata),
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.mem_ready(psram_mem_ready)
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);
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// ============================================================
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// PSRAM PHYSICAL INTERFACE
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// ============================================================
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wire [ADDR_WIDTH-1:0] psram_a;
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wire [DATA_WIDTH-1:0] psram_dq;
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wire psram_ce_n;
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wire psram_oe_n;
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wire psram_we_n;
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wire psram_lb_n;
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wire psram_ub_n;
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wire psram_zz_n;
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// ============================================================
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// PSRAM CONTROLLER
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// ============================================================
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psram_controller #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.CLK_FREQ_MHZ(80)
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) u_psram_ctrl (
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.clk(clk),
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.rst(rst),
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.mem_req(memory_mem_req),
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.mem_wr(memory_mem_wr),
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.mem_addr(memory_mem_addr),
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.mem_wdata(memory_mem_wdata),
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.mem_lb_n(memory_mem_lb_n),
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.mem_ub_n(memory_mem_ub_n),
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.mem_rdata(psram_mem_rdata),
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.mem_ready(psram_mem_ready),
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.psram_a(psram_a),
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.psram_dq(psram_dq),
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.psram_ce_n(psram_ce_n),
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.psram_oe_n(psram_oe_n),
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.psram_we_n(psram_we_n),
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.psram_lb_n(psram_lb_n),
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.psram_ub_n(psram_ub_n),
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.psram_zz_n(psram_zz_n)
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);
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// ============================================================
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// PSRAM MODEL
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// ============================================================
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psram_model #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(16384)
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) u_psram (
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.clk(clk),
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.a(psram_a),
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.dq(psram_dq),
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.ce_n(psram_ce_n),
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.oe_n(psram_oe_n),
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.we_n(psram_we_n),
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.lb_n(psram_lb_n),
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.ub_n(psram_ub_n),
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.zz_n(psram_zz_n)
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);
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// ============================================================
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// NEURON MEMORY (N_NEURONS = 3)
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// ============================================================
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neuron_memory #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(8),
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.N_INPUTS(N_INPUTS),
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.N_NEURONS(N_NEURONS),
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.PARALLEL(8),
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.ACC_WIDTH(32)
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) u_neuron (
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.clk(clk),
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.rst(rst),
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.start(start),
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.mem_req(neuron_mem_req),
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.mem_wr(neuron_mem_wr),
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.mem_addr(neuron_mem_addr),
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.mem_wdata(neuron_mem_wdata),
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.mem_rdata(neuron_mem_rdata),
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.mem_ready(neuron_mem_ready),
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.x_base(x_base),
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.w_base(w_base),
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.bias_addr(bias_addr),
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.y_bus(y_bus),
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.busy(busy),
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.done(done)
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);
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// ============================================================
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// TB WORD WRITE
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// ============================================================
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task tb_write_word;
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input [ADDR_WIDTH-1:0] addr_i;
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input [15:0] data_i;
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begin
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@(posedge clk);
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tb_mem_addr <= addr_i;
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tb_mem_wdata <= data_i;
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tb_mem_wr <= 1'b1;
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tb_mem_lb_n <= 1'b0;
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tb_mem_ub_n <= 1'b0;
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tb_mem_req <= 1'b1;
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@(posedge clk);
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tb_mem_req <= 1'b0;
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wait (tb_mem_ready);
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@(posedge clk);
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end
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endtask
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// ============================================================
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// PRELOAD X (shared, all 32 inputs = 1)
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// ============================================================
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task preload_x;
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input [ADDR_WIDTH-1:0] base;
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integer k;
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begin
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for (k = 0; k < N_INPUTS; k = k + 2) begin
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tb_write_word((base >> 1) + (k >> 1), {8'sd1, 8'sd1});
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end
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end
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endtask
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// ============================================================
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// PRELOAD WEIGHTS FOR ONE NEURON
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//
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// Neuron n's weights live at w_base + n*N_INPUTS bytes
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// (neuron-major layout, same as layer.v's weights_bus).
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// ============================================================
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task preload_weights_n;
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input [ADDR_WIDTH-1:0] base;
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input integer n;
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input signed [7:0] value;
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integer k;
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reg [ADDR_WIDTH-1:0] neuron_base;
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begin
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neuron_base = base + n * N_INPUTS;
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for (k = 0; k < N_INPUTS; k = k + 2) begin
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tb_write_word((neuron_base >> 1) + (k >> 1), {value, value});
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end
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end
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endtask
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// ============================================================
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// PRELOAD BIAS FOR ALL 3 NEURONS
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//
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// Bias is 1 byte per neuron, contiguous: bias_addr + n.
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// Packs b0/b1 into one word, b2 alone into the next.
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// ============================================================
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task preload_bias_3;
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input [ADDR_WIDTH-1:0] base;
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input signed [7:0] b0;
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input signed [7:0] b1;
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input signed [7:0] b2;
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begin
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tb_write_word(base >> 1, {b1, b0});
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tb_write_word((base >> 1) + 1, {8'h00, b2});
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end
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endtask
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// ============================================================
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// RUN NEURON MEMORY AND CHECK ALL N_NEURONS OUTPUTS
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// ============================================================
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task run_and_check;
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input signed [7:0] expected0;
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input signed [7:0] expected1;
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input signed [7:0] expected2;
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integer errors_local;
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begin
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errors_local = 0;
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@(posedge clk);
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start <= 1'b1;
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@(posedge clk);
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start <= 1'b0;
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wait (done);
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$display("");
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$display("Neuron 0 = %0d expected = %0d", $signed(y_bus[0*8 +: 8]), expected0);
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$display("Neuron 1 = %0d expected = %0d", $signed(y_bus[1*8 +: 8]), expected1);
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$display("Neuron 2 = %0d expected = %0d", $signed(y_bus[2*8 +: 8]), expected2);
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if ($signed(y_bus[0*8 +: 8]) !== expected0) errors_local = errors_local + 1;
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if ($signed(y_bus[1*8 +: 8]) !== expected1) errors_local = errors_local + 1;
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if ($signed(y_bus[2*8 +: 8]) !== expected2) errors_local = errors_local + 1;
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if (busy !== 1'b0) begin
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$display("FAIL: busy still active after done");
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errors_local = errors_local + 1;
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end
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if (errors_local == 0) begin
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$display("PASS - MULTI-NEURON (N_NEURONS=%0d)", N_NEURONS);
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end else begin
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$display("FAIL - MULTI-NEURON: %0d mismatches", errors_local);
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$fatal;
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end
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@(posedge clk);
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end
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endtask
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// ============================================================
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// TEST
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// ============================================================
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initial begin
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start = 1'b0;
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x_base = 22'h000000;
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w_base = 22'h000100;
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bias_addr = 22'h000200;
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tb_mem_req = 1'b0;
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tb_mem_wr = 1'b0;
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tb_mem_addr = 0;
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tb_mem_wdata = 0;
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tb_mem_lb_n = 1'b1;
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tb_mem_ub_n = 1'b1;
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use_neuron_master = 1'b0;
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rst = 1'b1;
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$dumpfile("sim/neuron_memory_multi.vcd");
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$dumpvars(0, tb);
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repeat (5)
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@(posedge clk);
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rst = 1'b0;
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wait (u_psram_ctrl.state == u_psram_ctrl.STATE_IDLE);
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$display("");
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$display("========================================");
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$display("NEURON MEMORY MULTI-NEURON TEST (N_NEURONS=%0d)", N_NEURONS);
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$display("========================================");
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||||
$display("");
|
||||
|
||||
// --------------------------------------------------------
|
||||
// PRELOAD
|
||||
//
|
||||
// X shared = 1 (all 32 inputs)
|
||||
// Neuron 0: W=1, bias=0 -> 32
|
||||
// Neuron 1: W=2, bias=0 -> 64
|
||||
// Neuron 2: W=-1, bias=0 -> -32 -> ReLU -> 0
|
||||
// --------------------------------------------------------
|
||||
|
||||
$display("PRELOAD: X = 1 (shared)");
|
||||
preload_x(x_base);
|
||||
|
||||
$display("PRELOAD: W0 = 1, W1 = 2, W2 = -1");
|
||||
preload_weights_n(w_base, 0, 8'sd1);
|
||||
preload_weights_n(w_base, 1, 8'sd2);
|
||||
preload_weights_n(w_base, 2, -8'sd1);
|
||||
|
||||
$display("PRELOAD: bias0 = 0, bias1 = 0, bias2 = 0");
|
||||
preload_bias_3(bias_addr, 8'sd0, 8'sd0, 8'sd0);
|
||||
|
||||
use_neuron_master = 1'b1;
|
||||
|
||||
$display("");
|
||||
$display("MEMORY MASTER -> neuron_memory");
|
||||
|
||||
run_and_check(8'sd32, 8'sd64, 8'sd0);
|
||||
|
||||
$display("");
|
||||
$display("========================================");
|
||||
$display("NEURON MEMORY MULTI-NEURON TEST PASSED");
|
||||
$display("========================================");
|
||||
$display("");
|
||||
|
||||
$finish;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user