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feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

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Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:06:53 +02:00
co-authored by Claude Sonnet 5
parent 07a48e401f
commit dc0b331d3e
161 changed files with 1151210 additions and 0 deletions
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hardware/v1/sim/memory_interface_tb.v
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`timescale 1ns/1ps
module memory_interface_tb;
parameter ADDR_WIDTH = 23;
parameter DATA_WIDTH = 16;
reg clk;
reg rst;
// Host side
reg req;
reg wr;
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH-1:0] rdata;
wire ready;
// Memory side
wire mem_req;
wire mem_wr;
wire [ADDR_WIDTH-1:0] mem_addr;
wire [DATA_WIDTH-1:0] mem_wdata;
wire [DATA_WIDTH-1:0] mem_rdata;
wire mem_ready;
// ------------------------------------------------------------
// Clock
// ------------------------------------------------------------
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
// ------------------------------------------------------------
// DUT: Memory Interface
// ------------------------------------------------------------
memory_interface #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) dut (
.clk(clk),
.rst(rst),
.req(req),
.wr(wr),
.addr(addr),
.wdata(wdata),
.rdata(rdata),
.ready(ready),
.mem_req(mem_req),
.mem_wr(mem_wr),
.mem_addr(mem_addr),
.mem_wdata(mem_wdata),
.mem_rdata(mem_rdata),
.mem_ready(mem_ready)
);
// ------------------------------------------------------------
// Memory model
// ------------------------------------------------------------
memory_model #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(4096),
.READ_LATENCY(2)
) memory (
.clk(clk),
.rst(rst),
.req(mem_req),
.wr(mem_wr),
.addr(mem_addr),
.wdata(mem_wdata),
.rdata(mem_rdata),
.ready(mem_ready)
);
// ------------------------------------------------------------
// Test utilities
// ------------------------------------------------------------
task write_mem;
input [ADDR_WIDTH-1:0] address;
input [DATA_WIDTH-1:0] data;
begin
@(posedge clk);
addr <= address;
wdata <= data;
wr <= 1'b1;
req <= 1'b1;
@(posedge clk);
req <= 1'b0;
wait (ready);
@(posedge clk);
$display(
"WRITE addr=0x%08h data=0x%04h PASS",
address,
data
);
end
endtask
task read_mem;
input [ADDR_WIDTH-1:0] address;
input [DATA_WIDTH-1:0] expected;
reg [DATA_WIDTH-1:0] received;
begin
@(posedge clk);
addr <= address;
wr <= 1'b0;
req <= 1'b1;
@(posedge clk);
req <= 1'b0;
wait (ready);
received = rdata;
@(posedge clk);
if (received === expected) begin
$display(
"READ addr=0x%08h data=0x%04h PASS",
address,
received
);
end else begin
$display(
"READ addr=0x%08h got=0x%04h expected=0x%04h FAIL",
address,
received,
expected
);
$fatal;
end
end
endtask
// ------------------------------------------------------------
// Test sequence
// ------------------------------------------------------------
initial begin
// Defaults
rst = 1'b1;
req = 1'b0;
wr = 1'b0;
addr = {ADDR_WIDTH{1'b0}};
wdata = {DATA_WIDTH{1'b0}};
// Reset
repeat (3)
@(posedge clk);
rst = 1'b0;
$display("");
$display("========================================");
$display("MEMORY INTERFACE V1 TEST");
$display("ADDR_WIDTH = %0d", ADDR_WIDTH);
$display("DATA_WIDTH = %0d", DATA_WIDTH);
$display("========================================");
$display("");
// --------------------------------------------------------
// Test 1
// --------------------------------------------------------
write_mem(
22'h000001,
16'h1234
);
read_mem(
22'h000001,
16'h1234
);
// --------------------------------------------------------
// Test 2
// --------------------------------------------------------
write_mem(
22'h000010,
16'hABCD
);
read_mem(
22'h000010,
16'hABCD
);
// --------------------------------------------------------
// Test 3
// --------------------------------------------------------
write_mem(
22'h000100,
16'h55AA
);
read_mem(
22'h000100,
16'h55AA
);
// --------------------------------------------------------
// Test 4
// --------------------------------------------------------
// Consecutive different addresses
write_mem(
22'h000200,
16'h0001
);
write_mem(
22'h000201,
16'h0002
);
write_mem(
22'h000202,
16'h0003
);
read_mem(
22'h000200,
16'h0001
);
read_mem(
22'h000201,
16'h0002
);
read_mem(
22'h000202,
16'h0003
);
// --------------------------------------------------------
// Test 5
// --------------------------------------------------------
// Zero value
write_mem(
22'h000300,
16'h0000
);
read_mem(
22'h000300,
16'h0000
);
// --------------------------------------------------------
// Test 6
// --------------------------------------------------------
// Full 16-bit value
write_mem(
22'h000301,
16'hFFFF
);
read_mem(
22'h000301,
16'hFFFF
);
// --------------------------------------------------------
// Finished
// --------------------------------------------------------
$display("");
$display("========================================");
$display("MEMORY INTERFACE V1 TEST PASSED");
$display("========================================");
$display("");
$finish;
end
// ------------------------------------------------------------
// VCD
// ------------------------------------------------------------
initial begin
$dumpfile("sim/memory_interface.vcd");
$dumpvars(0, memory_interface_tb);
end
endmodule