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feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

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Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:06:53 +02:00
co-authored by Claude Sonnet 5
parent 07a48e401f
commit dc0b331d3e
161 changed files with 1151210 additions and 0 deletions
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hardware/v1/sim/act_buffer_tb.v
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`timescale 1ns/1ps
// ================================================================
// ACT_BUFFER TESTBENCH (Phase G1)
//
// Verifies:
// TEST 1 - write then read back (id 0, low end of range).
// TEST 2 - write then read back (id N_TOTAL-1, high end of range).
// TEST 3 - negative (signed) value round-trip.
// TEST 4 - read is REGISTERED: rd_data must NOT show the new value
// on the same cycle rd_addr changes, only one cycle later.
// TEST 5 - independent ports: write to addr X while reading addr Y
// in the same cycle does not disturb the read.
// TEST 6 - a burst of writes to many ids, then read them all back
// in a different order (models graph_engine's out-of-
// order gather pattern).
// ================================================================
module tb;
localparam N_TOTAL = 4096;
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = $clog2(N_TOTAL);
localparam CLK_PERIOD = 10.0;
reg clk;
initial begin
clk = 1'b0;
forever #(CLK_PERIOD / 2.0) clk = ~clk;
end
reg wr_en;
reg [ADDR_WIDTH-1:0] wr_addr;
reg signed [DATA_WIDTH-1:0] wr_data;
reg [ADDR_WIDTH-1:0] rd_addr;
wire signed [DATA_WIDTH-1:0] rd_data;
act_buffer #(
.N_TOTAL(N_TOTAL),
.DATA_WIDTH(DATA_WIDTH)
) dut (
.clk(clk),
.wr_en(wr_en), .wr_addr(wr_addr), .wr_data(wr_data),
.rd_addr(rd_addr), .rd_data(rd_data)
);
integer errors;
task write_id(input [ADDR_WIDTH-1:0] addr, input signed [DATA_WIDTH-1:0] data);
begin
@(negedge clk);
wr_en = 1'b1;
wr_addr = addr;
wr_data = data;
@(negedge clk);
wr_en = 1'b0;
end
endtask
task check_read(input [ADDR_WIDTH-1:0] addr, input signed [DATA_WIDTH-1:0] expected, input [255:0] name);
begin
@(negedge clk);
rd_addr = addr;
@(negedge clk); // rd_data now reflects the address set above
if (rd_data !== expected) begin
$display("FAIL %0s: addr=%0d expected=%0d got=%0d", name, addr, expected, rd_data);
errors = errors + 1;
end else begin
$display("PASS %0s: addr=%0d data=%0d", name, addr, rd_data);
end
end
endtask
integer i;
initial begin
errors = 0;
wr_en = 1'b0;
wr_addr = 0;
wr_data = 0;
rd_addr = 0;
@(negedge clk);
// TEST 1 - low end of range
write_id(0, 8'sd42);
check_read(0, 8'sd42, "TEST1 id0");
// TEST 2 - high end of range
write_id(N_TOTAL-1, 8'sd100);
check_read(N_TOTAL-1, 8'sd100, "TEST2 id_max");
// TEST 3 - negative value round-trip
write_id(10, -8'sd77);
check_read(10, -8'sd77, "TEST3 negative");
// TEST 4 - read is registered (1-cycle latency), not
// combinational: changing rd_addr must not show the new
// value until the NEXT clock edge.
@(negedge clk);
rd_addr = 0; // id0 = 42
@(negedge clk);
if (rd_data !== 8'sd42) begin
$display("FAIL TEST4 setup: expected 42 got %0d", rd_data);
errors = errors + 1;
end
rd_addr = 10; // id10 = -77, but rd_data must still show id0's value THIS cycle
if (rd_data !== 8'sd42) begin
$display("FAIL TEST4 latency: rd_data changed same-cycle as rd_addr (got %0d, expected still 42)", rd_data);
errors = errors + 1;
end else begin
$display("PASS TEST4 latency: rd_data still 42 same-cycle as rd_addr change");
end
@(negedge clk);
if (rd_data !== -8'sd77) begin
$display("FAIL TEST4 next-cycle: expected -77 got %0d", rd_data);
errors = errors + 1;
end else begin
$display("PASS TEST4 next-cycle: rd_data=-77 one cycle after rd_addr=10");
end
// TEST 5 - independent ports: write addr 20 while reading addr 10
@(negedge clk);
rd_addr = 10;
wr_en = 1'b1;
wr_addr = 20;
wr_data = 8'sd55;
@(negedge clk);
wr_en = 1'b0;
if (rd_data !== -8'sd77) begin
$display("FAIL TEST5: concurrent write disturbed read (expected -77 got %0d)", rd_data);
errors = errors + 1;
end else begin
$display("PASS TEST5: concurrent write to a different address did not disturb read");
end
check_read(20, 8'sd55, "TEST5 followup id20");
// TEST 6 - burst write many ids, read back out of order
for (i = 0; i < 16; i = i + 1) begin
write_id(100 + i, i[7:0]);
end
for (i = 15; i >= 0; i = i - 1) begin
check_read(100 + i, i[7:0], "TEST6 burst reverse-order");
end
if (errors == 0) begin
$display("ALL TESTS PASSED");
end else begin
$display("%0d TEST(S) FAILED", errors);
end
$finish;
end
endmodule