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feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

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Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:06:53 +02:00
co-authored by Claude Sonnet 5
parent 07a48e401f
commit dc0b331d3e
161 changed files with 1151210 additions and 0 deletions
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hardware/v1/rtl/spi_slave.v
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`timescale 1ns/1ps
// ================================================================
// SPI SLAVE - physical layer
//
// SPI Mode 0 (CPOL=0, CPHA=0), MSB-first, single SPI.
// Per docs/FPGA-NeuralNetwork-Engine.md §8.1: the FPGA is always
// SPI slave; one command per CS-low period.
//
// SCLK/MOSI/CS_N arrive from an external, clock-asynchronous SPI
// master, so they are double-flop synchronized into the `clk`
// domain before any edge detection. This module only implements
// the byte-level shift register and CS framing; opcode/protocol
// decoding lives in spi_engine.v.
//
// Mode 0 timing: MOSI is sampled on the RISING edge of SCLK; MISO
// is driven on the FALLING edge (so it is stable well before the
// master's next rising-edge sample).
// ================================================================
module spi_slave (
input wire clk,
input wire rst,
// ------------------------------------------------------------
// External SPI pins
// ------------------------------------------------------------
input wire sclk,
input wire mosi,
output reg miso,
input wire cs_n,
// ------------------------------------------------------------
// Byte-level interface to spi_engine
// ------------------------------------------------------------
output reg [7:0] rx_byte,
output reg rx_valid, // one clk pulse: rx_byte is valid
// IMPORTANT / load-bearing contract:
// tx_byte_req is a PREFETCH hint, not a "byte consumed" event.
// It fires once at cs_fell (to load byte 1) and once more after
// EVERY byte's last bit (to have the next byte ready in time
// for MISO, in case the master keeps clocking) -- including
// after the LAST byte of a transaction, since the slave cannot
// know in advance that no further byte will follow until CS
// actually deasserts. A consumer MUST NOT treat tx_byte_req as
// a destructive "advance/pop the next byte" trigger, or it will
// over-advance by exactly one byte on every transaction (e.g.
// over-incrementing a RAM read pointer). Use `rx_valid` instead
// to advance any stateful pointer: it pulses exactly once per
// REAL byte transferred, never an extra time, because it is
// driven purely by counted SCLK edges that actually happened.
input wire [7:0] tx_byte, // next byte to shift out on MISO
output reg tx_byte_req, // one clk pulse: refresh tx_byte now (prefetch hint, see above)
output wire cs_active, // level: transaction in progress
output reg cs_start, // one clk pulse: CS just went low
output reg cs_end // one clk pulse: CS just went high
);
// ============================================================
// CDC SYNCHRONIZERS (double flip-flop)
// ============================================================
reg [2:0] sclk_sync;
reg [2:0] mosi_sync;
reg [2:0] cs_n_sync;
always @(posedge clk) begin
if (rst) begin
sclk_sync <= 3'b000;
mosi_sync <= 3'b000;
cs_n_sync <= 3'b111;
end else begin
sclk_sync <= {sclk_sync[1:0], sclk};
mosi_sync <= {mosi_sync[1:0], mosi};
cs_n_sync <= {cs_n_sync[1:0], cs_n};
end
end
wire sclk_s = sclk_sync[2];
wire mosi_s = mosi_sync[2];
wire cs_n_s = cs_n_sync[2];
// Edge detects on the synchronized (2-deep) signal using one
// extra history bit, so "rising"/"falling" mean the edge that
// just became visible to `clk`.
reg sclk_prev;
reg cs_n_prev;
always @(posedge clk) begin
if (rst) begin
sclk_prev <= 1'b0;
cs_n_prev <= 1'b1;
end else begin
sclk_prev <= sclk_s;
cs_n_prev <= cs_n_s;
end
end
wire sclk_rise = sclk_s & ~sclk_prev;
wire sclk_fall = ~sclk_s & sclk_prev;
wire cs_fell = ~cs_n_s & cs_n_prev; // CS just went active (low)
wire cs_rose = cs_n_s & ~cs_n_prev; // CS just went inactive (high)
assign cs_active = ~cs_n_s;
// ============================================================
// BIT COUNTER / SHIFT REGISTERS
// ============================================================
reg [2:0] bit_count; // 0..7, counts bits received/sent within a byte
reg [7:0] rx_shift;
reg [7:0] tx_shift;
always @(posedge clk) begin
if (rst) begin
bit_count <= 3'd0;
rx_shift <= 8'h00;
tx_shift <= 8'h00;
rx_byte <= 8'h00;
rx_valid <= 1'b0;
tx_byte_req <= 1'b0;
miso <= 1'b0;
cs_start <= 1'b0;
cs_end <= 1'b0;
end else begin
// ------------------------------------------------
// Default pulses
// ------------------------------------------------
rx_valid <= 1'b0;
tx_byte_req <= 1'b0;
cs_start <= 1'b0;
cs_end <= 1'b0;
if (cs_fell) begin
// New transaction: reset bit counter, arm the
// first tx byte load and pre-load MISO with its
// MSB so it is valid before the first SCLK rise.
bit_count <= 3'd0;
tx_shift <= tx_byte;
tx_byte_req <= 1'b1;
miso <= tx_byte[7];
cs_start <= 1'b1;
end else if (cs_rose) begin
cs_end <= 1'b1;
end else if (cs_active) begin
if (sclk_rise) begin
// Sample MOSI (mode 0: data valid on rising edge)
rx_shift <= {rx_shift[6:0], mosi_s};
if (bit_count == 3'd7) begin
bit_count <= 3'd0;
rx_byte <= {rx_shift[6:0], mosi_s};
rx_valid <= 1'b1;
end else begin
bit_count <= bit_count + 3'd1;
end
end else if (sclk_fall) begin
// Drive next MISO bit (mode 0: output changes
// on the falling edge, ahead of the next
// master-side rising-edge sample).
if (bit_count == 3'd0) begin
// A byte boundary just completed on the
// matching rising edge above; load the
// next tx byte now.
tx_shift <= tx_byte;
tx_byte_req <= 1'b1;
miso <= tx_byte[7];
end else begin
tx_shift <= {tx_shift[6:0], 1'b0};
miso <= tx_shift[6];
end
end
end
end
end
endmodule