feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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`timescale 1ns/1ps
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// ================================================================
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// LAYER_SEQUENCER (Phase 5 - Multi-Layer Network)
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//
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// Chains up to N_LAYERS runs of a single, reused neuron_memory
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// instance to execute a feedforward network of N_LAYERS dense
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// layers, without touching neuron_memory.v or the validated compute
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// core (neuron_parallel/mac8/mac_unit) at all.
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//
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// KEY DESIGN CHOICE: neuron_memory's N_INPUTS and N_NEURONS are both
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// fixed at synthesis to the SAME value (this module's N_WIDTH
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// parameter, e.g. 256). A logical layer with fewer real inputs or
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// neurons than N_WIDTH is handled entirely by DATA convention, not
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// RTL: the host zero-pads that layer's weight matrix beyond its
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// real input count (so the extra MAC lanes contribute 0 regardless
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// of input value) and its bias beyond its real neuron count. This
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// sequencer then always reads/writes the FULL N_WIDTH-byte buffer
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// for every layer transition -- it does not need to know any
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// layer's "real" input/neuron count at all. Trade-off: a layer with
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// few real inputs still takes as long as a full N_WIDTH-wide layer
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// (wasted MAC cycles on zero-weighted padding); documented as a
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// known Phase 7 (Optimization) follow-up, not solved here.
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//
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// Layer descriptor table (host-written via WRITE_RAM, read-only to
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// this module): N_LAYERS entries of 11 bytes each, MSB-first,
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// starting at `table_base`:
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// w_base(3B), bias_addr(3B), activation(1B, low 2 bits --
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// see rtl/neuron_parallel.v's ACT_* localparams),
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// n_inputs_real(2B), n_neurons_real(2B)
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// Layer 0's input is the external `x_base` (same register used for
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// single-layer/manual mode). Layer k>0's input is the ping-pong
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// output buffer (`buf_a_base`/`buf_b_base`) written by layer k-1.
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// The final layer's output is left both in neuron_memory's own
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// y_bus (readable via the existing READ_OUTPUT opcode, unchanged)
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// and in the ping-pong buffer it was copied to.
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//
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// n_inputs_real/n_neurons_real let ONE synthesized bitstream (fixed
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// N_WIDTH = neuron_memory's build-time max) serve any real network
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// topology up to that width: forwarded to neuron_memory verbatim
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// (see rtl/neuron_memory.v), and this sequencer copies exactly
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// n_neurons_real bytes of y_bus into the ping-pong buffer -- NOT the
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// full N_WIDTH -- so a narrower layer both computes AND is copied
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// out faster, no zero-padding required in RAM.
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// ================================================================
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module layer_sequencer #(
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parameter ADDR_WIDTH = 23,
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parameter DATA_WIDTH = 8,
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parameter N_WIDTH = 256, // = neuron_memory's N_INPUTS = N_NEURONS
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parameter N_LAYERS = 4
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)(
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input wire clk,
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input wire rst,
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// ------------------------------------------------------------
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// Trigger (from spi_engine's RUN_NETWORK opcode)
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// ------------------------------------------------------------
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input wire run_start, // one-cycle pulse
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input wire [7:0] run_num_layers, // 1..N_LAYERS
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output reg seq_busy,
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output reg seq_done, // one-cycle pulse, mirrors neuron_memory.done
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// ------------------------------------------------------------
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// Config registers (from spi_engine's SET_BASE)
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// ------------------------------------------------------------
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input wire [ADDR_WIDTH-1:0] x_base, // layer 0's external input
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input wire [ADDR_WIDTH-1:0] table_base,
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input wire [ADDR_WIDTH-1:0] buf_a_base,
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input wire [ADDR_WIDTH-1:0] buf_b_base,
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// ------------------------------------------------------------
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// neuron_memory control (sequencer-owned; only meaningful while
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// seq_busy -- the top level muxes these against spi_engine's
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// own direct-drive outputs based on seq_busy)
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// ------------------------------------------------------------
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output reg [ADDR_WIDTH-1:0] nm_x_base,
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output reg [ADDR_WIDTH-1:0] nm_w_base,
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output reg [ADDR_WIDTH-1:0] nm_bias_addr,
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output reg [1:0] nm_activation,
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output reg [15:0] nm_n_inputs,
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output reg [15:0] nm_n_neurons,
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output reg nm_start,
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input wire nm_busy,
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input wire nm_done, // one-cycle pulse
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input wire signed [DATA_WIDTH*N_WIDTH-1:0] y_bus,
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// ------------------------------------------------------------
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// Byte-level RAM master port (own arbiter port)
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// ------------------------------------------------------------
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output reg ram_req,
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output reg ram_wr,
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output reg [ADDR_WIDTH-1:0] ram_addr,
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output reg signed [7:0] ram_wdata,
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input wire signed [7:0] ram_rdata,
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input wire ram_ready
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);
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// ============================================================
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// STATES
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// ============================================================
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localparam ST_IDLE = 4'd0;
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localparam ST_READ_DESC = 4'd1;
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localparam ST_READ_WAIT = 4'd2;
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localparam ST_START_LAYER = 4'd3;
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localparam ST_WAIT_LAYER = 4'd4;
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localparam ST_COPY_ISSUE = 4'd5;
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localparam ST_COPY_WAIT = 4'd6;
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reg [3:0] state;
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reg [7:0] layer_idx;
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reg [7:0] num_layers_reg;
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reg [ADDR_WIDTH-1:0] desc_table_addr;
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reg [3:0] desc_byte_idx; // 0..10
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reg [23:0] w_base_acc;
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reg [23:0] bias_addr_acc;
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reg [7:0] activation_acc;
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reg [15:0] n_inputs_acc;
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reg [15:0] n_neurons_acc;
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reg cur_sel; // which ping-pong buffer to READ from for this layer (layer_idx>0)
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reg write_sel; // which ping-pong buffer to WRITE this layer's output to
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reg [$clog2(N_WIDTH+1)-1:0] copy_idx;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_IDLE;
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layer_idx <= 8'd0;
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num_layers_reg <= 8'd0;
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desc_table_addr <= {ADDR_WIDTH{1'b0}};
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desc_byte_idx <= 4'd0;
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w_base_acc <= 24'h0;
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bias_addr_acc <= 24'h0;
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activation_acc <= 8'h0;
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n_inputs_acc <= 16'h0;
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n_neurons_acc <= 16'h0;
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cur_sel <= 1'b0;
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write_sel <= 1'b0;
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copy_idx <= 0;
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nm_x_base <= {ADDR_WIDTH{1'b0}};
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nm_w_base <= {ADDR_WIDTH{1'b0}};
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nm_bias_addr <= {ADDR_WIDTH{1'b0}};
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nm_activation <= 2'd1; // ACT_RELU
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nm_n_inputs <= 16'h0;
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nm_n_neurons <= 16'h0;
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nm_start <= 1'b0;
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ram_req <= 1'b0;
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ram_wr <= 1'b0;
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ram_addr <= {ADDR_WIDTH{1'b0}};
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ram_wdata <= 8'sd0;
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seq_busy <= 1'b0;
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seq_done <= 1'b0;
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end else begin
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// --------------------------------------------------
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// Default pulses
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// --------------------------------------------------
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nm_start <= 1'b0;
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ram_req <= 1'b0;
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seq_done <= 1'b0;
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case (state)
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// =================================================
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// IDLE
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// =================================================
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ST_IDLE: begin
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if (run_start) begin
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// BUG-005 fix (docs/validation/bugs.md): with
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// no guard, run_num_layers=0 made layer_idx
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// (a full 8-bit counter) wrap the termination
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// check to 255, reading and executing 256
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// fabricated "layers" from PSRAM bytes far
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// past the real descriptor table. There is
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// nothing to sequence for zero layers -- treat
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// it as an immediate, safe no-op completion
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// instead (same convention as spi_engine.v's
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// WRITE_RAM/READ_RAM len==0 guard: accept the
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// command, do nothing, report done/no error).
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if (run_num_layers == 8'd0) begin
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seq_done <= 1'b1;
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state <= ST_IDLE;
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end else begin
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seq_busy <= 1'b1;
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layer_idx <= 8'd0;
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num_layers_reg <= run_num_layers;
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desc_table_addr <= table_base;
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desc_byte_idx <= 4'd0;
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write_sel <= 1'b0;
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state <= ST_READ_DESC;
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end
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end
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end
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// =================================================
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// READ DESCRIPTOR (6 bytes: w_base, bias_addr)
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// =================================================
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ST_READ_DESC: begin
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ram_req <= 1'b1;
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ram_wr <= 1'b0;
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ram_addr <= desc_table_addr + desc_byte_idx;
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state <= ST_READ_WAIT;
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end
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ST_READ_WAIT: begin
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if (ram_ready) begin
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case (desc_byte_idx)
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4'd0: w_base_acc[23:16] <= ram_rdata;
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4'd1: w_base_acc[15:8] <= ram_rdata;
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4'd2: w_base_acc[7:0] <= ram_rdata;
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4'd3: bias_addr_acc[23:16] <= ram_rdata;
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4'd4: bias_addr_acc[15:8] <= ram_rdata;
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4'd5: bias_addr_acc[7:0] <= ram_rdata;
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4'd6: activation_acc <= ram_rdata;
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4'd7: n_inputs_acc[15:8] <= ram_rdata;
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4'd8: n_inputs_acc[7:0] <= ram_rdata;
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4'd9: n_neurons_acc[15:8] <= ram_rdata;
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4'd10: n_neurons_acc[7:0] <= ram_rdata;
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endcase
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if (desc_byte_idx == 4'd10) begin
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desc_byte_idx <= 4'd0;
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state <= ST_START_LAYER;
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end else begin
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desc_byte_idx <= desc_byte_idx + 4'd1;
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state <= ST_READ_DESC;
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end
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end
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end
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// =================================================
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// START LAYER
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// =================================================
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ST_START_LAYER: begin
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nm_w_base <= w_base_acc[ADDR_WIDTH-1:0];
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nm_bias_addr <= bias_addr_acc[ADDR_WIDTH-1:0];
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nm_activation <= activation_acc[1:0];
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nm_n_inputs <= n_inputs_acc;
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nm_n_neurons <= n_neurons_acc;
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nm_x_base <= (layer_idx == 8'd0)
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? x_base
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: (cur_sel ? buf_b_base : buf_a_base);
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nm_start <= 1'b1;
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state <= ST_WAIT_LAYER;
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end
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// =================================================
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// WAIT FOR THIS LAYER TO FINISH
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// =================================================
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ST_WAIT_LAYER: begin
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if (nm_done) begin
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copy_idx <= 0;
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state <= ST_COPY_ISSUE;
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end
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end
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// =================================================
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// COPY y_bus INTO THE PING-PONG OUTPUT BUFFER
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// =================================================
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ST_COPY_ISSUE: begin
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ram_req <= 1'b1;
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ram_wr <= 1'b1;
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ram_addr <= (write_sel ? buf_b_base : buf_a_base) + copy_idx;
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ram_wdata <= y_bus[copy_idx*DATA_WIDTH +: DATA_WIDTH];
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state <= ST_COPY_WAIT;
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end
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ST_COPY_WAIT: begin
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if (ram_ready) begin
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if (copy_idx == n_neurons_acc[$clog2(N_WIDTH+1)-1:0] - 1'b1) begin
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if (layer_idx == num_layers_reg - 8'd1) begin
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// Last layer done.
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seq_busy <= 1'b0;
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seq_done <= 1'b1;
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state <= ST_IDLE;
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end else begin
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// The buffer just written becomes
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// the next layer's input.
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cur_sel <= write_sel;
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write_sel <= ~write_sel;
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layer_idx <= layer_idx + 8'd1;
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desc_table_addr <= desc_table_addr + 11;
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desc_byte_idx <= 4'd0;
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state <= ST_READ_DESC;
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end
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end else begin
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copy_idx <= copy_idx + 1'b1;
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state <= ST_COPY_ISSUE;
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end
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end
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end
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default: begin
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state <= ST_IDLE;
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end
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endcase
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end
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end
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endmodule
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Block a user