feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v1/docs/validation/14-lavori-in-corso.md

@@ -0,0 +1,26 @@
+# C.14 — Lavori in corso (page-mode PSRAM, sottosistema flash)
+
+Data: 2026-09-04.
+
+## Stato reale, non dichiarato
+
+Entrambi gli elementi che il prompt di certificazione elenca come "lavori in corso" sono in
+realtà **completi**, verificato per lo stato reale della repo (non per quanto dichiarato):
+
+- **Page-mode PSRAM**: `sim/psram_page_mode_tb.v` esiste, copre `ACCESS_CYCLES`, `PAGE_CYCLES`,
+  `tCEM` (idle timeout e budget mid-burst), con `psram_model.v` che fa `$fatal` su
+  violazione di timing reale. Rieseguito PASS in Fase 0 (§C.3).
+- **Sottosistema flash**: `rtl/spi_flash_master.v`, `flash_copy_engine.v`,
+  `flash_slot_manager.v` esistono, 8 opcode SPI (0x40-0x47) integrati in
+  `spi_neuron_top.v`, bus SPI reso indipendente in Fase F7. 33 testbench del progetto
+  includono 9 dedicati al sottosistema flash, tutti PASS in Fase 0.
+
+**Nessun residuo "in corso" trovato**: non ci sono moduli RTL a metà, TODO irrisolti nel
+codice, o funzionalità dichiarate ma non implementate per questi due elementi.
+
+## Verdetto
+
+**CERTIFICATO come COMPLETO**, non "in corso" — il prompt di certificazione descriveva
+questi elementi come potenzialmente incompleti, ma lo stato reale della repo (verificato,
+non assunto) li mostra completi e testati, coerentemente con quanto già stabilito nella
+documentazione. Nessuno scostamento trovato qui.