feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v1/docs/validation/07-spi.md

@@ -0,0 +1,62 @@
+# C.7 — SPI slave + engine (`spi_slave.v`, `spi_engine.v`)
+
+Data: 2026-09-04.
+
+---
+
+## 7.1 CDC, framing, opcode dispatch — CERTIFICATO (copertura pre-esistente estesa, riverificata)
+
+Questo modulo ha già ricevuto lavoro di verifica sostanziale **in questa stessa sessione**
+(non solo dichiarato in sessioni precedenti):
+- **Una race reale trovata e corretta** nel meccanismo sticky di `STATUS` (Fase 4/9 di
+  sessioni precedenti, ma il fix e la sua verifica sono tracciabili e riverificati).
+- **CDC a 2/3 stadi per `sclk`/`mosi`/`cs_n`**: `sim/spi_slave_tb.v` include un test
+  esplicito con rapporto SCLK/clk diverso (TEST 4, "slower SPI clock... confirms no hidden
+  dependency on a specific SCLK/clk ratio") — non solo un singolo rapporto a piacere.
+- **`sim/spi_engine_tb.v`**: 10 test (A-J) coprono WRITE_RAM/READ_RAM round-trip, SET_BASE,
+  START idle/busy, STATUS live/sticky/clear-on-read, RESET, READ_OUTPUT (neuron-major),
+  READ_CONFIG, NOP (nessun side-effect), byte MOSI in eccesso ignorati, transazioni
+  back-to-back.
+- **Opcode sconosciuti**: `default: begin // OP_NOP and unknown opcodes` (riga 724) —
+  trattati esplicitamente come NOP, nessun rischio di hang per costruzione, coerente col
+  pattern già verificato per `spi_flash_master.v` (opcode illegale, Fase F1).
+- Rieseguito in Fase 0 di questa campagna (non solo citato): `spi_slave_tb.v` e
+  `spi_engine_tb.v` **PASS**, confermato dall'harness di regressione indipendente.
+
+**Verdetto: CERTIFICATO**, con la stessa evidenza di prima (riverificata, non solo citata).
+
+---
+
+## 7.2 `len=0` per WRITE_RAM/READ_RAM — CERTIFICATO (guard esplicito trovato per ispezione)
+
+Dato il pattern ricorrente in questa campagna (guard mancante su valori "reali=0" in più
+moduli, BUG-002/003/004/005/006), ho controllato se lo stesso buco esistesse anche qui.
+**Non esiste**: `rtl/spi_engine.v:817` ha un guard esplicito —
+
+```verilog
+if ({len_acc[7:0], rx_byte} == 16'h0) begin
+    state <= ST_IGNORE;
+end else if (opcode == OP_WRITE_RAM) begin
+    state <= ST_WRITE_DATA;
+...
+```
+
+`len=0` transita correttamente a `ST_IGNORE` (no-op sicuro) invece di entrare nel loop di
+trasferimento — a differenza di `layer_sequencer.v`/`graph_engine.v`, qui il caso limite è
+gestito esplicitamente. Non serviva un nuovo test dedicato: il guard è verificabile per
+ispezione diretta, inequivocabile.
+
+**Verdetto: CERTIFICATO.** Nota positiva per il registro: questo modulo dimostra che il
+progetto **non manca sistematicamente** di guardie sui valori limite — il buco è
+specifico ai moduli già segnalati (BUG-002 - BUG-006), non universale.
+
+---
+
+## 7.3 Verdetto complessivo C.7
+
+| Sotto-aspetto | Verdetto |
+|---|---|
+| CDC, framing, dispatch opcode, opcode sconosciuti | **CERTIFICATO** (copertura estesa pre-esistente, riverificata) |
+| `len=0` WRITE_RAM/READ_RAM | **CERTIFICATO** (guard esplicito confermato per ispezione) |
+
+Nessun nuovo bug trovato in questo aspetto.