From d4ae2417a40ba9a6017721947a0e6aebad310a92 Mon Sep 17 00:00:00 2001 From: Michele Bigi Date: Wed, 2 Sep 2026 09:27:04 +0200 Subject: [PATCH] test: validate parametric 32x4 layer with parallelism 8 --- rtl/layer.v | 83 + rtl/mac8.v | 122 ++ rtl/mac_unit.v | 23 + rtl/neuron_parallel.v | 119 ++ sim/layer.vcd | 3592 ++++++++++++++++++++++++++++++++++ sim/layer_sim | 3916 ++++++++++++++++++++++++++++++++++++++ sim/layer_tb.v | 240 +++ sim/neuron_parallel.vcd | 1027 ++++++++++ sim/neuron_parallel_tb.v | 286 +++ sim/neuron_sim | 822 ++++++++ sim/parametric.vcd | 1838 ++++++++++++++++++ sim/parametric_32x4 | 2118 +++++++++++++++++++++ sim/parametric_tb.v | 352 ++++ sim/top.v | 33 + 14 files changed, 14571 insertions(+) create mode 100644 rtl/layer.v create mode 100644 rtl/mac8.v create mode 100644 rtl/mac_unit.v create mode 100644 rtl/neuron_parallel.v create mode 100644 sim/layer.vcd create mode 100755 sim/layer_sim create mode 100644 sim/layer_tb.v create mode 100644 sim/neuron_parallel.vcd create mode 100644 sim/neuron_parallel_tb.v create mode 100755 sim/neuron_sim create mode 100644 sim/parametric.vcd create mode 100755 sim/parametric_32x4 create mode 100644 sim/parametric_tb.v create mode 100644 sim/top.v diff --git a/rtl/layer.v b/rtl/layer.v new file mode 100644 index 0000000..24fff2d --- /dev/null +++ b/rtl/layer.v @@ -0,0 +1,83 @@ +module layer #( + parameter DATA_WIDTH = 16, + parameter FRAC_BITS = 8, + parameter N_INPUTS = 64, + parameter N_NEURONS = 8, + parameter PARALLEL = 8, + parameter ACC_WIDTH = 40 +)( + input clk, + input rst, + input start, + + input signed [DATA_WIDTH*N_INPUTS-1:0] x_bus, + + input signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] + weights_bus, + + input signed [DATA_WIDTH*N_NEURONS-1:0] + bias_bus, + + output signed [DATA_WIDTH*N_NEURONS-1:0] + y_bus, + + output busy, + output done +); + + wire [N_NEURONS-1:0] neuron_busy; + wire [N_NEURONS-1:0] neuron_done; + + genvar n; + + generate + + for (n = 0; n < N_NEURONS; n = n + 1) begin : GEN_NEURON + + neuron_parallel #( + .DATA_WIDTH(DATA_WIDTH), + .FRAC_BITS(FRAC_BITS), + .N_INPUTS(N_INPUTS), + .PARALLEL(PARALLEL), + .ACC_WIDTH(ACC_WIDTH) + ) u_neuron ( + + .clk(clk), + .rst(rst), + .start(start), + + .x_bus(x_bus), + + .w_bus( + weights_bus[ + n*N_INPUTS*DATA_WIDTH + +: N_INPUTS*DATA_WIDTH + ] + ), + + .bias( + bias_bus[ + n*DATA_WIDTH + +: DATA_WIDTH + ] + ), + + .y( + y_bus[ + n*DATA_WIDTH + +: DATA_WIDTH + ] + ), + + .busy(neuron_busy[n]), + .done(neuron_done[n]) + ); + + end + + endgenerate + + assign busy = |neuron_busy; + assign done = &neuron_done; + +endmodule \ No newline at end of file diff --git a/rtl/mac8.v b/rtl/mac8.v new file mode 100644 index 0000000..9a63252 --- /dev/null +++ b/rtl/mac8.v @@ -0,0 +1,122 @@ +module mac8 #( + parameter DATA_WIDTH = 16, + parameter ACC_WIDTH = 40 +)( + input signed [DATA_WIDTH*8-1:0] x_bus, + input signed [DATA_WIDTH*8-1:0] w_bus, + input signed [ACC_WIDTH-1:0] acc_in, + output signed [ACC_WIDTH-1:0] acc_out +); + + wire signed [ACC_WIDTH-1:0] m0; + wire signed [ACC_WIDTH-1:0] m1; + wire signed [ACC_WIDTH-1:0] m2; + wire signed [ACC_WIDTH-1:0] m3; + wire signed [ACC_WIDTH-1:0] m4; + wire signed [ACC_WIDTH-1:0] m5; + wire signed [ACC_WIDTH-1:0] m6; + wire signed [ACC_WIDTH-1:0] m7; + + wire signed [ACC_WIDTH-1:0] s0; + wire signed [ACC_WIDTH-1:0] s1; + wire signed [ACC_WIDTH-1:0] s2; + wire signed [ACC_WIDTH-1:0] s3; + + wire signed [ACC_WIDTH-1:0] s4; + wire signed [ACC_WIDTH-1:0] s5; + + wire signed [ACC_WIDTH-1:0] sum; + + mac_unit #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) mac0 ( + .x(x_bus[0*DATA_WIDTH +: DATA_WIDTH]), + .w(w_bus[0*DATA_WIDTH +: DATA_WIDTH]), + .acc_in({ACC_WIDTH{1'b0}}), + .acc_out(m0) + ); + + mac_unit #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) mac1 ( + .x(x_bus[1*DATA_WIDTH +: DATA_WIDTH]), + .w(w_bus[1*DATA_WIDTH +: DATA_WIDTH]), + .acc_in({ACC_WIDTH{1'b0}}), + .acc_out(m1) + ); + + mac_unit #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) mac2 ( + .x(x_bus[2*DATA_WIDTH +: DATA_WIDTH]), + .w(w_bus[2*DATA_WIDTH +: DATA_WIDTH]), + .acc_in({ACC_WIDTH{1'b0}}), + .acc_out(m2) + ); + + mac_unit #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) mac3 ( + .x(x_bus[3*DATA_WIDTH +: DATA_WIDTH]), + .w(w_bus[3*DATA_WIDTH +: DATA_WIDTH]), + .acc_in({ACC_WIDTH{1'b0}}), + .acc_out(m3) + ); + + mac_unit #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) mac4 ( + .x(x_bus[4*DATA_WIDTH +: DATA_WIDTH]), + .w(w_bus[4*DATA_WIDTH +: DATA_WIDTH]), + .acc_in({ACC_WIDTH{1'b0}}), + .acc_out(m4) + ); + + mac_unit #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) mac5 ( + .x(x_bus[5*DATA_WIDTH +: DATA_WIDTH]), + .w(w_bus[5*DATA_WIDTH +: DATA_WIDTH]), + .acc_in({ACC_WIDTH{1'b0}}), + .acc_out(m5) + ); + + mac_unit #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) mac6 ( + .x(x_bus[6*DATA_WIDTH +: DATA_WIDTH]), + .w(w_bus[6*DATA_WIDTH +: DATA_WIDTH]), + .acc_in({ACC_WIDTH{1'b0}}), + .acc_out(m6) + ); + + mac_unit #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) mac7 ( + .x(x_bus[7*DATA_WIDTH +: DATA_WIDTH]), + .w(w_bus[7*DATA_WIDTH +: DATA_WIDTH]), + .acc_in({ACC_WIDTH{1'b0}}), + .acc_out(m7) + ); + + assign s0 = m0 + m1; + assign s1 = m2 + m3; + assign s2 = m4 + m5; + assign s3 = m6 + m7; + + assign s4 = s0 + s1; + assign s5 = s2 + s3; + + assign sum = s4 + s5; + + assign acc_out = acc_in + sum; + +endmodule \ No newline at end of file diff --git a/rtl/mac_unit.v b/rtl/mac_unit.v new file mode 100644 index 0000000..b45ff0d --- /dev/null +++ b/rtl/mac_unit.v @@ -0,0 +1,23 @@ +module mac_unit #( + parameter DATA_WIDTH = 16, + parameter ACC_WIDTH = 40 +)( + input signed [DATA_WIDTH-1:0] x, + input signed [DATA_WIDTH-1:0] w, + input signed [ACC_WIDTH-1:0] acc_in, + output signed [ACC_WIDTH-1:0] acc_out +); + + localparam PROD_WIDTH = 2 * DATA_WIDTH; + + wire signed [PROD_WIDTH-1:0] product; + wire signed [ACC_WIDTH-1:0] product_ext; + + assign product = x * w; + + assign product_ext = + {{(ACC_WIDTH-PROD_WIDTH){product[PROD_WIDTH-1]}}, product}; + + assign acc_out = acc_in + product_ext; + +endmodule \ No newline at end of file diff --git a/rtl/neuron_parallel.v b/rtl/neuron_parallel.v new file mode 100644 index 0000000..7931782 --- /dev/null +++ b/rtl/neuron_parallel.v @@ -0,0 +1,119 @@ +module neuron_parallel #( + parameter DATA_WIDTH = 16, + parameter FRAC_BITS = 8, + parameter N_INPUTS = 64, + parameter PARALLEL = 8, + parameter ACC_WIDTH = 40 +)( + input clk, + input rst, + input start, + + input signed [DATA_WIDTH*N_INPUTS-1:0] x_bus, + input signed [DATA_WIDTH*N_INPUTS-1:0] w_bus, + input signed [DATA_WIDTH-1:0] bias, + + output reg signed [DATA_WIDTH-1:0] y, + output reg busy, + output reg done +); + + localparam GROUPS = N_INPUTS / PARALLEL; + localparam GROUP_INDEX_WIDTH = + (GROUPS <= 1) ? 1 : $clog2(GROUPS); + + reg [GROUP_INDEX_WIDTH-1:0] group_index; + + reg signed [ACC_WIDTH-1:0] acc; + + wire signed [DATA_WIDTH*PARALLEL-1:0] x_group; + wire signed [DATA_WIDTH*PARALLEL-1:0] w_group; + + wire signed [ACC_WIDTH-1:0] acc_next; + + wire signed [DATA_WIDTH-1:0] bias_ext_small; + wire signed [ACC_WIDTH-1:0] bias_ext; + + wire signed [ACC_WIDTH-1:0] final_acc; + wire signed [ACC_WIDTH-1:0] final_value; + + assign x_group = + x_bus[group_index*PARALLEL*DATA_WIDTH + +: PARALLEL*DATA_WIDTH]; + + assign w_group = + w_bus[group_index*PARALLEL*DATA_WIDTH + +: PARALLEL*DATA_WIDTH]; + + mac8 #( + .DATA_WIDTH(DATA_WIDTH), + .ACC_WIDTH(ACC_WIDTH) + ) u_mac8 ( + .x_bus(x_group), + .w_bus(w_group), + .acc_in(acc), + .acc_out(acc_next) + ); + + assign bias_ext_small = bias; + + assign bias_ext = + {{(ACC_WIDTH-DATA_WIDTH){bias_ext_small[DATA_WIDTH-1]}}, + bias_ext_small}; + + assign final_acc = + acc_next + (bias_ext <<< FRAC_BITS); + + assign final_value = + final_acc >>> FRAC_BITS; + + always @(posedge clk) begin + + if (rst) begin + + group_index <= 0; + acc <= 0; + y <= 0; + busy <= 0; + done <= 0; + + end else begin + + done <= 0; + + if (start && !busy) begin + + group_index <= 0; + acc <= 0; + busy <= 1; + + end else if (busy) begin + + if (group_index == GROUPS-1) begin + + acc <= final_acc; + + if (final_value <= 0) begin + y <= 0; + end + else if (final_value > 32767) begin + y <= 16'sh7FFF; + end + else begin + y <= final_value[DATA_WIDTH-1:0]; + end + + busy <= 0; + done <= 1; + + end else begin + + acc <= acc_next; + group_index <= group_index + 1'b1; + + end + end + end + end + +endmodule \ No newline at end of file diff --git a/sim/layer.vcd b/sim/layer.vcd new file mode 100644 index 0000000..5eb741e --- /dev/null +++ b/sim/layer.vcd @@ -0,0 +1,3592 @@ +$date + Wed Sep 2 09:14:02 2026 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module tb $end +$var wire 128 ! y_bus [127:0] $end +$var wire 1 " done $end +$var wire 1 # busy $end +$var parameter 32 $ ACC_WIDTH $end +$var parameter 32 % DATA_WIDTH $end +$var parameter 32 & FRAC_BITS $end +$var parameter 32 ' N_INPUTS $end +$var parameter 32 ( N_NEURONS $end +$var parameter 32 ) PARALLEL $end +$var reg 128 * bias_bus [127:0] $end +$var reg 1 + clk $end +$var reg 1 , rst $end +$var reg 1 - start $end +$var reg 8192 . weights_bus [8191:0] $end +$var reg 1024 / x_bus [1023:0] $end +$var integer 32 0 errors [31:0] $end +$var integer 32 1 i [31:0] $end +$scope function q8_8 $end +$var real 1 2 value $end +$upscope $end +$scope module dut $end +$var wire 128 3 bias_bus [127:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 8192 4 weights_bus [8191:0] $end +$var wire 1024 5 x_bus [1023:0] $end +$var wire 128 6 y_bus [127:0] $end +$var wire 8 7 neuron_done [7:0] $end +$var wire 8 8 neuron_busy [7:0] $end +$var wire 1 " done $end +$var wire 1 # busy $end +$var parameter 32 9 ACC_WIDTH $end +$var parameter 32 : DATA_WIDTH $end +$var parameter 32 ; FRAC_BITS $end +$var parameter 32 < N_INPUTS $end +$var parameter 32 = N_NEURONS $end +$var parameter 32 > PARALLEL $end +$scope begin GEN_NEURON[0] $end +$var parameter 2 ? n $end +$scope module u_neuron $end +$var wire 16 @ bias [15:0] $end +$var wire 16 A bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 1024 B w_bus [1023:0] $end +$var wire 1024 C x_bus [1023:0] $end +$var wire 128 D x_group [127:0] $end +$var wire 128 E w_group [127:0] $end +$var wire 40 F final_value [39:0] $end +$var wire 40 G final_acc [39:0] $end +$var wire 40 H bias_ext [39:0] $end +$var wire 40 I acc_next [39:0] $end +$var parameter 32 J ACC_WIDTH $end +$var parameter 32 K DATA_WIDTH $end +$var parameter 32 L FRAC_BITS $end +$var parameter 32 M GROUPS $end +$var parameter 32 N GROUP_INDEX_WIDTH $end +$var parameter 32 O N_INPUTS $end +$var parameter 32 P PARALLEL $end +$var reg 40 Q acc [39:0] $end +$var reg 1 R busy $end +$var reg 1 S done $end +$var reg 3 T group_index [2:0] $end +$var reg 16 U y [15:0] $end +$scope module u_mac8 $end +$var wire 40 V acc_in [39:0] $end +$var wire 128 W w_bus [127:0] $end +$var wire 128 X x_bus [127:0] $end +$var wire 40 Y sum [39:0] $end +$var wire 40 Z s5 [39:0] $end +$var wire 40 [ s4 [39:0] $end +$var wire 40 \ s3 [39:0] $end +$var wire 40 ] s2 [39:0] $end +$var wire 40 ^ s1 [39:0] $end +$var wire 40 _ s0 [39:0] $end +$var wire 40 ` m7 [39:0] $end +$var wire 40 a m6 [39:0] $end +$var wire 40 b m5 [39:0] $end +$var wire 40 c m4 [39:0] $end +$var wire 40 d m3 [39:0] $end +$var wire 40 e m2 [39:0] $end +$var wire 40 f m1 [39:0] $end +$var wire 40 g m0 [39:0] $end +$var wire 40 h acc_out [39:0] $end +$var parameter 32 i ACC_WIDTH $end +$var parameter 32 j DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 k acc_in [39:0] $end +$var wire 16 l w [15:0] $end +$var wire 16 m x [15:0] $end +$var wire 40 n product_ext [39:0] $end +$var wire 32 o product [31:0] $end +$var wire 40 p acc_out [39:0] $end +$var parameter 32 q ACC_WIDTH $end +$var parameter 32 r DATA_WIDTH $end +$var parameter 64 s PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 t acc_in [39:0] $end +$var wire 16 u w [15:0] $end +$var wire 16 v x [15:0] $end +$var wire 40 w product_ext [39:0] $end +$var wire 32 x product [31:0] $end +$var wire 40 y acc_out [39:0] $end +$var parameter 32 z ACC_WIDTH $end +$var parameter 32 { DATA_WIDTH $end +$var parameter 64 | PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 } acc_in [39:0] $end +$var wire 16 ~ w [15:0] $end +$var wire 16 !" x [15:0] $end +$var wire 40 "" product_ext [39:0] $end +$var wire 32 #" product [31:0] $end +$var wire 40 $" acc_out [39:0] $end +$var parameter 32 %" ACC_WIDTH $end +$var parameter 32 &" DATA_WIDTH $end +$var parameter 64 '" PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 (" acc_in [39:0] $end +$var wire 16 )" w [15:0] $end +$var wire 16 *" x [15:0] $end +$var wire 40 +" product_ext [39:0] $end +$var wire 32 ," product [31:0] $end +$var wire 40 -" acc_out [39:0] $end +$var parameter 32 ." ACC_WIDTH $end +$var parameter 32 /" DATA_WIDTH $end +$var parameter 64 0" PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 1" acc_in [39:0] $end +$var wire 16 2" w [15:0] $end +$var wire 16 3" x [15:0] $end +$var wire 40 4" product_ext [39:0] $end +$var wire 32 5" product [31:0] $end +$var wire 40 6" acc_out [39:0] $end +$var parameter 32 7" ACC_WIDTH $end +$var parameter 32 8" DATA_WIDTH $end +$var parameter 64 9" PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 :" acc_in [39:0] $end +$var wire 16 ;" w [15:0] $end +$var wire 16 <" x [15:0] $end +$var wire 40 =" product_ext [39:0] $end +$var wire 32 >" product [31:0] $end +$var wire 40 ?" acc_out [39:0] $end +$var parameter 32 @" ACC_WIDTH $end +$var parameter 32 A" DATA_WIDTH $end +$var parameter 64 B" PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 C" acc_in [39:0] $end +$var wire 16 D" w [15:0] $end +$var wire 16 E" x [15:0] $end +$var wire 40 F" product_ext [39:0] $end +$var wire 32 G" product [31:0] $end +$var wire 40 H" acc_out [39:0] $end +$var parameter 32 I" ACC_WIDTH $end +$var parameter 32 J" DATA_WIDTH $end +$var parameter 64 K" PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 L" acc_in [39:0] $end +$var wire 16 M" w [15:0] $end +$var wire 16 N" x [15:0] $end +$var wire 40 O" product_ext [39:0] $end +$var wire 32 P" product [31:0] $end +$var wire 40 Q" acc_out [39:0] $end +$var parameter 32 R" ACC_WIDTH $end +$var parameter 32 S" DATA_WIDTH $end +$var parameter 64 T" PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[1] $end +$var parameter 2 U" n $end +$scope module u_neuron $end +$var wire 16 V" bias [15:0] $end +$var wire 16 W" bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 1024 X" w_bus [1023:0] $end +$var wire 1024 Y" x_bus [1023:0] $end +$var wire 128 Z" x_group [127:0] $end +$var wire 128 [" w_group [127:0] $end +$var wire 40 \" final_value [39:0] $end +$var wire 40 ]" final_acc [39:0] $end +$var wire 40 ^" bias_ext [39:0] $end +$var wire 40 _" acc_next [39:0] $end +$var parameter 32 `" ACC_WIDTH $end +$var parameter 32 a" DATA_WIDTH $end +$var parameter 32 b" FRAC_BITS $end +$var parameter 32 c" GROUPS $end +$var parameter 32 d" GROUP_INDEX_WIDTH $end +$var parameter 32 e" N_INPUTS $end +$var parameter 32 f" PARALLEL $end +$var reg 40 g" acc [39:0] $end +$var reg 1 h" busy $end +$var reg 1 i" done $end +$var reg 3 j" group_index [2:0] $end +$var reg 16 k" y [15:0] $end +$scope module u_mac8 $end +$var wire 40 l" acc_in [39:0] $end +$var wire 128 m" w_bus [127:0] $end +$var wire 128 n" x_bus [127:0] $end +$var wire 40 o" sum [39:0] $end +$var wire 40 p" s5 [39:0] $end +$var wire 40 q" s4 [39:0] $end +$var wire 40 r" s3 [39:0] $end +$var wire 40 s" s2 [39:0] $end +$var wire 40 t" s1 [39:0] $end +$var wire 40 u" s0 [39:0] $end +$var wire 40 v" m7 [39:0] $end +$var wire 40 w" m6 [39:0] $end +$var wire 40 x" m5 [39:0] $end +$var wire 40 y" m4 [39:0] $end +$var wire 40 z" m3 [39:0] $end +$var wire 40 {" m2 [39:0] $end +$var wire 40 |" m1 [39:0] $end +$var wire 40 }" m0 [39:0] $end +$var wire 40 ~" acc_out [39:0] $end +$var parameter 32 !# ACC_WIDTH $end +$var parameter 32 "# DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 ## acc_in [39:0] $end +$var wire 16 $# w [15:0] $end +$var wire 16 %# x [15:0] $end +$var wire 40 &# product_ext [39:0] $end +$var wire 32 '# product [31:0] $end +$var wire 40 (# acc_out [39:0] $end +$var parameter 32 )# ACC_WIDTH $end +$var parameter 32 *# DATA_WIDTH $end +$var parameter 64 +# PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 ,# acc_in [39:0] $end +$var wire 16 -# w [15:0] $end +$var wire 16 .# x [15:0] $end +$var wire 40 /# product_ext [39:0] $end +$var wire 32 0# product [31:0] $end +$var wire 40 1# acc_out [39:0] $end +$var parameter 32 2# ACC_WIDTH $end +$var parameter 32 3# DATA_WIDTH $end +$var parameter 64 4# PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 5# acc_in [39:0] $end +$var wire 16 6# w [15:0] $end +$var wire 16 7# x [15:0] $end +$var wire 40 8# product_ext [39:0] $end +$var wire 32 9# product [31:0] $end +$var wire 40 :# acc_out [39:0] $end +$var parameter 32 ;# ACC_WIDTH $end +$var parameter 32 <# DATA_WIDTH $end +$var parameter 64 =# PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 ># acc_in [39:0] $end +$var wire 16 ?# w [15:0] $end +$var wire 16 @# x [15:0] $end +$var wire 40 A# product_ext [39:0] $end +$var wire 32 B# product [31:0] $end +$var wire 40 C# acc_out [39:0] $end +$var parameter 32 D# ACC_WIDTH $end +$var parameter 32 E# DATA_WIDTH $end +$var parameter 64 F# PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 G# acc_in [39:0] $end +$var wire 16 H# w [15:0] $end +$var wire 16 I# x [15:0] $end +$var wire 40 J# product_ext [39:0] $end +$var wire 32 K# product [31:0] $end +$var wire 40 L# acc_out [39:0] $end +$var parameter 32 M# ACC_WIDTH $end +$var parameter 32 N# DATA_WIDTH $end +$var parameter 64 O# PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 P# acc_in [39:0] $end +$var wire 16 Q# w [15:0] $end +$var wire 16 R# x [15:0] $end +$var wire 40 S# product_ext [39:0] $end +$var wire 32 T# product [31:0] $end +$var wire 40 U# acc_out [39:0] $end +$var parameter 32 V# ACC_WIDTH $end +$var parameter 32 W# DATA_WIDTH $end +$var parameter 64 X# PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 Y# acc_in [39:0] $end +$var wire 16 Z# w [15:0] $end +$var wire 16 [# x [15:0] $end +$var wire 40 \# product_ext [39:0] $end +$var wire 32 ]# product [31:0] $end +$var wire 40 ^# acc_out [39:0] $end +$var parameter 32 _# ACC_WIDTH $end +$var parameter 32 `# DATA_WIDTH $end +$var parameter 64 a# PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 b# acc_in [39:0] $end +$var wire 16 c# w [15:0] $end +$var wire 16 d# x [15:0] $end +$var wire 40 e# product_ext [39:0] $end +$var wire 32 f# product [31:0] $end +$var wire 40 g# acc_out [39:0] $end +$var parameter 32 h# ACC_WIDTH $end +$var parameter 32 i# DATA_WIDTH $end +$var parameter 64 j# PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[2] $end +$var parameter 3 k# n $end +$scope module u_neuron $end +$var wire 16 l# bias [15:0] $end +$var wire 16 m# bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 1024 n# w_bus [1023:0] $end +$var wire 1024 o# x_bus [1023:0] $end +$var wire 128 p# x_group [127:0] $end +$var wire 128 q# w_group [127:0] $end +$var wire 40 r# final_value [39:0] $end +$var wire 40 s# final_acc [39:0] $end +$var wire 40 t# bias_ext [39:0] $end +$var wire 40 u# acc_next [39:0] $end +$var parameter 32 v# ACC_WIDTH $end +$var parameter 32 w# DATA_WIDTH $end +$var parameter 32 x# FRAC_BITS $end +$var parameter 32 y# GROUPS $end +$var parameter 32 z# GROUP_INDEX_WIDTH $end +$var parameter 32 {# N_INPUTS $end +$var parameter 32 |# PARALLEL $end +$var reg 40 }# acc [39:0] $end +$var reg 1 ~# busy $end +$var reg 1 !$ done $end +$var reg 3 "$ group_index [2:0] $end +$var reg 16 #$ y [15:0] $end +$scope module u_mac8 $end +$var wire 40 $$ acc_in [39:0] $end +$var wire 128 %$ w_bus [127:0] $end +$var wire 128 &$ x_bus [127:0] $end +$var wire 40 '$ sum [39:0] $end +$var wire 40 ($ s5 [39:0] $end +$var wire 40 )$ s4 [39:0] $end +$var wire 40 *$ s3 [39:0] $end +$var wire 40 +$ s2 [39:0] $end +$var wire 40 ,$ s1 [39:0] $end +$var wire 40 -$ s0 [39:0] $end +$var wire 40 .$ m7 [39:0] $end +$var wire 40 /$ m6 [39:0] $end +$var wire 40 0$ m5 [39:0] $end +$var wire 40 1$ m4 [39:0] $end +$var wire 40 2$ m3 [39:0] $end +$var wire 40 3$ m2 [39:0] $end +$var wire 40 4$ m1 [39:0] $end +$var wire 40 5$ m0 [39:0] $end +$var wire 40 6$ acc_out [39:0] $end +$var parameter 32 7$ ACC_WIDTH $end +$var parameter 32 8$ DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 9$ acc_in [39:0] $end +$var wire 16 :$ w [15:0] $end +$var wire 16 ;$ x [15:0] $end +$var wire 40 <$ product_ext [39:0] $end +$var wire 32 =$ product [31:0] $end +$var wire 40 >$ acc_out [39:0] $end +$var parameter 32 ?$ ACC_WIDTH $end +$var parameter 32 @$ DATA_WIDTH $end +$var parameter 64 A$ PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 B$ acc_in [39:0] $end +$var wire 16 C$ w [15:0] $end +$var wire 16 D$ x [15:0] $end +$var wire 40 E$ product_ext [39:0] $end +$var wire 32 F$ product [31:0] $end +$var wire 40 G$ acc_out [39:0] $end +$var parameter 32 H$ ACC_WIDTH $end +$var parameter 32 I$ DATA_WIDTH $end +$var parameter 64 J$ PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 K$ acc_in [39:0] $end +$var wire 16 L$ w [15:0] $end +$var wire 16 M$ x [15:0] $end +$var wire 40 N$ product_ext [39:0] $end +$var wire 32 O$ product [31:0] $end +$var wire 40 P$ acc_out [39:0] $end +$var parameter 32 Q$ ACC_WIDTH $end +$var parameter 32 R$ DATA_WIDTH $end +$var parameter 64 S$ PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 T$ acc_in [39:0] $end +$var wire 16 U$ w [15:0] $end +$var wire 16 V$ x [15:0] $end +$var wire 40 W$ product_ext [39:0] $end +$var wire 32 X$ product [31:0] $end +$var wire 40 Y$ acc_out [39:0] $end +$var parameter 32 Z$ ACC_WIDTH $end +$var parameter 32 [$ DATA_WIDTH $end +$var parameter 64 \$ PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 ]$ acc_in [39:0] $end +$var wire 16 ^$ w [15:0] $end +$var wire 16 _$ x [15:0] $end +$var wire 40 `$ product_ext [39:0] $end +$var wire 32 a$ product [31:0] $end +$var wire 40 b$ acc_out [39:0] $end +$var parameter 32 c$ ACC_WIDTH $end +$var parameter 32 d$ DATA_WIDTH $end +$var parameter 64 e$ PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 f$ acc_in [39:0] $end +$var wire 16 g$ w [15:0] $end +$var wire 16 h$ x [15:0] $end +$var wire 40 i$ product_ext [39:0] $end +$var wire 32 j$ product [31:0] $end +$var wire 40 k$ acc_out [39:0] $end +$var parameter 32 l$ ACC_WIDTH $end +$var parameter 32 m$ DATA_WIDTH $end +$var parameter 64 n$ PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 o$ acc_in [39:0] $end +$var wire 16 p$ w [15:0] $end +$var wire 16 q$ x [15:0] $end +$var wire 40 r$ product_ext [39:0] $end +$var wire 32 s$ product [31:0] $end +$var wire 40 t$ acc_out [39:0] $end +$var parameter 32 u$ ACC_WIDTH $end +$var parameter 32 v$ DATA_WIDTH $end +$var parameter 64 w$ PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 x$ acc_in [39:0] $end +$var wire 16 y$ w [15:0] $end +$var wire 16 z$ x [15:0] $end +$var wire 40 {$ product_ext [39:0] $end +$var wire 32 |$ product [31:0] $end +$var wire 40 }$ acc_out [39:0] $end +$var parameter 32 ~$ ACC_WIDTH $end +$var parameter 32 !% DATA_WIDTH $end +$var parameter 64 "% PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[3] $end +$var parameter 3 #% n $end +$scope module u_neuron $end +$var wire 16 $% bias [15:0] $end +$var wire 16 %% bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 1024 &% w_bus [1023:0] $end +$var wire 1024 '% x_bus [1023:0] $end +$var wire 128 (% x_group [127:0] $end +$var wire 128 )% w_group [127:0] $end +$var wire 40 *% final_value [39:0] $end +$var wire 40 +% final_acc [39:0] $end +$var wire 40 ,% bias_ext [39:0] $end +$var wire 40 -% acc_next [39:0] $end +$var parameter 32 .% ACC_WIDTH $end +$var parameter 32 /% DATA_WIDTH $end +$var parameter 32 0% FRAC_BITS $end +$var parameter 32 1% GROUPS $end +$var parameter 32 2% GROUP_INDEX_WIDTH $end +$var parameter 32 3% N_INPUTS $end +$var parameter 32 4% PARALLEL $end +$var reg 40 5% acc [39:0] $end +$var reg 1 6% busy $end +$var reg 1 7% done $end +$var reg 3 8% group_index [2:0] $end +$var reg 16 9% y [15:0] $end +$scope module u_mac8 $end +$var wire 40 :% acc_in [39:0] $end +$var wire 128 ;% w_bus [127:0] $end +$var wire 128 <% x_bus [127:0] $end +$var wire 40 =% sum [39:0] $end +$var wire 40 >% s5 [39:0] $end +$var wire 40 ?% s4 [39:0] $end +$var wire 40 @% s3 [39:0] $end +$var wire 40 A% s2 [39:0] $end +$var wire 40 B% s1 [39:0] $end +$var wire 40 C% s0 [39:0] $end +$var wire 40 D% m7 [39:0] $end +$var wire 40 E% m6 [39:0] $end +$var wire 40 F% m5 [39:0] $end +$var wire 40 G% m4 [39:0] $end +$var wire 40 H% m3 [39:0] $end +$var wire 40 I% m2 [39:0] $end +$var wire 40 J% m1 [39:0] $end +$var wire 40 K% m0 [39:0] $end +$var wire 40 L% acc_out [39:0] $end +$var parameter 32 M% ACC_WIDTH $end +$var parameter 32 N% DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 O% acc_in [39:0] $end +$var wire 16 P% w [15:0] $end +$var wire 16 Q% x [15:0] $end +$var wire 40 R% product_ext [39:0] $end +$var wire 32 S% product [31:0] $end +$var wire 40 T% acc_out [39:0] $end +$var parameter 32 U% ACC_WIDTH $end +$var parameter 32 V% DATA_WIDTH $end +$var parameter 64 W% PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 X% acc_in [39:0] $end +$var wire 16 Y% w [15:0] $end +$var wire 16 Z% x [15:0] $end +$var wire 40 [% product_ext [39:0] $end +$var wire 32 \% product [31:0] $end +$var wire 40 ]% acc_out [39:0] $end +$var parameter 32 ^% ACC_WIDTH $end +$var parameter 32 _% DATA_WIDTH $end +$var parameter 64 `% PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 a% acc_in [39:0] $end +$var wire 16 b% w [15:0] $end +$var wire 16 c% x [15:0] $end +$var wire 40 d% product_ext [39:0] $end +$var wire 32 e% product [31:0] $end +$var wire 40 f% acc_out [39:0] $end +$var parameter 32 g% ACC_WIDTH $end +$var parameter 32 h% DATA_WIDTH $end +$var parameter 64 i% PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 j% acc_in [39:0] $end +$var wire 16 k% w [15:0] $end +$var wire 16 l% x [15:0] $end +$var wire 40 m% product_ext [39:0] $end +$var wire 32 n% product [31:0] $end +$var wire 40 o% acc_out [39:0] $end +$var parameter 32 p% ACC_WIDTH $end +$var parameter 32 q% DATA_WIDTH $end +$var parameter 64 r% PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 s% acc_in [39:0] $end +$var wire 16 t% w [15:0] $end +$var wire 16 u% x [15:0] $end +$var wire 40 v% product_ext [39:0] $end +$var wire 32 w% product [31:0] $end +$var wire 40 x% acc_out [39:0] $end +$var parameter 32 y% ACC_WIDTH $end +$var parameter 32 z% DATA_WIDTH $end +$var parameter 64 {% PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 |% acc_in [39:0] $end +$var wire 16 }% w [15:0] $end +$var wire 16 ~% x [15:0] $end +$var wire 40 !& product_ext [39:0] $end +$var wire 32 "& product [31:0] $end +$var wire 40 #& acc_out [39:0] $end +$var parameter 32 $& ACC_WIDTH $end +$var parameter 32 %& DATA_WIDTH $end +$var parameter 64 && PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 '& acc_in [39:0] $end +$var wire 16 (& w [15:0] $end +$var wire 16 )& x [15:0] $end +$var wire 40 *& product_ext [39:0] $end +$var wire 32 +& product [31:0] $end +$var wire 40 ,& acc_out [39:0] $end +$var parameter 32 -& ACC_WIDTH $end +$var parameter 32 .& DATA_WIDTH $end +$var parameter 64 /& PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 0& acc_in [39:0] $end +$var wire 16 1& w [15:0] $end +$var wire 16 2& x [15:0] $end +$var wire 40 3& product_ext [39:0] $end +$var wire 32 4& product [31:0] $end +$var wire 40 5& acc_out [39:0] $end +$var parameter 32 6& ACC_WIDTH $end +$var parameter 32 7& DATA_WIDTH $end +$var parameter 64 8& PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[4] $end +$var parameter 4 9& n $end +$scope module u_neuron $end +$var wire 16 :& bias [15:0] $end +$var wire 16 ;& bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 1024 <& w_bus [1023:0] $end +$var wire 1024 =& x_bus [1023:0] $end +$var wire 128 >& x_group [127:0] $end +$var wire 128 ?& w_group [127:0] $end +$var wire 40 @& final_value [39:0] $end +$var wire 40 A& final_acc [39:0] $end +$var wire 40 B& bias_ext [39:0] $end +$var wire 40 C& acc_next [39:0] $end +$var parameter 32 D& ACC_WIDTH $end +$var parameter 32 E& DATA_WIDTH $end +$var parameter 32 F& FRAC_BITS $end +$var parameter 32 G& GROUPS $end +$var parameter 32 H& GROUP_INDEX_WIDTH $end +$var parameter 32 I& N_INPUTS $end +$var parameter 32 J& PARALLEL $end +$var reg 40 K& acc [39:0] $end +$var reg 1 L& busy $end +$var reg 1 M& done $end +$var reg 3 N& group_index [2:0] $end +$var reg 16 O& y [15:0] $end +$scope module u_mac8 $end +$var wire 40 P& acc_in [39:0] $end +$var wire 128 Q& w_bus [127:0] $end +$var wire 128 R& x_bus [127:0] $end +$var wire 40 S& sum [39:0] $end +$var wire 40 T& s5 [39:0] $end +$var wire 40 U& s4 [39:0] $end +$var wire 40 V& s3 [39:0] $end +$var wire 40 W& s2 [39:0] $end +$var wire 40 X& s1 [39:0] $end +$var wire 40 Y& s0 [39:0] $end +$var wire 40 Z& m7 [39:0] $end +$var wire 40 [& m6 [39:0] $end +$var wire 40 \& m5 [39:0] $end +$var wire 40 ]& m4 [39:0] $end +$var wire 40 ^& m3 [39:0] $end +$var wire 40 _& m2 [39:0] $end +$var wire 40 `& m1 [39:0] $end +$var wire 40 a& m0 [39:0] $end +$var wire 40 b& acc_out [39:0] $end +$var parameter 32 c& ACC_WIDTH $end +$var parameter 32 d& DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 e& acc_in [39:0] $end +$var wire 16 f& w [15:0] $end +$var wire 16 g& x [15:0] $end +$var wire 40 h& product_ext [39:0] $end +$var wire 32 i& product [31:0] $end +$var wire 40 j& acc_out [39:0] $end +$var parameter 32 k& ACC_WIDTH $end +$var parameter 32 l& DATA_WIDTH $end +$var parameter 64 m& PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 n& acc_in [39:0] $end +$var wire 16 o& w [15:0] $end +$var wire 16 p& x [15:0] $end +$var wire 40 q& product_ext [39:0] $end +$var wire 32 r& product [31:0] $end +$var wire 40 s& acc_out [39:0] $end +$var parameter 32 t& ACC_WIDTH $end +$var parameter 32 u& DATA_WIDTH $end +$var parameter 64 v& PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 w& acc_in [39:0] $end +$var wire 16 x& w [15:0] $end +$var wire 16 y& x [15:0] $end +$var wire 40 z& product_ext [39:0] $end +$var wire 32 {& product [31:0] $end +$var wire 40 |& acc_out [39:0] $end +$var parameter 32 }& ACC_WIDTH $end +$var parameter 32 ~& DATA_WIDTH $end +$var parameter 64 !' PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 "' acc_in [39:0] $end +$var wire 16 #' w [15:0] $end +$var wire 16 $' x [15:0] $end +$var wire 40 %' product_ext [39:0] $end +$var wire 32 &' product [31:0] $end +$var wire 40 '' acc_out [39:0] $end +$var parameter 32 (' ACC_WIDTH $end +$var parameter 32 )' DATA_WIDTH $end +$var parameter 64 *' PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 +' acc_in [39:0] $end +$var wire 16 ,' w [15:0] $end +$var wire 16 -' x [15:0] $end +$var wire 40 .' product_ext [39:0] $end +$var wire 32 /' product [31:0] $end +$var wire 40 0' acc_out [39:0] $end +$var parameter 32 1' ACC_WIDTH $end +$var parameter 32 2' DATA_WIDTH $end +$var parameter 64 3' PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 4' acc_in [39:0] $end +$var wire 16 5' w [15:0] $end +$var wire 16 6' x [15:0] $end +$var wire 40 7' product_ext [39:0] $end +$var wire 32 8' product [31:0] $end +$var wire 40 9' acc_out [39:0] $end +$var parameter 32 :' ACC_WIDTH $end +$var parameter 32 ;' DATA_WIDTH $end +$var parameter 64 <' PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 =' acc_in [39:0] $end +$var wire 16 >' w [15:0] $end +$var wire 16 ?' x [15:0] $end +$var wire 40 @' product_ext [39:0] $end +$var wire 32 A' product [31:0] $end +$var wire 40 B' acc_out [39:0] $end +$var parameter 32 C' ACC_WIDTH $end +$var parameter 32 D' DATA_WIDTH $end +$var parameter 64 E' PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 F' acc_in [39:0] $end +$var wire 16 G' w [15:0] $end +$var wire 16 H' x [15:0] $end +$var wire 40 I' product_ext [39:0] $end +$var wire 32 J' product [31:0] $end +$var wire 40 K' acc_out [39:0] $end +$var parameter 32 L' ACC_WIDTH $end +$var parameter 32 M' DATA_WIDTH $end +$var parameter 64 N' PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[5] $end +$var parameter 4 O' n $end +$scope module u_neuron $end +$var wire 16 P' bias [15:0] $end +$var wire 16 Q' bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 1024 R' w_bus [1023:0] $end +$var wire 1024 S' x_bus [1023:0] $end +$var wire 128 T' x_group [127:0] $end +$var wire 128 U' w_group [127:0] $end +$var wire 40 V' final_value [39:0] $end +$var wire 40 W' final_acc [39:0] $end +$var wire 40 X' bias_ext [39:0] $end +$var wire 40 Y' acc_next [39:0] $end +$var parameter 32 Z' ACC_WIDTH $end +$var parameter 32 [' DATA_WIDTH $end +$var parameter 32 \' FRAC_BITS $end +$var parameter 32 ]' GROUPS $end +$var parameter 32 ^' GROUP_INDEX_WIDTH $end +$var parameter 32 _' N_INPUTS $end +$var parameter 32 `' PARALLEL $end +$var reg 40 a' acc [39:0] $end +$var reg 1 b' busy $end +$var reg 1 c' done $end +$var reg 3 d' group_index [2:0] $end +$var reg 16 e' y [15:0] $end +$scope module u_mac8 $end +$var wire 40 f' acc_in [39:0] $end +$var wire 128 g' w_bus [127:0] $end +$var wire 128 h' x_bus [127:0] $end +$var wire 40 i' sum [39:0] $end +$var wire 40 j' s5 [39:0] $end +$var wire 40 k' s4 [39:0] $end +$var wire 40 l' s3 [39:0] $end +$var wire 40 m' s2 [39:0] $end +$var wire 40 n' s1 [39:0] $end +$var wire 40 o' s0 [39:0] $end +$var wire 40 p' m7 [39:0] $end +$var wire 40 q' m6 [39:0] $end +$var wire 40 r' m5 [39:0] $end +$var wire 40 s' m4 [39:0] $end +$var wire 40 t' m3 [39:0] $end +$var wire 40 u' m2 [39:0] $end +$var wire 40 v' m1 [39:0] $end +$var wire 40 w' m0 [39:0] $end +$var wire 40 x' acc_out [39:0] $end +$var parameter 32 y' ACC_WIDTH $end +$var parameter 32 z' DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 {' acc_in [39:0] $end +$var wire 16 |' w [15:0] $end +$var wire 16 }' x [15:0] $end +$var wire 40 ~' product_ext [39:0] $end +$var wire 32 !( product [31:0] $end +$var wire 40 "( acc_out [39:0] $end +$var parameter 32 #( ACC_WIDTH $end +$var parameter 32 $( DATA_WIDTH $end +$var parameter 64 %( PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 &( acc_in [39:0] $end +$var wire 16 '( w [15:0] $end +$var wire 16 (( x [15:0] $end +$var wire 40 )( product_ext [39:0] $end +$var wire 32 *( product [31:0] $end +$var wire 40 +( acc_out [39:0] $end +$var parameter 32 ,( ACC_WIDTH $end +$var parameter 32 -( DATA_WIDTH $end +$var parameter 64 .( PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 /( acc_in [39:0] $end +$var wire 16 0( w [15:0] $end +$var wire 16 1( x [15:0] $end +$var wire 40 2( product_ext [39:0] $end +$var wire 32 3( product [31:0] $end +$var wire 40 4( acc_out [39:0] $end +$var parameter 32 5( ACC_WIDTH $end +$var parameter 32 6( DATA_WIDTH $end +$var parameter 64 7( PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 8( acc_in [39:0] $end +$var wire 16 9( w [15:0] $end +$var wire 16 :( x [15:0] $end +$var wire 40 ;( product_ext [39:0] $end +$var wire 32 <( product [31:0] $end +$var wire 40 =( acc_out [39:0] $end +$var parameter 32 >( ACC_WIDTH $end +$var parameter 32 ?( DATA_WIDTH $end +$var parameter 64 @( PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 A( acc_in [39:0] $end +$var wire 16 B( w [15:0] $end +$var wire 16 C( x [15:0] $end +$var wire 40 D( product_ext [39:0] $end +$var wire 32 E( product [31:0] $end +$var wire 40 F( acc_out [39:0] $end +$var parameter 32 G( ACC_WIDTH $end +$var parameter 32 H( DATA_WIDTH $end +$var parameter 64 I( PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 J( acc_in [39:0] $end +$var wire 16 K( w [15:0] $end +$var wire 16 L( x [15:0] $end +$var wire 40 M( product_ext [39:0] $end +$var wire 32 N( product [31:0] $end +$var wire 40 O( acc_out [39:0] $end +$var parameter 32 P( ACC_WIDTH $end +$var parameter 32 Q( DATA_WIDTH $end +$var parameter 64 R( PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 S( acc_in [39:0] $end +$var wire 16 T( w [15:0] $end +$var wire 16 U( x [15:0] $end +$var wire 40 V( product_ext [39:0] $end +$var wire 32 W( product [31:0] $end +$var wire 40 X( acc_out [39:0] $end +$var parameter 32 Y( ACC_WIDTH $end +$var parameter 32 Z( DATA_WIDTH $end +$var parameter 64 [( PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 \( acc_in [39:0] $end +$var wire 16 ]( w [15:0] $end +$var wire 16 ^( x [15:0] $end +$var wire 40 _( product_ext [39:0] $end +$var wire 32 `( product [31:0] $end +$var wire 40 a( acc_out [39:0] $end +$var parameter 32 b( ACC_WIDTH $end +$var parameter 32 c( DATA_WIDTH $end +$var parameter 64 d( PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[6] $end +$var parameter 4 e( n $end +$scope module u_neuron $end +$var wire 16 f( bias [15:0] $end +$var wire 16 g( bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 1024 h( w_bus [1023:0] $end +$var wire 1024 i( x_bus [1023:0] $end +$var wire 128 j( x_group [127:0] $end +$var wire 128 k( w_group [127:0] $end +$var wire 40 l( final_value [39:0] $end +$var wire 40 m( final_acc [39:0] $end +$var wire 40 n( bias_ext [39:0] $end +$var wire 40 o( acc_next [39:0] $end +$var parameter 32 p( ACC_WIDTH $end +$var parameter 32 q( DATA_WIDTH $end +$var parameter 32 r( FRAC_BITS $end +$var parameter 32 s( GROUPS $end +$var parameter 32 t( GROUP_INDEX_WIDTH $end +$var parameter 32 u( N_INPUTS $end +$var parameter 32 v( PARALLEL $end +$var reg 40 w( acc [39:0] $end +$var reg 1 x( busy $end +$var reg 1 y( done $end +$var reg 3 z( group_index [2:0] $end +$var reg 16 {( y [15:0] $end +$scope module u_mac8 $end +$var wire 40 |( acc_in [39:0] $end +$var wire 128 }( w_bus [127:0] $end +$var wire 128 ~( x_bus [127:0] $end +$var wire 40 !) sum [39:0] $end +$var wire 40 ") s5 [39:0] $end +$var wire 40 #) s4 [39:0] $end +$var wire 40 $) s3 [39:0] $end +$var wire 40 %) s2 [39:0] $end +$var wire 40 &) s1 [39:0] $end +$var wire 40 ') s0 [39:0] $end +$var wire 40 () m7 [39:0] $end +$var wire 40 )) m6 [39:0] $end +$var wire 40 *) m5 [39:0] $end +$var wire 40 +) m4 [39:0] $end +$var wire 40 ,) m3 [39:0] $end +$var wire 40 -) m2 [39:0] $end +$var wire 40 .) m1 [39:0] $end +$var wire 40 /) m0 [39:0] $end +$var wire 40 0) acc_out [39:0] $end +$var parameter 32 1) ACC_WIDTH $end +$var parameter 32 2) DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 3) acc_in [39:0] $end +$var wire 16 4) w [15:0] $end +$var wire 16 5) x [15:0] $end +$var wire 40 6) product_ext [39:0] $end +$var wire 32 7) product [31:0] $end +$var wire 40 8) acc_out [39:0] $end +$var parameter 32 9) ACC_WIDTH $end +$var parameter 32 :) DATA_WIDTH $end +$var parameter 64 ;) PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 <) acc_in [39:0] $end +$var wire 16 =) w [15:0] $end +$var wire 16 >) x [15:0] $end +$var wire 40 ?) product_ext [39:0] $end +$var wire 32 @) product [31:0] $end +$var wire 40 A) acc_out [39:0] $end +$var parameter 32 B) ACC_WIDTH $end +$var parameter 32 C) DATA_WIDTH $end +$var parameter 64 D) PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 E) acc_in [39:0] $end +$var wire 16 F) w [15:0] $end +$var wire 16 G) x [15:0] $end +$var wire 40 H) product_ext [39:0] $end +$var wire 32 I) product [31:0] $end +$var wire 40 J) acc_out [39:0] $end +$var parameter 32 K) ACC_WIDTH $end +$var parameter 32 L) DATA_WIDTH $end +$var parameter 64 M) PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 N) acc_in [39:0] $end +$var wire 16 O) w [15:0] $end +$var wire 16 P) x [15:0] $end +$var wire 40 Q) product_ext [39:0] $end +$var wire 32 R) product [31:0] $end +$var wire 40 S) acc_out [39:0] $end +$var parameter 32 T) ACC_WIDTH $end +$var parameter 32 U) DATA_WIDTH $end +$var parameter 64 V) PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 W) acc_in [39:0] $end +$var wire 16 X) w [15:0] $end +$var wire 16 Y) x [15:0] $end +$var wire 40 Z) product_ext [39:0] $end +$var wire 32 [) product [31:0] $end +$var wire 40 \) acc_out [39:0] $end +$var parameter 32 ]) ACC_WIDTH $end +$var parameter 32 ^) DATA_WIDTH $end +$var parameter 64 _) PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 `) acc_in [39:0] $end +$var wire 16 a) w [15:0] $end +$var wire 16 b) x [15:0] $end +$var wire 40 c) product_ext [39:0] $end +$var wire 32 d) product [31:0] $end +$var wire 40 e) acc_out [39:0] $end +$var parameter 32 f) ACC_WIDTH $end +$var parameter 32 g) DATA_WIDTH $end +$var parameter 64 h) PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 i) acc_in [39:0] $end +$var wire 16 j) w [15:0] $end +$var wire 16 k) x [15:0] $end +$var wire 40 l) product_ext [39:0] $end +$var wire 32 m) product [31:0] $end +$var wire 40 n) acc_out [39:0] $end +$var parameter 32 o) ACC_WIDTH $end +$var parameter 32 p) DATA_WIDTH $end +$var parameter 64 q) PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 r) acc_in [39:0] $end +$var wire 16 s) w [15:0] $end +$var wire 16 t) x [15:0] $end +$var wire 40 u) product_ext [39:0] $end +$var wire 32 v) product [31:0] $end +$var wire 40 w) acc_out [39:0] $end +$var parameter 32 x) ACC_WIDTH $end +$var parameter 32 y) DATA_WIDTH $end +$var parameter 64 z) PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[7] $end +$var parameter 4 {) n $end +$scope module u_neuron $end +$var wire 16 |) bias [15:0] $end +$var wire 16 }) bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 1024 ~) w_bus [1023:0] $end +$var wire 1024 !* x_bus [1023:0] $end +$var wire 128 "* x_group [127:0] $end +$var wire 128 #* w_group [127:0] $end +$var wire 40 $* final_value [39:0] $end +$var wire 40 %* final_acc [39:0] $end +$var wire 40 &* bias_ext [39:0] $end +$var wire 40 '* acc_next [39:0] $end +$var parameter 32 (* ACC_WIDTH $end +$var parameter 32 )* DATA_WIDTH $end +$var parameter 32 ** FRAC_BITS $end +$var parameter 32 +* GROUPS $end +$var parameter 32 ,* GROUP_INDEX_WIDTH $end +$var parameter 32 -* N_INPUTS $end +$var parameter 32 .* PARALLEL $end +$var reg 40 /* acc [39:0] $end +$var reg 1 0* busy $end +$var reg 1 1* done $end +$var reg 3 2* group_index [2:0] $end +$var reg 16 3* y [15:0] $end +$scope module u_mac8 $end +$var wire 40 4* acc_in [39:0] $end +$var wire 128 5* w_bus [127:0] $end +$var wire 128 6* x_bus [127:0] $end +$var wire 40 7* sum [39:0] $end +$var wire 40 8* s5 [39:0] $end +$var wire 40 9* s4 [39:0] $end +$var wire 40 :* s3 [39:0] $end +$var wire 40 ;* s2 [39:0] $end +$var wire 40 <* s1 [39:0] $end +$var wire 40 =* s0 [39:0] $end +$var wire 40 >* m7 [39:0] $end +$var wire 40 ?* m6 [39:0] $end +$var wire 40 @* m5 [39:0] $end +$var wire 40 A* m4 [39:0] $end +$var wire 40 B* m3 [39:0] $end +$var wire 40 C* m2 [39:0] $end +$var wire 40 D* m1 [39:0] $end +$var wire 40 E* m0 [39:0] $end +$var wire 40 F* acc_out [39:0] $end +$var parameter 32 G* ACC_WIDTH $end +$var parameter 32 H* DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 I* acc_in [39:0] $end +$var wire 16 J* w [15:0] $end +$var wire 16 K* x [15:0] $end +$var wire 40 L* product_ext [39:0] $end +$var wire 32 M* product [31:0] $end +$var wire 40 N* acc_out [39:0] $end +$var parameter 32 O* ACC_WIDTH $end +$var parameter 32 P* DATA_WIDTH $end +$var parameter 64 Q* PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 R* acc_in [39:0] $end +$var wire 16 S* w [15:0] $end +$var wire 16 T* x [15:0] $end +$var wire 40 U* product_ext [39:0] $end +$var wire 32 V* product [31:0] $end +$var wire 40 W* acc_out [39:0] $end +$var parameter 32 X* ACC_WIDTH $end +$var parameter 32 Y* DATA_WIDTH $end +$var parameter 64 Z* PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 [* acc_in [39:0] $end +$var wire 16 \* w [15:0] $end +$var wire 16 ]* x [15:0] $end +$var wire 40 ^* product_ext [39:0] $end +$var wire 32 _* product [31:0] $end +$var wire 40 `* acc_out [39:0] $end +$var parameter 32 a* ACC_WIDTH $end +$var parameter 32 b* DATA_WIDTH $end +$var parameter 64 c* PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 d* acc_in [39:0] $end +$var wire 16 e* w [15:0] $end +$var wire 16 f* x [15:0] $end +$var wire 40 g* product_ext [39:0] $end +$var wire 32 h* product [31:0] $end +$var wire 40 i* acc_out [39:0] $end +$var parameter 32 j* ACC_WIDTH $end +$var parameter 32 k* DATA_WIDTH $end +$var parameter 64 l* PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 m* acc_in [39:0] $end +$var wire 16 n* w [15:0] $end +$var wire 16 o* x [15:0] $end +$var wire 40 p* product_ext [39:0] $end +$var wire 32 q* product [31:0] $end +$var wire 40 r* acc_out [39:0] $end +$var parameter 32 s* ACC_WIDTH $end +$var parameter 32 t* DATA_WIDTH $end +$var parameter 64 u* PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 v* acc_in [39:0] $end +$var wire 16 w* w [15:0] $end +$var wire 16 x* x [15:0] $end +$var wire 40 y* product_ext [39:0] $end +$var wire 32 z* product [31:0] $end +$var wire 40 {* acc_out [39:0] $end +$var parameter 32 |* ACC_WIDTH $end +$var parameter 32 }* DATA_WIDTH $end +$var parameter 64 ~* PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 !+ acc_in [39:0] $end +$var wire 16 "+ w [15:0] $end +$var wire 16 #+ x [15:0] $end +$var wire 40 $+ product_ext [39:0] $end +$var wire 32 %+ product [31:0] $end +$var wire 40 &+ acc_out [39:0] $end +$var parameter 32 '+ ACC_WIDTH $end +$var parameter 32 (+ DATA_WIDTH $end +$var parameter 64 )+ PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 *+ acc_in [39:0] $end +$var wire 16 ++ w [15:0] $end +$var wire 16 ,+ x [15:0] $end +$var wire 40 -+ product_ext [39:0] $end +$var wire 32 .+ product [31:0] $end +$var wire 40 /+ acc_out [39:0] $end +$var parameter 32 0+ ACC_WIDTH $end +$var parameter 32 1+ DATA_WIDTH $end +$var parameter 64 2+ PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope task run_layer $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +b100000 2+ +b10000 1+ +b101000 0+ +b100000 )+ +b10000 (+ +b101000 '+ +b100000 ~* +b10000 }* +b101000 |* +b100000 u* +b10000 t* +b101000 s* +b100000 l* +b10000 k* +b101000 j* +b100000 c* +b10000 b* +b101000 a* +b100000 Z* +b10000 Y* +b101000 X* +b100000 Q* +b10000 P* +b101000 O* +b10000 H* +b101000 G* +b1000 .* +b1000000 -* +b11 ,* +b1000 +* +b1000 ** +b10000 )* +b101000 (* +b111 {) +b100000 z) +b10000 y) +b101000 x) +b100000 q) +b10000 p) +b101000 o) +b100000 h) +b10000 g) +b101000 f) +b100000 _) +b10000 ^) +b101000 ]) +b100000 V) +b10000 U) +b101000 T) +b100000 M) +b10000 L) +b101000 K) +b100000 D) +b10000 C) +b101000 B) +b100000 ;) +b10000 :) +b101000 9) +b10000 2) +b101000 1) +b1000 v( +b1000000 u( +b11 t( +b1000 s( +b1000 r( +b10000 q( +b101000 p( +b110 e( +b100000 d( +b10000 c( +b101000 b( +b100000 [( +b10000 Z( +b101000 Y( +b100000 R( +b10000 Q( +b101000 P( +b100000 I( +b10000 H( +b101000 G( +b100000 @( +b10000 ?( +b101000 >( +b100000 7( +b10000 6( +b101000 5( +b100000 .( +b10000 -( +b101000 ,( +b100000 %( +b10000 $( +b101000 #( +b10000 z' +b101000 y' +b1000 `' +b1000000 _' +b11 ^' +b1000 ]' +b1000 \' +b10000 [' +b101000 Z' +b101 O' +b100000 N' +b10000 M' +b101000 L' +b100000 E' +b10000 D' +b101000 C' +b100000 <' +b10000 ;' +b101000 :' +b100000 3' +b10000 2' +b101000 1' +b100000 *' +b10000 )' +b101000 (' +b100000 !' +b10000 ~& +b101000 }& +b100000 v& +b10000 u& +b101000 t& +b100000 m& +b10000 l& +b101000 k& +b10000 d& +b101000 c& +b1000 J& +b1000000 I& +b11 H& +b1000 G& +b1000 F& +b10000 E& +b101000 D& +b100 9& +b100000 8& +b10000 7& +b101000 6& +b100000 /& +b10000 .& +b101000 -& +b100000 && +b10000 %& +b101000 $& +b100000 {% +b10000 z% +b101000 y% +b100000 r% +b10000 q% +b101000 p% +b100000 i% +b10000 h% +b101000 g% +b100000 `% +b10000 _% +b101000 ^% +b100000 W% +b10000 V% +b101000 U% +b10000 N% +b101000 M% +b1000 4% +b1000000 3% +b11 2% +b1000 1% +b1000 0% +b10000 /% +b101000 .% +b11 #% +b100000 "% +b10000 !% +b101000 ~$ +b100000 w$ +b10000 v$ +b101000 u$ +b100000 n$ +b10000 m$ +b101000 l$ +b100000 e$ +b10000 d$ +b101000 c$ +b100000 \$ +b10000 [$ +b101000 Z$ +b100000 S$ +b10000 R$ +b101000 Q$ +b100000 J$ +b10000 I$ +b101000 H$ +b100000 A$ +b10000 @$ +b101000 ?$ +b10000 8$ +b101000 7$ +b1000 |# +b1000000 {# +b11 z# +b1000 y# +b1000 x# +b10000 w# +b101000 v# +b10 k# +b100000 j# +b10000 i# +b101000 h# +b100000 a# +b10000 `# +b101000 _# +b100000 X# +b10000 W# +b101000 V# +b100000 O# +b10000 N# +b101000 M# +b100000 F# +b10000 E# +b101000 D# +b100000 =# +b10000 <# +b101000 ;# +b100000 4# +b10000 3# +b101000 2# +b100000 +# +b10000 *# +b101000 )# +b10000 "# +b101000 !# +b1000 f" +b1000000 e" +b11 d" +b1000 c" +b1000 b" +b10000 a" +b101000 `" +b1 U" +b100000 T" +b10000 S" +b101000 R" +b100000 K" +b10000 J" +b101000 I" +b100000 B" +b10000 A" +b101000 @" +b100000 9" +b10000 8" +b101000 7" +b100000 0" +b10000 /" +b101000 ." +b100000 '" +b10000 &" +b101000 %" +b100000 | +b10000 { +b101000 z +b100000 s +b10000 r +b101000 q +b10000 j +b101000 i +b1000 P +b1000000 O +b11 N +b1000 M +b1000 L +b10000 K +b101000 J +b0 ? +b1000 > +b1000 = +b1000000 < +b1000 ; +b10000 : +b101000 9 +b1000 ) +b1000 ( +b1000000 ' +b1000 & +b10000 % +b101000 $ +$end +#0 +$dumpvars +bx /+ +bx .+ +bx -+ +bx ,+ +bx ++ +b0 *+ +bx &+ +bx %+ +bx $+ +bx #+ +bx "+ +b0 !+ +bx {* +bx z* +bx y* +bx x* +bx w* +b0 v* +bx r* +bx q* +bx p* +bx o* +bx n* +b0 m* +bx i* +bx h* +bx g* +bx f* +bx e* +b0 d* +bx `* +bx _* +bx ^* +bx ]* +bx \* +b0 [* +bx W* +bx V* +bx U* +bx T* +bx S* +b0 R* +bx N* +bx M* +bx L* +bx K* +bx J* +b0 I* +bx F* +bx E* +bx D* +bx C* +bx B* +bx A* +bx @* +bx ?* +bx >* +bx =* +bx <* +bx ;* +bx :* +bx 9* +bx 8* +bx 7* +bx 6* +bx 5* +bx 4* +bx 3* +bx 2* +x1* +x0* +bx /* +bx '* +b0 &* +bx %* +bx $* +bx #* +bx "* +b0 !* +b0 ~) +b0 }) +b0 |) +bx w) +bx v) +bx u) +bx t) +bx s) +b0 r) +bx n) +bx m) +bx l) +bx k) +bx j) +b0 i) +bx e) +bx d) +bx c) +bx b) +bx a) +b0 `) +bx \) +bx [) +bx Z) +bx Y) +bx X) +b0 W) +bx S) +bx R) +bx Q) +bx P) +bx O) +b0 N) +bx J) +bx I) +bx H) +bx G) +bx F) +b0 E) +bx A) +bx @) +bx ?) +bx >) +bx =) +b0 <) +bx 8) +bx 7) +bx 6) +bx 5) +bx 4) +b0 3) +bx 0) +bx /) +bx .) +bx -) +bx ,) +bx +) +bx *) +bx )) +bx () +bx ') +bx &) +bx %) +bx $) +bx #) +bx ") +bx !) +bx ~( +bx }( +bx |( +bx {( +bx z( +xy( +xx( +bx w( +bx o( +b0 n( +bx m( +bx l( +bx k( +bx j( +b0 i( +b0 h( +b0 g( +b0 f( +bx a( +bx `( +bx _( +bx ^( +bx ]( +b0 \( +bx X( +bx W( +bx V( +bx U( +bx T( +b0 S( +bx O( +bx N( +bx M( +bx L( +bx K( +b0 J( +bx F( +bx E( +bx D( +bx C( +bx B( +b0 A( +bx =( +bx <( +bx ;( +bx :( +bx 9( +b0 8( +bx 4( +bx 3( +bx 2( +bx 1( +bx 0( +b0 /( +bx +( +bx *( +bx )( +bx (( +bx '( +b0 &( +bx "( +bx !( +bx ~' +bx }' +bx |' +b0 {' +bx x' +bx w' +bx v' +bx u' +bx t' +bx s' +bx r' +bx q' +bx p' +bx o' +bx n' +bx m' +bx l' +bx k' +bx j' +bx i' +bx h' +bx g' +bx f' +bx e' +bx d' +xc' +xb' +bx a' +bx Y' +b0 X' +bx W' +bx V' +bx U' +bx T' +b0 S' +b0 R' +b0 Q' +b0 P' +bx K' +bx J' +bx I' +bx H' +bx G' +b0 F' +bx B' +bx A' +bx @' +bx ?' +bx >' +b0 =' +bx 9' +bx 8' +bx 7' +bx 6' +bx 5' +b0 4' +bx 0' +bx /' +bx .' +bx -' +bx ,' +b0 +' +bx '' +bx &' +bx %' +bx $' +bx #' +b0 "' +bx |& +bx {& +bx z& +bx y& +bx x& +b0 w& +bx s& +bx r& +bx q& +bx p& +bx o& +b0 n& +bx j& +bx i& +bx h& +bx g& +bx f& +b0 e& +bx b& +bx a& +bx `& +bx _& +bx ^& +bx ]& +bx \& +bx [& +bx Z& +bx Y& +bx X& +bx W& +bx V& +bx U& +bx T& +bx S& +bx R& +bx Q& +bx P& +bx O& +bx N& +xM& +xL& +bx K& +bx C& +b0 B& +bx A& +bx @& +bx ?& +bx >& +b0 =& +b0 <& +b0 ;& +b0 :& +bx 5& +bx 4& +bx 3& +bx 2& +bx 1& +b0 0& +bx ,& +bx +& +bx *& +bx )& +bx (& +b0 '& +bx #& +bx "& +bx !& +bx ~% +bx }% +b0 |% +bx x% +bx w% +bx v% +bx u% +bx t% +b0 s% +bx o% +bx n% +bx m% +bx l% +bx k% +b0 j% +bx f% +bx e% +bx d% +bx c% +bx b% +b0 a% +bx ]% +bx \% +bx [% +bx Z% +bx Y% +b0 X% +bx T% +bx S% +bx R% +bx Q% +bx P% +b0 O% +bx L% +bx K% +bx J% +bx I% +bx H% +bx G% +bx F% +bx E% +bx D% +bx C% +bx B% +bx A% +bx @% +bx ?% +bx >% +bx =% +bx <% +bx ;% +bx :% +bx 9% +bx 8% +x7% +x6% +bx 5% +bx -% +b0 ,% +bx +% +bx *% +bx )% +bx (% +b0 '% +b0 &% +b0 %% +b0 $% +bx }$ +bx |$ +bx {$ +bx z$ +bx y$ +b0 x$ +bx t$ +bx s$ +bx r$ +bx q$ +bx p$ +b0 o$ +bx k$ +bx j$ +bx i$ +bx h$ +bx g$ +b0 f$ +bx b$ +bx a$ +bx `$ +bx _$ +bx ^$ +b0 ]$ +bx Y$ +bx X$ +bx W$ +bx V$ +bx U$ +b0 T$ +bx P$ +bx O$ +bx N$ +bx M$ +bx L$ +b0 K$ +bx G$ +bx F$ +bx E$ +bx D$ +bx C$ +b0 B$ +bx >$ +bx =$ +bx <$ +bx ;$ +bx :$ +b0 9$ +bx 6$ +bx 5$ +bx 4$ +bx 3$ +bx 2$ +bx 1$ +bx 0$ +bx /$ +bx .$ +bx -$ +bx ,$ +bx +$ +bx *$ +bx )$ +bx ($ +bx '$ +bx &$ +bx %$ +bx $$ +bx #$ +bx "$ +x!$ +x~# +bx }# +bx u# +b0 t# +bx s# +bx r# +bx q# +bx p# +b0 o# +b0 n# +b0 m# +b0 l# +bx g# +bx f# +bx e# +bx d# +bx c# +b0 b# +bx ^# +bx ]# +bx \# +bx [# +bx Z# +b0 Y# +bx U# +bx T# +bx S# +bx R# +bx Q# +b0 P# +bx L# +bx K# +bx J# +bx I# +bx H# +b0 G# +bx C# +bx B# +bx A# +bx @# +bx ?# +b0 ># +bx :# +bx 9# +bx 8# +bx 7# +bx 6# +b0 5# +bx 1# +bx 0# +bx /# +bx .# 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3* +b101000000000000000000 %* +b100110000000000000000 '* +b100110000000000000000 F* +b100010000000000000000 /* +b100010000000000000000 4* +1+ +#110 +0+ +#115 +0" +b0 7 +01* +0y( +0c' +0M& +07% +0!$ +0i" +0S +1+ diff --git a/sim/layer_sim b/sim/layer_sim new file mode 100755 index 0000000..48f040f --- /dev/null +++ b/sim/layer_sim @@ -0,0 +1,3916 @@ +#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp +:ivl_version "13.0 (stable)" "(v13_0)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi"; +S_0x102e61f00 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x102e63dc0 .scope module, "tb" "tb" 3 1; + .timescale 0 0; +P_0x102e63ae0 .param/l "ACC_WIDTH" 0 3 8, +C4<00000000000000000000000000101000>; +P_0x102e63b20 .param/l "DATA_WIDTH" 0 3 3, +C4<00000000000000000000000000010000>; +P_0x102e63b60 .param/l "FRAC_BITS" 0 3 4, +C4<00000000000000000000000000001000>; +P_0x102e63ba0 .param/l "N_INPUTS" 0 3 5, +C4<00000000000000000000000001000000>; +P_0x102e63be0 .param/l "N_NEURONS" 0 3 6, +C4<00000000000000000000000000001000>; +P_0x102e63c20 .param/l "PARALLEL" 0 3 7, +C4<00000000000000000000000000001000>; +v0x8d2d17700_0 .var/s "bias_bus", 127 0; +v0x8d2d177a0_0 .net "busy", 0 0, L_0x8d323ce60; 1 drivers +v0x8d2d17840_0 .var "clk", 0 0; +v0x8d2d178e0_0 .net "done", 0 0, L_0x8d323cf00; 1 drivers +v0x8d2d17980_0 .var/i "errors", 31 0; +v0x8d2d17a20_0 .var/i "i", 31 0; +v0x8d2d17ac0_0 .var "rst", 0 0; +v0x8d2d17b60_0 .var "start", 0 0; +v0x8d2d17c00_0 .var/s "weights_bus", 8191 0; +v0x8d2d17ca0_0 .var/s "x_bus", 1023 0; +v0x8d2d17d40_0 .net/s "y_bus", 127 0, L_0x8d3239040; 1 drivers +S_0x102e5b4b0 .scope module, "dut" "layer" 3 39, 4 1 0, S_0x102e63dc0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 8192 "weights_bus"; + .port_info 5 /INPUT 128 "bias_bus"; + .port_info 6 /OUTPUT 128 "y_bus"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e5b630 .param/l "ACC_WIDTH" 0 4 7, +C4<00000000000000000000000000101000>; +P_0x102e5b670 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0x102e5b6b0 .param/l "FRAC_BITS" 0 4 3, +C4<00000000000000000000000000001000>; +P_0x102e5b6f0 .param/l "N_INPUTS" 0 4 4, +C4<00000000000000000000000001000000>; +P_0x102e5b730 .param/l "N_NEURONS" 0 4 5, +C4<00000000000000000000000000001000>; +P_0x102e5b770 .param/l "PARALLEL" 0 4 6, +C4<00000000000000000000000000001000>; +v0x8d2d16ee0_0 .net/s "bias_bus", 127 0, v0x8d2d17700_0; 1 drivers +v0x8d2d16f80_0 .net "busy", 0 0, L_0x8d323ce60; alias, 1 drivers +v0x8d2d17020_0 .net "clk", 0 0, v0x8d2d17840_0; 1 drivers +v0x8d2d170c0_0 .net "done", 0 0, L_0x8d323cf00; alias, 1 drivers +v0x8d2d17160_0 .net "neuron_busy", 7 0, L_0x8d32390e0; 1 drivers +v0x8d2d17200_0 .net "neuron_done", 7 0, L_0x8d3239180; 1 drivers +v0x8d2d172a0_0 .net "rst", 0 0, v0x8d2d17ac0_0; 1 drivers +v0x8d2d17340_0 .net "start", 0 0, v0x8d2d17b60_0; 1 drivers +v0x8d2d173e0_0 .net/s "weights_bus", 8191 0, v0x8d2d17c00_0; 1 drivers +v0x8d2d17480_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; 1 drivers +v0x8d2d17520_0 .net/s "y_bus", 127 0, L_0x8d3239040; alias, 1 drivers +L_0x8d321c500 .part v0x8d2d17c00_0, 0, 1024; +L_0x8d321c5a0 .part v0x8d2d17700_0, 0, 16; +L_0x8d321d860 .part v0x8d2d17c00_0, 1024, 1024; +L_0x8d321d900 .part v0x8d2d17700_0, 16, 16; +L_0x8d321ebc0 .part v0x8d2d17c00_0, 2048, 1024; +L_0x8d321ec60 .part v0x8d2d17700_0, 32, 16; +L_0x8d321ff20 .part v0x8d2d17c00_0, 3072, 1024; +L_0x8d322c000 .part v0x8d2d17700_0, 48, 16; +L_0x8d322d2c0 .part v0x8d2d17c00_0, 4096, 1024; +L_0x8d322d360 .part v0x8d2d17700_0, 64, 16; +L_0x8d322e620 .part v0x8d2d17c00_0, 5120, 1024; +L_0x8d322e6c0 .part v0x8d2d17700_0, 80, 16; +L_0x8d322f980 .part v0x8d2d17c00_0, 6144, 1024; +L_0x8d322fa20 .part v0x8d2d17700_0, 96, 16; +L_0x8d323cd20 .part v0x8d2d17c00_0, 7168, 1024; +L_0x8d323cdc0 .part v0x8d2d17700_0, 112, 16; +LS_0x8d3239040_0_0 .concat8 [ 16 16 16 16], v0x8d2cedd60_0, v0x8d2cf3200_0, v0x8d2cfc6e0_0, v0x8d2d01b80_0; +LS_0x8d3239040_0_4 .concat8 [ 16 16 16 16], v0x8d2d07020_0, v0x8d2d0c500_0, v0x8d2d119a0_0, v0x8d2d16e40_0; +L_0x8d3239040 .concat8 [ 64 64 0 0], LS_0x8d3239040_0_0, LS_0x8d3239040_0_4; +LS_0x8d32390e0_0_0 .concat8 [ 1 1 1 1], v0x8d2ced5e0_0, v0x8d2cf2a80_0, v0x8d2cf7f20_0, v0x8d2d01400_0; +LS_0x8d32390e0_0_4 .concat8 [ 1 1 1 1], v0x8d2d068a0_0, v0x8d2d0bd40_0, v0x8d2d11220_0, v0x8d2d166c0_0; +L_0x8d32390e0 .concat8 [ 4 4 0 0], LS_0x8d32390e0_0_0, LS_0x8d32390e0_0_4; +LS_0x8d3239180_0_0 .concat8 [ 1 1 1 1], v0x8d2ced720_0, v0x8d2cf2bc0_0, v0x8d2cfc0a0_0, v0x8d2d01540_0; +LS_0x8d3239180_0_4 .concat8 [ 1 1 1 1], v0x8d2d069e0_0, v0x8d2d0be80_0, v0x8d2d11360_0, v0x8d2d16800_0; +L_0x8d3239180 .concat8 [ 4 4 0 0], LS_0x8d3239180_0_0, LS_0x8d3239180_0_4; +L_0x8d323ce60 .reduce/or L_0x8d32390e0; +L_0x8d323cf00 .reduce/and L_0x8d3239180; +S_0x102e57820 .scope generate, "GEN_NEURON[0]" "GEN_NEURON[0]" 4 35, 4 35 0, S_0x102e5b4b0; + .timescale 0 0; +P_0x8d2c3b0c0 .param/l "n" 1 4 35, +C4<00>; +S_0x102e579a0 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x102e57820; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e50910 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x102e50950 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x102e50990 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x102e509d0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; +P_0x102e50a10 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; +P_0x102e50a50 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; +P_0x102e50a90 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x8d307c150 .functor BUFZ 16, L_0x8d321c5a0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8d2cec780_0 .net *"_ivl_0", 31 0, L_0x8d30c3e80; 1 drivers +v0x8d2cec820_0 .net *"_ivl_11", 31 0, L_0x8d2d17e80; 1 drivers +v0x8d2cec8c0_0 .net *"_ivl_14", 31 0, L_0x8d30c3f20; 1 drivers +L_0x8d28540e8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cec960_0 .net *"_ivl_17", 28 0, L_0x8d28540e8; 1 drivers +L_0x8d2854130 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2ceca00_0 .net/2u *"_ivl_18", 31 0, L_0x8d2854130; 1 drivers +v0x8d2cecaa0_0 .net *"_ivl_21", 31 0, L_0x8d2d17f20; 1 drivers +L_0x8d2854178 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2cecb40_0 .net/2u *"_ivl_22", 31 0, L_0x8d2854178; 1 drivers +v0x8d2cecbe0_0 .net *"_ivl_25", 31 0, L_0x8d2d18000; 1 drivers +L_0x8d2854010 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cecc80_0 .net *"_ivl_3", 28 0, L_0x8d2854010; 1 drivers +v0x8d2cecd20_0 .net *"_ivl_31", 0 0, L_0x8d321c320; 1 drivers +v0x8d2cecdc0_0 .net *"_ivl_33", 23 0, L_0x8d2d194a0; 1 drivers +v0x8d2cece60_0 .net *"_ivl_36", 39 0, L_0x8d3194fa0; 1 drivers +v0x8d2cecf00_0 .net *"_ivl_38", 31 0, L_0x8d321c3c0; 1 drivers +L_0x8d2854058 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2cecfa0_0 .net/2u *"_ivl_4", 31 0, L_0x8d2854058; 1 drivers +L_0x8d2854400 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8d2ced040_0 .net *"_ivl_40", 7 0, L_0x8d2854400; 1 drivers +v0x8d2ced0e0_0 .net *"_ivl_46", 31 0, L_0x8d321c460; 1 drivers +v0x8d2ced180_0 .net *"_ivl_7", 31 0, L_0x8d2d17de0; 1 drivers +L_0x8d28540a0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2ced220_0 .net/2u *"_ivl_8", 31 0, L_0x8d28540a0; 1 drivers +v0x8d2ced2c0_0 .var/s "acc", 39 0; +v0x8d2ced360_0 .net/s "acc_next", 39 0, L_0x8d3194e60; 1 drivers +v0x8d2ced400_0 .net/s "bias", 15 0, L_0x8d321c5a0; 1 drivers +v0x8d2ced4a0_0 .net/s "bias_ext", 39 0, L_0x8d3194f00; 1 drivers +v0x8d2ced540_0 .net/s "bias_ext_small", 15 0, L_0x8d307c150; 1 drivers +v0x8d2ced5e0_0 .var "busy", 0 0; +v0x8d2ced680_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers +v0x8d2ced720_0 .var "done", 0 0; +v0x8d2ced7c0_0 .net/s "final_acc", 39 0, L_0x8d3195040; 1 drivers +v0x8d2ced860_0 .net/s "final_value", 39 0, L_0x8d2d19540; 1 drivers +v0x8d2ced900_0 .var "group_index", 2 0; +v0x8d2ced9a0_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers +v0x8d2ceda40_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers +v0x8d2cedae0_0 .net/s "w_bus", 1023 0, L_0x8d321c500; 1 drivers +v0x8d2cedb80_0 .net/s "w_group", 127 0, L_0x8d318b5c0; 1 drivers +v0x8d2cedc20_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers +v0x8d2cedcc0_0 .net/s "x_group", 127 0, L_0x8d318b8e0; 1 drivers +v0x8d2cedd60_0 .var/s "y", 15 0; +E_0x8d2ce4340 .event posedge, v0x8d2ced680_0; +L_0x8d30c3e80 .concat [ 3 29 0 0], v0x8d2ced900_0, L_0x8d2854010; +L_0x8d2d17de0 .arith/mult 32, L_0x8d30c3e80, L_0x8d2854058; +L_0x8d2d17e80 .arith/mult 32, L_0x8d2d17de0, L_0x8d28540a0; +L_0x8d318b8e0 .part/v v0x8d2d17ca0_0, L_0x8d2d17e80, 128; +L_0x8d30c3f20 .concat [ 3 29 0 0], v0x8d2ced900_0, L_0x8d28540e8; +L_0x8d2d17f20 .arith/mult 32, L_0x8d30c3f20, L_0x8d2854130; +L_0x8d2d18000 .arith/mult 32, L_0x8d2d17f20, L_0x8d2854178; +L_0x8d318b5c0 .part/v L_0x8d321c500, L_0x8d2d18000, 128; +L_0x8d321c320 .part L_0x8d307c150, 15, 1; +L_0x8d2d194a0 .repeat 24, 24, L_0x8d321c320; +L_0x8d3194f00 .concat [ 16 24 0 0], L_0x8d307c150, L_0x8d2d194a0; +L_0x8d321c3c0 .part L_0x8d3194f00, 0, 32; +L_0x8d3194fa0 .concat [ 8 32 0 0], L_0x8d2854400, L_0x8d321c3c0; +L_0x8d3195040 .arith/sum 40, L_0x8d3194e60, L_0x8d3194fa0; +L_0x8d321c460 .part L_0x8d3195040, 8, 32; +L_0x8d2d19540 .extend/s 40, L_0x8d321c460; +S_0x102e52fe0 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x102e579a0; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d30a0600 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8d30a0640 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8d2c9bb60_0 .net/s "acc_in", 39 0, v0x8d2ced2c0_0; 1 drivers +v0x8d2c9bc00_0 .net/s "acc_out", 39 0, L_0x8d3194e60; alias, 1 drivers +v0x8d2c9bca0_0 .net/s "m0", 39 0, L_0x8d31940a0; 1 drivers +v0x8d2c9bd40_0 .net/s "m1", 39 0, L_0x8d31941e0; 1 drivers +v0x8d2c9bde0_0 .net/s "m2", 39 0, L_0x8d3194320; 1 drivers +v0x8d2c9be80_0 .net/s "m3", 39 0, L_0x8d3194460; 1 drivers +v0x8d2c9bf20_0 .net/s "m4", 39 0, L_0x8d31945a0; 1 drivers +v0x8d2cec000_0 .net/s "m5", 39 0, L_0x8d31946e0; 1 drivers +v0x8d2cec0a0_0 .net/s "m6", 39 0, L_0x8d3194820; 1 drivers +v0x8d2cec140_0 .net/s "m7", 39 0, L_0x8d3194960; 1 drivers +v0x8d2cec1e0_0 .net/s "s0", 39 0, L_0x8d3194a00; 1 drivers +v0x8d2cec280_0 .net/s "s1", 39 0, L_0x8d3194aa0; 1 drivers +v0x8d2cec320_0 .net/s "s2", 39 0, L_0x8d3194b40; 1 drivers +v0x8d2cec3c0_0 .net/s "s3", 39 0, L_0x8d3194be0; 1 drivers +v0x8d2cec460_0 .net/s "s4", 39 0, L_0x8d3194c80; 1 drivers +v0x8d2cec500_0 .net/s "s5", 39 0, L_0x8d3194d20; 1 drivers +v0x8d2cec5a0_0 .net/s "sum", 39 0, L_0x8d3194dc0; 1 drivers +v0x8d2cec640_0 .net/s "w_bus", 127 0, L_0x8d318b5c0; alias, 1 drivers +v0x8d2cec6e0_0 .net/s "x_bus", 127 0, L_0x8d318b8e0; alias, 1 drivers +L_0x8d318ba20 .part L_0x8d318b8e0, 0, 16; +L_0x8d318bac0 .part L_0x8d318b5c0, 0, 16; +L_0x8d318bc00 .part L_0x8d318b8e0, 16, 16; +L_0x8d318bca0 .part L_0x8d318b5c0, 16, 16; +L_0x8d318bde0 .part L_0x8d318b8e0, 32, 16; +L_0x8d318be80 .part L_0x8d318b5c0, 32, 16; +L_0x8d3064460 .part L_0x8d318b8e0, 48, 16; +L_0x8d3064500 .part L_0x8d318b5c0, 48, 16; +L_0x8d317b7a0 .part L_0x8d318b8e0, 64, 16; +L_0x8d316f980 .part L_0x8d318b5c0, 64, 16; +L_0x8d313fd40 .part L_0x8d318b8e0, 80, 16; +L_0x8d3137f20 .part L_0x8d318b5c0, 80, 16; +L_0x8d321c000 .part L_0x8d318b8e0, 96, 16; +L_0x8d321c0a0 .part L_0x8d318b5c0, 96, 16; +L_0x8d321c1e0 .part L_0x8d318b8e0, 112, 16; +L_0x8d321c280 .part L_0x8d318b5c0, 112, 16; +L_0x8d3194a00 .arith/sum 40, L_0x8d31940a0, L_0x8d31941e0; +L_0x8d3194aa0 .arith/sum 40, L_0x8d3194320, L_0x8d3194460; +L_0x8d3194b40 .arith/sum 40, L_0x8d31945a0, L_0x8d31946e0; +L_0x8d3194be0 .arith/sum 40, L_0x8d3194820, L_0x8d3194960; +L_0x8d3194c80 .arith/sum 40, L_0x8d3194a00, L_0x8d3194aa0; +L_0x8d3194d20 .arith/sum 40, L_0x8d3194b40, L_0x8d3194be0; +L_0x8d3194dc0 .arith/sum 40, L_0x8d3194c80, L_0x8d3194d20; +L_0x8d3194e60 .arith/sum 40, v0x8d2ced2c0_0, L_0x8d3194dc0; +S_0x102e53160 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x102e52fe0; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c0c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c100 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c140 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2c98960_0 .net/s *"_ivl_0", 31 0, L_0x8d2d180a0; 1 drivers +v0x8d2c98a00_0 .net/s *"_ivl_2", 31 0, L_0x8d2d18140; 1 drivers +v0x8d2c98aa0_0 .net *"_ivl_7", 0 0, L_0x8d318b980; 1 drivers +v0x8d2c98b40_0 .net *"_ivl_9", 7 0, L_0x8d2d18280; 1 drivers +L_0x8d28541c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2c98be0_0 .net/s "acc_in", 39 0, L_0x8d28541c0; 1 drivers +v0x8d2c98c80_0 .net/s "acc_out", 39 0, L_0x8d31940a0; alias, 1 drivers +v0x8d2c98d20_0 .net/s "product", 31 0, L_0x8d2d181e0; 1 drivers +v0x8d2c98dc0_0 .net/s "product_ext", 39 0, L_0x8d3194000; 1 drivers +v0x8d2c98e60_0 .net/s "w", 15 0, L_0x8d318bac0; 1 drivers +v0x8d2c98f00_0 .net/s "x", 15 0, L_0x8d318ba20; 1 drivers +L_0x8d2d180a0 .extend/s 32, L_0x8d318ba20; +L_0x8d2d18140 .extend/s 32, L_0x8d318bac0; +L_0x8d2d181e0 .arith/mult 32, L_0x8d2d180a0, L_0x8d2d18140; +L_0x8d318b980 .part L_0x8d2d181e0, 31, 1; +L_0x8d2d18280 .repeat 8, 8, L_0x8d318b980; +L_0x8d3194000 .concat [ 32 8 0 0], L_0x8d2d181e0, L_0x8d2d18280; +L_0x8d31940a0 .arith/sum 40, L_0x8d28541c0, L_0x8d3194000; +S_0x102e5aa50 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x102e52fe0; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c180 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c1c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c200 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2c98fa0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18320; 1 drivers +v0x8d2c99040_0 .net/s *"_ivl_2", 31 0, L_0x8d2d183c0; 1 drivers +v0x8d2c990e0_0 .net *"_ivl_7", 0 0, L_0x8d318bb60; 1 drivers +v0x8d2c99180_0 .net *"_ivl_9", 7 0, L_0x8d2d18500; 1 drivers +L_0x8d2854208 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2c99220_0 .net/s "acc_in", 39 0, L_0x8d2854208; 1 drivers +v0x8d2c992c0_0 .net/s "acc_out", 39 0, L_0x8d31941e0; alias, 1 drivers +v0x8d2c99360_0 .net/s "product", 31 0, L_0x8d2d18460; 1 drivers +v0x8d2c99400_0 .net/s "product_ext", 39 0, L_0x8d3194140; 1 drivers +v0x8d2c994a0_0 .net/s "w", 15 0, L_0x8d318bca0; 1 drivers +v0x8d2c99540_0 .net/s "x", 15 0, L_0x8d318bc00; 1 drivers +L_0x8d2d18320 .extend/s 32, L_0x8d318bc00; +L_0x8d2d183c0 .extend/s 32, L_0x8d318bca0; +L_0x8d2d18460 .arith/mult 32, L_0x8d2d18320, L_0x8d2d183c0; +L_0x8d318bb60 .part L_0x8d2d18460, 31, 1; +L_0x8d2d18500 .repeat 8, 8, L_0x8d318bb60; +L_0x8d3194140 .concat [ 32 8 0 0], L_0x8d2d18460, L_0x8d2d18500; +L_0x8d31941e0 .arith/sum 40, L_0x8d2854208, L_0x8d3194140; +S_0x102e5abd0 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x102e52fe0; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c240 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c280 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c2c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2c995e0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d185a0; 1 drivers +v0x8d2c99680_0 .net/s *"_ivl_2", 31 0, L_0x8d2d18640; 1 drivers +v0x8d2c99720_0 .net *"_ivl_7", 0 0, L_0x8d318bd40; 1 drivers +v0x8d2c997c0_0 .net *"_ivl_9", 7 0, L_0x8d2d18780; 1 drivers +L_0x8d2854250 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2c99860_0 .net/s "acc_in", 39 0, L_0x8d2854250; 1 drivers +v0x8d2c99900_0 .net/s "acc_out", 39 0, L_0x8d3194320; alias, 1 drivers +v0x8d2c999a0_0 .net/s "product", 31 0, L_0x8d2d186e0; 1 drivers +v0x8d2c99a40_0 .net/s "product_ext", 39 0, L_0x8d3194280; 1 drivers +v0x8d2c99ae0_0 .net/s "w", 15 0, L_0x8d318be80; 1 drivers +v0x8d2c99b80_0 .net/s "x", 15 0, L_0x8d318bde0; 1 drivers +L_0x8d2d185a0 .extend/s 32, L_0x8d318bde0; +L_0x8d2d18640 .extend/s 32, L_0x8d318be80; +L_0x8d2d186e0 .arith/mult 32, L_0x8d2d185a0, L_0x8d2d18640; +L_0x8d318bd40 .part L_0x8d2d186e0, 31, 1; +L_0x8d2d18780 .repeat 8, 8, L_0x8d318bd40; +L_0x8d3194280 .concat [ 32 8 0 0], L_0x8d2d186e0, L_0x8d2d18780; +L_0x8d3194320 .arith/sum 40, L_0x8d2854250, L_0x8d3194280; +S_0x102e65950 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x102e52fe0; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c300 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c340 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c380 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2c99c20_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18820; 1 drivers +v0x8d2c99cc0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d188c0; 1 drivers +v0x8d2c99d60_0 .net *"_ivl_7", 0 0, L_0x8d318bf20; 1 drivers +v0x8d2c99e00_0 .net *"_ivl_9", 7 0, L_0x8d2d18a00; 1 drivers +L_0x8d2854298 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2c99ea0_0 .net/s "acc_in", 39 0, L_0x8d2854298; 1 drivers +v0x8d2c99f40_0 .net/s "acc_out", 39 0, L_0x8d3194460; alias, 1 drivers +v0x8d2c99fe0_0 .net/s "product", 31 0, L_0x8d2d18960; 1 drivers +v0x8d2c9a080_0 .net/s "product_ext", 39 0, L_0x8d31943c0; 1 drivers +v0x8d2c9a120_0 .net/s "w", 15 0, L_0x8d3064500; 1 drivers +v0x8d2c9a1c0_0 .net/s "x", 15 0, L_0x8d3064460; 1 drivers +L_0x8d2d18820 .extend/s 32, L_0x8d3064460; +L_0x8d2d188c0 .extend/s 32, L_0x8d3064500; +L_0x8d2d18960 .arith/mult 32, L_0x8d2d18820, L_0x8d2d188c0; +L_0x8d318bf20 .part L_0x8d2d18960, 31, 1; +L_0x8d2d18a00 .repeat 8, 8, L_0x8d318bf20; +L_0x8d31943c0 .concat [ 32 8 0 0], L_0x8d2d18960, L_0x8d2d18a00; +L_0x8d3194460 .arith/sum 40, L_0x8d2854298, L_0x8d31943c0; +S_0x8d31fc000 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x102e52fe0; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c3c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c400 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c440 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2c9a260_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18aa0; 1 drivers +v0x8d2c9a300_0 .net/s *"_ivl_2", 31 0, L_0x8d2d18b40; 1 drivers +v0x8d2c9a3a0_0 .net *"_ivl_7", 0 0, L_0x8d3064640; 1 drivers +v0x8d2c9a440_0 .net *"_ivl_9", 7 0, L_0x8d2d18c80; 1 drivers +L_0x8d28542e0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2c9a4e0_0 .net/s "acc_in", 39 0, L_0x8d28542e0; 1 drivers +v0x8d2c9a580_0 .net/s "acc_out", 39 0, L_0x8d31945a0; alias, 1 drivers +v0x8d2c9a620_0 .net/s "product", 31 0, L_0x8d2d18be0; 1 drivers +v0x8d2c9a6c0_0 .net/s "product_ext", 39 0, L_0x8d3194500; 1 drivers +v0x8d2c9a760_0 .net/s "w", 15 0, L_0x8d316f980; 1 drivers +v0x8d2c9a800_0 .net/s "x", 15 0, L_0x8d317b7a0; 1 drivers +L_0x8d2d18aa0 .extend/s 32, L_0x8d317b7a0; +L_0x8d2d18b40 .extend/s 32, L_0x8d316f980; +L_0x8d2d18be0 .arith/mult 32, L_0x8d2d18aa0, L_0x8d2d18b40; +L_0x8d3064640 .part L_0x8d2d18be0, 31, 1; +L_0x8d2d18c80 .repeat 8, 8, L_0x8d3064640; +L_0x8d3194500 .concat [ 32 8 0 0], L_0x8d2d18be0, L_0x8d2d18c80; +L_0x8d31945a0 .arith/sum 40, L_0x8d28542e0, L_0x8d3194500; +S_0x8d31fc180 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x102e52fe0; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c480 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c4c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c500 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2c9a8a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18d20; 1 drivers +v0x8d2c9a940_0 .net/s *"_ivl_2", 31 0, L_0x8d2d18dc0; 1 drivers +v0x8d2c9a9e0_0 .net *"_ivl_7", 0 0, L_0x8d315fb60; 1 drivers +v0x8d2c9aa80_0 .net *"_ivl_9", 7 0, L_0x8d2d18f00; 1 drivers +L_0x8d2854328 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2c9ab20_0 .net/s "acc_in", 39 0, L_0x8d2854328; 1 drivers +v0x8d2c9abc0_0 .net/s "acc_out", 39 0, L_0x8d31946e0; alias, 1 drivers +v0x8d2c9ac60_0 .net/s "product", 31 0, L_0x8d2d18e60; 1 drivers +v0x8d2c9ad00_0 .net/s "product_ext", 39 0, L_0x8d3194640; 1 drivers +v0x8d2c9ada0_0 .net/s "w", 15 0, L_0x8d3137f20; 1 drivers +v0x8d2c9ae40_0 .net/s "x", 15 0, L_0x8d313fd40; 1 drivers +L_0x8d2d18d20 .extend/s 32, L_0x8d313fd40; +L_0x8d2d18dc0 .extend/s 32, L_0x8d3137f20; +L_0x8d2d18e60 .arith/mult 32, L_0x8d2d18d20, L_0x8d2d18dc0; +L_0x8d315fb60 .part L_0x8d2d18e60, 31, 1; +L_0x8d2d18f00 .repeat 8, 8, L_0x8d315fb60; +L_0x8d3194640 .concat [ 32 8 0 0], L_0x8d2d18e60, L_0x8d2d18f00; +L_0x8d31946e0 .arith/sum 40, L_0x8d2854328, L_0x8d3194640; +S_0x8d31fc300 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x102e52fe0; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c540 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c580 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c5c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2c9aee0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d18fa0; 1 drivers +v0x8d2c9af80_0 .net/s *"_ivl_2", 31 0, L_0x8d2d19040; 1 drivers +v0x8d2c9b020_0 .net *"_ivl_7", 0 0, L_0x8d3134140; 1 drivers +v0x8d2c9b0c0_0 .net *"_ivl_9", 7 0, L_0x8d2d19180; 1 drivers +L_0x8d2854370 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2c9b160_0 .net/s "acc_in", 39 0, L_0x8d2854370; 1 drivers +v0x8d2c9b200_0 .net/s "acc_out", 39 0, L_0x8d3194820; alias, 1 drivers +v0x8d2c9b2a0_0 .net/s "product", 31 0, L_0x8d2d190e0; 1 drivers +v0x8d2c9b340_0 .net/s "product_ext", 39 0, L_0x8d3194780; 1 drivers +v0x8d2c9b3e0_0 .net/s "w", 15 0, L_0x8d321c0a0; 1 drivers +v0x8d2c9b480_0 .net/s "x", 15 0, L_0x8d321c000; 1 drivers +L_0x8d2d18fa0 .extend/s 32, L_0x8d321c000; +L_0x8d2d19040 .extend/s 32, L_0x8d321c0a0; +L_0x8d2d190e0 .arith/mult 32, L_0x8d2d18fa0, L_0x8d2d19040; +L_0x8d3134140 .part L_0x8d2d190e0, 31, 1; +L_0x8d2d19180 .repeat 8, 8, L_0x8d3134140; +L_0x8d3194780 .concat [ 32 8 0 0], L_0x8d2d190e0, L_0x8d2d19180; +L_0x8d3194820 .arith/sum 40, L_0x8d2854370, L_0x8d3194780; +S_0x8d31fc480 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x102e52fe0; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c600 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c640 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c680 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2c9b520_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19220; 1 drivers +v0x8d2c9b5c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d192c0; 1 drivers +v0x8d2c9b660_0 .net *"_ivl_7", 0 0, L_0x8d321c140; 1 drivers +v0x8d2c9b700_0 .net *"_ivl_9", 7 0, L_0x8d2d19400; 1 drivers +L_0x8d28543b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2c9b7a0_0 .net/s "acc_in", 39 0, L_0x8d28543b8; 1 drivers +v0x8d2c9b840_0 .net/s "acc_out", 39 0, L_0x8d3194960; alias, 1 drivers +v0x8d2c9b8e0_0 .net/s "product", 31 0, L_0x8d2d19360; 1 drivers +v0x8d2c9b980_0 .net/s "product_ext", 39 0, L_0x8d31948c0; 1 drivers +v0x8d2c9ba20_0 .net/s "w", 15 0, L_0x8d321c280; 1 drivers +v0x8d2c9bac0_0 .net/s "x", 15 0, L_0x8d321c1e0; 1 drivers +L_0x8d2d19220 .extend/s 32, L_0x8d321c1e0; +L_0x8d2d192c0 .extend/s 32, L_0x8d321c280; +L_0x8d2d19360 .arith/mult 32, L_0x8d2d19220, L_0x8d2d192c0; +L_0x8d321c140 .part L_0x8d2d19360, 31, 1; +L_0x8d2d19400 .repeat 8, 8, L_0x8d321c140; +L_0x8d31948c0 .concat [ 32 8 0 0], L_0x8d2d19360, L_0x8d2d19400; +L_0x8d3194960 .arith/sum 40, L_0x8d28543b8, L_0x8d31948c0; +S_0x8d31fc600 .scope generate, "GEN_NEURON[1]" "GEN_NEURON[1]" 4 35, 4 35 0, S_0x102e5b4b0; + .timescale 0 0; +P_0x8d2c3b100 .param/l "n" 1 4 35, +C4<01>; +S_0x8d31fc780 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d31fc600; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e662f0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x102e66330 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x102e66370 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x102e663b0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; +P_0x102e663f0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; +P_0x102e66430 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; +P_0x102e66470 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x8d307c1c0 .functor BUFZ 16, L_0x8d321d900, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8d2cf1c20_0 .net *"_ivl_0", 31 0, L_0x8d31950e0; 1 drivers +v0x8d2cf1cc0_0 .net *"_ivl_11", 31 0, L_0x8d2d19680; 1 drivers +v0x8d2cf1d60_0 .net *"_ivl_14", 31 0, L_0x8d3195180; 1 drivers +L_0x8d2854520 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf1e00_0 .net *"_ivl_17", 28 0, L_0x8d2854520; 1 drivers +L_0x8d2854568 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf1ea0_0 .net/2u *"_ivl_18", 31 0, L_0x8d2854568; 1 drivers +v0x8d2cf1f40_0 .net *"_ivl_21", 31 0, L_0x8d2d19720; 1 drivers +L_0x8d28545b0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf1fe0_0 .net/2u *"_ivl_22", 31 0, L_0x8d28545b0; 1 drivers +v0x8d2cf2080_0 .net *"_ivl_25", 31 0, L_0x8d2d197c0; 1 drivers +L_0x8d2854448 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf2120_0 .net *"_ivl_3", 28 0, L_0x8d2854448; 1 drivers +v0x8d2cf21c0_0 .net *"_ivl_31", 0 0, L_0x8d321d680; 1 drivers +v0x8d2cf2260_0 .net *"_ivl_33", 23 0, L_0x8d2d1ac60; 1 drivers +v0x8d2cf2300_0 .net *"_ivl_36", 39 0, L_0x8d31961c0; 1 drivers +v0x8d2cf23a0_0 .net *"_ivl_38", 31 0, L_0x8d321d720; 1 drivers +L_0x8d2854490 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf2440_0 .net/2u *"_ivl_4", 31 0, L_0x8d2854490; 1 drivers +L_0x8d2854838 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf24e0_0 .net *"_ivl_40", 7 0, L_0x8d2854838; 1 drivers +v0x8d2cf2580_0 .net *"_ivl_46", 31 0, L_0x8d321d7c0; 1 drivers +v0x8d2cf2620_0 .net *"_ivl_7", 31 0, L_0x8d2d195e0; 1 drivers +L_0x8d28544d8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf26c0_0 .net/2u *"_ivl_8", 31 0, L_0x8d28544d8; 1 drivers +v0x8d2cf2760_0 .var/s "acc", 39 0; +v0x8d2cf2800_0 .net/s "acc_next", 39 0, L_0x8d3196080; 1 drivers +v0x8d2cf28a0_0 .net/s "bias", 15 0, L_0x8d321d900; 1 drivers +v0x8d2cf2940_0 .net/s "bias_ext", 39 0, L_0x8d3196120; 1 drivers +v0x8d2cf29e0_0 .net/s "bias_ext_small", 15 0, L_0x8d307c1c0; 1 drivers +v0x8d2cf2a80_0 .var "busy", 0 0; +v0x8d2cf2b20_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers +v0x8d2cf2bc0_0 .var "done", 0 0; +v0x8d2cf2c60_0 .net/s "final_acc", 39 0, L_0x8d3196260; 1 drivers +v0x8d2cf2d00_0 .net/s "final_value", 39 0, L_0x8d2d1ad00; 1 drivers +v0x8d2cf2da0_0 .var "group_index", 2 0; +v0x8d2cf2e40_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers +v0x8d2cf2ee0_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers +v0x8d2cf2f80_0 .net/s "w_bus", 1023 0, L_0x8d321d860; 1 drivers +v0x8d2cf3020_0 .net/s "w_group", 127 0, L_0x8d321c6e0; 1 drivers +v0x8d2cf30c0_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers +v0x8d2cf3160_0 .net/s "x_group", 127 0, L_0x8d321c640; 1 drivers +v0x8d2cf3200_0 .var/s "y", 15 0; +L_0x8d31950e0 .concat [ 3 29 0 0], v0x8d2cf2da0_0, L_0x8d2854448; +L_0x8d2d195e0 .arith/mult 32, L_0x8d31950e0, L_0x8d2854490; +L_0x8d2d19680 .arith/mult 32, L_0x8d2d195e0, L_0x8d28544d8; +L_0x8d321c640 .part/v v0x8d2d17ca0_0, L_0x8d2d19680, 128; +L_0x8d3195180 .concat [ 3 29 0 0], v0x8d2cf2da0_0, L_0x8d2854520; +L_0x8d2d19720 .arith/mult 32, L_0x8d3195180, L_0x8d2854568; +L_0x8d2d197c0 .arith/mult 32, L_0x8d2d19720, L_0x8d28545b0; +L_0x8d321c6e0 .part/v L_0x8d321d860, L_0x8d2d197c0, 128; +L_0x8d321d680 .part L_0x8d307c1c0, 15, 1; +L_0x8d2d1ac60 .repeat 24, 24, L_0x8d321d680; +L_0x8d3196120 .concat [ 16 24 0 0], L_0x8d307c1c0, L_0x8d2d1ac60; +L_0x8d321d720 .part L_0x8d3196120, 0, 32; +L_0x8d31961c0 .concat [ 8 32 0 0], L_0x8d2854838, L_0x8d321d720; +L_0x8d3196260 .arith/sum 40, L_0x8d3196080, L_0x8d31961c0; +L_0x8d321d7c0 .part L_0x8d3196260, 8, 32; +L_0x8d2d1ad00 .extend/s 40, L_0x8d321d7c0; +S_0x8d31fc900 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d31fc780; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d30a0680 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8d30a06c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8d2cf1040_0 .net/s "acc_in", 39 0, v0x8d2cf2760_0; 1 drivers +v0x8d2cf10e0_0 .net/s "acc_out", 39 0, L_0x8d3196080; alias, 1 drivers +v0x8d2cf1180_0 .net/s "m0", 39 0, L_0x8d31952c0; 1 drivers +v0x8d2cf1220_0 .net/s "m1", 39 0, L_0x8d3195400; 1 drivers +v0x8d2cf12c0_0 .net/s "m2", 39 0, L_0x8d3195540; 1 drivers +v0x8d2cf1360_0 .net/s "m3", 39 0, L_0x8d3195680; 1 drivers +v0x8d2cf1400_0 .net/s "m4", 39 0, L_0x8d31957c0; 1 drivers +v0x8d2cf14a0_0 .net/s "m5", 39 0, L_0x8d3195900; 1 drivers +v0x8d2cf1540_0 .net/s "m6", 39 0, L_0x8d3195a40; 1 drivers +v0x8d2cf15e0_0 .net/s "m7", 39 0, L_0x8d3195b80; 1 drivers +v0x8d2cf1680_0 .net/s "s0", 39 0, L_0x8d3195c20; 1 drivers +v0x8d2cf1720_0 .net/s "s1", 39 0, L_0x8d3195cc0; 1 drivers +v0x8d2cf17c0_0 .net/s "s2", 39 0, L_0x8d3195d60; 1 drivers +v0x8d2cf1860_0 .net/s "s3", 39 0, L_0x8d3195e00; 1 drivers +v0x8d2cf1900_0 .net/s "s4", 39 0, L_0x8d3195ea0; 1 drivers +v0x8d2cf19a0_0 .net/s "s5", 39 0, L_0x8d3195f40; 1 drivers +v0x8d2cf1a40_0 .net/s "sum", 39 0, L_0x8d3195fe0; 1 drivers +v0x8d2cf1ae0_0 .net/s "w_bus", 127 0, L_0x8d321c6e0; alias, 1 drivers +v0x8d2cf1b80_0 .net/s "x_bus", 127 0, L_0x8d321c640; alias, 1 drivers +L_0x8d321c820 .part L_0x8d321c640, 0, 16; +L_0x8d321c8c0 .part L_0x8d321c6e0, 0, 16; +L_0x8d321ca00 .part L_0x8d321c640, 16, 16; +L_0x8d321caa0 .part L_0x8d321c6e0, 16, 16; +L_0x8d321cbe0 .part L_0x8d321c640, 32, 16; +L_0x8d321cc80 .part L_0x8d321c6e0, 32, 16; +L_0x8d321cdc0 .part L_0x8d321c640, 48, 16; +L_0x8d321ce60 .part L_0x8d321c6e0, 48, 16; +L_0x8d321cfa0 .part L_0x8d321c640, 64, 16; +L_0x8d321d040 .part L_0x8d321c6e0, 64, 16; +L_0x8d321d180 .part L_0x8d321c640, 80, 16; +L_0x8d321d220 .part L_0x8d321c6e0, 80, 16; +L_0x8d321d360 .part L_0x8d321c640, 96, 16; +L_0x8d321d400 .part L_0x8d321c6e0, 96, 16; +L_0x8d321d540 .part L_0x8d321c640, 112, 16; +L_0x8d321d5e0 .part L_0x8d321c6e0, 112, 16; +L_0x8d3195c20 .arith/sum 40, L_0x8d31952c0, L_0x8d3195400; +L_0x8d3195cc0 .arith/sum 40, L_0x8d3195540, L_0x8d3195680; +L_0x8d3195d60 .arith/sum 40, L_0x8d31957c0, L_0x8d3195900; +L_0x8d3195e00 .arith/sum 40, L_0x8d3195a40, L_0x8d3195b80; +L_0x8d3195ea0 .arith/sum 40, L_0x8d3195c20, L_0x8d3195cc0; +L_0x8d3195f40 .arith/sum 40, L_0x8d3195d60, L_0x8d3195e00; +L_0x8d3195fe0 .arith/sum 40, L_0x8d3195ea0, L_0x8d3195f40; +L_0x8d3196080 .arith/sum 40, v0x8d2cf2760_0, L_0x8d3195fe0; +S_0x8d31fca80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d31fc900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c6c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c700 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c740 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cede00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19860; 1 drivers +v0x8d2cedea0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d19900; 1 drivers +v0x8d2cedf40_0 .net *"_ivl_7", 0 0, L_0x8d321c780; 1 drivers +v0x8d2cedfe0_0 .net *"_ivl_9", 7 0, L_0x8d2d19a40; 1 drivers +L_0x8d28545f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cee080_0 .net/s "acc_in", 39 0, L_0x8d28545f8; 1 drivers +v0x8d2cee120_0 .net/s "acc_out", 39 0, L_0x8d31952c0; alias, 1 drivers +v0x8d2cee1c0_0 .net/s "product", 31 0, L_0x8d2d199a0; 1 drivers +v0x8d2cee260_0 .net/s "product_ext", 39 0, L_0x8d3195220; 1 drivers +v0x8d2cee300_0 .net/s "w", 15 0, L_0x8d321c8c0; 1 drivers +v0x8d2cee3a0_0 .net/s "x", 15 0, L_0x8d321c820; 1 drivers +L_0x8d2d19860 .extend/s 32, L_0x8d321c820; +L_0x8d2d19900 .extend/s 32, L_0x8d321c8c0; +L_0x8d2d199a0 .arith/mult 32, L_0x8d2d19860, L_0x8d2d19900; +L_0x8d321c780 .part L_0x8d2d199a0, 31, 1; +L_0x8d2d19a40 .repeat 8, 8, L_0x8d321c780; +L_0x8d3195220 .concat [ 32 8 0 0], L_0x8d2d199a0, L_0x8d2d19a40; +L_0x8d31952c0 .arith/sum 40, L_0x8d28545f8, L_0x8d3195220; +S_0x8d31fcc00 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d31fc900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c780 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c7c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c800 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cee440_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19ae0; 1 drivers +v0x8d2cee4e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d19b80; 1 drivers +v0x8d2cee580_0 .net *"_ivl_7", 0 0, L_0x8d321c960; 1 drivers +v0x8d2cee620_0 .net *"_ivl_9", 7 0, L_0x8d2d19cc0; 1 drivers +L_0x8d2854640 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cee6c0_0 .net/s "acc_in", 39 0, L_0x8d2854640; 1 drivers +v0x8d2cee760_0 .net/s "acc_out", 39 0, L_0x8d3195400; alias, 1 drivers +v0x8d2cee800_0 .net/s "product", 31 0, L_0x8d2d19c20; 1 drivers +v0x8d2cee8a0_0 .net/s "product_ext", 39 0, L_0x8d3195360; 1 drivers +v0x8d2cee940_0 .net/s "w", 15 0, L_0x8d321caa0; 1 drivers +v0x8d2cee9e0_0 .net/s "x", 15 0, L_0x8d321ca00; 1 drivers +L_0x8d2d19ae0 .extend/s 32, L_0x8d321ca00; +L_0x8d2d19b80 .extend/s 32, L_0x8d321caa0; +L_0x8d2d19c20 .arith/mult 32, L_0x8d2d19ae0, L_0x8d2d19b80; +L_0x8d321c960 .part L_0x8d2d19c20, 31, 1; +L_0x8d2d19cc0 .repeat 8, 8, L_0x8d321c960; +L_0x8d3195360 .concat [ 32 8 0 0], L_0x8d2d19c20, L_0x8d2d19cc0; +L_0x8d3195400 .arith/sum 40, L_0x8d2854640, L_0x8d3195360; +S_0x8d31fcd80 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d31fc900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c840 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c880 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c8c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2ceea80_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19d60; 1 drivers +v0x8d2ceeb20_0 .net/s *"_ivl_2", 31 0, L_0x8d2d19e00; 1 drivers +v0x8d2ceebc0_0 .net *"_ivl_7", 0 0, L_0x8d321cb40; 1 drivers +v0x8d2ceec60_0 .net *"_ivl_9", 7 0, L_0x8d2d19f40; 1 drivers +L_0x8d2854688 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2ceed00_0 .net/s "acc_in", 39 0, L_0x8d2854688; 1 drivers +v0x8d2ceeda0_0 .net/s "acc_out", 39 0, L_0x8d3195540; alias, 1 drivers +v0x8d2ceee40_0 .net/s "product", 31 0, L_0x8d2d19ea0; 1 drivers +v0x8d2ceeee0_0 .net/s "product_ext", 39 0, L_0x8d31954a0; 1 drivers +v0x8d2ceef80_0 .net/s "w", 15 0, L_0x8d321cc80; 1 drivers +v0x8d2cef020_0 .net/s "x", 15 0, L_0x8d321cbe0; 1 drivers +L_0x8d2d19d60 .extend/s 32, L_0x8d321cbe0; +L_0x8d2d19e00 .extend/s 32, L_0x8d321cc80; +L_0x8d2d19ea0 .arith/mult 32, L_0x8d2d19d60, L_0x8d2d19e00; +L_0x8d321cb40 .part L_0x8d2d19ea0, 31, 1; +L_0x8d2d19f40 .repeat 8, 8, L_0x8d321cb40; +L_0x8d31954a0 .concat [ 32 8 0 0], L_0x8d2d19ea0, L_0x8d2d19f40; +L_0x8d3195540 .arith/sum 40, L_0x8d2854688, L_0x8d31954a0; +S_0x8d31fcf00 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d31fc900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c900 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306c940 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306c980 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cef0c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d19fe0; 1 drivers +v0x8d2cef160_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1a080; 1 drivers +v0x8d2cef200_0 .net *"_ivl_7", 0 0, L_0x8d321cd20; 1 drivers +v0x8d2cef2a0_0 .net *"_ivl_9", 7 0, L_0x8d2d1a1c0; 1 drivers +L_0x8d28546d0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cef340_0 .net/s "acc_in", 39 0, L_0x8d28546d0; 1 drivers +v0x8d2cef3e0_0 .net/s "acc_out", 39 0, L_0x8d3195680; alias, 1 drivers +v0x8d2cef480_0 .net/s "product", 31 0, L_0x8d2d1a120; 1 drivers +v0x8d2cef520_0 .net/s "product_ext", 39 0, L_0x8d31955e0; 1 drivers +v0x8d2cef5c0_0 .net/s "w", 15 0, L_0x8d321ce60; 1 drivers +v0x8d2cef660_0 .net/s "x", 15 0, L_0x8d321cdc0; 1 drivers +L_0x8d2d19fe0 .extend/s 32, L_0x8d321cdc0; +L_0x8d2d1a080 .extend/s 32, L_0x8d321ce60; +L_0x8d2d1a120 .arith/mult 32, L_0x8d2d19fe0, L_0x8d2d1a080; +L_0x8d321cd20 .part L_0x8d2d1a120, 31, 1; +L_0x8d2d1a1c0 .repeat 8, 8, L_0x8d321cd20; +L_0x8d31955e0 .concat [ 32 8 0 0], L_0x8d2d1a120, L_0x8d2d1a1c0; +L_0x8d3195680 .arith/sum 40, L_0x8d28546d0, L_0x8d31955e0; +S_0x8d31fd080 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d31fc900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306c9c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306ca00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ca40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cef700_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1a260; 1 drivers +v0x8d2cef7a0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1a300; 1 drivers +v0x8d2cef840_0 .net *"_ivl_7", 0 0, L_0x8d321cf00; 1 drivers +v0x8d2cef8e0_0 .net *"_ivl_9", 7 0, L_0x8d2d1a440; 1 drivers +L_0x8d2854718 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cef980_0 .net/s "acc_in", 39 0, L_0x8d2854718; 1 drivers +v0x8d2cefa20_0 .net/s "acc_out", 39 0, L_0x8d31957c0; alias, 1 drivers +v0x8d2cefac0_0 .net/s "product", 31 0, L_0x8d2d1a3a0; 1 drivers +v0x8d2cefb60_0 .net/s "product_ext", 39 0, L_0x8d3195720; 1 drivers +v0x8d2cefc00_0 .net/s "w", 15 0, L_0x8d321d040; 1 drivers +v0x8d2cefca0_0 .net/s "x", 15 0, L_0x8d321cfa0; 1 drivers +L_0x8d2d1a260 .extend/s 32, L_0x8d321cfa0; +L_0x8d2d1a300 .extend/s 32, L_0x8d321d040; +L_0x8d2d1a3a0 .arith/mult 32, L_0x8d2d1a260, L_0x8d2d1a300; +L_0x8d321cf00 .part L_0x8d2d1a3a0, 31, 1; +L_0x8d2d1a440 .repeat 8, 8, L_0x8d321cf00; +L_0x8d3195720 .concat [ 32 8 0 0], L_0x8d2d1a3a0, L_0x8d2d1a440; +L_0x8d31957c0 .arith/sum 40, L_0x8d2854718, L_0x8d3195720; +S_0x8d31fd200 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d31fc900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306ca80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306cac0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306cb00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cefd40_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1a4e0; 1 drivers +v0x8d2cefde0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1a580; 1 drivers +v0x8d2cefe80_0 .net *"_ivl_7", 0 0, L_0x8d321d0e0; 1 drivers +v0x8d2ceff20_0 .net *"_ivl_9", 7 0, L_0x8d2d1a6c0; 1 drivers +L_0x8d2854760 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf0000_0 .net/s "acc_in", 39 0, L_0x8d2854760; 1 drivers +v0x8d2cf00a0_0 .net/s "acc_out", 39 0, L_0x8d3195900; alias, 1 drivers +v0x8d2cf0140_0 .net/s "product", 31 0, L_0x8d2d1a620; 1 drivers +v0x8d2cf01e0_0 .net/s "product_ext", 39 0, L_0x8d3195860; 1 drivers +v0x8d2cf0280_0 .net/s "w", 15 0, L_0x8d321d220; 1 drivers +v0x8d2cf0320_0 .net/s "x", 15 0, L_0x8d321d180; 1 drivers +L_0x8d2d1a4e0 .extend/s 32, L_0x8d321d180; +L_0x8d2d1a580 .extend/s 32, L_0x8d321d220; +L_0x8d2d1a620 .arith/mult 32, L_0x8d2d1a4e0, L_0x8d2d1a580; +L_0x8d321d0e0 .part L_0x8d2d1a620, 31, 1; +L_0x8d2d1a6c0 .repeat 8, 8, L_0x8d321d0e0; +L_0x8d3195860 .concat [ 32 8 0 0], L_0x8d2d1a620, L_0x8d2d1a6c0; +L_0x8d3195900 .arith/sum 40, L_0x8d2854760, L_0x8d3195860; +S_0x8d31fd380 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d31fc900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306cb40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306cb80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306cbc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf03c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1a760; 1 drivers +v0x8d2cf0460_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1a800; 1 drivers +v0x8d2cf0500_0 .net *"_ivl_7", 0 0, L_0x8d321d2c0; 1 drivers +v0x8d2cf05a0_0 .net *"_ivl_9", 7 0, L_0x8d2d1a940; 1 drivers +L_0x8d28547a8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf0640_0 .net/s "acc_in", 39 0, L_0x8d28547a8; 1 drivers +v0x8d2cf06e0_0 .net/s "acc_out", 39 0, L_0x8d3195a40; alias, 1 drivers +v0x8d2cf0780_0 .net/s "product", 31 0, L_0x8d2d1a8a0; 1 drivers +v0x8d2cf0820_0 .net/s "product_ext", 39 0, L_0x8d31959a0; 1 drivers +v0x8d2cf08c0_0 .net/s "w", 15 0, L_0x8d321d400; 1 drivers +v0x8d2cf0960_0 .net/s "x", 15 0, L_0x8d321d360; 1 drivers +L_0x8d2d1a760 .extend/s 32, L_0x8d321d360; +L_0x8d2d1a800 .extend/s 32, L_0x8d321d400; +L_0x8d2d1a8a0 .arith/mult 32, L_0x8d2d1a760, L_0x8d2d1a800; +L_0x8d321d2c0 .part L_0x8d2d1a8a0, 31, 1; +L_0x8d2d1a940 .repeat 8, 8, L_0x8d321d2c0; +L_0x8d31959a0 .concat [ 32 8 0 0], L_0x8d2d1a8a0, L_0x8d2d1a940; +L_0x8d3195a40 .arith/sum 40, L_0x8d28547a8, L_0x8d31959a0; +S_0x8d31fd500 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d31fc900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306cc00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306cc40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306cc80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf0a00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1a9e0; 1 drivers +v0x8d2cf0aa0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1aa80; 1 drivers +v0x8d2cf0b40_0 .net *"_ivl_7", 0 0, L_0x8d321d4a0; 1 drivers +v0x8d2cf0be0_0 .net *"_ivl_9", 7 0, L_0x8d2d1abc0; 1 drivers +L_0x8d28547f0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf0c80_0 .net/s "acc_in", 39 0, L_0x8d28547f0; 1 drivers +v0x8d2cf0d20_0 .net/s "acc_out", 39 0, L_0x8d3195b80; alias, 1 drivers +v0x8d2cf0dc0_0 .net/s "product", 31 0, L_0x8d2d1ab20; 1 drivers +v0x8d2cf0e60_0 .net/s "product_ext", 39 0, L_0x8d3195ae0; 1 drivers +v0x8d2cf0f00_0 .net/s "w", 15 0, L_0x8d321d5e0; 1 drivers +v0x8d2cf0fa0_0 .net/s "x", 15 0, L_0x8d321d540; 1 drivers +L_0x8d2d1a9e0 .extend/s 32, L_0x8d321d540; +L_0x8d2d1aa80 .extend/s 32, L_0x8d321d5e0; +L_0x8d2d1ab20 .arith/mult 32, L_0x8d2d1a9e0, L_0x8d2d1aa80; +L_0x8d321d4a0 .part L_0x8d2d1ab20, 31, 1; +L_0x8d2d1abc0 .repeat 8, 8, L_0x8d321d4a0; +L_0x8d3195ae0 .concat [ 32 8 0 0], L_0x8d2d1ab20, L_0x8d2d1abc0; +L_0x8d3195b80 .arith/sum 40, L_0x8d28547f0, L_0x8d3195ae0; +S_0x8d31fd680 .scope generate, "GEN_NEURON[2]" "GEN_NEURON[2]" 4 35, 4 35 0, S_0x102e5b4b0; + .timescale 0 0; +P_0x8d2c3b140 .param/l "n" 1 4 35, +C4<010>; +S_0x8d31fd800 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d31fd680; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e666b0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x102e666f0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x102e66730 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x102e66770 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; +P_0x102e667b0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; +P_0x102e667f0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; +P_0x102e66830 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x8d307c230 .functor BUFZ 16, L_0x8d321ec60, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8d2cf70c0_0 .net *"_ivl_0", 31 0, L_0x8d3196300; 1 drivers +v0x8d2cf7160_0 .net *"_ivl_11", 31 0, L_0x8d2d1ae40; 1 drivers +v0x8d2cf7200_0 .net *"_ivl_14", 31 0, L_0x8d31963a0; 1 drivers +L_0x8d2854958 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf72a0_0 .net *"_ivl_17", 28 0, L_0x8d2854958; 1 drivers +L_0x8d28549a0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf7340_0 .net/2u *"_ivl_18", 31 0, L_0x8d28549a0; 1 drivers +v0x8d2cf73e0_0 .net *"_ivl_21", 31 0, L_0x8d2d1aee0; 1 drivers +L_0x8d28549e8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf7480_0 .net/2u *"_ivl_22", 31 0, L_0x8d28549e8; 1 drivers +v0x8d2cf7520_0 .net *"_ivl_25", 31 0, L_0x8d2d1af80; 1 drivers +L_0x8d2854880 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf75c0_0 .net *"_ivl_3", 28 0, L_0x8d2854880; 1 drivers +v0x8d2cf7660_0 .net *"_ivl_31", 0 0, L_0x8d321e9e0; 1 drivers +v0x8d2cf7700_0 .net *"_ivl_33", 23 0, L_0x8d2d1c460; 1 drivers +v0x8d2cf77a0_0 .net *"_ivl_36", 39 0, L_0x8d31973e0; 1 drivers +v0x8d2cf7840_0 .net *"_ivl_38", 31 0, L_0x8d321ea80; 1 drivers +L_0x8d28548c8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf78e0_0 .net/2u *"_ivl_4", 31 0, L_0x8d28548c8; 1 drivers +L_0x8d2854c70 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf7980_0 .net *"_ivl_40", 7 0, L_0x8d2854c70; 1 drivers +v0x8d2cf7a20_0 .net *"_ivl_46", 31 0, L_0x8d321eb20; 1 drivers +v0x8d2cf7ac0_0 .net *"_ivl_7", 31 0, L_0x8d2d1ada0; 1 drivers +L_0x8d2854910 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf7b60_0 .net/2u *"_ivl_8", 31 0, L_0x8d2854910; 1 drivers +v0x8d2cf7c00_0 .var/s "acc", 39 0; +v0x8d2cf7ca0_0 .net/s "acc_next", 39 0, L_0x8d31972a0; 1 drivers +v0x8d2cf7d40_0 .net/s "bias", 15 0, L_0x8d321ec60; 1 drivers +v0x8d2cf7de0_0 .net/s "bias_ext", 39 0, L_0x8d3197340; 1 drivers +v0x8d2cf7e80_0 .net/s "bias_ext_small", 15 0, L_0x8d307c230; 1 drivers +v0x8d2cf7f20_0 .var "busy", 0 0; +v0x8d2cfc000_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers +v0x8d2cfc0a0_0 .var "done", 0 0; +v0x8d2cfc140_0 .net/s "final_acc", 39 0, L_0x8d3197480; 1 drivers +v0x8d2cfc1e0_0 .net/s "final_value", 39 0, L_0x8d2d1c500; 1 drivers +v0x8d2cfc280_0 .var "group_index", 2 0; +v0x8d2cfc320_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers +v0x8d2cfc3c0_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers +v0x8d2cfc460_0 .net/s "w_bus", 1023 0, L_0x8d321ebc0; 1 drivers +v0x8d2cfc500_0 .net/s "w_group", 127 0, L_0x8d321da40; 1 drivers +v0x8d2cfc5a0_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers +v0x8d2cfc640_0 .net/s "x_group", 127 0, L_0x8d321d9a0; 1 drivers +v0x8d2cfc6e0_0 .var/s "y", 15 0; +L_0x8d3196300 .concat [ 3 29 0 0], v0x8d2cfc280_0, L_0x8d2854880; +L_0x8d2d1ada0 .arith/mult 32, L_0x8d3196300, L_0x8d28548c8; +L_0x8d2d1ae40 .arith/mult 32, L_0x8d2d1ada0, L_0x8d2854910; +L_0x8d321d9a0 .part/v v0x8d2d17ca0_0, L_0x8d2d1ae40, 128; +L_0x8d31963a0 .concat [ 3 29 0 0], v0x8d2cfc280_0, L_0x8d2854958; +L_0x8d2d1aee0 .arith/mult 32, L_0x8d31963a0, L_0x8d28549a0; +L_0x8d2d1af80 .arith/mult 32, L_0x8d2d1aee0, L_0x8d28549e8; +L_0x8d321da40 .part/v L_0x8d321ebc0, L_0x8d2d1af80, 128; +L_0x8d321e9e0 .part L_0x8d307c230, 15, 1; +L_0x8d2d1c460 .repeat 24, 24, L_0x8d321e9e0; +L_0x8d3197340 .concat [ 16 24 0 0], L_0x8d307c230, L_0x8d2d1c460; +L_0x8d321ea80 .part L_0x8d3197340, 0, 32; +L_0x8d31973e0 .concat [ 8 32 0 0], L_0x8d2854c70, L_0x8d321ea80; +L_0x8d3197480 .arith/sum 40, L_0x8d31972a0, L_0x8d31973e0; +L_0x8d321eb20 .part L_0x8d3197480, 8, 32; +L_0x8d2d1c500 .extend/s 40, L_0x8d321eb20; +S_0x8d31fd980 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d31fd800; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d30a0700 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8d30a0740 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8d2cf64e0_0 .net/s "acc_in", 39 0, v0x8d2cf7c00_0; 1 drivers +v0x8d2cf6580_0 .net/s "acc_out", 39 0, L_0x8d31972a0; alias, 1 drivers +v0x8d2cf6620_0 .net/s "m0", 39 0, L_0x8d31964e0; 1 drivers +v0x8d2cf66c0_0 .net/s "m1", 39 0, L_0x8d3196620; 1 drivers +v0x8d2cf6760_0 .net/s "m2", 39 0, L_0x8d3196760; 1 drivers +v0x8d2cf6800_0 .net/s "m3", 39 0, L_0x8d31968a0; 1 drivers +v0x8d2cf68a0_0 .net/s "m4", 39 0, L_0x8d31969e0; 1 drivers +v0x8d2cf6940_0 .net/s "m5", 39 0, L_0x8d3196b20; 1 drivers +v0x8d2cf69e0_0 .net/s "m6", 39 0, L_0x8d3196c60; 1 drivers +v0x8d2cf6a80_0 .net/s "m7", 39 0, L_0x8d3196da0; 1 drivers +v0x8d2cf6b20_0 .net/s "s0", 39 0, L_0x8d3196e40; 1 drivers +v0x8d2cf6bc0_0 .net/s "s1", 39 0, L_0x8d3196ee0; 1 drivers +v0x8d2cf6c60_0 .net/s "s2", 39 0, L_0x8d3196f80; 1 drivers +v0x8d2cf6d00_0 .net/s "s3", 39 0, L_0x8d3197020; 1 drivers +v0x8d2cf6da0_0 .net/s "s4", 39 0, L_0x8d31970c0; 1 drivers +v0x8d2cf6e40_0 .net/s "s5", 39 0, L_0x8d3197160; 1 drivers +v0x8d2cf6ee0_0 .net/s "sum", 39 0, L_0x8d3197200; 1 drivers +v0x8d2cf6f80_0 .net/s "w_bus", 127 0, L_0x8d321da40; alias, 1 drivers +v0x8d2cf7020_0 .net/s "x_bus", 127 0, L_0x8d321d9a0; alias, 1 drivers +L_0x8d321db80 .part L_0x8d321d9a0, 0, 16; +L_0x8d321dc20 .part L_0x8d321da40, 0, 16; +L_0x8d321dd60 .part L_0x8d321d9a0, 16, 16; +L_0x8d321de00 .part L_0x8d321da40, 16, 16; +L_0x8d321df40 .part L_0x8d321d9a0, 32, 16; +L_0x8d321dfe0 .part L_0x8d321da40, 32, 16; +L_0x8d321e120 .part L_0x8d321d9a0, 48, 16; +L_0x8d321e1c0 .part L_0x8d321da40, 48, 16; +L_0x8d321e300 .part L_0x8d321d9a0, 64, 16; +L_0x8d321e3a0 .part L_0x8d321da40, 64, 16; +L_0x8d321e4e0 .part L_0x8d321d9a0, 80, 16; +L_0x8d321e580 .part L_0x8d321da40, 80, 16; +L_0x8d321e6c0 .part L_0x8d321d9a0, 96, 16; +L_0x8d321e760 .part L_0x8d321da40, 96, 16; +L_0x8d321e8a0 .part L_0x8d321d9a0, 112, 16; +L_0x8d321e940 .part L_0x8d321da40, 112, 16; +L_0x8d3196e40 .arith/sum 40, L_0x8d31964e0, L_0x8d3196620; +L_0x8d3196ee0 .arith/sum 40, L_0x8d3196760, L_0x8d31968a0; +L_0x8d3196f80 .arith/sum 40, L_0x8d31969e0, L_0x8d3196b20; +L_0x8d3197020 .arith/sum 40, L_0x8d3196c60, L_0x8d3196da0; +L_0x8d31970c0 .arith/sum 40, L_0x8d3196e40, L_0x8d3196ee0; +L_0x8d3197160 .arith/sum 40, L_0x8d3196f80, L_0x8d3197020; +L_0x8d3197200 .arith/sum 40, L_0x8d31970c0, L_0x8d3197160; +L_0x8d31972a0 .arith/sum 40, v0x8d2cf7c00_0, L_0x8d3197200; +S_0x8d31fdb00 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d31fd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306ccc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306cd00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306cd40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf32a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1b020; 1 drivers +v0x8d2cf3340_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1b0c0; 1 drivers +v0x8d2cf33e0_0 .net *"_ivl_7", 0 0, L_0x8d321dae0; 1 drivers +v0x8d2cf3480_0 .net *"_ivl_9", 7 0, L_0x8d2d1b200; 1 drivers +L_0x8d2854a30 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf3520_0 .net/s "acc_in", 39 0, L_0x8d2854a30; 1 drivers +v0x8d2cf35c0_0 .net/s "acc_out", 39 0, L_0x8d31964e0; alias, 1 drivers +v0x8d2cf3660_0 .net/s "product", 31 0, L_0x8d2d1b160; 1 drivers +v0x8d2cf3700_0 .net/s "product_ext", 39 0, L_0x8d3196440; 1 drivers +v0x8d2cf37a0_0 .net/s "w", 15 0, L_0x8d321dc20; 1 drivers +v0x8d2cf3840_0 .net/s "x", 15 0, L_0x8d321db80; 1 drivers +L_0x8d2d1b020 .extend/s 32, L_0x8d321db80; +L_0x8d2d1b0c0 .extend/s 32, L_0x8d321dc20; +L_0x8d2d1b160 .arith/mult 32, L_0x8d2d1b020, L_0x8d2d1b0c0; +L_0x8d321dae0 .part L_0x8d2d1b160, 31, 1; +L_0x8d2d1b200 .repeat 8, 8, L_0x8d321dae0; +L_0x8d3196440 .concat [ 32 8 0 0], L_0x8d2d1b160, L_0x8d2d1b200; +L_0x8d31964e0 .arith/sum 40, L_0x8d2854a30, L_0x8d3196440; +S_0x8d31fdc80 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d31fd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306cd80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306cdc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ce00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf38e0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1b2a0; 1 drivers +v0x8d2cf3980_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1b340; 1 drivers +v0x8d2cf3a20_0 .net *"_ivl_7", 0 0, L_0x8d321dcc0; 1 drivers +v0x8d2cf3ac0_0 .net *"_ivl_9", 7 0, L_0x8d2d1b480; 1 drivers +L_0x8d2854a78 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf3b60_0 .net/s "acc_in", 39 0, L_0x8d2854a78; 1 drivers +v0x8d2cf3c00_0 .net/s "acc_out", 39 0, L_0x8d3196620; alias, 1 drivers +v0x8d2cf3ca0_0 .net/s "product", 31 0, L_0x8d2d1b3e0; 1 drivers +v0x8d2cf3d40_0 .net/s "product_ext", 39 0, L_0x8d3196580; 1 drivers +v0x8d2cf3de0_0 .net/s "w", 15 0, L_0x8d321de00; 1 drivers +v0x8d2cf3e80_0 .net/s "x", 15 0, L_0x8d321dd60; 1 drivers +L_0x8d2d1b2a0 .extend/s 32, L_0x8d321dd60; +L_0x8d2d1b340 .extend/s 32, L_0x8d321de00; +L_0x8d2d1b3e0 .arith/mult 32, L_0x8d2d1b2a0, L_0x8d2d1b340; +L_0x8d321dcc0 .part L_0x8d2d1b3e0, 31, 1; +L_0x8d2d1b480 .repeat 8, 8, L_0x8d321dcc0; +L_0x8d3196580 .concat [ 32 8 0 0], L_0x8d2d1b3e0, L_0x8d2d1b480; +L_0x8d3196620 .arith/sum 40, L_0x8d2854a78, L_0x8d3196580; +S_0x8d31fde00 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d31fd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306ce40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306ce80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306cec0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf3f20_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1b520; 1 drivers +v0x8d2cf4000_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1b5c0; 1 drivers +v0x8d2cf40a0_0 .net *"_ivl_7", 0 0, L_0x8d321dea0; 1 drivers +v0x8d2cf4140_0 .net *"_ivl_9", 7 0, L_0x8d2d1b700; 1 drivers +L_0x8d2854ac0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf41e0_0 .net/s "acc_in", 39 0, L_0x8d2854ac0; 1 drivers +v0x8d2cf4280_0 .net/s "acc_out", 39 0, L_0x8d3196760; alias, 1 drivers +v0x8d2cf4320_0 .net/s "product", 31 0, L_0x8d2d1b660; 1 drivers +v0x8d2cf43c0_0 .net/s "product_ext", 39 0, L_0x8d31966c0; 1 drivers +v0x8d2cf4460_0 .net/s "w", 15 0, L_0x8d321dfe0; 1 drivers +v0x8d2cf4500_0 .net/s "x", 15 0, L_0x8d321df40; 1 drivers +L_0x8d2d1b520 .extend/s 32, L_0x8d321df40; +L_0x8d2d1b5c0 .extend/s 32, L_0x8d321dfe0; +L_0x8d2d1b660 .arith/mult 32, L_0x8d2d1b520, L_0x8d2d1b5c0; +L_0x8d321dea0 .part L_0x8d2d1b660, 31, 1; +L_0x8d2d1b700 .repeat 8, 8, L_0x8d321dea0; +L_0x8d31966c0 .concat [ 32 8 0 0], L_0x8d2d1b660, L_0x8d2d1b700; +L_0x8d3196760 .arith/sum 40, L_0x8d2854ac0, L_0x8d31966c0; +S_0x8d31fdf80 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d31fd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306cf00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306cf40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306cf80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf45a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1b7a0; 1 drivers +v0x8d2cf4640_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1b840; 1 drivers +v0x8d2cf46e0_0 .net *"_ivl_7", 0 0, L_0x8d321e080; 1 drivers +v0x8d2cf4780_0 .net *"_ivl_9", 7 0, L_0x8d2d1b980; 1 drivers +L_0x8d2854b08 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf4820_0 .net/s "acc_in", 39 0, L_0x8d2854b08; 1 drivers +v0x8d2cf48c0_0 .net/s "acc_out", 39 0, L_0x8d31968a0; alias, 1 drivers +v0x8d2cf4960_0 .net/s "product", 31 0, L_0x8d2d1b8e0; 1 drivers +v0x8d2cf4a00_0 .net/s "product_ext", 39 0, L_0x8d3196800; 1 drivers +v0x8d2cf4aa0_0 .net/s "w", 15 0, L_0x8d321e1c0; 1 drivers +v0x8d2cf4b40_0 .net/s "x", 15 0, L_0x8d321e120; 1 drivers +L_0x8d2d1b7a0 .extend/s 32, L_0x8d321e120; +L_0x8d2d1b840 .extend/s 32, L_0x8d321e1c0; +L_0x8d2d1b8e0 .arith/mult 32, L_0x8d2d1b7a0, L_0x8d2d1b840; +L_0x8d321e080 .part L_0x8d2d1b8e0, 31, 1; +L_0x8d2d1b980 .repeat 8, 8, L_0x8d321e080; +L_0x8d3196800 .concat [ 32 8 0 0], L_0x8d2d1b8e0, L_0x8d2d1b980; +L_0x8d31968a0 .arith/sum 40, L_0x8d2854b08, L_0x8d3196800; +S_0x8d31fe100 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d31fd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306cfc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d000 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d040 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf4be0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1ba20; 1 drivers +v0x8d2cf4c80_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1bac0; 1 drivers +v0x8d2cf4d20_0 .net *"_ivl_7", 0 0, L_0x8d321e260; 1 drivers +v0x8d2cf4dc0_0 .net *"_ivl_9", 7 0, L_0x8d2d1bc00; 1 drivers +L_0x8d2854b50 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf4e60_0 .net/s "acc_in", 39 0, L_0x8d2854b50; 1 drivers +v0x8d2cf4f00_0 .net/s "acc_out", 39 0, L_0x8d31969e0; alias, 1 drivers +v0x8d2cf4fa0_0 .net/s "product", 31 0, L_0x8d2d1bb60; 1 drivers +v0x8d2cf5040_0 .net/s "product_ext", 39 0, L_0x8d3196940; 1 drivers +v0x8d2cf50e0_0 .net/s "w", 15 0, L_0x8d321e3a0; 1 drivers +v0x8d2cf5180_0 .net/s "x", 15 0, L_0x8d321e300; 1 drivers +L_0x8d2d1ba20 .extend/s 32, L_0x8d321e300; +L_0x8d2d1bac0 .extend/s 32, L_0x8d321e3a0; +L_0x8d2d1bb60 .arith/mult 32, L_0x8d2d1ba20, L_0x8d2d1bac0; +L_0x8d321e260 .part L_0x8d2d1bb60, 31, 1; +L_0x8d2d1bc00 .repeat 8, 8, L_0x8d321e260; +L_0x8d3196940 .concat [ 32 8 0 0], L_0x8d2d1bb60, L_0x8d2d1bc00; +L_0x8d31969e0 .arith/sum 40, L_0x8d2854b50, L_0x8d3196940; +S_0x8d31fe280 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d31fd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d080 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d0c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d100 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf5220_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1bca0; 1 drivers +v0x8d2cf52c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1bd40; 1 drivers +v0x8d2cf5360_0 .net *"_ivl_7", 0 0, L_0x8d321e440; 1 drivers +v0x8d2cf5400_0 .net *"_ivl_9", 7 0, L_0x8d2d1be80; 1 drivers +L_0x8d2854b98 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf54a0_0 .net/s "acc_in", 39 0, L_0x8d2854b98; 1 drivers +v0x8d2cf5540_0 .net/s "acc_out", 39 0, L_0x8d3196b20; alias, 1 drivers +v0x8d2cf55e0_0 .net/s "product", 31 0, L_0x8d2d1bde0; 1 drivers +v0x8d2cf5680_0 .net/s "product_ext", 39 0, L_0x8d3196a80; 1 drivers +v0x8d2cf5720_0 .net/s "w", 15 0, L_0x8d321e580; 1 drivers +v0x8d2cf57c0_0 .net/s "x", 15 0, L_0x8d321e4e0; 1 drivers +L_0x8d2d1bca0 .extend/s 32, L_0x8d321e4e0; +L_0x8d2d1bd40 .extend/s 32, L_0x8d321e580; +L_0x8d2d1bde0 .arith/mult 32, L_0x8d2d1bca0, L_0x8d2d1bd40; +L_0x8d321e440 .part L_0x8d2d1bde0, 31, 1; +L_0x8d2d1be80 .repeat 8, 8, L_0x8d321e440; +L_0x8d3196a80 .concat [ 32 8 0 0], L_0x8d2d1bde0, L_0x8d2d1be80; +L_0x8d3196b20 .arith/sum 40, L_0x8d2854b98, L_0x8d3196a80; +S_0x8d31fe400 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d31fd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d140 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d180 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d1c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf5860_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1bf20; 1 drivers +v0x8d2cf5900_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1c000; 1 drivers +v0x8d2cf59a0_0 .net *"_ivl_7", 0 0, L_0x8d321e620; 1 drivers +v0x8d2cf5a40_0 .net *"_ivl_9", 7 0, L_0x8d2d1c140; 1 drivers +L_0x8d2854be0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf5ae0_0 .net/s "acc_in", 39 0, L_0x8d2854be0; 1 drivers +v0x8d2cf5b80_0 .net/s "acc_out", 39 0, L_0x8d3196c60; alias, 1 drivers +v0x8d2cf5c20_0 .net/s "product", 31 0, L_0x8d2d1c0a0; 1 drivers +v0x8d2cf5cc0_0 .net/s "product_ext", 39 0, L_0x8d3196bc0; 1 drivers +v0x8d2cf5d60_0 .net/s "w", 15 0, L_0x8d321e760; 1 drivers +v0x8d2cf5e00_0 .net/s "x", 15 0, L_0x8d321e6c0; 1 drivers +L_0x8d2d1bf20 .extend/s 32, L_0x8d321e6c0; +L_0x8d2d1c000 .extend/s 32, L_0x8d321e760; +L_0x8d2d1c0a0 .arith/mult 32, L_0x8d2d1bf20, L_0x8d2d1c000; +L_0x8d321e620 .part L_0x8d2d1c0a0, 31, 1; +L_0x8d2d1c140 .repeat 8, 8, L_0x8d321e620; +L_0x8d3196bc0 .concat [ 32 8 0 0], L_0x8d2d1c0a0, L_0x8d2d1c140; +L_0x8d3196c60 .arith/sum 40, L_0x8d2854be0, L_0x8d3196bc0; +S_0x8d31fe580 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d31fd980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d200 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d240 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d280 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cf5ea0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1c1e0; 1 drivers +v0x8d2cf5f40_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1c280; 1 drivers +v0x8d2cf5fe0_0 .net *"_ivl_7", 0 0, L_0x8d321e800; 1 drivers +v0x8d2cf6080_0 .net *"_ivl_9", 7 0, L_0x8d2d1c3c0; 1 drivers +L_0x8d2854c28 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cf6120_0 .net/s "acc_in", 39 0, L_0x8d2854c28; 1 drivers +v0x8d2cf61c0_0 .net/s "acc_out", 39 0, L_0x8d3196da0; alias, 1 drivers +v0x8d2cf6260_0 .net/s "product", 31 0, L_0x8d2d1c320; 1 drivers +v0x8d2cf6300_0 .net/s "product_ext", 39 0, L_0x8d3196d00; 1 drivers +v0x8d2cf63a0_0 .net/s "w", 15 0, L_0x8d321e940; 1 drivers +v0x8d2cf6440_0 .net/s "x", 15 0, L_0x8d321e8a0; 1 drivers +L_0x8d2d1c1e0 .extend/s 32, L_0x8d321e8a0; +L_0x8d2d1c280 .extend/s 32, L_0x8d321e940; +L_0x8d2d1c320 .arith/mult 32, L_0x8d2d1c1e0, L_0x8d2d1c280; +L_0x8d321e800 .part L_0x8d2d1c320, 31, 1; +L_0x8d2d1c3c0 .repeat 8, 8, L_0x8d321e800; +L_0x8d3196d00 .concat [ 32 8 0 0], L_0x8d2d1c320, L_0x8d2d1c3c0; +L_0x8d3196da0 .arith/sum 40, L_0x8d2854c28, L_0x8d3196d00; +S_0x8d31fe700 .scope generate, "GEN_NEURON[3]" "GEN_NEURON[3]" 4 35, 4 35 0, S_0x102e5b4b0; + .timescale 0 0; +P_0x8d2c3b180 .param/l "n" 1 4 35, +C4<011>; +S_0x8d31fe880 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d31fe700; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e66a70 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x102e66ab0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x102e66af0 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x102e66b30 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; +P_0x102e66b70 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; +P_0x102e66bb0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; +P_0x102e66bf0 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x8d307c2a0 .functor BUFZ 16, L_0x8d322c000, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8d2d005a0_0 .net *"_ivl_0", 31 0, L_0x8d3197520; 1 drivers +v0x8d2d00640_0 .net *"_ivl_11", 31 0, L_0x8d2d1c640; 1 drivers +v0x8d2d006e0_0 .net *"_ivl_14", 31 0, L_0x8d31975c0; 1 drivers +L_0x8d2854d90 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d00780_0 .net *"_ivl_17", 28 0, L_0x8d2854d90; 1 drivers +L_0x8d2854dd8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d00820_0 .net/2u *"_ivl_18", 31 0, L_0x8d2854dd8; 1 drivers +v0x8d2d008c0_0 .net *"_ivl_21", 31 0, L_0x8d2d1c6e0; 1 drivers +L_0x8d2854e20 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d00960_0 .net/2u *"_ivl_22", 31 0, L_0x8d2854e20; 1 drivers +v0x8d2d00a00_0 .net *"_ivl_25", 31 0, L_0x8d2d1c780; 1 drivers +L_0x8d2854cb8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d00aa0_0 .net *"_ivl_3", 28 0, L_0x8d2854cb8; 1 drivers +v0x8d2d00b40_0 .net *"_ivl_31", 0 0, L_0x8d321fd40; 1 drivers +v0x8d2d00be0_0 .net *"_ivl_33", 23 0, L_0x8d2d1dc20; 1 drivers +v0x8d2d00c80_0 .net *"_ivl_36", 39 0, L_0x8d3228640; 1 drivers +v0x8d2d00d20_0 .net *"_ivl_38", 31 0, L_0x8d321fde0; 1 drivers +L_0x8d2854d00 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d00dc0_0 .net/2u *"_ivl_4", 31 0, L_0x8d2854d00; 1 drivers +L_0x8d28550a8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d00e60_0 .net *"_ivl_40", 7 0, L_0x8d28550a8; 1 drivers +v0x8d2d00f00_0 .net *"_ivl_46", 31 0, L_0x8d321fe80; 1 drivers +v0x8d2d00fa0_0 .net *"_ivl_7", 31 0, L_0x8d2d1c5a0; 1 drivers +L_0x8d2854d48 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d01040_0 .net/2u *"_ivl_8", 31 0, L_0x8d2854d48; 1 drivers +v0x8d2d010e0_0 .var/s "acc", 39 0; +v0x8d2d01180_0 .net/s "acc_next", 39 0, L_0x8d3228500; 1 drivers +v0x8d2d01220_0 .net/s "bias", 15 0, L_0x8d322c000; 1 drivers +v0x8d2d012c0_0 .net/s "bias_ext", 39 0, L_0x8d32285a0; 1 drivers +v0x8d2d01360_0 .net/s "bias_ext_small", 15 0, L_0x8d307c2a0; 1 drivers +v0x8d2d01400_0 .var "busy", 0 0; +v0x8d2d014a0_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers +v0x8d2d01540_0 .var "done", 0 0; +v0x8d2d015e0_0 .net/s "final_acc", 39 0, L_0x8d32286e0; 1 drivers +v0x8d2d01680_0 .net/s "final_value", 39 0, L_0x8d2d1dcc0; 1 drivers +v0x8d2d01720_0 .var "group_index", 2 0; +v0x8d2d017c0_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers +v0x8d2d01860_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers +v0x8d2d01900_0 .net/s "w_bus", 1023 0, L_0x8d321ff20; 1 drivers +v0x8d2d019a0_0 .net/s "w_group", 127 0, L_0x8d321eda0; 1 drivers +v0x8d2d01a40_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers +v0x8d2d01ae0_0 .net/s "x_group", 127 0, L_0x8d321ed00; 1 drivers +v0x8d2d01b80_0 .var/s "y", 15 0; +L_0x8d3197520 .concat [ 3 29 0 0], v0x8d2d01720_0, L_0x8d2854cb8; +L_0x8d2d1c5a0 .arith/mult 32, L_0x8d3197520, L_0x8d2854d00; +L_0x8d2d1c640 .arith/mult 32, L_0x8d2d1c5a0, L_0x8d2854d48; +L_0x8d321ed00 .part/v v0x8d2d17ca0_0, L_0x8d2d1c640, 128; +L_0x8d31975c0 .concat [ 3 29 0 0], v0x8d2d01720_0, L_0x8d2854d90; +L_0x8d2d1c6e0 .arith/mult 32, L_0x8d31975c0, L_0x8d2854dd8; +L_0x8d2d1c780 .arith/mult 32, L_0x8d2d1c6e0, L_0x8d2854e20; +L_0x8d321eda0 .part/v L_0x8d321ff20, L_0x8d2d1c780, 128; +L_0x8d321fd40 .part L_0x8d307c2a0, 15, 1; +L_0x8d2d1dc20 .repeat 24, 24, L_0x8d321fd40; +L_0x8d32285a0 .concat [ 16 24 0 0], L_0x8d307c2a0, L_0x8d2d1dc20; +L_0x8d321fde0 .part L_0x8d32285a0, 0, 32; +L_0x8d3228640 .concat [ 8 32 0 0], L_0x8d28550a8, L_0x8d321fde0; +L_0x8d32286e0 .arith/sum 40, L_0x8d3228500, L_0x8d3228640; +L_0x8d321fe80 .part L_0x8d32286e0, 8, 32; +L_0x8d2d1dcc0 .extend/s 40, L_0x8d321fe80; +S_0x8d31fea00 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d31fe880; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d30a0780 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8d30a07c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8d2cff980_0 .net/s "acc_in", 39 0, v0x8d2d010e0_0; 1 drivers +v0x8d2cffa20_0 .net/s "acc_out", 39 0, L_0x8d3228500; alias, 1 drivers +v0x8d2cffac0_0 .net/s "m0", 39 0, L_0x8d3197700; 1 drivers +v0x8d2cffb60_0 .net/s "m1", 39 0, L_0x8d3197840; 1 drivers +v0x8d2cffc00_0 .net/s "m2", 39 0, L_0x8d3197980; 1 drivers +v0x8d2cffca0_0 .net/s "m3", 39 0, L_0x8d3197ac0; 1 drivers +v0x8d2cffd40_0 .net/s "m4", 39 0, L_0x8d3197c00; 1 drivers +v0x8d2cffde0_0 .net/s "m5", 39 0, L_0x8d3197d40; 1 drivers +v0x8d2cffe80_0 .net/s "m6", 39 0, L_0x8d3197e80; 1 drivers +v0x8d2cfff20_0 .net/s "m7", 39 0, L_0x8d3228000; 1 drivers +v0x8d2d00000_0 .net/s "s0", 39 0, L_0x8d32280a0; 1 drivers +v0x8d2d000a0_0 .net/s "s1", 39 0, L_0x8d3228140; 1 drivers +v0x8d2d00140_0 .net/s "s2", 39 0, L_0x8d32281e0; 1 drivers +v0x8d2d001e0_0 .net/s "s3", 39 0, L_0x8d3228280; 1 drivers +v0x8d2d00280_0 .net/s "s4", 39 0, L_0x8d3228320; 1 drivers +v0x8d2d00320_0 .net/s "s5", 39 0, L_0x8d32283c0; 1 drivers +v0x8d2d003c0_0 .net/s "sum", 39 0, L_0x8d3228460; 1 drivers +v0x8d2d00460_0 .net/s "w_bus", 127 0, L_0x8d321eda0; alias, 1 drivers +v0x8d2d00500_0 .net/s "x_bus", 127 0, L_0x8d321ed00; alias, 1 drivers +L_0x8d321eee0 .part L_0x8d321ed00, 0, 16; +L_0x8d321ef80 .part L_0x8d321eda0, 0, 16; +L_0x8d321f0c0 .part L_0x8d321ed00, 16, 16; +L_0x8d321f160 .part L_0x8d321eda0, 16, 16; +L_0x8d321f2a0 .part L_0x8d321ed00, 32, 16; +L_0x8d321f340 .part L_0x8d321eda0, 32, 16; +L_0x8d321f480 .part L_0x8d321ed00, 48, 16; +L_0x8d321f520 .part L_0x8d321eda0, 48, 16; +L_0x8d321f660 .part L_0x8d321ed00, 64, 16; +L_0x8d321f700 .part L_0x8d321eda0, 64, 16; +L_0x8d321f840 .part L_0x8d321ed00, 80, 16; +L_0x8d321f8e0 .part L_0x8d321eda0, 80, 16; +L_0x8d321fa20 .part L_0x8d321ed00, 96, 16; +L_0x8d321fac0 .part L_0x8d321eda0, 96, 16; +L_0x8d321fc00 .part L_0x8d321ed00, 112, 16; +L_0x8d321fca0 .part L_0x8d321eda0, 112, 16; +L_0x8d32280a0 .arith/sum 40, L_0x8d3197700, L_0x8d3197840; +L_0x8d3228140 .arith/sum 40, L_0x8d3197980, L_0x8d3197ac0; +L_0x8d32281e0 .arith/sum 40, L_0x8d3197c00, L_0x8d3197d40; +L_0x8d3228280 .arith/sum 40, L_0x8d3197e80, L_0x8d3228000; +L_0x8d3228320 .arith/sum 40, L_0x8d32280a0, L_0x8d3228140; +L_0x8d32283c0 .arith/sum 40, L_0x8d32281e0, L_0x8d3228280; +L_0x8d3228460 .arith/sum 40, L_0x8d3228320, L_0x8d32283c0; +L_0x8d3228500 .arith/sum 40, v0x8d2d010e0_0, L_0x8d3228460; +S_0x8d31feb80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d31fea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d2c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d300 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d340 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cfc780_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1c820; 1 drivers +v0x8d2cfc820_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1c8c0; 1 drivers +v0x8d2cfc8c0_0 .net *"_ivl_7", 0 0, L_0x8d321ee40; 1 drivers +v0x8d2cfc960_0 .net *"_ivl_9", 7 0, L_0x8d2d1ca00; 1 drivers +L_0x8d2854e68 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cfca00_0 .net/s "acc_in", 39 0, L_0x8d2854e68; 1 drivers +v0x8d2cfcaa0_0 .net/s "acc_out", 39 0, L_0x8d3197700; alias, 1 drivers +v0x8d2cfcb40_0 .net/s "product", 31 0, L_0x8d2d1c960; 1 drivers +v0x8d2cfcbe0_0 .net/s "product_ext", 39 0, L_0x8d3197660; 1 drivers +v0x8d2cfcc80_0 .net/s "w", 15 0, L_0x8d321ef80; 1 drivers +v0x8d2cfcd20_0 .net/s "x", 15 0, L_0x8d321eee0; 1 drivers +L_0x8d2d1c820 .extend/s 32, L_0x8d321eee0; +L_0x8d2d1c8c0 .extend/s 32, L_0x8d321ef80; +L_0x8d2d1c960 .arith/mult 32, L_0x8d2d1c820, L_0x8d2d1c8c0; +L_0x8d321ee40 .part L_0x8d2d1c960, 31, 1; +L_0x8d2d1ca00 .repeat 8, 8, L_0x8d321ee40; +L_0x8d3197660 .concat [ 32 8 0 0], L_0x8d2d1c960, L_0x8d2d1ca00; +L_0x8d3197700 .arith/sum 40, L_0x8d2854e68, L_0x8d3197660; +S_0x8d31fed00 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d31fea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d380 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d3c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d400 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cfcdc0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1caa0; 1 drivers +v0x8d2cfce60_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1cb40; 1 drivers +v0x8d2cfcf00_0 .net *"_ivl_7", 0 0, L_0x8d321f020; 1 drivers +v0x8d2cfcfa0_0 .net *"_ivl_9", 7 0, L_0x8d2d1cc80; 1 drivers +L_0x8d2854eb0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cfd040_0 .net/s "acc_in", 39 0, L_0x8d2854eb0; 1 drivers +v0x8d2cfd0e0_0 .net/s "acc_out", 39 0, L_0x8d3197840; alias, 1 drivers +v0x8d2cfd180_0 .net/s "product", 31 0, L_0x8d2d1cbe0; 1 drivers +v0x8d2cfd220_0 .net/s "product_ext", 39 0, L_0x8d31977a0; 1 drivers +v0x8d2cfd2c0_0 .net/s "w", 15 0, L_0x8d321f160; 1 drivers +v0x8d2cfd360_0 .net/s "x", 15 0, L_0x8d321f0c0; 1 drivers +L_0x8d2d1caa0 .extend/s 32, L_0x8d321f0c0; +L_0x8d2d1cb40 .extend/s 32, L_0x8d321f160; +L_0x8d2d1cbe0 .arith/mult 32, L_0x8d2d1caa0, L_0x8d2d1cb40; +L_0x8d321f020 .part L_0x8d2d1cbe0, 31, 1; +L_0x8d2d1cc80 .repeat 8, 8, L_0x8d321f020; +L_0x8d31977a0 .concat [ 32 8 0 0], L_0x8d2d1cbe0, L_0x8d2d1cc80; +L_0x8d3197840 .arith/sum 40, L_0x8d2854eb0, L_0x8d31977a0; +S_0x8d31fee80 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d31fea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d440 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d480 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d4c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cfd400_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1cd20; 1 drivers +v0x8d2cfd4a0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1cdc0; 1 drivers +v0x8d2cfd540_0 .net *"_ivl_7", 0 0, L_0x8d321f200; 1 drivers +v0x8d2cfd5e0_0 .net *"_ivl_9", 7 0, L_0x8d2d1cf00; 1 drivers +L_0x8d2854ef8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cfd680_0 .net/s "acc_in", 39 0, L_0x8d2854ef8; 1 drivers +v0x8d2cfd720_0 .net/s "acc_out", 39 0, L_0x8d3197980; alias, 1 drivers +v0x8d2cfd7c0_0 .net/s "product", 31 0, L_0x8d2d1ce60; 1 drivers +v0x8d2cfd860_0 .net/s "product_ext", 39 0, L_0x8d31978e0; 1 drivers +v0x8d2cfd900_0 .net/s "w", 15 0, L_0x8d321f340; 1 drivers +v0x8d2cfd9a0_0 .net/s "x", 15 0, L_0x8d321f2a0; 1 drivers +L_0x8d2d1cd20 .extend/s 32, L_0x8d321f2a0; +L_0x8d2d1cdc0 .extend/s 32, L_0x8d321f340; +L_0x8d2d1ce60 .arith/mult 32, L_0x8d2d1cd20, L_0x8d2d1cdc0; +L_0x8d321f200 .part L_0x8d2d1ce60, 31, 1; +L_0x8d2d1cf00 .repeat 8, 8, L_0x8d321f200; +L_0x8d31978e0 .concat [ 32 8 0 0], L_0x8d2d1ce60, L_0x8d2d1cf00; +L_0x8d3197980 .arith/sum 40, L_0x8d2854ef8, L_0x8d31978e0; +S_0x8d31ff000 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d31fea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d500 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d540 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d580 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cfda40_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1cfa0; 1 drivers +v0x8d2cfdae0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1d040; 1 drivers +v0x8d2cfdb80_0 .net *"_ivl_7", 0 0, L_0x8d321f3e0; 1 drivers +v0x8d2cfdc20_0 .net *"_ivl_9", 7 0, L_0x8d2d1d180; 1 drivers +L_0x8d2854f40 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cfdcc0_0 .net/s "acc_in", 39 0, L_0x8d2854f40; 1 drivers +v0x8d2cfdd60_0 .net/s "acc_out", 39 0, L_0x8d3197ac0; alias, 1 drivers +v0x8d2cfde00_0 .net/s "product", 31 0, L_0x8d2d1d0e0; 1 drivers +v0x8d2cfdea0_0 .net/s "product_ext", 39 0, L_0x8d3197a20; 1 drivers +v0x8d2cfdf40_0 .net/s "w", 15 0, L_0x8d321f520; 1 drivers +v0x8d2cfdfe0_0 .net/s "x", 15 0, L_0x8d321f480; 1 drivers +L_0x8d2d1cfa0 .extend/s 32, L_0x8d321f480; +L_0x8d2d1d040 .extend/s 32, L_0x8d321f520; +L_0x8d2d1d0e0 .arith/mult 32, L_0x8d2d1cfa0, L_0x8d2d1d040; +L_0x8d321f3e0 .part L_0x8d2d1d0e0, 31, 1; +L_0x8d2d1d180 .repeat 8, 8, L_0x8d321f3e0; +L_0x8d3197a20 .concat [ 32 8 0 0], L_0x8d2d1d0e0, L_0x8d2d1d180; +L_0x8d3197ac0 .arith/sum 40, L_0x8d2854f40, L_0x8d3197a20; +S_0x8d31ff180 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d31fea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d5c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d600 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d640 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cfe080_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1d220; 1 drivers +v0x8d2cfe120_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1d2c0; 1 drivers +v0x8d2cfe1c0_0 .net *"_ivl_7", 0 0, L_0x8d321f5c0; 1 drivers +v0x8d2cfe260_0 .net *"_ivl_9", 7 0, L_0x8d2d1d400; 1 drivers +L_0x8d2854f88 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cfe300_0 .net/s "acc_in", 39 0, L_0x8d2854f88; 1 drivers +v0x8d2cfe3a0_0 .net/s "acc_out", 39 0, L_0x8d3197c00; alias, 1 drivers +v0x8d2cfe440_0 .net/s "product", 31 0, L_0x8d2d1d360; 1 drivers +v0x8d2cfe4e0_0 .net/s "product_ext", 39 0, L_0x8d3197b60; 1 drivers +v0x8d2cfe580_0 .net/s "w", 15 0, L_0x8d321f700; 1 drivers +v0x8d2cfe620_0 .net/s "x", 15 0, L_0x8d321f660; 1 drivers +L_0x8d2d1d220 .extend/s 32, L_0x8d321f660; +L_0x8d2d1d2c0 .extend/s 32, L_0x8d321f700; +L_0x8d2d1d360 .arith/mult 32, L_0x8d2d1d220, L_0x8d2d1d2c0; +L_0x8d321f5c0 .part L_0x8d2d1d360, 31, 1; +L_0x8d2d1d400 .repeat 8, 8, L_0x8d321f5c0; +L_0x8d3197b60 .concat [ 32 8 0 0], L_0x8d2d1d360, L_0x8d2d1d400; +L_0x8d3197c00 .arith/sum 40, L_0x8d2854f88, L_0x8d3197b60; +S_0x8d31ff300 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d31fea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d680 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d6c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d700 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cfe6c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1d4a0; 1 drivers +v0x8d2cfe760_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1d540; 1 drivers +v0x8d2cfe800_0 .net *"_ivl_7", 0 0, L_0x8d321f7a0; 1 drivers +v0x8d2cfe8a0_0 .net *"_ivl_9", 7 0, L_0x8d2d1d680; 1 drivers +L_0x8d2854fd0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cfe940_0 .net/s "acc_in", 39 0, L_0x8d2854fd0; 1 drivers +v0x8d2cfe9e0_0 .net/s "acc_out", 39 0, L_0x8d3197d40; alias, 1 drivers +v0x8d2cfea80_0 .net/s "product", 31 0, L_0x8d2d1d5e0; 1 drivers +v0x8d2cfeb20_0 .net/s "product_ext", 39 0, L_0x8d3197ca0; 1 drivers +v0x8d2cfebc0_0 .net/s "w", 15 0, L_0x8d321f8e0; 1 drivers +v0x8d2cfec60_0 .net/s "x", 15 0, L_0x8d321f840; 1 drivers +L_0x8d2d1d4a0 .extend/s 32, L_0x8d321f840; +L_0x8d2d1d540 .extend/s 32, L_0x8d321f8e0; +L_0x8d2d1d5e0 .arith/mult 32, L_0x8d2d1d4a0, L_0x8d2d1d540; +L_0x8d321f7a0 .part L_0x8d2d1d5e0, 31, 1; +L_0x8d2d1d680 .repeat 8, 8, L_0x8d321f7a0; +L_0x8d3197ca0 .concat [ 32 8 0 0], L_0x8d2d1d5e0, L_0x8d2d1d680; +L_0x8d3197d40 .arith/sum 40, L_0x8d2854fd0, L_0x8d3197ca0; +S_0x8d31ff480 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d31fea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d740 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d780 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d7c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cfed00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1d720; 1 drivers +v0x8d2cfeda0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1d7c0; 1 drivers +v0x8d2cfee40_0 .net *"_ivl_7", 0 0, L_0x8d321f980; 1 drivers +v0x8d2cfeee0_0 .net *"_ivl_9", 7 0, L_0x8d2d1d900; 1 drivers +L_0x8d2855018 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cfef80_0 .net/s "acc_in", 39 0, L_0x8d2855018; 1 drivers +v0x8d2cff020_0 .net/s "acc_out", 39 0, L_0x8d3197e80; alias, 1 drivers +v0x8d2cff0c0_0 .net/s "product", 31 0, L_0x8d2d1d860; 1 drivers +v0x8d2cff160_0 .net/s "product_ext", 39 0, L_0x8d3197de0; 1 drivers +v0x8d2cff200_0 .net/s "w", 15 0, L_0x8d321fac0; 1 drivers +v0x8d2cff2a0_0 .net/s "x", 15 0, L_0x8d321fa20; 1 drivers +L_0x8d2d1d720 .extend/s 32, L_0x8d321fa20; +L_0x8d2d1d7c0 .extend/s 32, L_0x8d321fac0; +L_0x8d2d1d860 .arith/mult 32, L_0x8d2d1d720, L_0x8d2d1d7c0; +L_0x8d321f980 .part L_0x8d2d1d860, 31, 1; +L_0x8d2d1d900 .repeat 8, 8, L_0x8d321f980; +L_0x8d3197de0 .concat [ 32 8 0 0], L_0x8d2d1d860, L_0x8d2d1d900; +L_0x8d3197e80 .arith/sum 40, L_0x8d2855018, L_0x8d3197de0; +S_0x8d31ff600 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d31fea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d800 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d840 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d880 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2cff340_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1d9a0; 1 drivers +v0x8d2cff3e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1da40; 1 drivers +v0x8d2cff480_0 .net *"_ivl_7", 0 0, L_0x8d321fb60; 1 drivers +v0x8d2cff520_0 .net *"_ivl_9", 7 0, L_0x8d2d1db80; 1 drivers +L_0x8d2855060 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2cff5c0_0 .net/s "acc_in", 39 0, L_0x8d2855060; 1 drivers +v0x8d2cff660_0 .net/s "acc_out", 39 0, L_0x8d3228000; alias, 1 drivers +v0x8d2cff700_0 .net/s "product", 31 0, L_0x8d2d1dae0; 1 drivers +v0x8d2cff7a0_0 .net/s "product_ext", 39 0, L_0x8d3197f20; 1 drivers +v0x8d2cff840_0 .net/s "w", 15 0, L_0x8d321fca0; 1 drivers +v0x8d2cff8e0_0 .net/s "x", 15 0, L_0x8d321fc00; 1 drivers +L_0x8d2d1d9a0 .extend/s 32, L_0x8d321fc00; +L_0x8d2d1da40 .extend/s 32, L_0x8d321fca0; +L_0x8d2d1dae0 .arith/mult 32, L_0x8d2d1d9a0, L_0x8d2d1da40; +L_0x8d321fb60 .part L_0x8d2d1dae0, 31, 1; +L_0x8d2d1db80 .repeat 8, 8, L_0x8d321fb60; +L_0x8d3197f20 .concat [ 32 8 0 0], L_0x8d2d1dae0, L_0x8d2d1db80; +L_0x8d3228000 .arith/sum 40, L_0x8d2855060, L_0x8d3197f20; +S_0x8d31ff780 .scope generate, "GEN_NEURON[4]" "GEN_NEURON[4]" 4 35, 4 35 0, S_0x102e5b4b0; + .timescale 0 0; +P_0x8d2c3b1c0 .param/l "n" 1 4 35, +C4<0100>; +S_0x8d31ff900 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d31ff780; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e66e30 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x102e66e70 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x102e66eb0 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x102e66ef0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; +P_0x102e66f30 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; +P_0x102e66f70 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; +P_0x102e66fb0 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x8d307c310 .functor BUFZ 16, L_0x8d322d360, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8d2d05a40_0 .net *"_ivl_0", 31 0, L_0x8d3228780; 1 drivers +v0x8d2d05ae0_0 .net *"_ivl_11", 31 0, L_0x8d2d1de00; 1 drivers +v0x8d2d05b80_0 .net *"_ivl_14", 31 0, L_0x8d3228820; 1 drivers +L_0x8d28551c8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d05c20_0 .net *"_ivl_17", 28 0, L_0x8d28551c8; 1 drivers +L_0x8d2855210 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d05cc0_0 .net/2u *"_ivl_18", 31 0, L_0x8d2855210; 1 drivers +v0x8d2d05d60_0 .net *"_ivl_21", 31 0, L_0x8d2d1dea0; 1 drivers +L_0x8d2855258 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d05e00_0 .net/2u *"_ivl_22", 31 0, L_0x8d2855258; 1 drivers +v0x8d2d05ea0_0 .net *"_ivl_25", 31 0, L_0x8d2d1df40; 1 drivers +L_0x8d28550f0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d05f40_0 .net *"_ivl_3", 28 0, L_0x8d28550f0; 1 drivers +v0x8d2d05fe0_0 .net *"_ivl_31", 0 0, L_0x8d322d0e0; 1 drivers +v0x8d2d06080_0 .net *"_ivl_33", 23 0, L_0x8d2d1f3e0; 1 drivers +v0x8d2d06120_0 .net *"_ivl_36", 39 0, L_0x8d3229860; 1 drivers +v0x8d2d061c0_0 .net *"_ivl_38", 31 0, L_0x8d322d180; 1 drivers +L_0x8d2855138 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d06260_0 .net/2u *"_ivl_4", 31 0, L_0x8d2855138; 1 drivers +L_0x8d28554e0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d06300_0 .net *"_ivl_40", 7 0, L_0x8d28554e0; 1 drivers +v0x8d2d063a0_0 .net *"_ivl_46", 31 0, L_0x8d322d220; 1 drivers +v0x8d2d06440_0 .net *"_ivl_7", 31 0, L_0x8d2d1dd60; 1 drivers +L_0x8d2855180 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d064e0_0 .net/2u *"_ivl_8", 31 0, L_0x8d2855180; 1 drivers +v0x8d2d06580_0 .var/s "acc", 39 0; +v0x8d2d06620_0 .net/s "acc_next", 39 0, L_0x8d3229720; 1 drivers +v0x8d2d066c0_0 .net/s "bias", 15 0, L_0x8d322d360; 1 drivers +v0x8d2d06760_0 .net/s "bias_ext", 39 0, L_0x8d32297c0; 1 drivers +v0x8d2d06800_0 .net/s "bias_ext_small", 15 0, L_0x8d307c310; 1 drivers +v0x8d2d068a0_0 .var "busy", 0 0; +v0x8d2d06940_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers +v0x8d2d069e0_0 .var "done", 0 0; +v0x8d2d06a80_0 .net/s "final_acc", 39 0, L_0x8d3229900; 1 drivers +v0x8d2d06b20_0 .net/s "final_value", 39 0, L_0x8d2d1f480; 1 drivers +v0x8d2d06bc0_0 .var "group_index", 2 0; +v0x8d2d06c60_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers +v0x8d2d06d00_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers +v0x8d2d06da0_0 .net/s "w_bus", 1023 0, L_0x8d322d2c0; 1 drivers +v0x8d2d06e40_0 .net/s "w_group", 127 0, L_0x8d322c140; 1 drivers +v0x8d2d06ee0_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers +v0x8d2d06f80_0 .net/s "x_group", 127 0, L_0x8d322c0a0; 1 drivers +v0x8d2d07020_0 .var/s "y", 15 0; +L_0x8d3228780 .concat [ 3 29 0 0], v0x8d2d06bc0_0, L_0x8d28550f0; +L_0x8d2d1dd60 .arith/mult 32, L_0x8d3228780, L_0x8d2855138; +L_0x8d2d1de00 .arith/mult 32, L_0x8d2d1dd60, L_0x8d2855180; +L_0x8d322c0a0 .part/v v0x8d2d17ca0_0, L_0x8d2d1de00, 128; +L_0x8d3228820 .concat [ 3 29 0 0], v0x8d2d06bc0_0, L_0x8d28551c8; +L_0x8d2d1dea0 .arith/mult 32, L_0x8d3228820, L_0x8d2855210; +L_0x8d2d1df40 .arith/mult 32, L_0x8d2d1dea0, L_0x8d2855258; +L_0x8d322c140 .part/v L_0x8d322d2c0, L_0x8d2d1df40, 128; +L_0x8d322d0e0 .part L_0x8d307c310, 15, 1; +L_0x8d2d1f3e0 .repeat 24, 24, L_0x8d322d0e0; +L_0x8d32297c0 .concat [ 16 24 0 0], L_0x8d307c310, L_0x8d2d1f3e0; +L_0x8d322d180 .part L_0x8d32297c0, 0, 32; +L_0x8d3229860 .concat [ 8 32 0 0], L_0x8d28554e0, L_0x8d322d180; +L_0x8d3229900 .arith/sum 40, L_0x8d3229720, L_0x8d3229860; +L_0x8d322d220 .part L_0x8d3229900, 8, 32; +L_0x8d2d1f480 .extend/s 40, L_0x8d322d220; +S_0x8d31ffa80 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d31ff900; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d30a0800 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8d30a0840 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8d2d04e60_0 .net/s "acc_in", 39 0, v0x8d2d06580_0; 1 drivers +v0x8d2d04f00_0 .net/s "acc_out", 39 0, L_0x8d3229720; alias, 1 drivers +v0x8d2d04fa0_0 .net/s "m0", 39 0, L_0x8d3228960; 1 drivers +v0x8d2d05040_0 .net/s "m1", 39 0, L_0x8d3228aa0; 1 drivers +v0x8d2d050e0_0 .net/s "m2", 39 0, L_0x8d3228be0; 1 drivers +v0x8d2d05180_0 .net/s "m3", 39 0, L_0x8d3228d20; 1 drivers +v0x8d2d05220_0 .net/s "m4", 39 0, L_0x8d3228e60; 1 drivers +v0x8d2d052c0_0 .net/s "m5", 39 0, L_0x8d3228fa0; 1 drivers +v0x8d2d05360_0 .net/s "m6", 39 0, L_0x8d32290e0; 1 drivers +v0x8d2d05400_0 .net/s "m7", 39 0, L_0x8d3229220; 1 drivers +v0x8d2d054a0_0 .net/s "s0", 39 0, L_0x8d32292c0; 1 drivers +v0x8d2d05540_0 .net/s "s1", 39 0, L_0x8d3229360; 1 drivers +v0x8d2d055e0_0 .net/s "s2", 39 0, L_0x8d3229400; 1 drivers +v0x8d2d05680_0 .net/s "s3", 39 0, L_0x8d32294a0; 1 drivers +v0x8d2d05720_0 .net/s "s4", 39 0, L_0x8d3229540; 1 drivers +v0x8d2d057c0_0 .net/s "s5", 39 0, L_0x8d32295e0; 1 drivers +v0x8d2d05860_0 .net/s "sum", 39 0, L_0x8d3229680; 1 drivers +v0x8d2d05900_0 .net/s "w_bus", 127 0, L_0x8d322c140; alias, 1 drivers +v0x8d2d059a0_0 .net/s "x_bus", 127 0, L_0x8d322c0a0; alias, 1 drivers +L_0x8d322c280 .part L_0x8d322c0a0, 0, 16; +L_0x8d322c320 .part L_0x8d322c140, 0, 16; +L_0x8d322c460 .part L_0x8d322c0a0, 16, 16; +L_0x8d322c500 .part L_0x8d322c140, 16, 16; +L_0x8d322c640 .part L_0x8d322c0a0, 32, 16; +L_0x8d322c6e0 .part L_0x8d322c140, 32, 16; +L_0x8d322c820 .part L_0x8d322c0a0, 48, 16; +L_0x8d322c8c0 .part L_0x8d322c140, 48, 16; +L_0x8d322ca00 .part L_0x8d322c0a0, 64, 16; +L_0x8d322caa0 .part L_0x8d322c140, 64, 16; +L_0x8d322cbe0 .part L_0x8d322c0a0, 80, 16; +L_0x8d322cc80 .part L_0x8d322c140, 80, 16; +L_0x8d322cdc0 .part L_0x8d322c0a0, 96, 16; +L_0x8d322ce60 .part L_0x8d322c140, 96, 16; +L_0x8d322cfa0 .part L_0x8d322c0a0, 112, 16; +L_0x8d322d040 .part L_0x8d322c140, 112, 16; +L_0x8d32292c0 .arith/sum 40, L_0x8d3228960, L_0x8d3228aa0; +L_0x8d3229360 .arith/sum 40, L_0x8d3228be0, L_0x8d3228d20; +L_0x8d3229400 .arith/sum 40, L_0x8d3228e60, L_0x8d3228fa0; +L_0x8d32294a0 .arith/sum 40, L_0x8d32290e0, L_0x8d3229220; +L_0x8d3229540 .arith/sum 40, L_0x8d32292c0, L_0x8d3229360; +L_0x8d32295e0 .arith/sum 40, L_0x8d3229400, L_0x8d32294a0; +L_0x8d3229680 .arith/sum 40, L_0x8d3229540, L_0x8d32295e0; +L_0x8d3229720 .arith/sum 40, v0x8d2d06580_0, L_0x8d3229680; +S_0x8d31ffc00 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d31ffa80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d8c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d900 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306d940 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d01c20_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1dfe0; 1 drivers +v0x8d2d01cc0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1e080; 1 drivers +v0x8d2d01d60_0 .net *"_ivl_7", 0 0, L_0x8d322c1e0; 1 drivers +v0x8d2d01e00_0 .net *"_ivl_9", 7 0, L_0x8d2d1e1c0; 1 drivers +L_0x8d28552a0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d01ea0_0 .net/s "acc_in", 39 0, L_0x8d28552a0; 1 drivers +v0x8d2d01f40_0 .net/s "acc_out", 39 0, L_0x8d3228960; alias, 1 drivers +v0x8d2d01fe0_0 .net/s "product", 31 0, L_0x8d2d1e120; 1 drivers +v0x8d2d02080_0 .net/s "product_ext", 39 0, L_0x8d32288c0; 1 drivers +v0x8d2d02120_0 .net/s "w", 15 0, L_0x8d322c320; 1 drivers +v0x8d2d021c0_0 .net/s "x", 15 0, L_0x8d322c280; 1 drivers +L_0x8d2d1dfe0 .extend/s 32, L_0x8d322c280; +L_0x8d2d1e080 .extend/s 32, L_0x8d322c320; +L_0x8d2d1e120 .arith/mult 32, L_0x8d2d1dfe0, L_0x8d2d1e080; +L_0x8d322c1e0 .part L_0x8d2d1e120, 31, 1; +L_0x8d2d1e1c0 .repeat 8, 8, L_0x8d322c1e0; +L_0x8d32288c0 .concat [ 32 8 0 0], L_0x8d2d1e120, L_0x8d2d1e1c0; +L_0x8d3228960 .arith/sum 40, L_0x8d28552a0, L_0x8d32288c0; +S_0x8d31ffd80 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d31ffa80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306d980 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306d9c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306da00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d02260_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1e260; 1 drivers +v0x8d2d02300_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1e300; 1 drivers +v0x8d2d023a0_0 .net *"_ivl_7", 0 0, L_0x8d322c3c0; 1 drivers +v0x8d2d02440_0 .net *"_ivl_9", 7 0, L_0x8d2d1e440; 1 drivers +L_0x8d28552e8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d024e0_0 .net/s "acc_in", 39 0, L_0x8d28552e8; 1 drivers +v0x8d2d02580_0 .net/s "acc_out", 39 0, L_0x8d3228aa0; alias, 1 drivers +v0x8d2d02620_0 .net/s "product", 31 0, L_0x8d2d1e3a0; 1 drivers +v0x8d2d026c0_0 .net/s "product_ext", 39 0, L_0x8d3228a00; 1 drivers +v0x8d2d02760_0 .net/s "w", 15 0, L_0x8d322c500; 1 drivers +v0x8d2d02800_0 .net/s "x", 15 0, L_0x8d322c460; 1 drivers +L_0x8d2d1e260 .extend/s 32, L_0x8d322c460; +L_0x8d2d1e300 .extend/s 32, L_0x8d322c500; +L_0x8d2d1e3a0 .arith/mult 32, L_0x8d2d1e260, L_0x8d2d1e300; +L_0x8d322c3c0 .part L_0x8d2d1e3a0, 31, 1; +L_0x8d2d1e440 .repeat 8, 8, L_0x8d322c3c0; +L_0x8d3228a00 .concat [ 32 8 0 0], L_0x8d2d1e3a0, L_0x8d2d1e440; +L_0x8d3228aa0 .arith/sum 40, L_0x8d28552e8, L_0x8d3228a00; +S_0x8d3208000 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d31ffa80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306da40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306da80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306dac0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d028a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1e4e0; 1 drivers +v0x8d2d02940_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1e580; 1 drivers +v0x8d2d029e0_0 .net *"_ivl_7", 0 0, L_0x8d322c5a0; 1 drivers +v0x8d2d02a80_0 .net *"_ivl_9", 7 0, L_0x8d2d1e6c0; 1 drivers +L_0x8d2855330 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d02b20_0 .net/s "acc_in", 39 0, L_0x8d2855330; 1 drivers +v0x8d2d02bc0_0 .net/s "acc_out", 39 0, L_0x8d3228be0; alias, 1 drivers +v0x8d2d02c60_0 .net/s "product", 31 0, L_0x8d2d1e620; 1 drivers +v0x8d2d02d00_0 .net/s "product_ext", 39 0, L_0x8d3228b40; 1 drivers +v0x8d2d02da0_0 .net/s "w", 15 0, L_0x8d322c6e0; 1 drivers +v0x8d2d02e40_0 .net/s "x", 15 0, L_0x8d322c640; 1 drivers +L_0x8d2d1e4e0 .extend/s 32, L_0x8d322c640; +L_0x8d2d1e580 .extend/s 32, L_0x8d322c6e0; +L_0x8d2d1e620 .arith/mult 32, L_0x8d2d1e4e0, L_0x8d2d1e580; +L_0x8d322c5a0 .part L_0x8d2d1e620, 31, 1; +L_0x8d2d1e6c0 .repeat 8, 8, L_0x8d322c5a0; +L_0x8d3228b40 .concat [ 32 8 0 0], L_0x8d2d1e620, L_0x8d2d1e6c0; +L_0x8d3228be0 .arith/sum 40, L_0x8d2855330, L_0x8d3228b40; +S_0x8d3208180 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d31ffa80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306db00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306db40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306db80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d02ee0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1e760; 1 drivers +v0x8d2d02f80_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1e800; 1 drivers +v0x8d2d03020_0 .net *"_ivl_7", 0 0, L_0x8d322c780; 1 drivers +v0x8d2d030c0_0 .net *"_ivl_9", 7 0, L_0x8d2d1e940; 1 drivers +L_0x8d2855378 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d03160_0 .net/s "acc_in", 39 0, L_0x8d2855378; 1 drivers +v0x8d2d03200_0 .net/s "acc_out", 39 0, L_0x8d3228d20; alias, 1 drivers +v0x8d2d032a0_0 .net/s "product", 31 0, L_0x8d2d1e8a0; 1 drivers +v0x8d2d03340_0 .net/s "product_ext", 39 0, L_0x8d3228c80; 1 drivers +v0x8d2d033e0_0 .net/s "w", 15 0, L_0x8d322c8c0; 1 drivers +v0x8d2d03480_0 .net/s "x", 15 0, L_0x8d322c820; 1 drivers +L_0x8d2d1e760 .extend/s 32, L_0x8d322c820; +L_0x8d2d1e800 .extend/s 32, L_0x8d322c8c0; +L_0x8d2d1e8a0 .arith/mult 32, L_0x8d2d1e760, L_0x8d2d1e800; +L_0x8d322c780 .part L_0x8d2d1e8a0, 31, 1; +L_0x8d2d1e940 .repeat 8, 8, L_0x8d322c780; +L_0x8d3228c80 .concat [ 32 8 0 0], L_0x8d2d1e8a0, L_0x8d2d1e940; +L_0x8d3228d20 .arith/sum 40, L_0x8d2855378, L_0x8d3228c80; +S_0x8d3208300 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d31ffa80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306dbc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306dc00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306dc40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d03520_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1e9e0; 1 drivers +v0x8d2d035c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1ea80; 1 drivers +v0x8d2d03660_0 .net *"_ivl_7", 0 0, L_0x8d322c960; 1 drivers +v0x8d2d03700_0 .net *"_ivl_9", 7 0, L_0x8d2d1ebc0; 1 drivers +L_0x8d28553c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d037a0_0 .net/s "acc_in", 39 0, L_0x8d28553c0; 1 drivers +v0x8d2d03840_0 .net/s "acc_out", 39 0, L_0x8d3228e60; alias, 1 drivers +v0x8d2d038e0_0 .net/s "product", 31 0, L_0x8d2d1eb20; 1 drivers +v0x8d2d03980_0 .net/s "product_ext", 39 0, L_0x8d3228dc0; 1 drivers +v0x8d2d03a20_0 .net/s "w", 15 0, L_0x8d322caa0; 1 drivers +v0x8d2d03ac0_0 .net/s "x", 15 0, L_0x8d322ca00; 1 drivers +L_0x8d2d1e9e0 .extend/s 32, L_0x8d322ca00; +L_0x8d2d1ea80 .extend/s 32, L_0x8d322caa0; +L_0x8d2d1eb20 .arith/mult 32, L_0x8d2d1e9e0, L_0x8d2d1ea80; +L_0x8d322c960 .part L_0x8d2d1eb20, 31, 1; +L_0x8d2d1ebc0 .repeat 8, 8, L_0x8d322c960; +L_0x8d3228dc0 .concat [ 32 8 0 0], L_0x8d2d1eb20, L_0x8d2d1ebc0; +L_0x8d3228e60 .arith/sum 40, L_0x8d28553c0, L_0x8d3228dc0; +S_0x8d3208480 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d31ffa80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306dc80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306dcc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306dd00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d03b60_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1ec60; 1 drivers +v0x8d2d03c00_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1ed00; 1 drivers +v0x8d2d03ca0_0 .net *"_ivl_7", 0 0, L_0x8d322cb40; 1 drivers +v0x8d2d03d40_0 .net *"_ivl_9", 7 0, L_0x8d2d1ee40; 1 drivers +L_0x8d2855408 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d03de0_0 .net/s "acc_in", 39 0, L_0x8d2855408; 1 drivers +v0x8d2d03e80_0 .net/s "acc_out", 39 0, L_0x8d3228fa0; alias, 1 drivers +v0x8d2d03f20_0 .net/s "product", 31 0, L_0x8d2d1eda0; 1 drivers +v0x8d2d04000_0 .net/s "product_ext", 39 0, L_0x8d3228f00; 1 drivers +v0x8d2d040a0_0 .net/s "w", 15 0, L_0x8d322cc80; 1 drivers +v0x8d2d04140_0 .net/s "x", 15 0, L_0x8d322cbe0; 1 drivers +L_0x8d2d1ec60 .extend/s 32, L_0x8d322cbe0; +L_0x8d2d1ed00 .extend/s 32, L_0x8d322cc80; +L_0x8d2d1eda0 .arith/mult 32, L_0x8d2d1ec60, L_0x8d2d1ed00; +L_0x8d322cb40 .part L_0x8d2d1eda0, 31, 1; +L_0x8d2d1ee40 .repeat 8, 8, L_0x8d322cb40; +L_0x8d3228f00 .concat [ 32 8 0 0], L_0x8d2d1eda0, L_0x8d2d1ee40; +L_0x8d3228fa0 .arith/sum 40, L_0x8d2855408, L_0x8d3228f00; +S_0x8d3208600 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d31ffa80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306dd40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306dd80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ddc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d041e0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1eee0; 1 drivers +v0x8d2d04280_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1ef80; 1 drivers +v0x8d2d04320_0 .net *"_ivl_7", 0 0, L_0x8d322cd20; 1 drivers +v0x8d2d043c0_0 .net *"_ivl_9", 7 0, L_0x8d2d1f0c0; 1 drivers +L_0x8d2855450 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d04460_0 .net/s "acc_in", 39 0, L_0x8d2855450; 1 drivers +v0x8d2d04500_0 .net/s "acc_out", 39 0, L_0x8d32290e0; alias, 1 drivers +v0x8d2d045a0_0 .net/s "product", 31 0, L_0x8d2d1f020; 1 drivers +v0x8d2d04640_0 .net/s "product_ext", 39 0, L_0x8d3229040; 1 drivers +v0x8d2d046e0_0 .net/s "w", 15 0, L_0x8d322ce60; 1 drivers +v0x8d2d04780_0 .net/s "x", 15 0, L_0x8d322cdc0; 1 drivers +L_0x8d2d1eee0 .extend/s 32, L_0x8d322cdc0; +L_0x8d2d1ef80 .extend/s 32, L_0x8d322ce60; +L_0x8d2d1f020 .arith/mult 32, L_0x8d2d1eee0, L_0x8d2d1ef80; +L_0x8d322cd20 .part L_0x8d2d1f020, 31, 1; +L_0x8d2d1f0c0 .repeat 8, 8, L_0x8d322cd20; +L_0x8d3229040 .concat [ 32 8 0 0], L_0x8d2d1f020, L_0x8d2d1f0c0; +L_0x8d32290e0 .arith/sum 40, L_0x8d2855450, L_0x8d3229040; +S_0x8d3208780 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d31ffa80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306de00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306de40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306de80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d04820_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1f160; 1 drivers +v0x8d2d048c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1f200; 1 drivers +v0x8d2d04960_0 .net *"_ivl_7", 0 0, L_0x8d322cf00; 1 drivers +v0x8d2d04a00_0 .net *"_ivl_9", 7 0, L_0x8d2d1f340; 1 drivers +L_0x8d2855498 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d04aa0_0 .net/s "acc_in", 39 0, L_0x8d2855498; 1 drivers +v0x8d2d04b40_0 .net/s "acc_out", 39 0, L_0x8d3229220; alias, 1 drivers +v0x8d2d04be0_0 .net/s "product", 31 0, L_0x8d2d1f2a0; 1 drivers +v0x8d2d04c80_0 .net/s "product_ext", 39 0, L_0x8d3229180; 1 drivers +v0x8d2d04d20_0 .net/s "w", 15 0, L_0x8d322d040; 1 drivers +v0x8d2d04dc0_0 .net/s "x", 15 0, L_0x8d322cfa0; 1 drivers +L_0x8d2d1f160 .extend/s 32, L_0x8d322cfa0; +L_0x8d2d1f200 .extend/s 32, L_0x8d322d040; +L_0x8d2d1f2a0 .arith/mult 32, L_0x8d2d1f160, L_0x8d2d1f200; +L_0x8d322cf00 .part L_0x8d2d1f2a0, 31, 1; +L_0x8d2d1f340 .repeat 8, 8, L_0x8d322cf00; +L_0x8d3229180 .concat [ 32 8 0 0], L_0x8d2d1f2a0, L_0x8d2d1f340; +L_0x8d3229220 .arith/sum 40, L_0x8d2855498, L_0x8d3229180; +S_0x8d3208900 .scope generate, "GEN_NEURON[5]" "GEN_NEURON[5]" 4 35, 4 35 0, S_0x102e5b4b0; + .timescale 0 0; +P_0x8d2c3b200 .param/l "n" 1 4 35, +C4<0101>; +S_0x8d3208a80 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d3208900; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e671f0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x102e67230 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x102e67270 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x102e672b0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; +P_0x102e672f0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; +P_0x102e67330 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; +P_0x102e67370 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x8d307c380 .functor BUFZ 16, L_0x8d322e6c0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8d2d0aee0_0 .net *"_ivl_0", 31 0, L_0x8d32299a0; 1 drivers +v0x8d2d0af80_0 .net *"_ivl_11", 31 0, L_0x8d2d1f5c0; 1 drivers +v0x8d2d0b020_0 .net *"_ivl_14", 31 0, L_0x8d3229a40; 1 drivers +L_0x8d2855600 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0b0c0_0 .net *"_ivl_17", 28 0, L_0x8d2855600; 1 drivers +L_0x8d2855648 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0b160_0 .net/2u *"_ivl_18", 31 0, L_0x8d2855648; 1 drivers +v0x8d2d0b200_0 .net *"_ivl_21", 31 0, L_0x8d2d1f660; 1 drivers +L_0x8d2855690 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0b2a0_0 .net/2u *"_ivl_22", 31 0, L_0x8d2855690; 1 drivers +v0x8d2d0b340_0 .net *"_ivl_25", 31 0, L_0x8d2d1f700; 1 drivers +L_0x8d2855528 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0b3e0_0 .net *"_ivl_3", 28 0, L_0x8d2855528; 1 drivers +v0x8d2d0b480_0 .net *"_ivl_31", 0 0, L_0x8d322e440; 1 drivers +v0x8d2d0b520_0 .net *"_ivl_33", 23 0, L_0x8d2d20be0; 1 drivers +v0x8d2d0b5c0_0 .net *"_ivl_36", 39 0, L_0x8d322aa80; 1 drivers +v0x8d2d0b660_0 .net *"_ivl_38", 31 0, L_0x8d322e4e0; 1 drivers +L_0x8d2855570 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0b700_0 .net/2u *"_ivl_4", 31 0, L_0x8d2855570; 1 drivers +L_0x8d2855918 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0b7a0_0 .net *"_ivl_40", 7 0, L_0x8d2855918; 1 drivers +v0x8d2d0b840_0 .net *"_ivl_46", 31 0, L_0x8d322e580; 1 drivers +v0x8d2d0b8e0_0 .net *"_ivl_7", 31 0, L_0x8d2d1f520; 1 drivers +L_0x8d28555b8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0b980_0 .net/2u *"_ivl_8", 31 0, L_0x8d28555b8; 1 drivers +v0x8d2d0ba20_0 .var/s "acc", 39 0; +v0x8d2d0bac0_0 .net/s "acc_next", 39 0, L_0x8d322a940; 1 drivers +v0x8d2d0bb60_0 .net/s "bias", 15 0, L_0x8d322e6c0; 1 drivers +v0x8d2d0bc00_0 .net/s "bias_ext", 39 0, L_0x8d322a9e0; 1 drivers +v0x8d2d0bca0_0 .net/s "bias_ext_small", 15 0, L_0x8d307c380; 1 drivers +v0x8d2d0bd40_0 .var "busy", 0 0; +v0x8d2d0bde0_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers +v0x8d2d0be80_0 .var "done", 0 0; +v0x8d2d0bf20_0 .net/s "final_acc", 39 0, L_0x8d322ab20; 1 drivers +v0x8d2d0c000_0 .net/s "final_value", 39 0, L_0x8d2d20c80; 1 drivers +v0x8d2d0c0a0_0 .var "group_index", 2 0; +v0x8d2d0c140_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers +v0x8d2d0c1e0_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers +v0x8d2d0c280_0 .net/s "w_bus", 1023 0, L_0x8d322e620; 1 drivers +v0x8d2d0c320_0 .net/s "w_group", 127 0, L_0x8d322d4a0; 1 drivers +v0x8d2d0c3c0_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers +v0x8d2d0c460_0 .net/s "x_group", 127 0, L_0x8d322d400; 1 drivers +v0x8d2d0c500_0 .var/s "y", 15 0; +L_0x8d32299a0 .concat [ 3 29 0 0], v0x8d2d0c0a0_0, L_0x8d2855528; +L_0x8d2d1f520 .arith/mult 32, L_0x8d32299a0, L_0x8d2855570; +L_0x8d2d1f5c0 .arith/mult 32, L_0x8d2d1f520, L_0x8d28555b8; +L_0x8d322d400 .part/v v0x8d2d17ca0_0, L_0x8d2d1f5c0, 128; +L_0x8d3229a40 .concat [ 3 29 0 0], v0x8d2d0c0a0_0, L_0x8d2855600; +L_0x8d2d1f660 .arith/mult 32, L_0x8d3229a40, L_0x8d2855648; +L_0x8d2d1f700 .arith/mult 32, L_0x8d2d1f660, L_0x8d2855690; +L_0x8d322d4a0 .part/v L_0x8d322e620, L_0x8d2d1f700, 128; +L_0x8d322e440 .part L_0x8d307c380, 15, 1; +L_0x8d2d20be0 .repeat 24, 24, L_0x8d322e440; +L_0x8d322a9e0 .concat [ 16 24 0 0], L_0x8d307c380, L_0x8d2d20be0; +L_0x8d322e4e0 .part L_0x8d322a9e0, 0, 32; +L_0x8d322aa80 .concat [ 8 32 0 0], L_0x8d2855918, L_0x8d322e4e0; +L_0x8d322ab20 .arith/sum 40, L_0x8d322a940, L_0x8d322aa80; +L_0x8d322e580 .part L_0x8d322ab20, 8, 32; +L_0x8d2d20c80 .extend/s 40, L_0x8d322e580; +S_0x8d3208c00 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d3208a80; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d30a0880 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8d30a08c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8d2d0a300_0 .net/s "acc_in", 39 0, v0x8d2d0ba20_0; 1 drivers +v0x8d2d0a3a0_0 .net/s "acc_out", 39 0, L_0x8d322a940; alias, 1 drivers +v0x8d2d0a440_0 .net/s "m0", 39 0, L_0x8d3229b80; 1 drivers +v0x8d2d0a4e0_0 .net/s "m1", 39 0, L_0x8d3229cc0; 1 drivers +v0x8d2d0a580_0 .net/s "m2", 39 0, L_0x8d3229e00; 1 drivers +v0x8d2d0a620_0 .net/s "m3", 39 0, L_0x8d3229f40; 1 drivers +v0x8d2d0a6c0_0 .net/s "m4", 39 0, L_0x8d322a080; 1 drivers +v0x8d2d0a760_0 .net/s "m5", 39 0, L_0x8d322a1c0; 1 drivers +v0x8d2d0a800_0 .net/s "m6", 39 0, L_0x8d322a300; 1 drivers +v0x8d2d0a8a0_0 .net/s "m7", 39 0, L_0x8d322a440; 1 drivers +v0x8d2d0a940_0 .net/s "s0", 39 0, L_0x8d322a4e0; 1 drivers +v0x8d2d0a9e0_0 .net/s "s1", 39 0, L_0x8d322a580; 1 drivers +v0x8d2d0aa80_0 .net/s "s2", 39 0, L_0x8d322a620; 1 drivers +v0x8d2d0ab20_0 .net/s "s3", 39 0, L_0x8d322a6c0; 1 drivers +v0x8d2d0abc0_0 .net/s "s4", 39 0, L_0x8d322a760; 1 drivers +v0x8d2d0ac60_0 .net/s "s5", 39 0, L_0x8d322a800; 1 drivers +v0x8d2d0ad00_0 .net/s "sum", 39 0, L_0x8d322a8a0; 1 drivers +v0x8d2d0ada0_0 .net/s "w_bus", 127 0, L_0x8d322d4a0; alias, 1 drivers +v0x8d2d0ae40_0 .net/s "x_bus", 127 0, L_0x8d322d400; alias, 1 drivers +L_0x8d322d5e0 .part L_0x8d322d400, 0, 16; +L_0x8d322d680 .part L_0x8d322d4a0, 0, 16; +L_0x8d322d7c0 .part L_0x8d322d400, 16, 16; +L_0x8d322d860 .part L_0x8d322d4a0, 16, 16; +L_0x8d322d9a0 .part L_0x8d322d400, 32, 16; +L_0x8d322da40 .part L_0x8d322d4a0, 32, 16; +L_0x8d322db80 .part L_0x8d322d400, 48, 16; +L_0x8d322dc20 .part L_0x8d322d4a0, 48, 16; +L_0x8d322dd60 .part L_0x8d322d400, 64, 16; +L_0x8d322de00 .part L_0x8d322d4a0, 64, 16; +L_0x8d322df40 .part L_0x8d322d400, 80, 16; +L_0x8d322dfe0 .part L_0x8d322d4a0, 80, 16; +L_0x8d322e120 .part L_0x8d322d400, 96, 16; +L_0x8d322e1c0 .part L_0x8d322d4a0, 96, 16; +L_0x8d322e300 .part L_0x8d322d400, 112, 16; +L_0x8d322e3a0 .part L_0x8d322d4a0, 112, 16; +L_0x8d322a4e0 .arith/sum 40, L_0x8d3229b80, L_0x8d3229cc0; +L_0x8d322a580 .arith/sum 40, L_0x8d3229e00, L_0x8d3229f40; +L_0x8d322a620 .arith/sum 40, L_0x8d322a080, L_0x8d322a1c0; +L_0x8d322a6c0 .arith/sum 40, L_0x8d322a300, L_0x8d322a440; +L_0x8d322a760 .arith/sum 40, L_0x8d322a4e0, L_0x8d322a580; +L_0x8d322a800 .arith/sum 40, L_0x8d322a620, L_0x8d322a6c0; +L_0x8d322a8a0 .arith/sum 40, L_0x8d322a760, L_0x8d322a800; +L_0x8d322a940 .arith/sum 40, v0x8d2d0ba20_0, L_0x8d322a8a0; +S_0x8d3208d80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d3208c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306dec0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306df00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306df40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d070c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1f7a0; 1 drivers +v0x8d2d07160_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1f840; 1 drivers +v0x8d2d07200_0 .net *"_ivl_7", 0 0, L_0x8d322d540; 1 drivers +v0x8d2d072a0_0 .net *"_ivl_9", 7 0, L_0x8d2d1f980; 1 drivers +L_0x8d28556d8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d07340_0 .net/s "acc_in", 39 0, L_0x8d28556d8; 1 drivers +v0x8d2d073e0_0 .net/s "acc_out", 39 0, L_0x8d3229b80; alias, 1 drivers +v0x8d2d07480_0 .net/s "product", 31 0, L_0x8d2d1f8e0; 1 drivers +v0x8d2d07520_0 .net/s "product_ext", 39 0, L_0x8d3229ae0; 1 drivers +v0x8d2d075c0_0 .net/s "w", 15 0, L_0x8d322d680; 1 drivers +v0x8d2d07660_0 .net/s "x", 15 0, L_0x8d322d5e0; 1 drivers +L_0x8d2d1f7a0 .extend/s 32, L_0x8d322d5e0; +L_0x8d2d1f840 .extend/s 32, L_0x8d322d680; +L_0x8d2d1f8e0 .arith/mult 32, L_0x8d2d1f7a0, L_0x8d2d1f840; +L_0x8d322d540 .part L_0x8d2d1f8e0, 31, 1; +L_0x8d2d1f980 .repeat 8, 8, L_0x8d322d540; +L_0x8d3229ae0 .concat [ 32 8 0 0], L_0x8d2d1f8e0, L_0x8d2d1f980; +L_0x8d3229b80 .arith/sum 40, L_0x8d28556d8, L_0x8d3229ae0; +S_0x8d3208f00 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d3208c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306df80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306dfc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e000 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d07700_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1fa20; 1 drivers +v0x8d2d077a0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1fac0; 1 drivers +v0x8d2d07840_0 .net *"_ivl_7", 0 0, L_0x8d322d720; 1 drivers +v0x8d2d078e0_0 .net *"_ivl_9", 7 0, L_0x8d2d1fc00; 1 drivers +L_0x8d2855720 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d07980_0 .net/s "acc_in", 39 0, L_0x8d2855720; 1 drivers +v0x8d2d07a20_0 .net/s "acc_out", 39 0, L_0x8d3229cc0; alias, 1 drivers +v0x8d2d07ac0_0 .net/s "product", 31 0, L_0x8d2d1fb60; 1 drivers +v0x8d2d07b60_0 .net/s "product_ext", 39 0, L_0x8d3229c20; 1 drivers +v0x8d2d07c00_0 .net/s "w", 15 0, L_0x8d322d860; 1 drivers +v0x8d2d07ca0_0 .net/s "x", 15 0, L_0x8d322d7c0; 1 drivers +L_0x8d2d1fa20 .extend/s 32, L_0x8d322d7c0; +L_0x8d2d1fac0 .extend/s 32, L_0x8d322d860; +L_0x8d2d1fb60 .arith/mult 32, L_0x8d2d1fa20, L_0x8d2d1fac0; +L_0x8d322d720 .part L_0x8d2d1fb60, 31, 1; +L_0x8d2d1fc00 .repeat 8, 8, L_0x8d322d720; +L_0x8d3229c20 .concat [ 32 8 0 0], L_0x8d2d1fb60, L_0x8d2d1fc00; +L_0x8d3229cc0 .arith/sum 40, L_0x8d2855720, L_0x8d3229c20; +S_0x8d3209080 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d3208c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e040 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e080 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e0c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d07d40_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1fca0; 1 drivers +v0x8d2d07de0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d1fd40; 1 drivers +v0x8d2d07e80_0 .net *"_ivl_7", 0 0, L_0x8d322d900; 1 drivers +v0x8d2d07f20_0 .net *"_ivl_9", 7 0, L_0x8d2d1fe80; 1 drivers +L_0x8d2855768 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d08000_0 .net/s "acc_in", 39 0, L_0x8d2855768; 1 drivers +v0x8d2d080a0_0 .net/s "acc_out", 39 0, L_0x8d3229e00; alias, 1 drivers +v0x8d2d08140_0 .net/s "product", 31 0, L_0x8d2d1fde0; 1 drivers +v0x8d2d081e0_0 .net/s "product_ext", 39 0, L_0x8d3229d60; 1 drivers +v0x8d2d08280_0 .net/s "w", 15 0, L_0x8d322da40; 1 drivers +v0x8d2d08320_0 .net/s "x", 15 0, L_0x8d322d9a0; 1 drivers +L_0x8d2d1fca0 .extend/s 32, L_0x8d322d9a0; +L_0x8d2d1fd40 .extend/s 32, L_0x8d322da40; +L_0x8d2d1fde0 .arith/mult 32, L_0x8d2d1fca0, L_0x8d2d1fd40; +L_0x8d322d900 .part L_0x8d2d1fde0, 31, 1; +L_0x8d2d1fe80 .repeat 8, 8, L_0x8d322d900; +L_0x8d3229d60 .concat [ 32 8 0 0], L_0x8d2d1fde0, L_0x8d2d1fe80; +L_0x8d3229e00 .arith/sum 40, L_0x8d2855768, L_0x8d3229d60; +S_0x8d3209200 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d3208c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e100 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e140 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e180 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d083c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d1ff20; 1 drivers +v0x8d2d08460_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20000; 1 drivers +v0x8d2d08500_0 .net *"_ivl_7", 0 0, L_0x8d322dae0; 1 drivers +v0x8d2d085a0_0 .net *"_ivl_9", 7 0, L_0x8d2d20140; 1 drivers +L_0x8d28557b0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d08640_0 .net/s "acc_in", 39 0, L_0x8d28557b0; 1 drivers +v0x8d2d086e0_0 .net/s "acc_out", 39 0, L_0x8d3229f40; alias, 1 drivers +v0x8d2d08780_0 .net/s "product", 31 0, L_0x8d2d200a0; 1 drivers +v0x8d2d08820_0 .net/s "product_ext", 39 0, L_0x8d3229ea0; 1 drivers +v0x8d2d088c0_0 .net/s "w", 15 0, L_0x8d322dc20; 1 drivers +v0x8d2d08960_0 .net/s "x", 15 0, L_0x8d322db80; 1 drivers +L_0x8d2d1ff20 .extend/s 32, L_0x8d322db80; +L_0x8d2d20000 .extend/s 32, L_0x8d322dc20; +L_0x8d2d200a0 .arith/mult 32, L_0x8d2d1ff20, L_0x8d2d20000; +L_0x8d322dae0 .part L_0x8d2d200a0, 31, 1; +L_0x8d2d20140 .repeat 8, 8, L_0x8d322dae0; +L_0x8d3229ea0 .concat [ 32 8 0 0], L_0x8d2d200a0, L_0x8d2d20140; +L_0x8d3229f40 .arith/sum 40, L_0x8d28557b0, L_0x8d3229ea0; +S_0x8d3209380 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d3208c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e1c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e200 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e240 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d08a00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d201e0; 1 drivers +v0x8d2d08aa0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20280; 1 drivers +v0x8d2d08b40_0 .net *"_ivl_7", 0 0, L_0x8d322dcc0; 1 drivers +v0x8d2d08be0_0 .net *"_ivl_9", 7 0, L_0x8d2d203c0; 1 drivers +L_0x8d28557f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d08c80_0 .net/s "acc_in", 39 0, L_0x8d28557f8; 1 drivers +v0x8d2d08d20_0 .net/s "acc_out", 39 0, L_0x8d322a080; alias, 1 drivers +v0x8d2d08dc0_0 .net/s "product", 31 0, L_0x8d2d20320; 1 drivers +v0x8d2d08e60_0 .net/s "product_ext", 39 0, L_0x8d3229fe0; 1 drivers +v0x8d2d08f00_0 .net/s "w", 15 0, L_0x8d322de00; 1 drivers +v0x8d2d08fa0_0 .net/s "x", 15 0, L_0x8d322dd60; 1 drivers +L_0x8d2d201e0 .extend/s 32, L_0x8d322dd60; +L_0x8d2d20280 .extend/s 32, L_0x8d322de00; +L_0x8d2d20320 .arith/mult 32, L_0x8d2d201e0, L_0x8d2d20280; +L_0x8d322dcc0 .part L_0x8d2d20320, 31, 1; +L_0x8d2d203c0 .repeat 8, 8, L_0x8d322dcc0; +L_0x8d3229fe0 .concat [ 32 8 0 0], L_0x8d2d20320, L_0x8d2d203c0; +L_0x8d322a080 .arith/sum 40, L_0x8d28557f8, L_0x8d3229fe0; +S_0x8d3209500 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d3208c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e280 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e2c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e300 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d09040_0 .net/s *"_ivl_0", 31 0, L_0x8d2d20460; 1 drivers +v0x8d2d090e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20500; 1 drivers +v0x8d2d09180_0 .net *"_ivl_7", 0 0, L_0x8d322dea0; 1 drivers +v0x8d2d09220_0 .net *"_ivl_9", 7 0, L_0x8d2d20640; 1 drivers +L_0x8d2855840 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d092c0_0 .net/s "acc_in", 39 0, L_0x8d2855840; 1 drivers +v0x8d2d09360_0 .net/s "acc_out", 39 0, L_0x8d322a1c0; alias, 1 drivers +v0x8d2d09400_0 .net/s "product", 31 0, L_0x8d2d205a0; 1 drivers +v0x8d2d094a0_0 .net/s "product_ext", 39 0, L_0x8d322a120; 1 drivers +v0x8d2d09540_0 .net/s "w", 15 0, L_0x8d322dfe0; 1 drivers +v0x8d2d095e0_0 .net/s "x", 15 0, L_0x8d322df40; 1 drivers +L_0x8d2d20460 .extend/s 32, L_0x8d322df40; +L_0x8d2d20500 .extend/s 32, L_0x8d322dfe0; +L_0x8d2d205a0 .arith/mult 32, L_0x8d2d20460, L_0x8d2d20500; +L_0x8d322dea0 .part L_0x8d2d205a0, 31, 1; +L_0x8d2d20640 .repeat 8, 8, L_0x8d322dea0; +L_0x8d322a120 .concat [ 32 8 0 0], L_0x8d2d205a0, L_0x8d2d20640; +L_0x8d322a1c0 .arith/sum 40, L_0x8d2855840, L_0x8d322a120; +S_0x8d3209680 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d3208c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e340 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e380 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e3c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d09680_0 .net/s *"_ivl_0", 31 0, L_0x8d2d206e0; 1 drivers +v0x8d2d09720_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20780; 1 drivers +v0x8d2d097c0_0 .net *"_ivl_7", 0 0, L_0x8d322e080; 1 drivers +v0x8d2d09860_0 .net *"_ivl_9", 7 0, L_0x8d2d208c0; 1 drivers +L_0x8d2855888 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d09900_0 .net/s "acc_in", 39 0, L_0x8d2855888; 1 drivers +v0x8d2d099a0_0 .net/s "acc_out", 39 0, L_0x8d322a300; alias, 1 drivers +v0x8d2d09a40_0 .net/s "product", 31 0, L_0x8d2d20820; 1 drivers +v0x8d2d09ae0_0 .net/s "product_ext", 39 0, L_0x8d322a260; 1 drivers +v0x8d2d09b80_0 .net/s "w", 15 0, L_0x8d322e1c0; 1 drivers +v0x8d2d09c20_0 .net/s "x", 15 0, L_0x8d322e120; 1 drivers +L_0x8d2d206e0 .extend/s 32, L_0x8d322e120; +L_0x8d2d20780 .extend/s 32, L_0x8d322e1c0; +L_0x8d2d20820 .arith/mult 32, L_0x8d2d206e0, L_0x8d2d20780; +L_0x8d322e080 .part L_0x8d2d20820, 31, 1; +L_0x8d2d208c0 .repeat 8, 8, L_0x8d322e080; +L_0x8d322a260 .concat [ 32 8 0 0], L_0x8d2d20820, L_0x8d2d208c0; +L_0x8d322a300 .arith/sum 40, L_0x8d2855888, L_0x8d322a260; +S_0x8d3209800 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d3208c00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e400 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e440 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e480 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d09cc0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d20960; 1 drivers +v0x8d2d09d60_0 .net/s *"_ivl_2", 31 0, L_0x8d2d20a00; 1 drivers +v0x8d2d09e00_0 .net *"_ivl_7", 0 0, L_0x8d322e260; 1 drivers +v0x8d2d09ea0_0 .net *"_ivl_9", 7 0, L_0x8d2d20b40; 1 drivers +L_0x8d28558d0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d09f40_0 .net/s "acc_in", 39 0, L_0x8d28558d0; 1 drivers +v0x8d2d09fe0_0 .net/s "acc_out", 39 0, L_0x8d322a440; alias, 1 drivers +v0x8d2d0a080_0 .net/s "product", 31 0, L_0x8d2d20aa0; 1 drivers +v0x8d2d0a120_0 .net/s "product_ext", 39 0, L_0x8d322a3a0; 1 drivers +v0x8d2d0a1c0_0 .net/s "w", 15 0, L_0x8d322e3a0; 1 drivers +v0x8d2d0a260_0 .net/s "x", 15 0, L_0x8d322e300; 1 drivers +L_0x8d2d20960 .extend/s 32, L_0x8d322e300; +L_0x8d2d20a00 .extend/s 32, L_0x8d322e3a0; +L_0x8d2d20aa0 .arith/mult 32, L_0x8d2d20960, L_0x8d2d20a00; +L_0x8d322e260 .part L_0x8d2d20aa0, 31, 1; +L_0x8d2d20b40 .repeat 8, 8, L_0x8d322e260; +L_0x8d322a3a0 .concat [ 32 8 0 0], L_0x8d2d20aa0, L_0x8d2d20b40; +L_0x8d322a440 .arith/sum 40, L_0x8d28558d0, L_0x8d322a3a0; +S_0x8d3209980 .scope generate, "GEN_NEURON[6]" "GEN_NEURON[6]" 4 35, 4 35 0, S_0x102e5b4b0; + .timescale 0 0; +P_0x8d2c3b240 .param/l "n" 1 4 35, +C4<0110>; +S_0x8d3209b00 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d3209980; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e673b0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x102e673f0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x102e67430 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x102e67470 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; +P_0x102e674b0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; +P_0x102e674f0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; +P_0x102e67530 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x8d307c3f0 .functor BUFZ 16, L_0x8d322fa20, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8d2d103c0_0 .net *"_ivl_0", 31 0, L_0x8d322abc0; 1 drivers +v0x8d2d10460_0 .net *"_ivl_11", 31 0, L_0x8d2d20dc0; 1 drivers +v0x8d2d10500_0 .net *"_ivl_14", 31 0, L_0x8d322ac60; 1 drivers +L_0x8d2855a38 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d105a0_0 .net *"_ivl_17", 28 0, L_0x8d2855a38; 1 drivers +L_0x8d2855a80 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d10640_0 .net/2u *"_ivl_18", 31 0, L_0x8d2855a80; 1 drivers +v0x8d2d106e0_0 .net *"_ivl_21", 31 0, L_0x8d2d20e60; 1 drivers +L_0x8d2855ac8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d10780_0 .net/2u *"_ivl_22", 31 0, L_0x8d2855ac8; 1 drivers +v0x8d2d10820_0 .net *"_ivl_25", 31 0, L_0x8d2d20f00; 1 drivers +L_0x8d2855960 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d108c0_0 .net *"_ivl_3", 28 0, L_0x8d2855960; 1 drivers +v0x8d2d10960_0 .net *"_ivl_31", 0 0, L_0x8d322f7a0; 1 drivers +v0x8d2d10a00_0 .net *"_ivl_33", 23 0, L_0x8d2d223a0; 1 drivers +v0x8d2d10aa0_0 .net *"_ivl_36", 39 0, L_0x8d322bca0; 1 drivers +v0x8d2d10b40_0 .net *"_ivl_38", 31 0, L_0x8d322f840; 1 drivers +L_0x8d28559a8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d10be0_0 .net/2u *"_ivl_4", 31 0, L_0x8d28559a8; 1 drivers +L_0x8d2855d50 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d10c80_0 .net *"_ivl_40", 7 0, L_0x8d2855d50; 1 drivers +v0x8d2d10d20_0 .net *"_ivl_46", 31 0, L_0x8d322f8e0; 1 drivers +v0x8d2d10dc0_0 .net *"_ivl_7", 31 0, L_0x8d2d20d20; 1 drivers +L_0x8d28559f0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d10e60_0 .net/2u *"_ivl_8", 31 0, L_0x8d28559f0; 1 drivers +v0x8d2d10f00_0 .var/s "acc", 39 0; +v0x8d2d10fa0_0 .net/s "acc_next", 39 0, L_0x8d322bb60; 1 drivers +v0x8d2d11040_0 .net/s "bias", 15 0, L_0x8d322fa20; 1 drivers +v0x8d2d110e0_0 .net/s "bias_ext", 39 0, L_0x8d322bc00; 1 drivers +v0x8d2d11180_0 .net/s "bias_ext_small", 15 0, L_0x8d307c3f0; 1 drivers +v0x8d2d11220_0 .var "busy", 0 0; +v0x8d2d112c0_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers +v0x8d2d11360_0 .var "done", 0 0; +v0x8d2d11400_0 .net/s "final_acc", 39 0, L_0x8d322bd40; 1 drivers +v0x8d2d114a0_0 .net/s "final_value", 39 0, L_0x8d2d22440; 1 drivers +v0x8d2d11540_0 .var "group_index", 2 0; +v0x8d2d115e0_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers +v0x8d2d11680_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers +v0x8d2d11720_0 .net/s "w_bus", 1023 0, L_0x8d322f980; 1 drivers +v0x8d2d117c0_0 .net/s "w_group", 127 0, L_0x8d322e800; 1 drivers +v0x8d2d11860_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers +v0x8d2d11900_0 .net/s "x_group", 127 0, L_0x8d322e760; 1 drivers +v0x8d2d119a0_0 .var/s "y", 15 0; +L_0x8d322abc0 .concat [ 3 29 0 0], v0x8d2d11540_0, L_0x8d2855960; +L_0x8d2d20d20 .arith/mult 32, L_0x8d322abc0, L_0x8d28559a8; +L_0x8d2d20dc0 .arith/mult 32, L_0x8d2d20d20, L_0x8d28559f0; +L_0x8d322e760 .part/v v0x8d2d17ca0_0, L_0x8d2d20dc0, 128; +L_0x8d322ac60 .concat [ 3 29 0 0], v0x8d2d11540_0, L_0x8d2855a38; +L_0x8d2d20e60 .arith/mult 32, L_0x8d322ac60, L_0x8d2855a80; +L_0x8d2d20f00 .arith/mult 32, L_0x8d2d20e60, L_0x8d2855ac8; +L_0x8d322e800 .part/v L_0x8d322f980, L_0x8d2d20f00, 128; +L_0x8d322f7a0 .part L_0x8d307c3f0, 15, 1; +L_0x8d2d223a0 .repeat 24, 24, L_0x8d322f7a0; +L_0x8d322bc00 .concat [ 16 24 0 0], L_0x8d307c3f0, L_0x8d2d223a0; +L_0x8d322f840 .part L_0x8d322bc00, 0, 32; +L_0x8d322bca0 .concat [ 8 32 0 0], L_0x8d2855d50, L_0x8d322f840; +L_0x8d322bd40 .arith/sum 40, L_0x8d322bb60, L_0x8d322bca0; +L_0x8d322f8e0 .part L_0x8d322bd40, 8, 32; +L_0x8d2d22440 .extend/s 40, L_0x8d322f8e0; +S_0x8d3209c80 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d3209b00; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d30a0900 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8d30a0940 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8d2d0f7a0_0 .net/s "acc_in", 39 0, v0x8d2d10f00_0; 1 drivers +v0x8d2d0f840_0 .net/s "acc_out", 39 0, L_0x8d322bb60; alias, 1 drivers +v0x8d2d0f8e0_0 .net/s "m0", 39 0, L_0x8d322ada0; 1 drivers +v0x8d2d0f980_0 .net/s "m1", 39 0, L_0x8d322aee0; 1 drivers +v0x8d2d0fa20_0 .net/s "m2", 39 0, L_0x8d322b020; 1 drivers +v0x8d2d0fac0_0 .net/s "m3", 39 0, L_0x8d322b160; 1 drivers +v0x8d2d0fb60_0 .net/s "m4", 39 0, L_0x8d322b2a0; 1 drivers +v0x8d2d0fc00_0 .net/s "m5", 39 0, L_0x8d322b3e0; 1 drivers +v0x8d2d0fca0_0 .net/s "m6", 39 0, L_0x8d322b520; 1 drivers +v0x8d2d0fd40_0 .net/s "m7", 39 0, L_0x8d322b660; 1 drivers +v0x8d2d0fde0_0 .net/s "s0", 39 0, L_0x8d322b700; 1 drivers +v0x8d2d0fe80_0 .net/s "s1", 39 0, L_0x8d322b7a0; 1 drivers +v0x8d2d0ff20_0 .net/s "s2", 39 0, L_0x8d322b840; 1 drivers +v0x8d2d10000_0 .net/s "s3", 39 0, L_0x8d322b8e0; 1 drivers +v0x8d2d100a0_0 .net/s "s4", 39 0, L_0x8d322b980; 1 drivers +v0x8d2d10140_0 .net/s "s5", 39 0, L_0x8d322ba20; 1 drivers +v0x8d2d101e0_0 .net/s "sum", 39 0, L_0x8d322bac0; 1 drivers +v0x8d2d10280_0 .net/s "w_bus", 127 0, L_0x8d322e800; alias, 1 drivers +v0x8d2d10320_0 .net/s "x_bus", 127 0, L_0x8d322e760; alias, 1 drivers +L_0x8d322e940 .part L_0x8d322e760, 0, 16; +L_0x8d322e9e0 .part L_0x8d322e800, 0, 16; +L_0x8d322eb20 .part L_0x8d322e760, 16, 16; +L_0x8d322ebc0 .part L_0x8d322e800, 16, 16; +L_0x8d322ed00 .part L_0x8d322e760, 32, 16; +L_0x8d322eda0 .part L_0x8d322e800, 32, 16; +L_0x8d322eee0 .part L_0x8d322e760, 48, 16; +L_0x8d322ef80 .part L_0x8d322e800, 48, 16; +L_0x8d322f0c0 .part L_0x8d322e760, 64, 16; +L_0x8d322f160 .part L_0x8d322e800, 64, 16; +L_0x8d322f2a0 .part L_0x8d322e760, 80, 16; +L_0x8d322f340 .part L_0x8d322e800, 80, 16; +L_0x8d322f480 .part L_0x8d322e760, 96, 16; +L_0x8d322f520 .part L_0x8d322e800, 96, 16; +L_0x8d322f660 .part L_0x8d322e760, 112, 16; +L_0x8d322f700 .part L_0x8d322e800, 112, 16; +L_0x8d322b700 .arith/sum 40, L_0x8d322ada0, L_0x8d322aee0; +L_0x8d322b7a0 .arith/sum 40, L_0x8d322b020, L_0x8d322b160; +L_0x8d322b840 .arith/sum 40, L_0x8d322b2a0, L_0x8d322b3e0; +L_0x8d322b8e0 .arith/sum 40, L_0x8d322b520, L_0x8d322b660; +L_0x8d322b980 .arith/sum 40, L_0x8d322b700, L_0x8d322b7a0; +L_0x8d322ba20 .arith/sum 40, L_0x8d322b840, L_0x8d322b8e0; +L_0x8d322bac0 .arith/sum 40, L_0x8d322b980, L_0x8d322ba20; +L_0x8d322bb60 .arith/sum 40, v0x8d2d10f00_0, L_0x8d322bac0; +S_0x8d3209e00 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d3209c80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e4c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e500 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e540 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d0c5a0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d20fa0; 1 drivers +v0x8d2d0c640_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21040; 1 drivers +v0x8d2d0c6e0_0 .net *"_ivl_7", 0 0, L_0x8d322e8a0; 1 drivers +v0x8d2d0c780_0 .net *"_ivl_9", 7 0, L_0x8d2d21180; 1 drivers +L_0x8d2855b10 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0c820_0 .net/s "acc_in", 39 0, L_0x8d2855b10; 1 drivers +v0x8d2d0c8c0_0 .net/s "acc_out", 39 0, L_0x8d322ada0; alias, 1 drivers +v0x8d2d0c960_0 .net/s "product", 31 0, L_0x8d2d210e0; 1 drivers +v0x8d2d0ca00_0 .net/s "product_ext", 39 0, L_0x8d322ad00; 1 drivers +v0x8d2d0caa0_0 .net/s "w", 15 0, L_0x8d322e9e0; 1 drivers +v0x8d2d0cb40_0 .net/s "x", 15 0, L_0x8d322e940; 1 drivers +L_0x8d2d20fa0 .extend/s 32, L_0x8d322e940; +L_0x8d2d21040 .extend/s 32, L_0x8d322e9e0; +L_0x8d2d210e0 .arith/mult 32, L_0x8d2d20fa0, L_0x8d2d21040; +L_0x8d322e8a0 .part L_0x8d2d210e0, 31, 1; +L_0x8d2d21180 .repeat 8, 8, L_0x8d322e8a0; +L_0x8d322ad00 .concat [ 32 8 0 0], L_0x8d2d210e0, L_0x8d2d21180; +L_0x8d322ada0 .arith/sum 40, L_0x8d2855b10, L_0x8d322ad00; +S_0x8d3209f80 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d3209c80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e580 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e5c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e600 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d0cbe0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d21220; 1 drivers +v0x8d2d0cc80_0 .net/s *"_ivl_2", 31 0, L_0x8d2d212c0; 1 drivers +v0x8d2d0cd20_0 .net *"_ivl_7", 0 0, L_0x8d322ea80; 1 drivers +v0x8d2d0cdc0_0 .net *"_ivl_9", 7 0, L_0x8d2d21400; 1 drivers +L_0x8d2855b58 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0ce60_0 .net/s "acc_in", 39 0, L_0x8d2855b58; 1 drivers +v0x8d2d0cf00_0 .net/s "acc_out", 39 0, L_0x8d322aee0; alias, 1 drivers +v0x8d2d0cfa0_0 .net/s "product", 31 0, L_0x8d2d21360; 1 drivers +v0x8d2d0d040_0 .net/s "product_ext", 39 0, L_0x8d322ae40; 1 drivers +v0x8d2d0d0e0_0 .net/s "w", 15 0, L_0x8d322ebc0; 1 drivers +v0x8d2d0d180_0 .net/s "x", 15 0, L_0x8d322eb20; 1 drivers +L_0x8d2d21220 .extend/s 32, L_0x8d322eb20; +L_0x8d2d212c0 .extend/s 32, L_0x8d322ebc0; +L_0x8d2d21360 .arith/mult 32, L_0x8d2d21220, L_0x8d2d212c0; +L_0x8d322ea80 .part L_0x8d2d21360, 31, 1; +L_0x8d2d21400 .repeat 8, 8, L_0x8d322ea80; +L_0x8d322ae40 .concat [ 32 8 0 0], L_0x8d2d21360, L_0x8d2d21400; +L_0x8d322aee0 .arith/sum 40, L_0x8d2855b58, L_0x8d322ae40; +S_0x8d320a100 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d3209c80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e640 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e680 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e6c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d0d220_0 .net/s *"_ivl_0", 31 0, L_0x8d2d214a0; 1 drivers +v0x8d2d0d2c0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21540; 1 drivers +v0x8d2d0d360_0 .net *"_ivl_7", 0 0, L_0x8d322ec60; 1 drivers +v0x8d2d0d400_0 .net *"_ivl_9", 7 0, L_0x8d2d21680; 1 drivers +L_0x8d2855ba0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0d4a0_0 .net/s "acc_in", 39 0, L_0x8d2855ba0; 1 drivers +v0x8d2d0d540_0 .net/s "acc_out", 39 0, L_0x8d322b020; alias, 1 drivers +v0x8d2d0d5e0_0 .net/s "product", 31 0, L_0x8d2d215e0; 1 drivers +v0x8d2d0d680_0 .net/s "product_ext", 39 0, L_0x8d322af80; 1 drivers +v0x8d2d0d720_0 .net/s "w", 15 0, L_0x8d322eda0; 1 drivers +v0x8d2d0d7c0_0 .net/s "x", 15 0, L_0x8d322ed00; 1 drivers +L_0x8d2d214a0 .extend/s 32, L_0x8d322ed00; +L_0x8d2d21540 .extend/s 32, L_0x8d322eda0; +L_0x8d2d215e0 .arith/mult 32, L_0x8d2d214a0, L_0x8d2d21540; +L_0x8d322ec60 .part L_0x8d2d215e0, 31, 1; +L_0x8d2d21680 .repeat 8, 8, L_0x8d322ec60; +L_0x8d322af80 .concat [ 32 8 0 0], L_0x8d2d215e0, L_0x8d2d21680; +L_0x8d322b020 .arith/sum 40, L_0x8d2855ba0, L_0x8d322af80; +S_0x8d320a280 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d3209c80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e700 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e740 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e780 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d0d860_0 .net/s *"_ivl_0", 31 0, L_0x8d2d21720; 1 drivers +v0x8d2d0d900_0 .net/s *"_ivl_2", 31 0, L_0x8d2d217c0; 1 drivers +v0x8d2d0d9a0_0 .net *"_ivl_7", 0 0, L_0x8d322ee40; 1 drivers +v0x8d2d0da40_0 .net *"_ivl_9", 7 0, L_0x8d2d21900; 1 drivers +L_0x8d2855be8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0dae0_0 .net/s "acc_in", 39 0, L_0x8d2855be8; 1 drivers +v0x8d2d0db80_0 .net/s "acc_out", 39 0, L_0x8d322b160; alias, 1 drivers +v0x8d2d0dc20_0 .net/s "product", 31 0, L_0x8d2d21860; 1 drivers +v0x8d2d0dcc0_0 .net/s "product_ext", 39 0, L_0x8d322b0c0; 1 drivers +v0x8d2d0dd60_0 .net/s "w", 15 0, L_0x8d322ef80; 1 drivers +v0x8d2d0de00_0 .net/s "x", 15 0, L_0x8d322eee0; 1 drivers +L_0x8d2d21720 .extend/s 32, L_0x8d322eee0; +L_0x8d2d217c0 .extend/s 32, L_0x8d322ef80; +L_0x8d2d21860 .arith/mult 32, L_0x8d2d21720, L_0x8d2d217c0; +L_0x8d322ee40 .part L_0x8d2d21860, 31, 1; +L_0x8d2d21900 .repeat 8, 8, L_0x8d322ee40; +L_0x8d322b0c0 .concat [ 32 8 0 0], L_0x8d2d21860, L_0x8d2d21900; +L_0x8d322b160 .arith/sum 40, L_0x8d2855be8, L_0x8d322b0c0; +S_0x8d320a400 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d3209c80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e7c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e800 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e840 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d0dea0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d219a0; 1 drivers +v0x8d2d0df40_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21a40; 1 drivers +v0x8d2d0dfe0_0 .net *"_ivl_7", 0 0, L_0x8d322f020; 1 drivers +v0x8d2d0e080_0 .net *"_ivl_9", 7 0, L_0x8d2d21b80; 1 drivers +L_0x8d2855c30 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0e120_0 .net/s "acc_in", 39 0, L_0x8d2855c30; 1 drivers +v0x8d2d0e1c0_0 .net/s "acc_out", 39 0, L_0x8d322b2a0; alias, 1 drivers +v0x8d2d0e260_0 .net/s "product", 31 0, L_0x8d2d21ae0; 1 drivers +v0x8d2d0e300_0 .net/s "product_ext", 39 0, L_0x8d322b200; 1 drivers +v0x8d2d0e3a0_0 .net/s "w", 15 0, L_0x8d322f160; 1 drivers +v0x8d2d0e440_0 .net/s "x", 15 0, L_0x8d322f0c0; 1 drivers +L_0x8d2d219a0 .extend/s 32, L_0x8d322f0c0; +L_0x8d2d21a40 .extend/s 32, L_0x8d322f160; +L_0x8d2d21ae0 .arith/mult 32, L_0x8d2d219a0, L_0x8d2d21a40; +L_0x8d322f020 .part L_0x8d2d21ae0, 31, 1; +L_0x8d2d21b80 .repeat 8, 8, L_0x8d322f020; +L_0x8d322b200 .concat [ 32 8 0 0], L_0x8d2d21ae0, L_0x8d2d21b80; +L_0x8d322b2a0 .arith/sum 40, L_0x8d2855c30, L_0x8d322b200; +S_0x8d320a580 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d3209c80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e880 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e8c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e900 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d0e4e0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d21c20; 1 drivers +v0x8d2d0e580_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21cc0; 1 drivers +v0x8d2d0e620_0 .net *"_ivl_7", 0 0, L_0x8d322f200; 1 drivers +v0x8d2d0e6c0_0 .net *"_ivl_9", 7 0, L_0x8d2d21e00; 1 drivers +L_0x8d2855c78 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0e760_0 .net/s "acc_in", 39 0, L_0x8d2855c78; 1 drivers +v0x8d2d0e800_0 .net/s "acc_out", 39 0, L_0x8d322b3e0; alias, 1 drivers +v0x8d2d0e8a0_0 .net/s "product", 31 0, L_0x8d2d21d60; 1 drivers +v0x8d2d0e940_0 .net/s "product_ext", 39 0, L_0x8d322b340; 1 drivers +v0x8d2d0e9e0_0 .net/s "w", 15 0, L_0x8d322f340; 1 drivers +v0x8d2d0ea80_0 .net/s "x", 15 0, L_0x8d322f2a0; 1 drivers +L_0x8d2d21c20 .extend/s 32, L_0x8d322f2a0; +L_0x8d2d21cc0 .extend/s 32, L_0x8d322f340; +L_0x8d2d21d60 .arith/mult 32, L_0x8d2d21c20, L_0x8d2d21cc0; +L_0x8d322f200 .part L_0x8d2d21d60, 31, 1; +L_0x8d2d21e00 .repeat 8, 8, L_0x8d322f200; +L_0x8d322b340 .concat [ 32 8 0 0], L_0x8d2d21d60, L_0x8d2d21e00; +L_0x8d322b3e0 .arith/sum 40, L_0x8d2855c78, L_0x8d322b340; +S_0x8d320a700 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d3209c80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306e940 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306e980 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306e9c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d0eb20_0 .net/s *"_ivl_0", 31 0, L_0x8d2d21ea0; 1 drivers +v0x8d2d0ebc0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d21f40; 1 drivers +v0x8d2d0ec60_0 .net *"_ivl_7", 0 0, L_0x8d322f3e0; 1 drivers +v0x8d2d0ed00_0 .net *"_ivl_9", 7 0, L_0x8d2d22080; 1 drivers +L_0x8d2855cc0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0eda0_0 .net/s "acc_in", 39 0, L_0x8d2855cc0; 1 drivers +v0x8d2d0ee40_0 .net/s "acc_out", 39 0, L_0x8d322b520; alias, 1 drivers +v0x8d2d0eee0_0 .net/s "product", 31 0, L_0x8d2d21fe0; 1 drivers +v0x8d2d0ef80_0 .net/s "product_ext", 39 0, L_0x8d322b480; 1 drivers +v0x8d2d0f020_0 .net/s "w", 15 0, L_0x8d322f520; 1 drivers +v0x8d2d0f0c0_0 .net/s "x", 15 0, L_0x8d322f480; 1 drivers +L_0x8d2d21ea0 .extend/s 32, L_0x8d322f480; +L_0x8d2d21f40 .extend/s 32, L_0x8d322f520; +L_0x8d2d21fe0 .arith/mult 32, L_0x8d2d21ea0, L_0x8d2d21f40; +L_0x8d322f3e0 .part L_0x8d2d21fe0, 31, 1; +L_0x8d2d22080 .repeat 8, 8, L_0x8d322f3e0; +L_0x8d322b480 .concat [ 32 8 0 0], L_0x8d2d21fe0, L_0x8d2d22080; +L_0x8d322b520 .arith/sum 40, L_0x8d2855cc0, L_0x8d322b480; +S_0x8d320a880 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d3209c80; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306ea00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306ea40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ea80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d0f160_0 .net/s *"_ivl_0", 31 0, L_0x8d2d22120; 1 drivers +v0x8d2d0f200_0 .net/s *"_ivl_2", 31 0, L_0x8d2d221c0; 1 drivers +v0x8d2d0f2a0_0 .net *"_ivl_7", 0 0, L_0x8d322f5c0; 1 drivers +v0x8d2d0f340_0 .net *"_ivl_9", 7 0, L_0x8d2d22300; 1 drivers +L_0x8d2855d08 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d0f3e0_0 .net/s "acc_in", 39 0, L_0x8d2855d08; 1 drivers +v0x8d2d0f480_0 .net/s "acc_out", 39 0, L_0x8d322b660; alias, 1 drivers +v0x8d2d0f520_0 .net/s "product", 31 0, L_0x8d2d22260; 1 drivers +v0x8d2d0f5c0_0 .net/s "product_ext", 39 0, L_0x8d322b5c0; 1 drivers +v0x8d2d0f660_0 .net/s "w", 15 0, L_0x8d322f700; 1 drivers +v0x8d2d0f700_0 .net/s "x", 15 0, L_0x8d322f660; 1 drivers +L_0x8d2d22120 .extend/s 32, L_0x8d322f660; +L_0x8d2d221c0 .extend/s 32, L_0x8d322f700; +L_0x8d2d22260 .arith/mult 32, L_0x8d2d22120, L_0x8d2d221c0; +L_0x8d322f5c0 .part L_0x8d2d22260, 31, 1; +L_0x8d2d22300 .repeat 8, 8, L_0x8d322f5c0; +L_0x8d322b5c0 .concat [ 32 8 0 0], L_0x8d2d22260, L_0x8d2d22300; +L_0x8d322b660 .arith/sum 40, L_0x8d2855d08, L_0x8d322b5c0; +S_0x8d320aa00 .scope generate, "GEN_NEURON[7]" "GEN_NEURON[7]" 4 35, 4 35 0, S_0x102e5b4b0; + .timescale 0 0; +P_0x8d2c3b280 .param/l "n" 1 4 35, +C4<0111>; +S_0x8d320ab80 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8d320aa00; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x102e67570 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x102e675b0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x102e675f0 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x102e67630 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000001000>; +P_0x102e67670 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000011>; +P_0x102e676b0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000001000000>; +P_0x102e676f0 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x8d307c460 .functor BUFZ 16, L_0x8d323cdc0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8d2d15860_0 .net *"_ivl_0", 31 0, L_0x8d322bde0; 1 drivers +v0x8d2d15900_0 .net *"_ivl_11", 31 0, L_0x8d2d22580; 1 drivers +v0x8d2d159a0_0 .net *"_ivl_14", 31 0, L_0x8d322be80; 1 drivers +L_0x8d2855e70 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d15a40_0 .net *"_ivl_17", 28 0, L_0x8d2855e70; 1 drivers +L_0x8d2855eb8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d15ae0_0 .net/2u *"_ivl_18", 31 0, L_0x8d2855eb8; 1 drivers +v0x8d2d15b80_0 .net *"_ivl_21", 31 0, L_0x8d2d22620; 1 drivers +L_0x8d2855f00 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d15c20_0 .net/2u *"_ivl_22", 31 0, L_0x8d2855f00; 1 drivers +v0x8d2d15cc0_0 .net *"_ivl_25", 31 0, L_0x8d2d226c0; 1 drivers +L_0x8d2855d98 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d15d60_0 .net *"_ivl_3", 28 0, L_0x8d2855d98; 1 drivers +v0x8d2d15e00_0 .net *"_ivl_31", 0 0, L_0x8d323cb40; 1 drivers +v0x8d2d15ea0_0 .net *"_ivl_33", 23 0, L_0x8d2d23b60; 1 drivers +v0x8d2d15f40_0 .net *"_ivl_36", 39 0, L_0x8d3238f00; 1 drivers +v0x8d2d15fe0_0 .net *"_ivl_38", 31 0, L_0x8d323cbe0; 1 drivers +L_0x8d2855de0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8d2d16080_0 .net/2u *"_ivl_4", 31 0, L_0x8d2855de0; 1 drivers +L_0x8d2856188 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d16120_0 .net *"_ivl_40", 7 0, L_0x8d2856188; 1 drivers +v0x8d2d161c0_0 .net *"_ivl_46", 31 0, L_0x8d323cc80; 1 drivers +v0x8d2d16260_0 .net *"_ivl_7", 31 0, L_0x8d2d224e0; 1 drivers +L_0x8d2855e28 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8d2d16300_0 .net/2u *"_ivl_8", 31 0, L_0x8d2855e28; 1 drivers +v0x8d2d163a0_0 .var/s "acc", 39 0; +v0x8d2d16440_0 .net/s "acc_next", 39 0, L_0x8d3238dc0; 1 drivers +v0x8d2d164e0_0 .net/s "bias", 15 0, L_0x8d323cdc0; 1 drivers +v0x8d2d16580_0 .net/s "bias_ext", 39 0, L_0x8d3238e60; 1 drivers +v0x8d2d16620_0 .net/s "bias_ext_small", 15 0, L_0x8d307c460; 1 drivers +v0x8d2d166c0_0 .var "busy", 0 0; +v0x8d2d16760_0 .net "clk", 0 0, v0x8d2d17840_0; alias, 1 drivers +v0x8d2d16800_0 .var "done", 0 0; +v0x8d2d168a0_0 .net/s "final_acc", 39 0, L_0x8d3238fa0; 1 drivers +v0x8d2d16940_0 .net/s "final_value", 39 0, L_0x8d2d23c00; 1 drivers +v0x8d2d169e0_0 .var "group_index", 2 0; +v0x8d2d16a80_0 .net "rst", 0 0, v0x8d2d17ac0_0; alias, 1 drivers +v0x8d2d16b20_0 .net "start", 0 0, v0x8d2d17b60_0; alias, 1 drivers +v0x8d2d16bc0_0 .net/s "w_bus", 1023 0, L_0x8d323cd20; 1 drivers +v0x8d2d16c60_0 .net/s "w_group", 127 0, L_0x8d322fb60; 1 drivers +v0x8d2d16d00_0 .net/s "x_bus", 1023 0, v0x8d2d17ca0_0; alias, 1 drivers +v0x8d2d16da0_0 .net/s "x_group", 127 0, L_0x8d322fac0; 1 drivers +v0x8d2d16e40_0 .var/s "y", 15 0; +L_0x8d322bde0 .concat [ 3 29 0 0], v0x8d2d169e0_0, L_0x8d2855d98; +L_0x8d2d224e0 .arith/mult 32, L_0x8d322bde0, L_0x8d2855de0; +L_0x8d2d22580 .arith/mult 32, L_0x8d2d224e0, L_0x8d2855e28; +L_0x8d322fac0 .part/v v0x8d2d17ca0_0, L_0x8d2d22580, 128; +L_0x8d322be80 .concat [ 3 29 0 0], v0x8d2d169e0_0, L_0x8d2855e70; +L_0x8d2d22620 .arith/mult 32, L_0x8d322be80, L_0x8d2855eb8; +L_0x8d2d226c0 .arith/mult 32, L_0x8d2d22620, L_0x8d2855f00; +L_0x8d322fb60 .part/v L_0x8d323cd20, L_0x8d2d226c0, 128; +L_0x8d323cb40 .part L_0x8d307c460, 15, 1; +L_0x8d2d23b60 .repeat 24, 24, L_0x8d323cb40; +L_0x8d3238e60 .concat [ 16 24 0 0], L_0x8d307c460, L_0x8d2d23b60; +L_0x8d323cbe0 .part L_0x8d3238e60, 0, 32; +L_0x8d3238f00 .concat [ 8 32 0 0], L_0x8d2856188, L_0x8d323cbe0; +L_0x8d3238fa0 .arith/sum 40, L_0x8d3238dc0, L_0x8d3238f00; +L_0x8d323cc80 .part L_0x8d3238fa0, 8, 32; +L_0x8d2d23c00 .extend/s 40, L_0x8d323cc80; +S_0x8d320ad00 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8d320ab80; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d30a0980 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8d30a09c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8d2d14c80_0 .net/s "acc_in", 39 0, v0x8d2d163a0_0; 1 drivers +v0x8d2d14d20_0 .net/s "acc_out", 39 0, L_0x8d3238dc0; alias, 1 drivers +v0x8d2d14dc0_0 .net/s "m0", 39 0, L_0x8d3238000; 1 drivers +v0x8d2d14e60_0 .net/s "m1", 39 0, L_0x8d3238140; 1 drivers +v0x8d2d14f00_0 .net/s "m2", 39 0, L_0x8d3238280; 1 drivers +v0x8d2d14fa0_0 .net/s "m3", 39 0, L_0x8d32383c0; 1 drivers +v0x8d2d15040_0 .net/s "m4", 39 0, L_0x8d3238500; 1 drivers +v0x8d2d150e0_0 .net/s "m5", 39 0, L_0x8d3238640; 1 drivers +v0x8d2d15180_0 .net/s "m6", 39 0, L_0x8d3238780; 1 drivers +v0x8d2d15220_0 .net/s "m7", 39 0, L_0x8d32388c0; 1 drivers +v0x8d2d152c0_0 .net/s "s0", 39 0, L_0x8d3238960; 1 drivers +v0x8d2d15360_0 .net/s "s1", 39 0, L_0x8d3238a00; 1 drivers +v0x8d2d15400_0 .net/s "s2", 39 0, L_0x8d3238aa0; 1 drivers +v0x8d2d154a0_0 .net/s "s3", 39 0, L_0x8d3238b40; 1 drivers +v0x8d2d15540_0 .net/s "s4", 39 0, L_0x8d3238be0; 1 drivers +v0x8d2d155e0_0 .net/s "s5", 39 0, L_0x8d3238c80; 1 drivers +v0x8d2d15680_0 .net/s "sum", 39 0, L_0x8d3238d20; 1 drivers +v0x8d2d15720_0 .net/s "w_bus", 127 0, L_0x8d322fb60; alias, 1 drivers +v0x8d2d157c0_0 .net/s "x_bus", 127 0, L_0x8d322fac0; alias, 1 drivers +L_0x8d322fca0 .part L_0x8d322fac0, 0, 16; +L_0x8d322fd40 .part L_0x8d322fb60, 0, 16; +L_0x8d322fe80 .part L_0x8d322fac0, 16, 16; +L_0x8d322ff20 .part L_0x8d322fb60, 16, 16; +L_0x8d323c0a0 .part L_0x8d322fac0, 32, 16; +L_0x8d323c140 .part L_0x8d322fb60, 32, 16; +L_0x8d323c280 .part L_0x8d322fac0, 48, 16; +L_0x8d323c320 .part L_0x8d322fb60, 48, 16; +L_0x8d323c460 .part L_0x8d322fac0, 64, 16; +L_0x8d323c500 .part L_0x8d322fb60, 64, 16; +L_0x8d323c640 .part L_0x8d322fac0, 80, 16; +L_0x8d323c6e0 .part L_0x8d322fb60, 80, 16; +L_0x8d323c820 .part L_0x8d322fac0, 96, 16; +L_0x8d323c8c0 .part L_0x8d322fb60, 96, 16; +L_0x8d323ca00 .part L_0x8d322fac0, 112, 16; +L_0x8d323caa0 .part L_0x8d322fb60, 112, 16; +L_0x8d3238960 .arith/sum 40, L_0x8d3238000, L_0x8d3238140; +L_0x8d3238a00 .arith/sum 40, L_0x8d3238280, L_0x8d32383c0; +L_0x8d3238aa0 .arith/sum 40, L_0x8d3238500, L_0x8d3238640; +L_0x8d3238b40 .arith/sum 40, L_0x8d3238780, L_0x8d32388c0; +L_0x8d3238be0 .arith/sum 40, L_0x8d3238960, L_0x8d3238a00; +L_0x8d3238c80 .arith/sum 40, L_0x8d3238aa0, L_0x8d3238b40; +L_0x8d3238d20 .arith/sum 40, L_0x8d3238be0, L_0x8d3238c80; +L_0x8d3238dc0 .arith/sum 40, v0x8d2d163a0_0, L_0x8d3238d20; +S_0x8d320ae80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8d320ad00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306eac0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306eb00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306eb40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d11a40_0 .net/s *"_ivl_0", 31 0, L_0x8d2d22760; 1 drivers +v0x8d2d11ae0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d22800; 1 drivers +v0x8d2d11b80_0 .net *"_ivl_7", 0 0, L_0x8d322fc00; 1 drivers +v0x8d2d11c20_0 .net *"_ivl_9", 7 0, L_0x8d2d22940; 1 drivers +L_0x8d2855f48 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d11cc0_0 .net/s "acc_in", 39 0, L_0x8d2855f48; 1 drivers +v0x8d2d11d60_0 .net/s "acc_out", 39 0, L_0x8d3238000; alias, 1 drivers +v0x8d2d11e00_0 .net/s "product", 31 0, L_0x8d2d228a0; 1 drivers +v0x8d2d11ea0_0 .net/s "product_ext", 39 0, L_0x8d322bf20; 1 drivers +v0x8d2d11f40_0 .net/s "w", 15 0, L_0x8d322fd40; 1 drivers +v0x8d2d11fe0_0 .net/s "x", 15 0, L_0x8d322fca0; 1 drivers +L_0x8d2d22760 .extend/s 32, L_0x8d322fca0; +L_0x8d2d22800 .extend/s 32, L_0x8d322fd40; +L_0x8d2d228a0 .arith/mult 32, L_0x8d2d22760, L_0x8d2d22800; +L_0x8d322fc00 .part L_0x8d2d228a0, 31, 1; +L_0x8d2d22940 .repeat 8, 8, L_0x8d322fc00; +L_0x8d322bf20 .concat [ 32 8 0 0], L_0x8d2d228a0, L_0x8d2d22940; +L_0x8d3238000 .arith/sum 40, L_0x8d2855f48, L_0x8d322bf20; +S_0x8d320b000 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8d320ad00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306eb80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306ebc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ec00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d12080_0 .net/s *"_ivl_0", 31 0, L_0x8d2d229e0; 1 drivers +v0x8d2d12120_0 .net/s *"_ivl_2", 31 0, L_0x8d2d22a80; 1 drivers +v0x8d2d121c0_0 .net *"_ivl_7", 0 0, L_0x8d322fde0; 1 drivers +v0x8d2d12260_0 .net *"_ivl_9", 7 0, L_0x8d2d22bc0; 1 drivers +L_0x8d2855f90 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d12300_0 .net/s "acc_in", 39 0, L_0x8d2855f90; 1 drivers +v0x8d2d123a0_0 .net/s "acc_out", 39 0, L_0x8d3238140; alias, 1 drivers +v0x8d2d12440_0 .net/s "product", 31 0, L_0x8d2d22b20; 1 drivers +v0x8d2d124e0_0 .net/s "product_ext", 39 0, L_0x8d32380a0; 1 drivers +v0x8d2d12580_0 .net/s "w", 15 0, L_0x8d322ff20; 1 drivers +v0x8d2d12620_0 .net/s "x", 15 0, L_0x8d322fe80; 1 drivers +L_0x8d2d229e0 .extend/s 32, L_0x8d322fe80; +L_0x8d2d22a80 .extend/s 32, L_0x8d322ff20; +L_0x8d2d22b20 .arith/mult 32, L_0x8d2d229e0, L_0x8d2d22a80; +L_0x8d322fde0 .part L_0x8d2d22b20, 31, 1; +L_0x8d2d22bc0 .repeat 8, 8, L_0x8d322fde0; +L_0x8d32380a0 .concat [ 32 8 0 0], L_0x8d2d22b20, L_0x8d2d22bc0; +L_0x8d3238140 .arith/sum 40, L_0x8d2855f90, L_0x8d32380a0; +S_0x8d320b180 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8d320ad00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306ec40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306ec80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ecc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d126c0_0 .net/s *"_ivl_0", 31 0, L_0x8d2d22c60; 1 drivers +v0x8d2d12760_0 .net/s *"_ivl_2", 31 0, L_0x8d2d22d00; 1 drivers +v0x8d2d12800_0 .net *"_ivl_7", 0 0, L_0x8d323c000; 1 drivers +v0x8d2d128a0_0 .net *"_ivl_9", 7 0, L_0x8d2d22e40; 1 drivers +L_0x8d2855fd8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d12940_0 .net/s "acc_in", 39 0, L_0x8d2855fd8; 1 drivers +v0x8d2d129e0_0 .net/s "acc_out", 39 0, L_0x8d3238280; alias, 1 drivers +v0x8d2d12a80_0 .net/s "product", 31 0, L_0x8d2d22da0; 1 drivers +v0x8d2d12b20_0 .net/s "product_ext", 39 0, L_0x8d32381e0; 1 drivers +v0x8d2d12bc0_0 .net/s "w", 15 0, L_0x8d323c140; 1 drivers +v0x8d2d12c60_0 .net/s "x", 15 0, L_0x8d323c0a0; 1 drivers +L_0x8d2d22c60 .extend/s 32, L_0x8d323c0a0; +L_0x8d2d22d00 .extend/s 32, L_0x8d323c140; +L_0x8d2d22da0 .arith/mult 32, L_0x8d2d22c60, L_0x8d2d22d00; +L_0x8d323c000 .part L_0x8d2d22da0, 31, 1; +L_0x8d2d22e40 .repeat 8, 8, L_0x8d323c000; +L_0x8d32381e0 .concat [ 32 8 0 0], L_0x8d2d22da0, L_0x8d2d22e40; +L_0x8d3238280 .arith/sum 40, L_0x8d2855fd8, L_0x8d32381e0; +S_0x8d320b300 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8d320ad00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306ed00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306ed40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ed80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d12d00_0 .net/s *"_ivl_0", 31 0, L_0x8d2d22ee0; 1 drivers +v0x8d2d12da0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d22f80; 1 drivers +v0x8d2d12e40_0 .net *"_ivl_7", 0 0, L_0x8d323c1e0; 1 drivers +v0x8d2d12ee0_0 .net *"_ivl_9", 7 0, L_0x8d2d230c0; 1 drivers +L_0x8d2856020 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d12f80_0 .net/s "acc_in", 39 0, L_0x8d2856020; 1 drivers +v0x8d2d13020_0 .net/s "acc_out", 39 0, L_0x8d32383c0; alias, 1 drivers +v0x8d2d130c0_0 .net/s "product", 31 0, L_0x8d2d23020; 1 drivers +v0x8d2d13160_0 .net/s "product_ext", 39 0, L_0x8d3238320; 1 drivers +v0x8d2d13200_0 .net/s "w", 15 0, L_0x8d323c320; 1 drivers +v0x8d2d132a0_0 .net/s "x", 15 0, L_0x8d323c280; 1 drivers +L_0x8d2d22ee0 .extend/s 32, L_0x8d323c280; +L_0x8d2d22f80 .extend/s 32, L_0x8d323c320; +L_0x8d2d23020 .arith/mult 32, L_0x8d2d22ee0, L_0x8d2d22f80; +L_0x8d323c1e0 .part L_0x8d2d23020, 31, 1; +L_0x8d2d230c0 .repeat 8, 8, L_0x8d323c1e0; +L_0x8d3238320 .concat [ 32 8 0 0], L_0x8d2d23020, L_0x8d2d230c0; +L_0x8d32383c0 .arith/sum 40, L_0x8d2856020, L_0x8d3238320; +S_0x8d320b480 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8d320ad00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306edc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306ee00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ee40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d13340_0 .net/s *"_ivl_0", 31 0, L_0x8d2d23160; 1 drivers +v0x8d2d133e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d23200; 1 drivers +v0x8d2d13480_0 .net *"_ivl_7", 0 0, L_0x8d323c3c0; 1 drivers +v0x8d2d13520_0 .net *"_ivl_9", 7 0, L_0x8d2d23340; 1 drivers +L_0x8d2856068 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d135c0_0 .net/s "acc_in", 39 0, L_0x8d2856068; 1 drivers +v0x8d2d13660_0 .net/s "acc_out", 39 0, L_0x8d3238500; alias, 1 drivers +v0x8d2d13700_0 .net/s "product", 31 0, L_0x8d2d232a0; 1 drivers +v0x8d2d137a0_0 .net/s "product_ext", 39 0, L_0x8d3238460; 1 drivers +v0x8d2d13840_0 .net/s "w", 15 0, L_0x8d323c500; 1 drivers +v0x8d2d138e0_0 .net/s "x", 15 0, L_0x8d323c460; 1 drivers +L_0x8d2d23160 .extend/s 32, L_0x8d323c460; +L_0x8d2d23200 .extend/s 32, L_0x8d323c500; +L_0x8d2d232a0 .arith/mult 32, L_0x8d2d23160, L_0x8d2d23200; +L_0x8d323c3c0 .part L_0x8d2d232a0, 31, 1; +L_0x8d2d23340 .repeat 8, 8, L_0x8d323c3c0; +L_0x8d3238460 .concat [ 32 8 0 0], L_0x8d2d232a0, L_0x8d2d23340; +L_0x8d3238500 .arith/sum 40, L_0x8d2856068, L_0x8d3238460; +S_0x8d320b600 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8d320ad00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306ee80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306eec0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306ef00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d13980_0 .net/s *"_ivl_0", 31 0, L_0x8d2d233e0; 1 drivers +v0x8d2d13a20_0 .net/s *"_ivl_2", 31 0, L_0x8d2d23480; 1 drivers +v0x8d2d13ac0_0 .net *"_ivl_7", 0 0, L_0x8d323c5a0; 1 drivers +v0x8d2d13b60_0 .net *"_ivl_9", 7 0, L_0x8d2d235c0; 1 drivers +L_0x8d28560b0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d13c00_0 .net/s "acc_in", 39 0, L_0x8d28560b0; 1 drivers +v0x8d2d13ca0_0 .net/s "acc_out", 39 0, L_0x8d3238640; alias, 1 drivers +v0x8d2d13d40_0 .net/s "product", 31 0, L_0x8d2d23520; 1 drivers +v0x8d2d13de0_0 .net/s "product_ext", 39 0, L_0x8d32385a0; 1 drivers +v0x8d2d13e80_0 .net/s "w", 15 0, L_0x8d323c6e0; 1 drivers +v0x8d2d13f20_0 .net/s "x", 15 0, L_0x8d323c640; 1 drivers +L_0x8d2d233e0 .extend/s 32, L_0x8d323c640; +L_0x8d2d23480 .extend/s 32, L_0x8d323c6e0; +L_0x8d2d23520 .arith/mult 32, L_0x8d2d233e0, L_0x8d2d23480; +L_0x8d323c5a0 .part L_0x8d2d23520, 31, 1; +L_0x8d2d235c0 .repeat 8, 8, L_0x8d323c5a0; +L_0x8d32385a0 .concat [ 32 8 0 0], L_0x8d2d23520, L_0x8d2d235c0; +L_0x8d3238640 .arith/sum 40, L_0x8d28560b0, L_0x8d32385a0; +S_0x8d320b780 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8d320ad00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306ef40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306ef80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306efc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d14000_0 .net/s *"_ivl_0", 31 0, L_0x8d2d23660; 1 drivers +v0x8d2d140a0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d23700; 1 drivers +v0x8d2d14140_0 .net *"_ivl_7", 0 0, L_0x8d323c780; 1 drivers +v0x8d2d141e0_0 .net *"_ivl_9", 7 0, L_0x8d2d23840; 1 drivers +L_0x8d28560f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d14280_0 .net/s "acc_in", 39 0, L_0x8d28560f8; 1 drivers +v0x8d2d14320_0 .net/s "acc_out", 39 0, L_0x8d3238780; alias, 1 drivers +v0x8d2d143c0_0 .net/s "product", 31 0, L_0x8d2d237a0; 1 drivers +v0x8d2d14460_0 .net/s "product_ext", 39 0, L_0x8d32386e0; 1 drivers +v0x8d2d14500_0 .net/s "w", 15 0, L_0x8d323c8c0; 1 drivers +v0x8d2d145a0_0 .net/s "x", 15 0, L_0x8d323c820; 1 drivers +L_0x8d2d23660 .extend/s 32, L_0x8d323c820; +L_0x8d2d23700 .extend/s 32, L_0x8d323c8c0; +L_0x8d2d237a0 .arith/mult 32, L_0x8d2d23660, L_0x8d2d23700; +L_0x8d323c780 .part L_0x8d2d237a0, 31, 1; +L_0x8d2d23840 .repeat 8, 8, L_0x8d323c780; +L_0x8d32386e0 .concat [ 32 8 0 0], L_0x8d2d237a0, L_0x8d2d23840; +L_0x8d3238780 .arith/sum 40, L_0x8d28560f8, L_0x8d32386e0; +S_0x8d320b900 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8d320ad00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8d306f000 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8d306f040 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8d306f080 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8d2d14640_0 .net/s *"_ivl_0", 31 0, L_0x8d2d238e0; 1 drivers +v0x8d2d146e0_0 .net/s *"_ivl_2", 31 0, L_0x8d2d23980; 1 drivers +v0x8d2d14780_0 .net *"_ivl_7", 0 0, L_0x8d323c960; 1 drivers +v0x8d2d14820_0 .net *"_ivl_9", 7 0, L_0x8d2d23ac0; 1 drivers +L_0x8d2856140 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8d2d148c0_0 .net/s "acc_in", 39 0, L_0x8d2856140; 1 drivers +v0x8d2d14960_0 .net/s "acc_out", 39 0, L_0x8d32388c0; alias, 1 drivers +v0x8d2d14a00_0 .net/s "product", 31 0, L_0x8d2d23a20; 1 drivers +v0x8d2d14aa0_0 .net/s "product_ext", 39 0, L_0x8d3238820; 1 drivers +v0x8d2d14b40_0 .net/s "w", 15 0, L_0x8d323caa0; 1 drivers +v0x8d2d14be0_0 .net/s "x", 15 0, L_0x8d323ca00; 1 drivers +L_0x8d2d238e0 .extend/s 32, L_0x8d323ca00; +L_0x8d2d23980 .extend/s 32, L_0x8d323caa0; +L_0x8d2d23a20 .arith/mult 32, L_0x8d2d238e0, L_0x8d2d23980; +L_0x8d323c960 .part L_0x8d2d23a20, 31, 1; +L_0x8d2d23ac0 .repeat 8, 8, L_0x8d323c960; +L_0x8d3238820 .concat [ 32 8 0 0], L_0x8d2d23a20, L_0x8d2d23ac0; +L_0x8d32388c0 .arith/sum 40, L_0x8d2856140, L_0x8d3238820; +S_0x8d320ba80 .scope function.vec4.u16, "q8_8" "q8_8" 3 56, 3 56 0, S_0x102e63dc0; + .timescale 0 0; +; Variable q8_8 is vec4 return value of scope S_0x8d320ba80 +v0x8d2d17660_0 .var/real "value", 0 0; +TD_tb.q8_8 ; + %load/real v0x8d2d17660_0; + %pushi/real 1073741824, 4074; load=256.000 + %mul/wr; + %vpi_func 3 59 "$rtoi" 32, W<0,r> {0 1 0}; + %pad/s 16; + %ret/vec4 0, 0, 16; Assign to q8_8 (store_vec4_to_lval) + %end; +S_0x8d320bc00 .scope task, "run_layer" "run_layer" 3 63, 3 63 0, S_0x102e63dc0; + .timescale 0 0; +E_0x8d2ce4380 .event anyedge, v0x8d2d170c0_0; +TD_tb.run_layer ; + %wait E_0x8d2ce4340; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x8d2d17b60_0, 0, 1; + %wait E_0x8d2ce4340; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x8d2d17b60_0, 0, 1; +T_1.0 ; + %load/vec4 v0x8d2d178e0_0; + %pad/u 32; + %pushi/vec4 1, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %cmpi/ne 1, 0, 1; + %jmp/0xz T_1.1, 6; + %wait E_0x8d2ce4380; + %jmp T_1.0; +T_1.1 ; + %wait E_0x8d2ce4340; + %end; + .scope S_0x102e579a0; +T_2 ; + %wait E_0x8d2ce4340; + %load/vec4 v0x8d2ced9a0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2ced900_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2ced2c0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2cedd60_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2ced5e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2ced720_0, 0; + %jmp T_2.1; +T_2.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2ced720_0, 0; + %load/vec4 v0x8d2ceda40_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_2.4, 9; + %load/vec4 v0x8d2ced5e0_0; + %nor/r; + %and; +T_2.4; + %flag_set/vec4 8; + %jmp/0xz T_2.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2ced900_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2ced2c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2ced5e0_0, 0; + %jmp T_2.3; +T_2.2 ; + %load/vec4 v0x8d2ced5e0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.5, 8; + %load/vec4 v0x8d2ced900_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_2.7, 4; + %load/vec4 v0x8d2ced7c0_0; + %assign/vec4 v0x8d2ced2c0_0, 0; + %load/vec4 v0x8d2ced860_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_2.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2cedd60_0, 0; + %jmp T_2.10; +T_2.9 ; + %load/vec4 v0x8d2ced860_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_2.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8d2cedd60_0, 0; + %jmp T_2.12; +T_2.11 ; + %load/vec4 v0x8d2ced860_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8d2cedd60_0, 0; +T_2.12 ; +T_2.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2ced5e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2ced720_0, 0; + %jmp T_2.8; +T_2.7 ; + %load/vec4 v0x8d2ced360_0; + %assign/vec4 v0x8d2ced2c0_0, 0; + %load/vec4 v0x8d2ced900_0; + %addi 1, 0, 3; + %assign/vec4 v0x8d2ced900_0, 0; +T_2.8 ; +T_2.5 ; +T_2.3 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x8d31fc780; +T_3 ; + %wait E_0x8d2ce4340; + %load/vec4 v0x8d2cf2e40_0; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2cf2da0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2cf2760_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2cf3200_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2cf2a80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2cf2bc0_0, 0; + %jmp T_3.1; +T_3.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2cf2bc0_0, 0; + %load/vec4 v0x8d2cf2ee0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_3.4, 9; + %load/vec4 v0x8d2cf2a80_0; + %nor/r; + %and; +T_3.4; + %flag_set/vec4 8; + %jmp/0xz T_3.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2cf2da0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2cf2760_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2cf2a80_0, 0; + %jmp T_3.3; +T_3.2 ; + %load/vec4 v0x8d2cf2a80_0; + %flag_set/vec4 8; + %jmp/0xz T_3.5, 8; + %load/vec4 v0x8d2cf2da0_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_3.7, 4; + %load/vec4 v0x8d2cf2c60_0; + %assign/vec4 v0x8d2cf2760_0, 0; + %load/vec4 v0x8d2cf2d00_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_3.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2cf3200_0, 0; + %jmp T_3.10; +T_3.9 ; + %load/vec4 v0x8d2cf2d00_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_3.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8d2cf3200_0, 0; + %jmp T_3.12; +T_3.11 ; + %load/vec4 v0x8d2cf2d00_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8d2cf3200_0, 0; +T_3.12 ; +T_3.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2cf2a80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2cf2bc0_0, 0; + %jmp T_3.8; +T_3.7 ; + %load/vec4 v0x8d2cf2800_0; + %assign/vec4 v0x8d2cf2760_0, 0; + %load/vec4 v0x8d2cf2da0_0; + %addi 1, 0, 3; + %assign/vec4 v0x8d2cf2da0_0, 0; +T_3.8 ; +T_3.5 ; +T_3.3 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x8d31fd800; +T_4 ; + %wait E_0x8d2ce4340; + %load/vec4 v0x8d2cfc320_0; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2cfc280_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2cf7c00_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2cfc6e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2cf7f20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2cfc0a0_0, 0; + %jmp T_4.1; +T_4.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2cfc0a0_0, 0; + %load/vec4 v0x8d2cfc3c0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_4.4, 9; + %load/vec4 v0x8d2cf7f20_0; + %nor/r; + %and; +T_4.4; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2cfc280_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2cf7c00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2cf7f20_0, 0; + %jmp T_4.3; +T_4.2 ; + %load/vec4 v0x8d2cf7f20_0; + %flag_set/vec4 8; + %jmp/0xz T_4.5, 8; + %load/vec4 v0x8d2cfc280_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_4.7, 4; + %load/vec4 v0x8d2cfc140_0; + %assign/vec4 v0x8d2cf7c00_0, 0; + %load/vec4 v0x8d2cfc1e0_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_4.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2cfc6e0_0, 0; + %jmp T_4.10; +T_4.9 ; + %load/vec4 v0x8d2cfc1e0_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_4.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8d2cfc6e0_0, 0; + %jmp T_4.12; +T_4.11 ; + %load/vec4 v0x8d2cfc1e0_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8d2cfc6e0_0, 0; +T_4.12 ; +T_4.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2cf7f20_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2cfc0a0_0, 0; + %jmp T_4.8; +T_4.7 ; + %load/vec4 v0x8d2cf7ca0_0; + %assign/vec4 v0x8d2cf7c00_0, 0; + %load/vec4 v0x8d2cfc280_0; + %addi 1, 0, 3; + %assign/vec4 v0x8d2cfc280_0, 0; +T_4.8 ; +T_4.5 ; +T_4.3 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x8d31fe880; +T_5 ; + %wait E_0x8d2ce4340; + %load/vec4 v0x8d2d017c0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d01720_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d010e0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d01b80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d01400_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d01540_0, 0; + %jmp T_5.1; +T_5.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d01540_0, 0; + %load/vec4 v0x8d2d01860_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_5.4, 9; + %load/vec4 v0x8d2d01400_0; + %nor/r; + %and; +T_5.4; + %flag_set/vec4 8; + %jmp/0xz T_5.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d01720_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d010e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d01400_0, 0; + %jmp T_5.3; +T_5.2 ; + %load/vec4 v0x8d2d01400_0; + %flag_set/vec4 8; + %jmp/0xz T_5.5, 8; + %load/vec4 v0x8d2d01720_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_5.7, 4; + %load/vec4 v0x8d2d015e0_0; + %assign/vec4 v0x8d2d010e0_0, 0; + %load/vec4 v0x8d2d01680_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_5.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d01b80_0, 0; + %jmp T_5.10; +T_5.9 ; + %load/vec4 v0x8d2d01680_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_5.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8d2d01b80_0, 0; + %jmp T_5.12; +T_5.11 ; + %load/vec4 v0x8d2d01680_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8d2d01b80_0, 0; +T_5.12 ; +T_5.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d01400_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d01540_0, 0; + %jmp T_5.8; +T_5.7 ; + %load/vec4 v0x8d2d01180_0; + %assign/vec4 v0x8d2d010e0_0, 0; + %load/vec4 v0x8d2d01720_0; + %addi 1, 0, 3; + %assign/vec4 v0x8d2d01720_0, 0; +T_5.8 ; +T_5.5 ; +T_5.3 ; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0x8d31ff900; +T_6 ; + %wait E_0x8d2ce4340; + %load/vec4 v0x8d2d06c60_0; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d06bc0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d06580_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d07020_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d068a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d069e0_0, 0; + %jmp T_6.1; +T_6.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d069e0_0, 0; + %load/vec4 v0x8d2d06d00_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_6.4, 9; + %load/vec4 v0x8d2d068a0_0; + %nor/r; + %and; +T_6.4; + %flag_set/vec4 8; + %jmp/0xz T_6.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d06bc0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d06580_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d068a0_0, 0; + %jmp T_6.3; +T_6.2 ; + %load/vec4 v0x8d2d068a0_0; + %flag_set/vec4 8; + %jmp/0xz T_6.5, 8; + %load/vec4 v0x8d2d06bc0_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_6.7, 4; + %load/vec4 v0x8d2d06a80_0; + %assign/vec4 v0x8d2d06580_0, 0; + %load/vec4 v0x8d2d06b20_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_6.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d07020_0, 0; + %jmp T_6.10; +T_6.9 ; + %load/vec4 v0x8d2d06b20_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_6.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8d2d07020_0, 0; + %jmp T_6.12; +T_6.11 ; + %load/vec4 v0x8d2d06b20_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8d2d07020_0, 0; +T_6.12 ; +T_6.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d068a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d069e0_0, 0; + %jmp T_6.8; +T_6.7 ; + %load/vec4 v0x8d2d06620_0; + %assign/vec4 v0x8d2d06580_0, 0; + %load/vec4 v0x8d2d06bc0_0; + %addi 1, 0, 3; + %assign/vec4 v0x8d2d06bc0_0, 0; +T_6.8 ; +T_6.5 ; +T_6.3 ; +T_6.1 ; + %jmp T_6; + .thread T_6; + .scope S_0x8d3208a80; +T_7 ; + %wait E_0x8d2ce4340; + %load/vec4 v0x8d2d0c140_0; + %flag_set/vec4 8; + %jmp/0xz T_7.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d0c0a0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d0ba20_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d0c500_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d0bd40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d0be80_0, 0; + %jmp T_7.1; +T_7.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d0be80_0, 0; + %load/vec4 v0x8d2d0c1e0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_7.4, 9; + %load/vec4 v0x8d2d0bd40_0; + %nor/r; + %and; +T_7.4; + %flag_set/vec4 8; + %jmp/0xz T_7.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d0c0a0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d0ba20_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d0bd40_0, 0; + %jmp T_7.3; +T_7.2 ; + %load/vec4 v0x8d2d0bd40_0; + %flag_set/vec4 8; + %jmp/0xz T_7.5, 8; + %load/vec4 v0x8d2d0c0a0_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_7.7, 4; + %load/vec4 v0x8d2d0bf20_0; + %assign/vec4 v0x8d2d0ba20_0, 0; + %load/vec4 v0x8d2d0c000_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_7.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d0c500_0, 0; + %jmp T_7.10; +T_7.9 ; + %load/vec4 v0x8d2d0c000_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_7.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8d2d0c500_0, 0; + %jmp T_7.12; +T_7.11 ; + %load/vec4 v0x8d2d0c000_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8d2d0c500_0, 0; +T_7.12 ; +T_7.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d0bd40_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d0be80_0, 0; + %jmp T_7.8; +T_7.7 ; + %load/vec4 v0x8d2d0bac0_0; + %assign/vec4 v0x8d2d0ba20_0, 0; + %load/vec4 v0x8d2d0c0a0_0; + %addi 1, 0, 3; + %assign/vec4 v0x8d2d0c0a0_0, 0; +T_7.8 ; +T_7.5 ; +T_7.3 ; +T_7.1 ; + %jmp T_7; + .thread T_7; + .scope S_0x8d3209b00; +T_8 ; + %wait E_0x8d2ce4340; + %load/vec4 v0x8d2d115e0_0; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d11540_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d10f00_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d119a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d11220_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d11360_0, 0; + %jmp T_8.1; +T_8.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d11360_0, 0; + %load/vec4 v0x8d2d11680_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_8.4, 9; + %load/vec4 v0x8d2d11220_0; + %nor/r; + %and; +T_8.4; + %flag_set/vec4 8; + %jmp/0xz T_8.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d11540_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d10f00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d11220_0, 0; + %jmp T_8.3; +T_8.2 ; + %load/vec4 v0x8d2d11220_0; + %flag_set/vec4 8; + %jmp/0xz T_8.5, 8; + %load/vec4 v0x8d2d11540_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_8.7, 4; + %load/vec4 v0x8d2d11400_0; + %assign/vec4 v0x8d2d10f00_0, 0; + %load/vec4 v0x8d2d114a0_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_8.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d119a0_0, 0; + %jmp T_8.10; +T_8.9 ; + %load/vec4 v0x8d2d114a0_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_8.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8d2d119a0_0, 0; + %jmp T_8.12; +T_8.11 ; + %load/vec4 v0x8d2d114a0_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8d2d119a0_0, 0; +T_8.12 ; +T_8.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d11220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d11360_0, 0; + %jmp T_8.8; +T_8.7 ; + %load/vec4 v0x8d2d10fa0_0; + %assign/vec4 v0x8d2d10f00_0, 0; + %load/vec4 v0x8d2d11540_0; + %addi 1, 0, 3; + %assign/vec4 v0x8d2d11540_0, 0; +T_8.8 ; +T_8.5 ; +T_8.3 ; +T_8.1 ; + %jmp T_8; + .thread T_8; + .scope S_0x8d320ab80; +T_9 ; + %wait E_0x8d2ce4340; + %load/vec4 v0x8d2d16a80_0; + %flag_set/vec4 8; + %jmp/0xz T_9.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d169e0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d163a0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d16e40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d166c0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d16800_0, 0; + %jmp T_9.1; +T_9.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d16800_0, 0; + %load/vec4 v0x8d2d16b20_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_9.4, 9; + %load/vec4 v0x8d2d166c0_0; + %nor/r; + %and; +T_9.4; + %flag_set/vec4 8; + %jmp/0xz T_9.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x8d2d169e0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8d2d163a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d166c0_0, 0; + %jmp T_9.3; +T_9.2 ; + %load/vec4 v0x8d2d166c0_0; + %flag_set/vec4 8; + %jmp/0xz T_9.5, 8; + %load/vec4 v0x8d2d169e0_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_9.7, 4; + %load/vec4 v0x8d2d168a0_0; + %assign/vec4 v0x8d2d163a0_0, 0; + %load/vec4 v0x8d2d16940_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_9.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8d2d16e40_0, 0; + %jmp T_9.10; +T_9.9 ; + %load/vec4 v0x8d2d16940_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_9.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8d2d16e40_0, 0; + %jmp T_9.12; +T_9.11 ; + %load/vec4 v0x8d2d16940_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8d2d16e40_0, 0; +T_9.12 ; +T_9.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8d2d166c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8d2d16800_0, 0; + %jmp T_9.8; +T_9.7 ; + %load/vec4 v0x8d2d16440_0; + %assign/vec4 v0x8d2d163a0_0, 0; + %load/vec4 v0x8d2d169e0_0; + %addi 1, 0, 3; + %assign/vec4 v0x8d2d169e0_0, 0; +T_9.8 ; +T_9.5 ; +T_9.3 ; +T_9.1 ; + %jmp T_9; + .thread T_9; + .scope S_0x102e63dc0; +T_10 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x8d2d17840_0, 0, 1; +T_10.0 ; + %delay 5, 0; + %load/vec4 v0x8d2d17840_0; + %inv; + %store/vec4 v0x8d2d17840_0, 0, 1; + %jmp T_10.0; +T_10.1 ; + %end; + .thread T_10; + .scope S_0x102e63dc0; +T_11 ; + %vpi_call/w 3 79 "$dumpfile", "sim/layer.vcd" {0 0 0}; + %vpi_call/w 3 80 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x102e63dc0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x8d2d17ac0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x8d2d17b60_0, 0, 1; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x8d2d17ca0_0, 0, 1024; + %pushi/vec4 0, 0, 8192; + %store/vec4 v0x8d2d17c00_0, 0, 8192; + %pushi/vec4 0, 0, 128; + %store/vec4 v0x8d2d17700_0, 0, 128; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; + %pushi/vec4 2, 0, 32; +T_11.0 %dup/vec4; + %cmpi/s 0, 0, 32; + %jmp/1xz T_11.1, 5; + %jmp/1 T_11.1, 4; + %subi 1, 0, 32; + %wait E_0x8d2ce4340; + %jmp T_11.0; +T_11.1 ; + %pop/vec4 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x8d2d17ac0_0, 0, 1; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; +T_11.2 ; Top of for-loop + %load/vec4 v0x8d2d17a20_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_11.3, 5; + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %load/vec4 v0x8d2d17a20_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x8d2d17ca0_0, 4, 16; +T_11.4 ; for-loop step statement + %load/vec4 v0x8d2d17a20_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; + %jmp T_11.2; +T_11.3 ; for-loop exit label + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; +T_11.5 ; Top of for-loop + %load/vec4 v0x8d2d17a20_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_11.6, 5; + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x8d2d17a20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8d2d17c00_0, 4, 16; +T_11.7 ; for-loop step statement + %load/vec4 v0x8d2d17a20_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; + %jmp T_11.5; +T_11.6 ; for-loop exit label + %pushi/real 0, 4065; load=0.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x8d2d17700_0, 4, 16; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; +T_11.8 ; Top of for-loop + %load/vec4 v0x8d2d17a20_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_11.9, 5; + %pushi/real 1073741824, 4065; load=0.500000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %pushi/vec4 1024, 0, 32; + %load/vec4 v0x8d2d17a20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8d2d17c00_0, 4, 16; +T_11.10 ; for-loop step statement + %load/vec4 v0x8d2d17a20_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; + %jmp T_11.8; +T_11.9 ; for-loop exit label + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; +T_11.11 ; Top of for-loop + %load/vec4 v0x8d2d17a20_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_11.12, 5; + %pushi/real 1073741824, 20449; load=-0.500000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %pushi/vec4 2048, 0, 32; + %load/vec4 v0x8d2d17a20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8d2d17c00_0, 4, 16; +T_11.13 ; for-loop step statement + %load/vec4 v0x8d2d17a20_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; + %jmp T_11.11; +T_11.12 ; for-loop exit label + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; +T_11.14 ; Top of for-loop + %load/vec4 v0x8d2d17a20_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_11.15, 5; + %pushi/real 1073741824, 4067; load=2.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %pushi/vec4 3072, 0, 32; + %load/vec4 v0x8d2d17a20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8d2d17c00_0, 4, 16; +T_11.16 ; for-loop step statement + %load/vec4 v0x8d2d17a20_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; + %jmp T_11.14; +T_11.15 ; for-loop exit label + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %ix/load 4, 64, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x8d2d17700_0, 4, 16; + %pushi/real 1073741824, 20450; load=-1.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %ix/load 4, 80, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x8d2d17700_0, 4, 16; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; +T_11.17 ; Top of for-loop + %load/vec4 v0x8d2d17a20_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_11.18, 5; + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %pushi/vec4 6144, 0, 32; + %load/vec4 v0x8d2d17a20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8d2d17c00_0, 4, 16; +T_11.19 ; for-loop step statement + %load/vec4 v0x8d2d17a20_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; + %jmp T_11.17; +T_11.18 ; for-loop exit label + %pushi/real 1073741824, 20450; load=-1.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %ix/load 4, 96, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x8d2d17700_0, 4, 16; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; +T_11.20 ; Top of for-loop + %load/vec4 v0x8d2d17a20_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_11.21, 5; + %pushi/real 1073741824, 4064; load=0.250000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %pushi/vec4 7168, 0, 32; + %load/vec4 v0x8d2d17a20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8d2d17c00_0, 4, 16; +T_11.22 ; for-loop step statement + %load/vec4 v0x8d2d17a20_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17a20_0, 0, 32; + %jmp T_11.20; +T_11.21 ; for-loop exit label + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x8d2d17660_0; + %callf/vec4 TD_tb.q8_8, S_0x8d320ba80; + %ix/load 4, 112, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x8d2d17700_0, 4, 16; + %vpi_call/w 3 197 "$display", "\000" {0 0 0}; + %vpi_call/w 3 198 "$display", "==============================" {0 0 0}; + %vpi_call/w 3 199 "$display", "LAYER TEST" {0 0 0}; + %vpi_call/w 3 200 "$display", "==============================" {0 0 0}; + %fork TD_tb.run_layer, S_0x8d320bc00; + %join; + %vpi_call/w 3 204 "$display", "Neuron 0 = %5d expected = 16384", &PV {0 0 0}; + %vpi_call/w 3 205 "$display", "Neuron 1 = %5d expected = 8192", &PV {0 0 0}; + %vpi_call/w 3 206 "$display", "Neuron 2 = %5d expected = 0", &PV {0 0 0}; + %vpi_call/w 3 207 "$display", "Neuron 3 = %5d expected = 32767", &PV {0 0 0}; + %vpi_call/w 3 208 "$display", "Neuron 4 = %5d expected = 256", &PV {0 0 0}; + %vpi_call/w 3 209 "$display", "Neuron 5 = %5d expected = 0", &PV {0 0 0}; + %vpi_call/w 3 210 "$display", "Neuron 6 = %5d expected = 16128", &PV {0 0 0}; + %vpi_call/w 3 211 "$display", "Neuron 7 = %5d expected = 4352", &PV {0 0 0}; + %load/vec4 v0x8d2d17d40_0; + %parti/s 16, 0, 2; + %cmpi/ne 16384, 0, 16; + %jmp/0xz T_11.23, 6; + %load/vec4 v0x8d2d17980_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; +T_11.23 ; + %load/vec4 v0x8d2d17d40_0; + %parti/s 16, 16, 6; + %cmpi/ne 8192, 0, 16; + %jmp/0xz T_11.25, 6; + %load/vec4 v0x8d2d17980_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; +T_11.25 ; + %load/vec4 v0x8d2d17d40_0; + %parti/s 16, 32, 7; + %cmpi/ne 0, 0, 16; + %jmp/0xz T_11.27, 6; + %load/vec4 v0x8d2d17980_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; +T_11.27 ; + %load/vec4 v0x8d2d17d40_0; + %parti/s 16, 48, 7; + %cmpi/ne 32767, 0, 16; + %jmp/0xz T_11.29, 6; + %load/vec4 v0x8d2d17980_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; +T_11.29 ; + %load/vec4 v0x8d2d17d40_0; + %parti/s 16, 64, 8; + %cmpi/ne 256, 0, 16; + %jmp/0xz T_11.31, 6; + %load/vec4 v0x8d2d17980_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; +T_11.31 ; + %load/vec4 v0x8d2d17d40_0; + %parti/s 16, 80, 8; + %cmpi/ne 0, 0, 16; + %jmp/0xz T_11.33, 6; + %load/vec4 v0x8d2d17980_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; +T_11.33 ; + %load/vec4 v0x8d2d17d40_0; + %parti/s 16, 96, 8; + %cmpi/ne 16128, 0, 16; + %jmp/0xz T_11.35, 6; + %load/vec4 v0x8d2d17980_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; +T_11.35 ; + %load/vec4 v0x8d2d17d40_0; + %parti/s 16, 112, 8; + %cmpi/ne 4352, 0, 16; + %jmp/0xz T_11.37, 6; + %load/vec4 v0x8d2d17980_0; + %addi 1, 0, 32; + %store/vec4 v0x8d2d17980_0, 0, 32; +T_11.37 ; + %vpi_call/w 3 222 "$display", "busy = %0d", v0x8d2d177a0_0 {0 0 0}; + %vpi_call/w 3 223 "$display", "done = %0d", v0x8d2d178e0_0 {0 0 0}; + %vpi_call/w 3 225 "$display", "\000" {0 0 0}; + %vpi_call/w 3 226 "$display", "==============================" {0 0 0}; + %load/vec4 v0x8d2d17980_0; + %cmpi/e 0, 0, 32; + %jmp/0xz T_11.39, 4; + %vpi_call/w 3 229 "$display", "PASS - ALL 8 NEURONS" {0 0 0}; + %jmp T_11.40; +T_11.39 ; + %vpi_call/w 3 231 "$display", "FAIL - %0d ERRORS", v0x8d2d17980_0 {0 0 0}; +T_11.40 ; + %vpi_call/w 3 233 "$display", "==============================" {0 0 0}; + %vpi_call/w 3 234 "$display", "LAYER TEST FINISHED" {0 0 0}; + %vpi_call/w 3 235 "$display", "\000" {0 0 0}; + %vpi_call/w 3 237 "$finish" {0 0 0}; + %end; + .thread T_11; +# The file index is used to find the file name in the following table. +:file_names 8; + "N/A"; + ""; + "-"; + "sim/layer_tb.v"; + "rtl/layer.v"; + "rtl/neuron_parallel.v"; + "rtl/mac8.v"; + "rtl/mac_unit.v"; diff --git a/sim/layer_tb.v b/sim/layer_tb.v new file mode 100644 index 0000000..9d33ad7 --- /dev/null +++ b/sim/layer_tb.v @@ -0,0 +1,240 @@ +module tb; + + parameter DATA_WIDTH = 16; + parameter FRAC_BITS = 8; + parameter N_INPUTS = 64; + parameter N_NEURONS = 8; + parameter PARALLEL = 8; + parameter ACC_WIDTH = 40; + + reg clk; + reg rst; + reg start; + + reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus; + + reg signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] + weights_bus; + + reg signed [DATA_WIDTH*N_NEURONS-1:0] + bias_bus; + + wire signed [DATA_WIDTH*N_NEURONS-1:0] + y_bus; + + wire busy; + wire done; + + integer i; + integer n; + integer errors; + + layer #( + .DATA_WIDTH(DATA_WIDTH), + .FRAC_BITS(FRAC_BITS), + .N_INPUTS(N_INPUTS), + .N_NEURONS(N_NEURONS), + .PARALLEL(PARALLEL), + .ACC_WIDTH(ACC_WIDTH) + ) dut ( + .clk(clk), + .rst(rst), + .start(start), + .x_bus(x_bus), + .weights_bus(weights_bus), + .bias_bus(bias_bus), + .y_bus(y_bus), + .busy(busy), + .done(done) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + function signed [15:0] q8_8; + input real value; + begin + q8_8 = $rtoi(value * 256.0); + end + endfunction + + task run_layer; + begin + @(posedge clk); + start = 1; + + @(posedge clk); + start = 0; + + wait(done == 1); + + @(posedge clk); + end + endtask + + initial begin + + $dumpfile("sim/layer.vcd"); + $dumpvars(0, tb); + + rst = 1; + start = 0; + x_bus = 0; + weights_bus = 0; + bias_bus = 0; + errors = 0; + + repeat (2) @(posedge clk); + + rst = 0; + + /* + * Input vector: + * all inputs = 1.0 + */ + for (i = 0; i < N_INPUTS; i = i + 1) + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + + /* + * Neuron 0: + * weights = 1.0 + * bias = 0 + * result = 64 + */ + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 0*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(1.0); + + bias_bus[0*DATA_WIDTH +: DATA_WIDTH] = q8_8(0.0); + + /* + * Neuron 1: + * weights = 0.5 + * result = 32 + */ + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 1*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(0.5); + + /* + * Neuron 2: + * weights = -0.5 + * result = -32 -> ReLU = 0 + */ + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 2*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(-0.5); + + /* + * Neuron 3: + * weights = 2.0 + * result = 128 -> saturation = 127.996... + */ + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 3*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(2.0); + + /* + * Neuron 4: + * weights = 0 + * bias = +1 + * result = 1 + */ + bias_bus[4*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + + /* + * Neuron 5: + * weights = 0 + * bias = -1 + * ReLU = 0 + */ + bias_bus[5*DATA_WIDTH +: DATA_WIDTH] = q8_8(-1.0); + + /* + * Neuron 6: + * weights = 1.0 + * bias = -1.0 + * result = 63 + */ + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 6*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(1.0); + + bias_bus[6*DATA_WIDTH +: DATA_WIDTH] = q8_8(-1.0); + + /* + * Neuron 7: + * weights = 0.25 + * bias = +1 + * result = 16 + 1 = 17 + */ + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 7*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(0.25); + + bias_bus[7*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + + $display(""); + $display("=============================="); + $display("LAYER TEST"); + $display("=============================="); + + run_layer; + + $display("Neuron 0 = %5d expected = 16384", y_bus[0*16 +: 16]); + $display("Neuron 1 = %5d expected = 8192", y_bus[1*16 +: 16]); + $display("Neuron 2 = %5d expected = 0", y_bus[2*16 +: 16]); + $display("Neuron 3 = %5d expected = 32767", y_bus[3*16 +: 16]); + $display("Neuron 4 = %5d expected = 256", y_bus[4*16 +: 16]); + $display("Neuron 5 = %5d expected = 0", y_bus[5*16 +: 16]); + $display("Neuron 6 = %5d expected = 16128", y_bus[6*16 +: 16]); + $display("Neuron 7 = %5d expected = 4352", y_bus[7*16 +: 16]); + + if (y_bus[0*16 +: 16] !== 16'sd16384) errors = errors + 1; + if (y_bus[1*16 +: 16] !== 16'sd8192) errors = errors + 1; + if (y_bus[2*16 +: 16] !== 16'sd0) errors = errors + 1; + if (y_bus[3*16 +: 16] !== 16'sd32767) errors = errors + 1; + if (y_bus[4*16 +: 16] !== 16'sd256) errors = errors + 1; + if (y_bus[5*16 +: 16] !== 16'sd0) errors = errors + 1; + if (y_bus[6*16 +: 16] !== 16'sd16128) errors = errors + 1; + if (y_bus[7*16 +: 16] !== 16'sd4352) errors = errors + 1; + + $display("busy = %0d", busy); + $display("done = %0d", done); + + $display(""); + $display("=============================="); + + if (errors == 0) + $display("PASS - ALL 8 NEURONS"); + else + $display("FAIL - %0d ERRORS", errors); + + $display("=============================="); + $display("LAYER TEST FINISHED"); + $display(""); + + $finish; + end + +endmodule \ No newline at end of file diff --git a/sim/neuron_parallel.vcd b/sim/neuron_parallel.vcd new file mode 100644 index 0000000..0ffe3f8 --- /dev/null +++ b/sim/neuron_parallel.vcd @@ -0,0 +1,1027 @@ +$date + Wed Sep 2 08:54:48 2026 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module tb $end +$var wire 16 ! y [15:0] $end +$var wire 1 " done $end +$var wire 1 # busy $end +$var parameter 32 $ ACC_WIDTH $end +$var parameter 32 % DATA_WIDTH $end +$var parameter 32 & FRAC_BITS $end +$var parameter 32 ' N_INPUTS $end +$var parameter 32 ( PARALLEL $end +$var reg 16 ) bias [15:0] $end +$var reg 1 * clk $end +$var reg 1 + rst $end +$var reg 1 , start $end +$var reg 1024 - w_bus [1023:0] $end +$var reg 1024 . x_bus [1023:0] $end +$var integer 32 / errors [31:0] $end +$var integer 32 0 i [31:0] $end +$scope function q8_8 $end +$var real 1 1 value $end +$upscope $end +$scope module dut $end +$var wire 16 2 bias [15:0] $end +$var wire 16 3 bias_ext_small [15:0] $end +$var wire 1 * clk $end +$var wire 1 + rst $end +$var wire 1 , start $end +$var wire 1024 4 w_bus [1023:0] $end +$var wire 1024 5 x_bus [1023:0] $end +$var wire 128 6 x_group [127:0] $end +$var wire 128 7 w_group [127:0] $end +$var wire 40 8 final_value [39:0] $end +$var wire 40 9 final_acc [39:0] $end +$var wire 40 : bias_ext [39:0] $end +$var wire 40 ; acc_next [39:0] $end +$var parameter 32 < ACC_WIDTH $end +$var parameter 32 = DATA_WIDTH $end +$var parameter 32 > FRAC_BITS $end +$var parameter 32 ? GROUPS $end +$var parameter 32 @ GROUP_INDEX_WIDTH $end +$var parameter 32 A N_INPUTS $end +$var parameter 32 B PARALLEL $end +$var reg 40 C acc [39:0] $end +$var reg 1 # busy $end +$var reg 1 " done $end +$var reg 3 D group_index [2:0] $end +$var reg 16 E y [15:0] $end +$scope module u_mac8 $end +$var wire 40 F acc_in [39:0] $end +$var wire 128 G w_bus [127:0] $end +$var wire 128 H x_bus [127:0] $end +$var wire 40 I sum [39:0] $end +$var wire 40 J s5 [39:0] $end +$var wire 40 K s4 [39:0] $end +$var wire 40 L s3 [39:0] $end +$var wire 40 M s2 [39:0] $end +$var wire 40 N s1 [39:0] $end +$var wire 40 O s0 [39:0] $end +$var wire 40 P m7 [39:0] $end +$var wire 40 Q m6 [39:0] $end +$var wire 40 R m5 [39:0] $end +$var wire 40 S m4 [39:0] $end +$var wire 40 T m3 [39:0] $end +$var wire 40 U m2 [39:0] $end +$var wire 40 V m1 [39:0] $end +$var wire 40 W m0 [39:0] $end +$var wire 40 X acc_out [39:0] $end +$var parameter 32 Y ACC_WIDTH $end +$var parameter 32 Z DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 [ acc_in [39:0] $end +$var wire 16 \ w [15:0] $end +$var wire 16 ] x [15:0] $end +$var wire 40 ^ product_ext [39:0] $end +$var wire 32 _ product [31:0] $end +$var wire 40 ` acc_out [39:0] $end +$var parameter 32 a ACC_WIDTH $end +$var parameter 32 b DATA_WIDTH $end +$var parameter 64 c PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 d acc_in [39:0] $end +$var wire 16 e w [15:0] $end +$var wire 16 f x [15:0] $end +$var wire 40 g product_ext [39:0] $end +$var wire 32 h product [31:0] $end +$var wire 40 i acc_out [39:0] $end +$var parameter 32 j ACC_WIDTH $end +$var parameter 32 k DATA_WIDTH $end +$var parameter 64 l PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 m acc_in [39:0] $end +$var wire 16 n w [15:0] $end +$var wire 16 o x [15:0] $end +$var wire 40 p product_ext [39:0] $end +$var wire 32 q product [31:0] $end +$var wire 40 r acc_out [39:0] $end +$var parameter 32 s ACC_WIDTH $end +$var parameter 32 t DATA_WIDTH $end +$var parameter 64 u PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 v acc_in [39:0] $end +$var wire 16 w w [15:0] $end +$var wire 16 x x [15:0] $end +$var wire 40 y product_ext [39:0] $end +$var wire 32 z product [31:0] $end +$var wire 40 { acc_out [39:0] $end +$var parameter 32 | ACC_WIDTH $end +$var parameter 32 } DATA_WIDTH $end +$var parameter 64 ~ PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 !" acc_in [39:0] $end +$var wire 16 "" w [15:0] $end +$var wire 16 #" x [15:0] $end +$var wire 40 $" product_ext [39:0] $end +$var wire 32 %" product [31:0] $end +$var wire 40 &" acc_out [39:0] $end +$var parameter 32 '" ACC_WIDTH $end +$var parameter 32 (" DATA_WIDTH $end +$var parameter 64 )" PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 *" acc_in [39:0] $end +$var wire 16 +" w [15:0] $end +$var wire 16 ," x [15:0] $end +$var wire 40 -" product_ext [39:0] $end +$var wire 32 ." product [31:0] $end +$var wire 40 /" acc_out [39:0] $end +$var parameter 32 0" ACC_WIDTH $end +$var parameter 32 1" DATA_WIDTH $end +$var parameter 64 2" PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 3" acc_in [39:0] $end +$var wire 16 4" w [15:0] $end +$var wire 16 5" x [15:0] $end +$var wire 40 6" product_ext [39:0] $end +$var wire 32 7" product [31:0] $end +$var wire 40 8" acc_out [39:0] $end +$var parameter 32 9" ACC_WIDTH $end +$var parameter 32 :" DATA_WIDTH $end +$var parameter 64 ;" PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 <" acc_in [39:0] $end +$var wire 16 =" w [15:0] $end +$var wire 16 >" x [15:0] $end +$var wire 40 ?" product_ext [39:0] $end +$var wire 32 @" product [31:0] $end +$var wire 40 A" acc_out [39:0] $end +$var parameter 32 B" ACC_WIDTH $end +$var parameter 32 C" DATA_WIDTH $end +$var parameter 64 D" PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$scope task run_neuron $end +$upscope $end +$scope task test_1 $end +$upscope $end +$scope task test_2 $end +$upscope $end +$scope task test_3 $end +$upscope $end +$scope task test_4 $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +b100000 D" +b10000 C" +b101000 B" +b100000 ;" +b10000 :" +b101000 9" +b100000 2" +b10000 1" +b101000 0" +b100000 )" +b10000 (" +b101000 '" +b100000 ~ +b10000 } +b101000 | +b100000 u +b10000 t +b101000 s +b100000 l +b10000 k +b101000 j +b100000 c +b10000 b +b101000 a +b10000 Z +b101000 Y +b1000 B +b1000000 A +b11 @ +b1000 ? +b1000 > +b10000 = +b101000 < +b1000 ( +b1000000 ' +b1000 & +b10000 % +b101000 $ +$end +#0 +$dumpvars +bx A" +bx @" +bx ?" +bx >" +bx =" +b0 <" +bx 8" +bx 7" +bx 6" +bx 5" +bx 4" +b0 3" +bx /" +bx ." +bx -" +bx ," +bx +" +b0 *" +bx &" +bx %" +bx $" +bx #" +bx "" +b0 !" +bx { +bx z +bx y +bx x +bx w +b0 v +bx r +bx q +bx p +bx o +bx n +b0 m +bx i +bx h +bx g +bx f +bx e +b0 d +bx ` +bx _ +bx ^ +bx ] +bx \ +b0 [ +bx X +bx W +bx V +bx U +bx T +bx S +bx R +bx Q +bx P +bx O +bx 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FRAC_BITS = 8; + parameter N_INPUTS = 64; + parameter PARALLEL = 8; + parameter ACC_WIDTH = 40; + + reg clk; + reg rst; + reg start; + + reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus; + reg signed [DATA_WIDTH*N_INPUTS-1:0] w_bus; + reg signed [DATA_WIDTH-1:0] bias; + + wire signed [DATA_WIDTH-1:0] y; + wire busy; + wire done; + + integer i; + integer errors; + + neuron_parallel #( + .DATA_WIDTH(DATA_WIDTH), + .FRAC_BITS(FRAC_BITS), + .N_INPUTS(N_INPUTS), + .PARALLEL(PARALLEL), + .ACC_WIDTH(ACC_WIDTH) + ) dut ( + .clk(clk), + .rst(rst), + .start(start), + .x_bus(x_bus), + .w_bus(w_bus), + .bias(bias), + .y(y), + .busy(busy), + .done(done) + ); + + // Clock: 10 ns + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + // ------------------------------------------------------------ + // Helper: convert real value to Q8.8 + // ------------------------------------------------------------ + function signed [15:0] q8_8; + input real value; + begin + q8_8 = $rtoi(value * 256.0); + end + endfunction + + // ------------------------------------------------------------ + // Start neuron and wait for completion + // ------------------------------------------------------------ + task run_neuron; + begin + @(posedge clk); + start = 1; + + @(posedge clk); + start = 0; + + wait(done == 1); + + @(posedge clk); + end + endtask + + // ------------------------------------------------------------ + // TEST 1 + // + // Diverse vector: + // + // x0 = 1.5 w0 = 2.0 -> 3.0 + // x1 = 2.0 w1 = -1.0 -> -2.0 + // x2 = 0.5 w2 = 0.25 -> 0.125 + // + // bias = 0.609375 + // + // total = 1.734375 + // Q8.8 = 444 + // ------------------------------------------------------------ + task test_1; + begin + $display(""); + $display("TEST 1: DIVERSE VECTOR"); + + x_bus = 0; + w_bus = 0; + bias = q8_8(0.609375); + + x_bus[0*16 +: 16] = q8_8(1.5); + w_bus[0*16 +: 16] = q8_8(2.0); + + x_bus[1*16 +: 16] = q8_8(2.0); + w_bus[1*16 +: 16] = q8_8(-1.0); + + x_bus[2*16 +: 16] = q8_8(0.5); + w_bus[2*16 +: 16] = q8_8(0.25); + + run_neuron; + + $display("RTL = %0d", y); + $display("EXPECTED = 444"); + + if (y !== 16'sd444) begin + $display("FAIL - TEST 1"); + errors = errors + 1; + end + else begin + $display("PASS - TEST 1"); + end + end + endtask + + // ------------------------------------------------------------ + // TEST 2 + // + // All products negative. + // ReLU must force output to zero. + // ------------------------------------------------------------ + task test_2; + begin + $display(""); + $display("TEST 2: RELU"); + + x_bus = 0; + w_bus = 0; + bias = 0; + + for (i = 0; i < N_INPUTS; i = i + 1) begin + x_bus[i*16 +: 16] = q8_8(1.0); + w_bus[i*16 +: 16] = q8_8(-1.0); + end + + run_neuron; + + $display("RTL = %0d", y); + $display("EXPECTED = 0"); + + if (y !== 16'sd0) begin + $display("FAIL - TEST 2"); + errors = errors + 1; + end + else begin + $display("PASS - TEST 2"); + end + end + endtask + + // ------------------------------------------------------------ + // TEST 3 + // + // Large positive result. + // Must saturate to +32767. + // ------------------------------------------------------------ + task test_3; + begin + $display(""); + $display("TEST 3: POSITIVE SATURATION"); + + x_bus = 0; + w_bus = 0; + bias = 0; + + for (i = 0; i < N_INPUTS; i = i + 1) begin + x_bus[i*16 +: 16] = q8_8(127.0); + w_bus[i*16 +: 16] = q8_8(2.0); + end + + run_neuron; + + $display("RTL = %0d", y); + $display("EXPECTED = 32767"); + + if (y !== 16'sd32767) begin + $display("FAIL - TEST 3"); + errors = errors + 1; + end + else begin + $display("PASS - TEST 3"); + end + end + endtask + + // ------------------------------------------------------------ + // TEST 4 + // + // Mixed positive/negative products. + // + // 32 x (+1) + // 32 x (-1) + // sum = 0 + // bias = -1 + // + // ReLU -> 0 + // ------------------------------------------------------------ + task test_4; + begin + $display(""); + $display("TEST 4: MIXED VALUES + NEGATIVE BIAS"); + + x_bus = 0; + w_bus = 0; + bias = q8_8(-1.0); + + for (i = 0; i < N_INPUTS; i = i + 1) begin + if ((i % 2) == 0) begin + x_bus[i*16 +: 16] = q8_8(2.0); + w_bus[i*16 +: 16] = q8_8(0.5); + end + else begin + x_bus[i*16 +: 16] = q8_8(-1.0); + w_bus[i*16 +: 16] = q8_8(1.0); + end + end + + run_neuron; + + $display("RTL = %0d", y); + $display("EXPECTED = 0"); + + if (y !== 16'sd0) begin + $display("FAIL - TEST 4"); + errors = errors + 1; + end + else begin + $display("PASS - TEST 4"); + end + end + endtask + + // ------------------------------------------------------------ + // MAIN + // ------------------------------------------------------------ + initial begin + + $dumpfile("sim/neuron_parallel.vcd"); + $dumpvars(0, tb); + + rst = 1; + start = 0; + x_bus = 0; + w_bus = 0; + bias = 0; + errors = 0; + + repeat (2) @(posedge clk); + + rst = 0; + + $display(""); + $display("=============================="); + $display("NEURON_PARALLEL TESTBENCH"); + $display("=============================="); + + test_1; + test_2; + test_3; + test_4; + + $display(""); + $display("=============================="); + + if (errors == 0) begin + $display("ALL TESTS PASSED"); + end + else begin + $display("FAILURES = %0d", errors); + end + + $display("=============================="); + $display(""); + + $finish; + end + +endmodule \ No newline at end of file diff --git a/sim/neuron_sim b/sim/neuron_sim new file mode 100755 index 0000000..2424e25 --- /dev/null +++ b/sim/neuron_sim @@ -0,0 +1,822 @@ +#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp +:ivl_version "13.0 (stable)" "(v13_0)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi"; +S_0x1012719d0 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x1012716f0 .scope module, "tb" "tb" 3 3; + .timescale -9 -12; +P_0x7e30a43c0 .param/l "ACC_WIDTH" 0 3 9, +C4<00000000000000000000000000101000>; +P_0x7e30a4400 .param/l "DATA_WIDTH" 0 3 5, +C4<00000000000000000000000000010000>; +P_0x7e30a4440 .param/l "FRAC_BITS" 0 3 6, +C4<00000000000000000000000000001000>; +P_0x7e30a4480 .param/l "N_INPUTS" 0 3 7, +C4<00000000000000000000000001000000>; +P_0x7e30a44c0 .param/l "PARALLEL" 0 3 8, +C4<00000000000000000000000000001000>; +v0x7e30b9040_0 .var/s "bias", 15 0; +v0x7e30b90e0_0 .net "busy", 0 0, v0x7e30b86e0_0; 1 drivers +v0x7e30b9180_0 .var "clk", 0 0; +v0x7e30b9220_0 .net "done", 0 0, v0x7e30b8820_0; 1 drivers +v0x7e30b92c0_0 .var/i "errors", 31 0; +v0x7e30b9360_0 .var/i "i", 31 0; +v0x7e30b9400_0 .var "rst", 0 0; +v0x7e30b94a0_0 .var "start", 0 0; +v0x7e30b9540_0 .var/s "w_bus", 1023 0; +v0x7e30b95e0_0 .var/s "x_bus", 1023 0; +v0x7e30b9680_0 .net/s "y", 15 0, v0x7e30b8e60_0; 1 drivers +S_0x1012679f0 .scope module, "dut" "neuron_parallel" 3 32, 4 1 0, S_0x1012716f0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 1024 "x_bus"; + .port_info 4 /INPUT 1024 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x101267b70 .param/l "ACC_WIDTH" 0 4 6, +C4<00000000000000000000000000101000>; +P_0x101267bb0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0x101267bf0 .param/l "FRAC_BITS" 0 4 3, +C4<00000000000000000000000000001000>; +P_0x101267c30 .param/l "GROUPS" 1 4 21, +C4<00000000000000000000000000001000>; +P_0x101267c70 .param/l "GROUP_INDEX_WIDTH" 1 4 22, +C4<00000000000000000000000000000011>; +P_0x101267cb0 .param/l "N_INPUTS" 0 4 4, +C4<00000000000000000000000001000000>; +P_0x101267cf0 .param/l "PARALLEL" 0 4 5, +C4<00000000000000000000000000001000>; +L_0x7e2c2c2a0 .functor BUFZ 16, v0x7e30b9040_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x7e30b7840_0 .net *"_ivl_0", 31 0, L_0x7e30b9720; 1 drivers +v0x7e30b78e0_0 .net *"_ivl_11", 31 0, L_0x7e30b9860; 1 drivers +v0x7e30b7980_0 .net *"_ivl_14", 31 0, L_0x7e30b9900; 1 drivers +L_0x7e28540e8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b7a20_0 .net *"_ivl_17", 28 0, L_0x7e28540e8; 1 drivers +L_0x7e2854130 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x7e30b7ac0_0 .net/2u *"_ivl_18", 31 0, L_0x7e2854130; 1 drivers +v0x7e30b7b60_0 .net *"_ivl_21", 31 0, L_0x7e30b99a0; 1 drivers +L_0x7e2854178 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x7e30b7c00_0 .net/2u *"_ivl_22", 31 0, L_0x7e2854178; 1 drivers +v0x7e30b7ca0_0 .net *"_ivl_25", 31 0, L_0x7e30b9a40; 1 drivers +L_0x7e2854010 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b7d40_0 .net *"_ivl_3", 28 0, L_0x7e2854010; 1 drivers +v0x7e30b7de0_0 .net *"_ivl_31", 0 0, L_0x7e2c857c0; 1 drivers +v0x7e30b7e80_0 .net *"_ivl_33", 23 0, L_0x7e2c85860; 1 drivers +v0x7e30b7f20_0 .net *"_ivl_36", 39 0, L_0x7e30baf80; 1 drivers +v0x7e30b8000_0 .net *"_ivl_38", 31 0, L_0x7e2c85900; 1 drivers +L_0x7e2854058 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x7e30b80a0_0 .net/2u *"_ivl_4", 31 0, L_0x7e2854058; 1 drivers +L_0x7e2854400 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b8140_0 .net *"_ivl_40", 7 0, L_0x7e2854400; 1 drivers +v0x7e30b81e0_0 .net *"_ivl_46", 31 0, L_0x7e2c859a0; 1 drivers +v0x7e30b8280_0 .net *"_ivl_7", 31 0, L_0x7e30b97c0; 1 drivers +L_0x7e28540a0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x7e30b8320_0 .net/2u *"_ivl_8", 31 0, L_0x7e28540a0; 1 drivers +v0x7e30b83c0_0 .var/s "acc", 39 0; +v0x7e30b8460_0 .net/s "acc_next", 39 0, L_0x7e2c590e0; 1 drivers +v0x7e30b8500_0 .net/s "bias", 15 0, v0x7e30b9040_0; 1 drivers +v0x7e30b85a0_0 .net/s "bias_ext", 39 0, L_0x7e30baee0; 1 drivers +v0x7e30b8640_0 .net/s "bias_ext_small", 15 0, L_0x7e2c2c2a0; 1 drivers +v0x7e30b86e0_0 .var "busy", 0 0; +v0x7e30b8780_0 .net "clk", 0 0, v0x7e30b9180_0; 1 drivers +v0x7e30b8820_0 .var "done", 0 0; +v0x7e30b88c0_0 .net/s "final_acc", 39 0, L_0x7e2c59180; 1 drivers +v0x7e30b8960_0 .net/s "final_value", 39 0, L_0x7e30bb020; 1 drivers +v0x7e30b8a00_0 .var "group_index", 2 0; +v0x7e30b8aa0_0 .net "rst", 0 0, v0x7e30b9400_0; 1 drivers +v0x7e30b8b40_0 .net "start", 0 0, v0x7e30b94a0_0; 1 drivers +v0x7e30b8be0_0 .net/s "w_bus", 1023 0, v0x7e30b9540_0; 1 drivers +v0x7e30b8c80_0 .net/s "w_group", 127 0, L_0x7e2c84320; 1 drivers +v0x7e30b8d20_0 .net/s "x_bus", 1023 0, v0x7e30b95e0_0; 1 drivers +v0x7e30b8dc0_0 .net/s "x_group", 127 0, L_0x7e2c84280; 1 drivers +v0x7e30b8e60_0 .var/s "y", 15 0; +E_0x7e2c81380 .event posedge, v0x7e30b8780_0; +L_0x7e30b9720 .concat [ 3 29 0 0], v0x7e30b8a00_0, L_0x7e2854010; +L_0x7e30b97c0 .arith/mult 32, L_0x7e30b9720, L_0x7e2854058; +L_0x7e30b9860 .arith/mult 32, L_0x7e30b97c0, L_0x7e28540a0; +L_0x7e2c84280 .part/v v0x7e30b95e0_0, L_0x7e30b9860, 128; +L_0x7e30b9900 .concat [ 3 29 0 0], v0x7e30b8a00_0, L_0x7e28540e8; +L_0x7e30b99a0 .arith/mult 32, L_0x7e30b9900, L_0x7e2854130; +L_0x7e30b9a40 .arith/mult 32, L_0x7e30b99a0, L_0x7e2854178; +L_0x7e2c84320 .part/v v0x7e30b9540_0, L_0x7e30b9a40, 128; +L_0x7e2c857c0 .part L_0x7e2c2c2a0, 15, 1; +L_0x7e2c85860 .repeat 24, 24, L_0x7e2c857c0; +L_0x7e30baee0 .concat [ 16 24 0 0], L_0x7e2c2c2a0, L_0x7e2c85860; +L_0x7e2c85900 .part L_0x7e30baee0, 0, 32; +L_0x7e30baf80 .concat [ 8 32 0 0], L_0x7e2854400, L_0x7e2c85900; +L_0x7e2c59180 .arith/sum 40, L_0x7e2c590e0, L_0x7e30baf80; +L_0x7e2c859a0 .part L_0x7e2c59180, 8, 32; +L_0x7e30bb020 .extend/s 40, L_0x7e2c859a0; +S_0x101263710 .scope module, "u_mac8" "mac8" 4 51, 5 1 0, S_0x1012679f0; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e3070b00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>; +P_0x7e3070b40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +v0x7e30b6c60_0 .net/s "acc_in", 39 0, v0x7e30b83c0_0; 1 drivers +v0x7e30b6d00_0 .net/s "acc_out", 39 0, L_0x7e2c590e0; alias, 1 drivers +v0x7e30b6da0_0 .net/s "m0", 39 0, L_0x7e2c58780; 1 drivers +v0x7e30b6e40_0 .net/s "m1", 39 0, L_0x7e2c58820; 1 drivers +v0x7e30b6ee0_0 .net/s "m2", 39 0, L_0x7e2c588c0; 1 drivers +v0x7e30b6f80_0 .net/s "m3", 39 0, L_0x7e2c58960; 1 drivers +v0x7e30b7020_0 .net/s "m4", 39 0, L_0x7e2c58a00; 1 drivers +v0x7e30b70c0_0 .net/s "m5", 39 0, L_0x7e2c58aa0; 1 drivers +v0x7e30b7160_0 .net/s "m6", 39 0, L_0x7e2c58b40; 1 drivers +v0x7e30b7200_0 .net/s "m7", 39 0, L_0x7e2c58be0; 1 drivers +v0x7e30b72a0_0 .net/s "s0", 39 0, L_0x7e2c58c80; 1 drivers +v0x7e30b7340_0 .net/s "s1", 39 0, L_0x7e2c58d20; 1 drivers +v0x7e30b73e0_0 .net/s "s2", 39 0, L_0x7e2c58dc0; 1 drivers +v0x7e30b7480_0 .net/s "s3", 39 0, L_0x7e2c58e60; 1 drivers +v0x7e30b7520_0 .net/s "s4", 39 0, L_0x7e2c58f00; 1 drivers +v0x7e30b75c0_0 .net/s "s5", 39 0, L_0x7e2c58fa0; 1 drivers +v0x7e30b7660_0 .net/s "sum", 39 0, L_0x7e2c59040; 1 drivers +v0x7e30b7700_0 .net/s "w_bus", 127 0, L_0x7e2c84320; alias, 1 drivers +v0x7e30b77a0_0 .net/s "x_bus", 127 0, L_0x7e2c84280; alias, 1 drivers +L_0x7e2c84500 .part L_0x7e2c84280, 0, 16; +L_0x7e2c845a0 .part L_0x7e2c84320, 0, 16; +L_0x7e2c84780 .part L_0x7e2c84280, 16, 16; +L_0x7e2c84820 .part L_0x7e2c84320, 16, 16; +L_0x7e2c84a00 .part L_0x7e2c84280, 32, 16; +L_0x7e2c84aa0 .part L_0x7e2c84320, 32, 16; +L_0x7e2c84c80 .part L_0x7e2c84280, 48, 16; +L_0x7e2c84d20 .part L_0x7e2c84320, 48, 16; +L_0x7e2c84f00 .part L_0x7e2c84280, 64, 16; +L_0x7e2c84fa0 .part L_0x7e2c84320, 64, 16; +L_0x7e2c85180 .part L_0x7e2c84280, 80, 16; +L_0x7e2c85220 .part L_0x7e2c84320, 80, 16; +L_0x7e2c85400 .part L_0x7e2c84280, 96, 16; +L_0x7e2c854a0 .part L_0x7e2c84320, 96, 16; +L_0x7e2c85680 .part L_0x7e2c84280, 112, 16; +L_0x7e2c85720 .part L_0x7e2c84320, 112, 16; +L_0x7e2c58c80 .arith/sum 40, L_0x7e2c58780, L_0x7e2c58820; +L_0x7e2c58d20 .arith/sum 40, L_0x7e2c588c0, L_0x7e2c58960; +L_0x7e2c58dc0 .arith/sum 40, L_0x7e2c58a00, L_0x7e2c58aa0; +L_0x7e2c58e60 .arith/sum 40, L_0x7e2c58b40, L_0x7e2c58be0; +L_0x7e2c58f00 .arith/sum 40, L_0x7e2c58c80, L_0x7e2c58d20; +L_0x7e2c58fa0 .arith/sum 40, L_0x7e2c58dc0, L_0x7e2c58e60; +L_0x7e2c59040 .arith/sum 40, L_0x7e2c58f00, L_0x7e2c58fa0; +L_0x7e2c590e0 .arith/sum 40, v0x7e30b83c0_0, L_0x7e2c59040; +S_0x101263890 .scope module, "mac0" "mac_unit" 5 33, 6 1 0, S_0x101263710; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e30b0000 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x7e30b0040 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x7e30b0080 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x101271870_0 .net/s *"_ivl_0", 31 0, L_0x7e30b9ae0; 1 drivers +v0x101271b50_0 .net/s *"_ivl_2", 31 0, L_0x7e30b9b80; 1 drivers +v0x10126f830_0 .net *"_ivl_7", 0 0, L_0x7e2c843c0; 1 drivers +v0x101271ff0_0 .net *"_ivl_9", 7 0, L_0x7e2c84460; 1 drivers +L_0x7e28541c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x101271e50_0 .net/s "acc_in", 39 0, L_0x7e28541c0; 1 drivers +v0x101271cb0_0 .net/s "acc_out", 39 0, L_0x7e2c58780; alias, 1 drivers +v0x1012714b0_0 .net/s "product", 31 0, L_0x7e30b9c20; 1 drivers +v0x1012712d0_0 .net/s "product_ext", 39 0, L_0x7e30b9cc0; 1 drivers +v0x101271090_0 .net/s "w", 15 0, L_0x7e2c845a0; 1 drivers +v0x7e30b4000_0 .net/s "x", 15 0, L_0x7e2c84500; 1 drivers +L_0x7e30b9ae0 .extend/s 32, L_0x7e2c84500; +L_0x7e30b9b80 .extend/s 32, L_0x7e2c845a0; +L_0x7e30b9c20 .arith/mult 32, L_0x7e30b9ae0, L_0x7e30b9b80; +L_0x7e2c843c0 .part L_0x7e30b9c20, 31, 1; +L_0x7e2c84460 .repeat 8, 8, L_0x7e2c843c0; +L_0x7e30b9cc0 .concat [ 32 8 0 0], L_0x7e30b9c20, L_0x7e2c84460; +L_0x7e2c58780 .arith/sum 40, L_0x7e28541c0, L_0x7e30b9cc0; +S_0x10125c9b0 .scope module, "mac1" "mac_unit" 5 43, 6 1 0, S_0x101263710; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e30b00c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x7e30b0100 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x7e30b0140 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x7e30b40a0_0 .net/s *"_ivl_0", 31 0, L_0x7e30b9d60; 1 drivers +v0x7e30b4140_0 .net/s *"_ivl_2", 31 0, L_0x7e30b9e00; 1 drivers +v0x7e30b41e0_0 .net *"_ivl_7", 0 0, L_0x7e2c84640; 1 drivers +v0x7e30b4280_0 .net *"_ivl_9", 7 0, L_0x7e2c846e0; 1 drivers +L_0x7e2854208 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b4320_0 .net/s "acc_in", 39 0, L_0x7e2854208; 1 drivers +v0x7e30b43c0_0 .net/s "acc_out", 39 0, L_0x7e2c58820; alias, 1 drivers +v0x7e30b4460_0 .net/s "product", 31 0, L_0x7e30b9ea0; 1 drivers +v0x7e30b4500_0 .net/s "product_ext", 39 0, L_0x7e30b9f40; 1 drivers +v0x7e30b45a0_0 .net/s "w", 15 0, L_0x7e2c84820; 1 drivers +v0x7e30b4640_0 .net/s "x", 15 0, L_0x7e2c84780; 1 drivers +L_0x7e30b9d60 .extend/s 32, L_0x7e2c84780; +L_0x7e30b9e00 .extend/s 32, L_0x7e2c84820; +L_0x7e30b9ea0 .arith/mult 32, L_0x7e30b9d60, L_0x7e30b9e00; +L_0x7e2c84640 .part L_0x7e30b9ea0, 31, 1; +L_0x7e2c846e0 .repeat 8, 8, L_0x7e2c84640; +L_0x7e30b9f40 .concat [ 32 8 0 0], L_0x7e30b9ea0, L_0x7e2c846e0; +L_0x7e2c58820 .arith/sum 40, L_0x7e2854208, L_0x7e30b9f40; +S_0x10125cb30 .scope module, "mac2" "mac_unit" 5 53, 6 1 0, S_0x101263710; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e30b0180 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x7e30b01c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x7e30b0200 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x7e30b46e0_0 .net/s *"_ivl_0", 31 0, L_0x7e30b9fe0; 1 drivers +v0x7e30b4780_0 .net/s *"_ivl_2", 31 0, L_0x7e30ba080; 1 drivers +v0x7e30b4820_0 .net *"_ivl_7", 0 0, L_0x7e2c848c0; 1 drivers +v0x7e30b48c0_0 .net *"_ivl_9", 7 0, L_0x7e2c84960; 1 drivers +L_0x7e2854250 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b4960_0 .net/s "acc_in", 39 0, L_0x7e2854250; 1 drivers +v0x7e30b4a00_0 .net/s "acc_out", 39 0, L_0x7e2c588c0; alias, 1 drivers +v0x7e30b4aa0_0 .net/s "product", 31 0, L_0x7e30ba120; 1 drivers +v0x7e30b4b40_0 .net/s "product_ext", 39 0, L_0x7e30ba1c0; 1 drivers +v0x7e30b4be0_0 .net/s "w", 15 0, L_0x7e2c84aa0; 1 drivers +v0x7e30b4c80_0 .net/s "x", 15 0, L_0x7e2c84a00; 1 drivers +L_0x7e30b9fe0 .extend/s 32, L_0x7e2c84a00; +L_0x7e30ba080 .extend/s 32, L_0x7e2c84aa0; +L_0x7e30ba120 .arith/mult 32, L_0x7e30b9fe0, L_0x7e30ba080; +L_0x7e2c848c0 .part L_0x7e30ba120, 31, 1; +L_0x7e2c84960 .repeat 8, 8, L_0x7e2c848c0; +L_0x7e30ba1c0 .concat [ 32 8 0 0], L_0x7e30ba120, L_0x7e2c84960; +L_0x7e2c588c0 .arith/sum 40, L_0x7e2854250, L_0x7e30ba1c0; +S_0x10125f110 .scope module, "mac3" "mac_unit" 5 63, 6 1 0, S_0x101263710; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e30b0240 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x7e30b0280 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x7e30b02c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x7e30b4d20_0 .net/s *"_ivl_0", 31 0, L_0x7e30ba260; 1 drivers +v0x7e30b4dc0_0 .net/s *"_ivl_2", 31 0, L_0x7e30ba300; 1 drivers +v0x7e30b4e60_0 .net *"_ivl_7", 0 0, L_0x7e2c84b40; 1 drivers +v0x7e30b4f00_0 .net *"_ivl_9", 7 0, L_0x7e2c84be0; 1 drivers +L_0x7e2854298 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b4fa0_0 .net/s "acc_in", 39 0, L_0x7e2854298; 1 drivers +v0x7e30b5040_0 .net/s "acc_out", 39 0, L_0x7e2c58960; alias, 1 drivers +v0x7e30b50e0_0 .net/s "product", 31 0, L_0x7e30ba3a0; 1 drivers +v0x7e30b5180_0 .net/s "product_ext", 39 0, L_0x7e30ba440; 1 drivers +v0x7e30b5220_0 .net/s "w", 15 0, L_0x7e2c84d20; 1 drivers +v0x7e30b52c0_0 .net/s "x", 15 0, L_0x7e2c84c80; 1 drivers +L_0x7e30ba260 .extend/s 32, L_0x7e2c84c80; +L_0x7e30ba300 .extend/s 32, L_0x7e2c84d20; +L_0x7e30ba3a0 .arith/mult 32, L_0x7e30ba260, L_0x7e30ba300; +L_0x7e2c84b40 .part L_0x7e30ba3a0, 31, 1; +L_0x7e2c84be0 .repeat 8, 8, L_0x7e2c84b40; +L_0x7e30ba440 .concat [ 32 8 0 0], L_0x7e30ba3a0, L_0x7e2c84be0; +L_0x7e2c58960 .arith/sum 40, L_0x7e2854298, L_0x7e30ba440; +S_0x10125f290 .scope module, "mac4" "mac_unit" 5 73, 6 1 0, S_0x101263710; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e30b0300 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x7e30b0340 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x7e30b0380 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x7e30b5360_0 .net/s *"_ivl_0", 31 0, L_0x7e30ba4e0; 1 drivers +v0x7e30b5400_0 .net/s *"_ivl_2", 31 0, L_0x7e30ba580; 1 drivers +v0x7e30b54a0_0 .net *"_ivl_7", 0 0, L_0x7e2c84dc0; 1 drivers +v0x7e30b5540_0 .net *"_ivl_9", 7 0, L_0x7e2c84e60; 1 drivers +L_0x7e28542e0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b55e0_0 .net/s "acc_in", 39 0, L_0x7e28542e0; 1 drivers +v0x7e30b5680_0 .net/s "acc_out", 39 0, L_0x7e2c58a00; alias, 1 drivers +v0x7e30b5720_0 .net/s "product", 31 0, L_0x7e30ba620; 1 drivers +v0x7e30b57c0_0 .net/s "product_ext", 39 0, L_0x7e30ba6c0; 1 drivers +v0x7e30b5860_0 .net/s "w", 15 0, L_0x7e2c84fa0; 1 drivers +v0x7e30b5900_0 .net/s "x", 15 0, L_0x7e2c84f00; 1 drivers +L_0x7e30ba4e0 .extend/s 32, L_0x7e2c84f00; +L_0x7e30ba580 .extend/s 32, L_0x7e2c84fa0; +L_0x7e30ba620 .arith/mult 32, L_0x7e30ba4e0, L_0x7e30ba580; +L_0x7e2c84dc0 .part L_0x7e30ba620, 31, 1; +L_0x7e2c84e60 .repeat 8, 8, L_0x7e2c84dc0; +L_0x7e30ba6c0 .concat [ 32 8 0 0], L_0x7e30ba620, L_0x7e2c84e60; +L_0x7e2c58a00 .arith/sum 40, L_0x7e28542e0, L_0x7e30ba6c0; +S_0x101272590 .scope module, "mac5" "mac_unit" 5 83, 6 1 0, S_0x101263710; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e30b03c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x7e30b0400 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x7e30b0440 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x7e30b59a0_0 .net/s *"_ivl_0", 31 0, L_0x7e30ba760; 1 drivers +v0x7e30b5a40_0 .net/s *"_ivl_2", 31 0, L_0x7e30ba800; 1 drivers +v0x7e30b5ae0_0 .net *"_ivl_7", 0 0, L_0x7e2c85040; 1 drivers +v0x7e30b5b80_0 .net *"_ivl_9", 7 0, L_0x7e2c850e0; 1 drivers +L_0x7e2854328 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b5c20_0 .net/s "acc_in", 39 0, L_0x7e2854328; 1 drivers +v0x7e30b5cc0_0 .net/s "acc_out", 39 0, L_0x7e2c58aa0; alias, 1 drivers +v0x7e30b5d60_0 .net/s "product", 31 0, L_0x7e30ba8a0; 1 drivers +v0x7e30b5e00_0 .net/s "product_ext", 39 0, L_0x7e30ba940; 1 drivers +v0x7e30b5ea0_0 .net/s "w", 15 0, L_0x7e2c85220; 1 drivers +v0x7e30b5f40_0 .net/s "x", 15 0, L_0x7e2c85180; 1 drivers +L_0x7e30ba760 .extend/s 32, L_0x7e2c85180; +L_0x7e30ba800 .extend/s 32, L_0x7e2c85220; +L_0x7e30ba8a0 .arith/mult 32, L_0x7e30ba760, L_0x7e30ba800; +L_0x7e2c85040 .part L_0x7e30ba8a0, 31, 1; +L_0x7e2c850e0 .repeat 8, 8, L_0x7e2c85040; +L_0x7e30ba940 .concat [ 32 8 0 0], L_0x7e30ba8a0, L_0x7e2c850e0; +L_0x7e2c58aa0 .arith/sum 40, L_0x7e2854328, L_0x7e30ba940; +S_0x1012700f0 .scope module, "mac6" "mac_unit" 5 93, 6 1 0, S_0x101263710; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e30b0480 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x7e30b04c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x7e30b0500 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x7e30b5fe0_0 .net/s *"_ivl_0", 31 0, L_0x7e30ba9e0; 1 drivers +v0x7e30b6080_0 .net/s *"_ivl_2", 31 0, L_0x7e30baa80; 1 drivers +v0x7e30b6120_0 .net *"_ivl_7", 0 0, L_0x7e2c852c0; 1 drivers +v0x7e30b61c0_0 .net *"_ivl_9", 7 0, L_0x7e2c85360; 1 drivers +L_0x7e2854370 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b6260_0 .net/s "acc_in", 39 0, L_0x7e2854370; 1 drivers +v0x7e30b6300_0 .net/s "acc_out", 39 0, L_0x7e2c58b40; alias, 1 drivers +v0x7e30b63a0_0 .net/s "product", 31 0, L_0x7e30bab20; 1 drivers +v0x7e30b6440_0 .net/s "product_ext", 39 0, L_0x7e30babc0; 1 drivers +v0x7e30b64e0_0 .net/s "w", 15 0, L_0x7e2c854a0; 1 drivers +v0x7e30b6580_0 .net/s "x", 15 0, L_0x7e2c85400; 1 drivers +L_0x7e30ba9e0 .extend/s 32, L_0x7e2c85400; +L_0x7e30baa80 .extend/s 32, L_0x7e2c854a0; +L_0x7e30bab20 .arith/mult 32, L_0x7e30ba9e0, L_0x7e30baa80; +L_0x7e2c852c0 .part L_0x7e30bab20, 31, 1; +L_0x7e2c85360 .repeat 8, 8, L_0x7e2c852c0; +L_0x7e30babc0 .concat [ 32 8 0 0], L_0x7e30bab20, L_0x7e2c85360; +L_0x7e2c58b40 .arith/sum 40, L_0x7e2854370, L_0x7e30babc0; +S_0x101270270 .scope module, "mac7" "mac_unit" 5 103, 6 1 0, S_0x101263710; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x7e30b0540 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x7e30b0580 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +P_0x7e30b05c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x7e30b6620_0 .net/s *"_ivl_0", 31 0, L_0x7e30bac60; 1 drivers +v0x7e30b66c0_0 .net/s *"_ivl_2", 31 0, L_0x7e30bad00; 1 drivers +v0x7e30b6760_0 .net *"_ivl_7", 0 0, L_0x7e2c85540; 1 drivers +v0x7e30b6800_0 .net *"_ivl_9", 7 0, L_0x7e2c855e0; 1 drivers +L_0x7e28543b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x7e30b68a0_0 .net/s "acc_in", 39 0, L_0x7e28543b8; 1 drivers +v0x7e30b6940_0 .net/s "acc_out", 39 0, L_0x7e2c58be0; alias, 1 drivers +v0x7e30b69e0_0 .net/s "product", 31 0, L_0x7e30bada0; 1 drivers +v0x7e30b6a80_0 .net/s "product_ext", 39 0, L_0x7e30bae40; 1 drivers +v0x7e30b6b20_0 .net/s "w", 15 0, L_0x7e2c85720; 1 drivers +v0x7e30b6bc0_0 .net/s "x", 15 0, L_0x7e2c85680; 1 drivers +L_0x7e30bac60 .extend/s 32, L_0x7e2c85680; +L_0x7e30bad00 .extend/s 32, L_0x7e2c85720; +L_0x7e30bada0 .arith/mult 32, L_0x7e30bac60, L_0x7e30bad00; +L_0x7e2c85540 .part L_0x7e30bada0, 31, 1; +L_0x7e2c855e0 .repeat 8, 8, L_0x7e2c85540; +L_0x7e30bae40 .concat [ 32 8 0 0], L_0x7e30bada0, L_0x7e2c855e0; +L_0x7e2c58be0 .arith/sum 40, L_0x7e28543b8, L_0x7e30bae40; +S_0x7e2ca0000 .scope function.vec4.u16, "q8_8" "q8_8" 3 53, 3 53 0, S_0x1012716f0; + .timescale -9 -12; +; Variable q8_8 is vec4 return value of scope S_0x7e2ca0000 +v0x7e30b8fa0_0 .var/real "value", 0 0; +TD_tb.q8_8 ; + %load/real v0x7e30b8fa0_0; + %pushi/real 1073741824, 4074; load=256.000 + %mul/wr; + %vpi_func 3 56 "$rtoi" 32, W<0,r> {0 1 0}; + %pad/s 16; + %ret/vec4 0, 0, 16; Assign to q8_8 (store_vec4_to_lval) + %end; +S_0x7e2ca0180 .scope task, "run_neuron" "run_neuron" 3 63, 3 63 0, S_0x1012716f0; + .timescale -9 -12; +E_0x7e2c81600 .event anyedge, v0x7e30b8820_0; +TD_tb.run_neuron ; + %wait E_0x7e2c81380; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x7e30b94a0_0, 0, 1; + %wait E_0x7e2c81380; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x7e30b94a0_0, 0, 1; +T_1.0 ; + %load/vec4 v0x7e30b9220_0; + %pad/u 32; + %pushi/vec4 1, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %cmpi/ne 1, 0, 1; + %jmp/0xz T_1.1, 6; + %wait E_0x7e2c81600; + %jmp T_1.0; +T_1.1 ; + %wait E_0x7e2c81380; + %end; +S_0x7e2ca0300 .scope task, "test_1" "test_1" 3 91, 3 91 0, S_0x1012716f0; + .timescale -9 -12; +TD_tb.test_1 ; + %vpi_call/w 3 93 "$display", "\000" {0 0 0}; + %vpi_call/w 3 94 "$display", "TEST 1: DIVERSE VECTOR" {0 0 0}; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b95e0_0, 0, 1024; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b9540_0, 0, 1024; + %pushi/real 1308622848, 4065; load=0.609375 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %store/vec4 v0x7e30b9040_0, 0, 16; + %pushi/real 1610612736, 4066; load=1.50000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x7e30b95e0_0, 4, 16; + %pushi/real 1073741824, 4067; load=2.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x7e30b9540_0, 4, 16; + %pushi/real 1073741824, 4067; load=2.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %ix/load 4, 16, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x7e30b95e0_0, 4, 16; + %pushi/real 1073741824, 20450; load=-1.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %ix/load 4, 16, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x7e30b9540_0, 4, 16; + %pushi/real 1073741824, 4065; load=0.500000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %ix/load 4, 32, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x7e30b95e0_0, 4, 16; + %pushi/real 1073741824, 4064; load=0.250000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %ix/load 4, 32, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x7e30b9540_0, 4, 16; + %fork TD_tb.run_neuron, S_0x7e2ca0180; + %join; + %vpi_call/w 3 111 "$display", "RTL = %0d", v0x7e30b9680_0 {0 0 0}; + %vpi_call/w 3 112 "$display", "EXPECTED = 444" {0 0 0}; + %load/vec4 v0x7e30b9680_0; + %cmpi/ne 444, 0, 16; + %jmp/0xz T_2.2, 6; + %vpi_call/w 3 115 "$display", "FAIL - TEST 1" {0 0 0}; + %load/vec4 v0x7e30b92c0_0; + %addi 1, 0, 32; + %store/vec4 v0x7e30b92c0_0, 0, 32; + %jmp T_2.3; +T_2.2 ; + %vpi_call/w 3 119 "$display", "PASS - TEST 1" {0 0 0}; +T_2.3 ; + %end; +S_0x7e2ca0480 .scope task, "test_2" "test_2" 3 130, 3 130 0, S_0x1012716f0; + .timescale -9 -12; +TD_tb.test_2 ; + %vpi_call/w 3 132 "$display", "\000" {0 0 0}; + %vpi_call/w 3 133 "$display", "TEST 2: RELU" {0 0 0}; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b95e0_0, 0, 1024; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b9540_0, 0, 1024; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x7e30b9040_0, 0, 16; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x7e30b9360_0, 0, 32; +T_3.4 ; Top of for-loop + %load/vec4 v0x7e30b9360_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_3.5, 5; + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %load/vec4 v0x7e30b9360_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x7e30b95e0_0, 4, 16; + %pushi/real 1073741824, 20450; load=-1.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %load/vec4 v0x7e30b9360_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x7e30b9540_0, 4, 16; +T_3.6 ; for-loop step statement + %load/vec4 v0x7e30b9360_0; + %addi 1, 0, 32; + %store/vec4 v0x7e30b9360_0, 0, 32; + %jmp T_3.4; +T_3.5 ; for-loop exit label + %fork TD_tb.run_neuron, S_0x7e2ca0180; + %join; + %vpi_call/w 3 146 "$display", "RTL = %0d", v0x7e30b9680_0 {0 0 0}; + %vpi_call/w 3 147 "$display", "EXPECTED = 0" {0 0 0}; + %load/vec4 v0x7e30b9680_0; + %cmpi/ne 0, 0, 16; + %jmp/0xz T_3.7, 6; + %vpi_call/w 3 150 "$display", "FAIL - TEST 2" {0 0 0}; + %load/vec4 v0x7e30b92c0_0; + %addi 1, 0, 32; + %store/vec4 v0x7e30b92c0_0, 0, 32; + %jmp T_3.8; +T_3.7 ; + %vpi_call/w 3 154 "$display", "PASS - TEST 2" {0 0 0}; +T_3.8 ; + %end; +S_0x7e2ca0600 .scope task, "test_3" "test_3" 3 165, 3 165 0, S_0x1012716f0; + .timescale -9 -12; +TD_tb.test_3 ; + %vpi_call/w 3 167 "$display", "\000" {0 0 0}; + %vpi_call/w 3 168 "$display", "TEST 3: POSITIVE SATURATION" {0 0 0}; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b95e0_0, 0, 1024; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b9540_0, 0, 1024; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x7e30b9040_0, 0, 16; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x7e30b9360_0, 0, 32; +T_4.9 ; Top of for-loop + %load/vec4 v0x7e30b9360_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_4.10, 5; + %pushi/real 2130706432, 4072; load=127.000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %load/vec4 v0x7e30b9360_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x7e30b95e0_0, 4, 16; + %pushi/real 1073741824, 4067; load=2.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %load/vec4 v0x7e30b9360_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x7e30b9540_0, 4, 16; +T_4.11 ; for-loop step statement + %load/vec4 v0x7e30b9360_0; + %addi 1, 0, 32; + %store/vec4 v0x7e30b9360_0, 0, 32; + %jmp T_4.9; +T_4.10 ; for-loop exit label + %fork TD_tb.run_neuron, S_0x7e2ca0180; + %join; + %vpi_call/w 3 181 "$display", "RTL = %0d", v0x7e30b9680_0 {0 0 0}; + %vpi_call/w 3 182 "$display", "EXPECTED = 32767" {0 0 0}; + %load/vec4 v0x7e30b9680_0; + %cmpi/ne 32767, 0, 16; + %jmp/0xz T_4.12, 6; + %vpi_call/w 3 185 "$display", "FAIL - TEST 3" {0 0 0}; + %load/vec4 v0x7e30b92c0_0; + %addi 1, 0, 32; + %store/vec4 v0x7e30b92c0_0, 0, 32; + %jmp T_4.13; +T_4.12 ; + %vpi_call/w 3 189 "$display", "PASS - TEST 3" {0 0 0}; +T_4.13 ; + %end; +S_0x7e2ca0780 .scope task, "test_4" "test_4" 3 206, 3 206 0, S_0x1012716f0; + .timescale -9 -12; +TD_tb.test_4 ; + %vpi_call/w 3 208 "$display", "\000" {0 0 0}; + %vpi_call/w 3 209 "$display", "TEST 4: MIXED VALUES + NEGATIVE BIAS" {0 0 0}; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b95e0_0, 0, 1024; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b9540_0, 0, 1024; + %pushi/real 1073741824, 20450; load=-1.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %store/vec4 v0x7e30b9040_0, 0, 16; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x7e30b9360_0, 0, 32; +T_5.14 ; Top of for-loop + %load/vec4 v0x7e30b9360_0; + %cmpi/s 64, 0, 32; + %jmp/0xz T_5.15, 5; + %load/vec4 v0x7e30b9360_0; + %pushi/vec4 2, 0, 32; + %mod/s; + %cmpi/e 0, 0, 32; + %jmp/0xz T_5.17, 4; + %pushi/real 1073741824, 4067; load=2.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %load/vec4 v0x7e30b9360_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x7e30b95e0_0, 4, 16; + %pushi/real 1073741824, 4065; load=0.500000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %load/vec4 v0x7e30b9360_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x7e30b9540_0, 4, 16; + %jmp T_5.18; +T_5.17 ; + %pushi/real 1073741824, 20450; load=-1.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %load/vec4 v0x7e30b9360_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x7e30b95e0_0, 4, 16; + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x7e30b8fa0_0; + %callf/vec4 TD_tb.q8_8, S_0x7e2ca0000; + %load/vec4 v0x7e30b9360_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x7e30b9540_0, 4, 16; +T_5.18 ; +T_5.16 ; for-loop step statement + %load/vec4 v0x7e30b9360_0; + %addi 1, 0, 32; + %store/vec4 v0x7e30b9360_0, 0, 32; + %jmp T_5.14; +T_5.15 ; for-loop exit label + %fork TD_tb.run_neuron, S_0x7e2ca0180; + %join; + %vpi_call/w 3 228 "$display", "RTL = %0d", v0x7e30b9680_0 {0 0 0}; + %vpi_call/w 3 229 "$display", "EXPECTED = 0" {0 0 0}; + %load/vec4 v0x7e30b9680_0; + %cmpi/ne 0, 0, 16; + %jmp/0xz T_5.19, 6; + %vpi_call/w 3 232 "$display", "FAIL - TEST 4" {0 0 0}; + %load/vec4 v0x7e30b92c0_0; + %addi 1, 0, 32; + %store/vec4 v0x7e30b92c0_0, 0, 32; + %jmp T_5.20; +T_5.19 ; + %vpi_call/w 3 236 "$display", "PASS - TEST 4" {0 0 0}; +T_5.20 ; + %end; + .scope S_0x1012679f0; +T_6 ; + %wait E_0x7e2c81380; + %load/vec4 v0x7e30b8aa0_0; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x7e30b8a00_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x7e30b83c0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x7e30b8e60_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x7e30b86e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x7e30b8820_0, 0; + %jmp T_6.1; +T_6.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x7e30b8820_0, 0; + %load/vec4 v0x7e30b8b40_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_6.4, 9; + %load/vec4 v0x7e30b86e0_0; + %nor/r; + %and; +T_6.4; + %flag_set/vec4 8; + %jmp/0xz T_6.2, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x7e30b8a00_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x7e30b83c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x7e30b86e0_0, 0; + %jmp T_6.3; +T_6.2 ; + %load/vec4 v0x7e30b86e0_0; + %flag_set/vec4 8; + %jmp/0xz T_6.5, 8; + %load/vec4 v0x7e30b8a00_0; + %pad/u 32; + %cmpi/e 7, 0, 32; + %jmp/0xz T_6.7, 4; + %load/vec4 v0x7e30b88c0_0; + %assign/vec4 v0x7e30b83c0_0, 0; + %load/vec4 v0x7e30b8960_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_6.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x7e30b8e60_0, 0; + %jmp T_6.10; +T_6.9 ; + %load/vec4 v0x7e30b8960_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_6.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x7e30b8e60_0, 0; + %jmp T_6.12; +T_6.11 ; + %load/vec4 v0x7e30b8960_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x7e30b8e60_0, 0; +T_6.12 ; +T_6.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x7e30b86e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x7e30b8820_0, 0; + %jmp T_6.8; +T_6.7 ; + %load/vec4 v0x7e30b8460_0; + %assign/vec4 v0x7e30b83c0_0, 0; + %load/vec4 v0x7e30b8a00_0; + %addi 1, 0, 3; + %assign/vec4 v0x7e30b8a00_0, 0; +T_6.8 ; +T_6.5 ; +T_6.3 ; +T_6.1 ; + %jmp T_6; + .thread T_6; + .scope S_0x1012716f0; +T_7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x7e30b9180_0, 0, 1; +T_7.0 ; + %delay 5000, 0; + %load/vec4 v0x7e30b9180_0; + %inv; + %store/vec4 v0x7e30b9180_0, 0, 1; + %jmp T_7.0; +T_7.1 ; + %end; + .thread T_7; + .scope S_0x1012716f0; +T_8 ; + %vpi_call/w 3 246 "$dumpfile", "sim/neuron_parallel.vcd" {0 0 0}; + %vpi_call/w 3 247 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x1012716f0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x7e30b9400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x7e30b94a0_0, 0, 1; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b95e0_0, 0, 1024; + %pushi/vec4 0, 0, 1024; + %store/vec4 v0x7e30b9540_0, 0, 1024; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x7e30b9040_0, 0, 16; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x7e30b92c0_0, 0, 32; + %pushi/vec4 2, 0, 32; +T_8.0 %dup/vec4; + %cmpi/s 0, 0, 32; + %jmp/1xz T_8.1, 5; + %jmp/1 T_8.1, 4; + %subi 1, 0, 32; + %wait E_0x7e2c81380; + %jmp T_8.0; +T_8.1 ; + %pop/vec4 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x7e30b9400_0, 0, 1; + %vpi_call/w 3 260 "$display", "\000" {0 0 0}; + %vpi_call/w 3 261 "$display", "==============================" {0 0 0}; + %vpi_call/w 3 262 "$display", "NEURON_PARALLEL TESTBENCH" {0 0 0}; + %vpi_call/w 3 263 "$display", "==============================" {0 0 0}; + %fork TD_tb.test_1, S_0x7e2ca0300; + %join; + %fork TD_tb.test_2, S_0x7e2ca0480; + %join; + %fork TD_tb.test_3, S_0x7e2ca0600; + %join; + %fork TD_tb.test_4, S_0x7e2ca0780; + %join; + %vpi_call/w 3 270 "$display", "\000" {0 0 0}; + %vpi_call/w 3 271 "$display", "==============================" {0 0 0}; + %load/vec4 v0x7e30b92c0_0; + %cmpi/e 0, 0, 32; + %jmp/0xz T_8.2, 4; + %vpi_call/w 3 274 "$display", "ALL TESTS PASSED" {0 0 0}; + %jmp T_8.3; +T_8.2 ; + %vpi_call/w 3 277 "$display", "FAILURES = %0d", v0x7e30b92c0_0 {0 0 0}; +T_8.3 ; + %vpi_call/w 3 280 "$display", "==============================" {0 0 0}; + %vpi_call/w 3 281 "$display", "\000" {0 0 0}; + %vpi_call/w 3 283 "$finish" {0 0 0}; + %end; + .thread T_8; +# The file index is used to find the file name in the following table. +:file_names 7; + "N/A"; + ""; + "-"; + "sim/neuron_parallel_tb.v"; + "rtl/neuron_parallel.v"; + "rtl/mac8.v"; + "rtl/mac_unit.v"; diff --git a/sim/parametric.vcd b/sim/parametric.vcd new file mode 100644 index 0000000..e9308f0 --- /dev/null +++ b/sim/parametric.vcd @@ -0,0 +1,1838 @@ +$date + Wed Sep 2 09:26:12 2026 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module tb $end +$var wire 64 ! y_bus [63:0] $end +$var wire 1 " done $end +$var wire 1 # busy $end +$var parameter 32 $ ACC_WIDTH $end +$var parameter 32 % DATA_WIDTH $end +$var parameter 32 & FRAC_BITS $end +$var parameter 32 ' N_INPUTS $end +$var parameter 32 ( N_NEURONS $end +$var parameter 32 ) PARALLEL $end +$var reg 64 * bias_bus [63:0] $end +$var reg 1 + clk $end +$var reg 1 , rst $end +$var reg 1 - start $end +$var reg 2048 . weights_bus [2047:0] $end +$var reg 512 / x_bus [511:0] $end +$var integer 32 0 errors [31:0] $end +$var integer 32 1 expected [31:0] $end +$var integer 32 2 i [31:0] $end +$scope function q8_8 $end +$var real 1 3 value $end +$upscope $end +$scope module dut $end +$var wire 64 4 bias_bus [63:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 2048 5 weights_bus [2047:0] $end +$var wire 512 6 x_bus [511:0] $end +$var wire 64 7 y_bus [63:0] $end +$var wire 4 8 neuron_done [3:0] $end +$var wire 4 9 neuron_busy [3:0] $end +$var wire 1 " done $end +$var wire 1 # busy $end +$var parameter 32 : ACC_WIDTH $end +$var parameter 32 ; DATA_WIDTH $end +$var parameter 32 < FRAC_BITS $end +$var parameter 32 = N_INPUTS $end +$var parameter 32 > N_NEURONS $end +$var parameter 32 ? PARALLEL $end +$scope begin GEN_NEURON[0] $end +$var parameter 2 @ n $end +$scope module u_neuron $end +$var wire 16 A bias [15:0] $end +$var wire 16 B bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 512 C w_bus [511:0] $end +$var wire 512 D x_bus [511:0] $end +$var wire 128 E x_group [127:0] $end +$var wire 128 F w_group [127:0] $end +$var wire 40 G final_value [39:0] $end +$var wire 40 H final_acc [39:0] $end +$var wire 40 I bias_ext [39:0] $end +$var wire 40 J acc_next [39:0] $end +$var parameter 32 K ACC_WIDTH $end +$var parameter 32 L DATA_WIDTH $end +$var parameter 32 M FRAC_BITS $end +$var parameter 32 N GROUPS $end +$var parameter 32 O GROUP_INDEX_WIDTH $end +$var parameter 32 P N_INPUTS $end +$var parameter 32 Q PARALLEL $end +$var reg 40 R acc [39:0] $end +$var reg 1 S busy $end +$var reg 1 T done $end +$var reg 2 U group_index [1:0] $end +$var reg 16 V y [15:0] $end +$scope module u_mac8 $end +$var wire 40 W acc_in [39:0] $end +$var wire 128 X w_bus [127:0] $end +$var wire 128 Y x_bus [127:0] $end +$var wire 40 Z sum [39:0] $end +$var wire 40 [ s5 [39:0] $end +$var wire 40 \ s4 [39:0] $end +$var wire 40 ] s3 [39:0] $end +$var wire 40 ^ s2 [39:0] $end +$var wire 40 _ s1 [39:0] $end +$var wire 40 ` s0 [39:0] $end +$var wire 40 a m7 [39:0] $end +$var wire 40 b m6 [39:0] $end +$var wire 40 c m5 [39:0] $end +$var wire 40 d m4 [39:0] $end +$var wire 40 e m3 [39:0] $end +$var wire 40 f m2 [39:0] $end +$var wire 40 g m1 [39:0] $end +$var wire 40 h m0 [39:0] $end +$var wire 40 i acc_out [39:0] $end +$var parameter 32 j ACC_WIDTH $end +$var parameter 32 k DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 l acc_in [39:0] $end +$var wire 16 m w [15:0] $end +$var wire 16 n x [15:0] $end +$var wire 40 o product_ext [39:0] $end +$var wire 32 p product [31:0] $end +$var wire 40 q acc_out [39:0] $end +$var parameter 32 r ACC_WIDTH $end +$var parameter 32 s DATA_WIDTH $end +$var parameter 64 t PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 u acc_in [39:0] $end +$var wire 16 v w [15:0] $end +$var wire 16 w x [15:0] $end +$var wire 40 x product_ext [39:0] $end +$var wire 32 y product [31:0] $end +$var wire 40 z acc_out [39:0] $end +$var parameter 32 { ACC_WIDTH $end +$var parameter 32 | DATA_WIDTH $end +$var parameter 64 } PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 ~ acc_in [39:0] $end +$var wire 16 !" w [15:0] $end +$var wire 16 "" x [15:0] $end +$var wire 40 #" product_ext [39:0] $end +$var wire 32 $" product [31:0] $end +$var wire 40 %" acc_out [39:0] $end +$var parameter 32 &" ACC_WIDTH $end +$var parameter 32 '" DATA_WIDTH $end +$var parameter 64 (" PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 )" acc_in [39:0] $end +$var wire 16 *" w [15:0] $end +$var wire 16 +" x [15:0] $end +$var wire 40 ," product_ext [39:0] $end +$var wire 32 -" product [31:0] $end +$var wire 40 ." acc_out [39:0] $end +$var parameter 32 /" ACC_WIDTH $end +$var parameter 32 0" DATA_WIDTH $end +$var parameter 64 1" PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 2" acc_in [39:0] $end +$var wire 16 3" w [15:0] $end +$var wire 16 4" x [15:0] $end +$var wire 40 5" product_ext [39:0] $end +$var wire 32 6" product [31:0] $end +$var wire 40 7" acc_out [39:0] $end +$var parameter 32 8" ACC_WIDTH $end +$var parameter 32 9" DATA_WIDTH $end +$var parameter 64 :" PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 ;" acc_in [39:0] $end +$var wire 16 <" w [15:0] $end +$var wire 16 =" x [15:0] $end +$var wire 40 >" product_ext [39:0] $end +$var wire 32 ?" product [31:0] $end +$var wire 40 @" acc_out [39:0] $end +$var parameter 32 A" ACC_WIDTH $end +$var parameter 32 B" DATA_WIDTH $end +$var parameter 64 C" PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 D" acc_in [39:0] $end +$var wire 16 E" w [15:0] $end +$var wire 16 F" x [15:0] $end +$var wire 40 G" product_ext [39:0] $end +$var wire 32 H" product [31:0] $end +$var wire 40 I" acc_out [39:0] $end +$var parameter 32 J" ACC_WIDTH $end +$var parameter 32 K" DATA_WIDTH $end +$var parameter 64 L" PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 M" acc_in [39:0] $end +$var wire 16 N" w [15:0] $end +$var wire 16 O" x [15:0] $end +$var wire 40 P" product_ext [39:0] $end +$var wire 32 Q" product [31:0] $end +$var wire 40 R" acc_out [39:0] $end +$var parameter 32 S" ACC_WIDTH $end +$var parameter 32 T" DATA_WIDTH $end +$var parameter 64 U" PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[1] $end +$var parameter 2 V" n $end +$scope module u_neuron $end +$var wire 16 W" bias [15:0] $end +$var wire 16 X" bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 512 Y" w_bus [511:0] $end +$var wire 512 Z" x_bus [511:0] $end +$var wire 128 [" x_group [127:0] $end +$var wire 128 \" w_group [127:0] $end +$var wire 40 ]" final_value [39:0] $end +$var wire 40 ^" final_acc [39:0] $end +$var wire 40 _" bias_ext [39:0] $end +$var wire 40 `" acc_next [39:0] $end +$var parameter 32 a" ACC_WIDTH $end +$var parameter 32 b" DATA_WIDTH $end +$var parameter 32 c" FRAC_BITS $end +$var parameter 32 d" GROUPS $end +$var parameter 32 e" GROUP_INDEX_WIDTH $end +$var parameter 32 f" N_INPUTS $end +$var parameter 32 g" PARALLEL $end +$var reg 40 h" acc [39:0] $end +$var reg 1 i" busy $end +$var reg 1 j" done $end +$var reg 2 k" group_index [1:0] $end +$var reg 16 l" y [15:0] $end +$scope module u_mac8 $end +$var wire 40 m" acc_in [39:0] $end +$var wire 128 n" w_bus [127:0] $end +$var wire 128 o" x_bus [127:0] $end +$var wire 40 p" sum [39:0] $end +$var wire 40 q" s5 [39:0] $end +$var wire 40 r" s4 [39:0] $end +$var wire 40 s" s3 [39:0] $end +$var wire 40 t" s2 [39:0] $end +$var wire 40 u" s1 [39:0] $end +$var wire 40 v" s0 [39:0] $end +$var wire 40 w" m7 [39:0] $end +$var wire 40 x" m6 [39:0] $end +$var wire 40 y" m5 [39:0] $end +$var wire 40 z" m4 [39:0] $end +$var wire 40 {" m3 [39:0] $end +$var wire 40 |" m2 [39:0] $end +$var wire 40 }" m1 [39:0] $end +$var wire 40 ~" m0 [39:0] $end +$var wire 40 !# acc_out [39:0] $end +$var parameter 32 "# ACC_WIDTH $end +$var parameter 32 ## DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 $# acc_in [39:0] $end +$var wire 16 %# w [15:0] $end +$var wire 16 &# x [15:0] $end +$var wire 40 '# product_ext [39:0] $end +$var wire 32 (# product [31:0] $end +$var wire 40 )# acc_out [39:0] $end +$var parameter 32 *# ACC_WIDTH $end +$var parameter 32 +# DATA_WIDTH $end +$var parameter 64 ,# PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 -# acc_in [39:0] $end +$var wire 16 .# w [15:0] $end +$var wire 16 /# x [15:0] $end +$var wire 40 0# product_ext [39:0] $end +$var wire 32 1# product [31:0] $end +$var wire 40 2# acc_out [39:0] $end +$var parameter 32 3# ACC_WIDTH $end +$var parameter 32 4# DATA_WIDTH $end +$var parameter 64 5# PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 6# acc_in [39:0] $end +$var wire 16 7# w [15:0] $end +$var wire 16 8# x [15:0] $end +$var wire 40 9# product_ext [39:0] $end +$var wire 32 :# product [31:0] $end +$var wire 40 ;# acc_out [39:0] $end +$var parameter 32 <# ACC_WIDTH $end +$var parameter 32 =# DATA_WIDTH $end +$var parameter 64 ># PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 ?# acc_in [39:0] $end +$var wire 16 @# w [15:0] $end +$var wire 16 A# x [15:0] $end +$var wire 40 B# product_ext [39:0] $end +$var wire 32 C# product [31:0] $end +$var wire 40 D# acc_out [39:0] $end +$var parameter 32 E# ACC_WIDTH $end +$var parameter 32 F# DATA_WIDTH $end +$var parameter 64 G# PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 H# acc_in [39:0] $end +$var wire 16 I# w [15:0] $end +$var wire 16 J# x [15:0] $end +$var wire 40 K# product_ext [39:0] $end +$var wire 32 L# product [31:0] $end +$var wire 40 M# acc_out [39:0] $end +$var parameter 32 N# ACC_WIDTH $end +$var parameter 32 O# DATA_WIDTH $end +$var parameter 64 P# PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 Q# acc_in [39:0] $end +$var wire 16 R# w [15:0] $end +$var wire 16 S# x [15:0] $end +$var wire 40 T# product_ext [39:0] $end +$var wire 32 U# product [31:0] $end +$var wire 40 V# acc_out [39:0] $end +$var parameter 32 W# ACC_WIDTH $end +$var parameter 32 X# DATA_WIDTH $end +$var parameter 64 Y# PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 Z# acc_in [39:0] $end +$var wire 16 [# w [15:0] $end +$var wire 16 \# x [15:0] $end +$var wire 40 ]# product_ext [39:0] $end +$var wire 32 ^# product [31:0] $end +$var wire 40 _# acc_out [39:0] $end +$var parameter 32 `# ACC_WIDTH $end +$var parameter 32 a# DATA_WIDTH $end +$var parameter 64 b# PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 c# acc_in [39:0] $end +$var wire 16 d# w [15:0] $end +$var wire 16 e# x [15:0] $end +$var wire 40 f# product_ext [39:0] $end +$var wire 32 g# product [31:0] $end +$var wire 40 h# acc_out [39:0] $end +$var parameter 32 i# ACC_WIDTH $end +$var parameter 32 j# DATA_WIDTH $end +$var parameter 64 k# PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[2] $end +$var parameter 3 l# n $end +$scope module u_neuron $end +$var wire 16 m# bias [15:0] $end +$var wire 16 n# bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 512 o# w_bus [511:0] $end +$var wire 512 p# x_bus [511:0] $end +$var wire 128 q# x_group [127:0] $end +$var wire 128 r# w_group [127:0] $end +$var wire 40 s# final_value [39:0] $end +$var wire 40 t# final_acc [39:0] $end +$var wire 40 u# bias_ext [39:0] $end +$var wire 40 v# acc_next [39:0] $end +$var parameter 32 w# ACC_WIDTH $end +$var parameter 32 x# DATA_WIDTH $end +$var parameter 32 y# FRAC_BITS $end +$var parameter 32 z# GROUPS $end +$var parameter 32 {# GROUP_INDEX_WIDTH $end +$var parameter 32 |# N_INPUTS $end +$var parameter 32 }# PARALLEL $end +$var reg 40 ~# acc [39:0] $end +$var reg 1 !$ busy $end +$var reg 1 "$ done $end +$var reg 2 #$ group_index [1:0] $end +$var reg 16 $$ y [15:0] $end +$scope module u_mac8 $end +$var wire 40 %$ acc_in [39:0] $end +$var wire 128 &$ w_bus [127:0] $end +$var wire 128 '$ x_bus [127:0] $end +$var wire 40 ($ sum [39:0] $end +$var wire 40 )$ s5 [39:0] $end +$var wire 40 *$ s4 [39:0] $end +$var wire 40 +$ s3 [39:0] $end +$var wire 40 ,$ s2 [39:0] $end +$var wire 40 -$ s1 [39:0] $end +$var wire 40 .$ s0 [39:0] $end +$var wire 40 /$ m7 [39:0] $end +$var wire 40 0$ m6 [39:0] $end +$var wire 40 1$ m5 [39:0] $end +$var wire 40 2$ m4 [39:0] $end +$var wire 40 3$ m3 [39:0] $end +$var wire 40 4$ m2 [39:0] $end +$var wire 40 5$ m1 [39:0] $end +$var wire 40 6$ m0 [39:0] $end +$var wire 40 7$ acc_out [39:0] $end +$var parameter 32 8$ ACC_WIDTH $end +$var parameter 32 9$ DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 :$ acc_in [39:0] $end +$var wire 16 ;$ w [15:0] $end +$var wire 16 <$ x [15:0] $end +$var wire 40 =$ product_ext [39:0] $end +$var wire 32 >$ product [31:0] $end +$var wire 40 ?$ acc_out [39:0] $end +$var parameter 32 @$ ACC_WIDTH $end +$var parameter 32 A$ DATA_WIDTH $end +$var parameter 64 B$ PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 C$ acc_in [39:0] $end +$var wire 16 D$ w [15:0] $end +$var wire 16 E$ x [15:0] $end +$var wire 40 F$ product_ext [39:0] $end +$var wire 32 G$ product [31:0] $end +$var wire 40 H$ acc_out [39:0] $end +$var parameter 32 I$ ACC_WIDTH $end +$var parameter 32 J$ DATA_WIDTH $end +$var parameter 64 K$ PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 L$ acc_in [39:0] $end +$var wire 16 M$ w [15:0] $end +$var wire 16 N$ x [15:0] $end +$var wire 40 O$ product_ext [39:0] $end +$var wire 32 P$ product [31:0] $end +$var wire 40 Q$ acc_out [39:0] $end +$var parameter 32 R$ ACC_WIDTH $end +$var parameter 32 S$ DATA_WIDTH $end +$var parameter 64 T$ PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 U$ acc_in [39:0] $end +$var wire 16 V$ w [15:0] $end +$var wire 16 W$ x [15:0] $end +$var wire 40 X$ product_ext [39:0] $end +$var wire 32 Y$ product [31:0] $end +$var wire 40 Z$ acc_out [39:0] $end +$var parameter 32 [$ ACC_WIDTH $end +$var parameter 32 \$ DATA_WIDTH $end +$var parameter 64 ]$ PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 ^$ acc_in [39:0] $end +$var wire 16 _$ w [15:0] $end +$var wire 16 `$ x [15:0] $end +$var wire 40 a$ product_ext [39:0] $end +$var wire 32 b$ product [31:0] $end +$var wire 40 c$ acc_out [39:0] $end +$var parameter 32 d$ ACC_WIDTH $end +$var parameter 32 e$ DATA_WIDTH $end +$var parameter 64 f$ PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 g$ acc_in [39:0] $end +$var wire 16 h$ w [15:0] $end +$var wire 16 i$ x [15:0] $end +$var wire 40 j$ product_ext [39:0] $end +$var wire 32 k$ product [31:0] $end +$var wire 40 l$ acc_out [39:0] $end +$var parameter 32 m$ ACC_WIDTH $end +$var parameter 32 n$ DATA_WIDTH $end +$var parameter 64 o$ PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 p$ acc_in [39:0] $end +$var wire 16 q$ w [15:0] $end +$var wire 16 r$ x [15:0] $end +$var wire 40 s$ product_ext [39:0] $end +$var wire 32 t$ product [31:0] $end +$var wire 40 u$ acc_out [39:0] $end +$var parameter 32 v$ ACC_WIDTH $end +$var parameter 32 w$ DATA_WIDTH $end +$var parameter 64 x$ PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 y$ acc_in [39:0] $end +$var wire 16 z$ w [15:0] $end +$var wire 16 {$ x [15:0] $end +$var wire 40 |$ product_ext [39:0] $end +$var wire 32 }$ product [31:0] $end +$var wire 40 ~$ acc_out [39:0] $end +$var parameter 32 !% ACC_WIDTH $end +$var parameter 32 "% DATA_WIDTH $end +$var parameter 64 #% PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin GEN_NEURON[3] $end +$var parameter 3 $% n $end +$scope module u_neuron $end +$var wire 16 %% bias [15:0] $end +$var wire 16 &% bias_ext_small [15:0] $end +$var wire 1 + clk $end +$var wire 1 , rst $end +$var wire 1 - start $end +$var wire 512 '% w_bus [511:0] $end +$var wire 512 (% x_bus [511:0] $end +$var wire 128 )% x_group [127:0] $end +$var wire 128 *% w_group [127:0] $end +$var wire 40 +% final_value [39:0] $end +$var wire 40 ,% final_acc [39:0] $end +$var wire 40 -% bias_ext [39:0] $end +$var wire 40 .% acc_next [39:0] $end +$var parameter 32 /% ACC_WIDTH $end +$var parameter 32 0% DATA_WIDTH $end +$var parameter 32 1% FRAC_BITS $end +$var parameter 32 2% GROUPS $end +$var parameter 32 3% GROUP_INDEX_WIDTH $end +$var parameter 32 4% N_INPUTS $end +$var parameter 32 5% PARALLEL $end +$var reg 40 6% acc [39:0] $end +$var reg 1 7% busy $end +$var reg 1 8% done $end +$var reg 2 9% group_index [1:0] $end +$var reg 16 :% y [15:0] $end +$scope module u_mac8 $end +$var wire 40 ;% acc_in [39:0] $end +$var wire 128 <% w_bus [127:0] $end +$var wire 128 =% x_bus [127:0] $end +$var wire 40 >% sum [39:0] $end +$var wire 40 ?% s5 [39:0] $end +$var wire 40 @% s4 [39:0] $end +$var wire 40 A% s3 [39:0] $end +$var wire 40 B% s2 [39:0] $end +$var wire 40 C% s1 [39:0] $end +$var wire 40 D% s0 [39:0] $end +$var wire 40 E% m7 [39:0] $end +$var wire 40 F% m6 [39:0] $end +$var wire 40 G% m5 [39:0] $end +$var wire 40 H% m4 [39:0] $end +$var wire 40 I% m3 [39:0] $end +$var wire 40 J% m2 [39:0] $end +$var wire 40 K% m1 [39:0] $end +$var wire 40 L% m0 [39:0] $end +$var wire 40 M% acc_out [39:0] $end +$var parameter 32 N% ACC_WIDTH $end +$var parameter 32 O% DATA_WIDTH $end +$scope module mac0 $end +$var wire 40 P% acc_in [39:0] $end +$var wire 16 Q% w [15:0] $end +$var wire 16 R% x [15:0] $end +$var wire 40 S% product_ext [39:0] $end +$var wire 32 T% product [31:0] $end +$var wire 40 U% acc_out [39:0] $end +$var parameter 32 V% ACC_WIDTH $end +$var parameter 32 W% DATA_WIDTH $end +$var parameter 64 X% PROD_WIDTH $end +$upscope $end +$scope module mac1 $end +$var wire 40 Y% acc_in [39:0] $end +$var wire 16 Z% w [15:0] $end +$var wire 16 [% x [15:0] $end +$var wire 40 \% product_ext [39:0] $end +$var wire 32 ]% product [31:0] $end +$var wire 40 ^% acc_out [39:0] $end +$var parameter 32 _% ACC_WIDTH $end +$var parameter 32 `% DATA_WIDTH $end +$var parameter 64 a% PROD_WIDTH $end +$upscope $end +$scope module mac2 $end +$var wire 40 b% acc_in [39:0] $end +$var wire 16 c% w [15:0] $end +$var wire 16 d% x [15:0] $end +$var wire 40 e% product_ext [39:0] $end +$var wire 32 f% product [31:0] $end +$var wire 40 g% acc_out [39:0] $end +$var parameter 32 h% ACC_WIDTH $end +$var parameter 32 i% DATA_WIDTH $end +$var parameter 64 j% PROD_WIDTH $end +$upscope $end +$scope module mac3 $end +$var wire 40 k% acc_in [39:0] $end +$var wire 16 l% w [15:0] $end +$var wire 16 m% x [15:0] $end +$var wire 40 n% product_ext [39:0] $end +$var wire 32 o% product [31:0] $end +$var wire 40 p% acc_out [39:0] $end +$var parameter 32 q% ACC_WIDTH $end +$var parameter 32 r% DATA_WIDTH $end +$var parameter 64 s% PROD_WIDTH $end +$upscope $end +$scope module mac4 $end +$var wire 40 t% acc_in [39:0] $end +$var wire 16 u% w [15:0] $end +$var wire 16 v% x [15:0] $end +$var wire 40 w% product_ext [39:0] $end +$var wire 32 x% product [31:0] $end +$var wire 40 y% acc_out [39:0] $end +$var parameter 32 z% ACC_WIDTH $end +$var parameter 32 {% DATA_WIDTH $end +$var parameter 64 |% PROD_WIDTH $end +$upscope $end +$scope module mac5 $end +$var wire 40 }% acc_in [39:0] $end +$var wire 16 ~% w [15:0] $end +$var wire 16 !& x [15:0] $end +$var wire 40 "& product_ext [39:0] $end +$var wire 32 #& product [31:0] $end +$var wire 40 $& acc_out [39:0] $end +$var parameter 32 %& ACC_WIDTH $end +$var parameter 32 && DATA_WIDTH $end +$var parameter 64 '& PROD_WIDTH $end +$upscope $end +$scope module mac6 $end +$var wire 40 (& acc_in [39:0] $end +$var wire 16 )& w [15:0] $end +$var wire 16 *& x [15:0] $end +$var wire 40 +& product_ext [39:0] $end +$var wire 32 ,& product [31:0] $end +$var wire 40 -& acc_out [39:0] $end +$var parameter 32 .& ACC_WIDTH $end +$var parameter 32 /& DATA_WIDTH $end +$var parameter 64 0& PROD_WIDTH $end +$upscope $end +$scope module mac7 $end +$var wire 40 1& acc_in [39:0] $end +$var wire 16 2& w [15:0] $end +$var wire 16 3& x [15:0] $end +$var wire 40 4& product_ext [39:0] $end +$var wire 32 5& product [31:0] $end +$var wire 40 6& acc_out [39:0] $end +$var parameter 32 7& ACC_WIDTH $end +$var parameter 32 8& DATA_WIDTH $end +$var parameter 64 9& PROD_WIDTH $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope task run_layer $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +b100000 9& +b10000 8& +b101000 7& +b100000 0& +b10000 /& +b101000 .& +b100000 '& +b10000 && +b101000 %& +b100000 |% +b10000 {% +b101000 z% +b100000 s% +b10000 r% +b101000 q% +b100000 j% +b10000 i% +b101000 h% +b100000 a% +b10000 `% +b101000 _% +b100000 X% +b10000 W% +b101000 V% +b10000 O% +b101000 N% +b1000 5% +b100000 4% +b10 3% +b100 2% +b1000 1% +b10000 0% +b101000 /% +b11 $% +b100000 #% +b10000 "% +b101000 !% +b100000 x$ +b10000 w$ +b101000 v$ +b100000 o$ +b10000 n$ +b101000 m$ +b100000 f$ +b10000 e$ +b101000 d$ +b100000 ]$ +b10000 \$ +b101000 [$ +b100000 T$ +b10000 S$ +b101000 R$ +b100000 K$ +b10000 J$ +b101000 I$ +b100000 B$ +b10000 A$ +b101000 @$ +b10000 9$ +b101000 8$ +b1000 }# +b100000 |# +b10 {# +b100 z# +b1000 y# +b10000 x# +b101000 w# +b10 l# +b100000 k# +b10000 j# +b101000 i# +b100000 b# +b10000 a# +b101000 `# +b100000 Y# +b10000 X# +b101000 W# +b100000 P# +b10000 O# +b101000 N# +b100000 G# +b10000 F# +b101000 E# +b100000 ># +b10000 =# +b101000 <# +b100000 5# +b10000 4# +b101000 3# +b100000 ,# +b10000 +# +b101000 *# +b10000 ## +b101000 "# +b1000 g" +b100000 f" +b10 e" +b100 d" +b1000 c" +b10000 b" +b101000 a" +b1 V" +b100000 U" +b10000 T" +b101000 S" +b100000 L" +b10000 K" +b101000 J" +b100000 C" +b10000 B" +b101000 A" +b100000 :" +b10000 9" +b101000 8" +b100000 1" +b10000 0" +b101000 /" +b100000 (" +b10000 '" +b101000 &" +b100000 } +b10000 | +b101000 { +b100000 t +b10000 s +b101000 r +b10000 k +b101000 j +b1000 Q +b100000 P +b10 O +b100 N +b1000 M +b10000 L +b101000 K +b0 @ +b1000 ? +b100 > +b100000 = +b1000 < +b10000 ; +b101000 : +b1000 ) +b100 ( +b100000 ' +b1000 & +b10000 % +b101000 $ +$end +#0 +$dumpvars +bx 6& +bx 5& +bx 4& +bx 3& +bx 2& +b0 1& +bx -& +bx ,& +bx +& +bx *& +bx )& +b0 (& +bx $& +bx #& +bx "& +bx !& +bx ~% +b0 }% +bx y% +bx x% +bx w% +bx v% +bx u% +b0 t% +bx p% +bx o% +bx n% +bx m% +bx l% +b0 k% +bx g% +bx f% +bx e% +bx d% +bx c% +b0 b% +bx ^% +bx ]% +bx \% +bx [% +bx Z% +b0 Y% +bx U% +bx T% +bx S% +bx R% +bx Q% +b0 P% +bx M% +bx L% +bx K% +bx J% +bx I% +bx H% +bx G% +bx F% +bx E% +bx D% +bx C% +bx B% +bx A% +bx @% +bx ?% +bx >% +bx =% +bx <% +bx ;% +bx :% +bx 9% +x8% +x7% +bx 6% +bx .% +b0 -% +bx ,% +bx +% +bx *% +bx )% +b0 (% +b0 '% +b0 &% +b0 %% +bx ~$ +bx }$ +bx |$ +bx {$ +bx z$ +b0 y$ +bx u$ +bx t$ +bx s$ +bx r$ +bx q$ +b0 p$ +bx l$ +bx k$ +bx j$ +bx i$ +bx h$ +b0 g$ +bx c$ +bx b$ +bx a$ +bx `$ +bx _$ +b0 ^$ +bx Z$ +bx Y$ +bx X$ +bx W$ +bx V$ +b0 U$ +bx Q$ +bx P$ +bx O$ +bx N$ +bx M$ +b0 L$ +bx H$ +bx G$ +bx F$ +bx E$ +bx D$ +b0 C$ +bx ?$ +bx >$ +bx =$ +bx <$ +bx ;$ +b0 :$ +bx 7$ +bx 6$ +bx 5$ +bx 4$ +bx 3$ +bx 2$ +bx 1$ +bx 0$ +bx /$ +bx .$ +bx -$ +bx ,$ +bx +$ +bx *$ +bx )$ +bx ($ +bx '$ +bx &$ +bx %$ +bx $$ +bx #$ +x"$ +x!$ +bx ~# +bx v# +b0 u# +bx t# +bx s# +bx r# +bx q# +b0 p# +b0 o# +b0 n# +b0 m# +bx h# +bx g# +bx f# +bx e# +bx d# +b0 c# +bx _# +bx ^# +bx ]# +bx \# +bx [# +b0 Z# +bx V# +bx U# +bx T# +bx S# +bx R# +b0 Q# +bx M# +bx L# +bx K# +bx J# +bx I# +b0 H# +bx D# +bx C# +bx B# +bx A# +bx @# +b0 ?# +bx ;# +bx :# +bx 9# +bx 8# +bx 7# +b0 6# +bx 2# +bx 1# +bx 0# +bx /# +bx .# +b0 -# +bx )# +bx (# +bx '# +bx &# +bx %# +b0 $# +bx !# +bx ~" +bx }" +bx |" +bx {" +bx z" +bx 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+b10000000000000000000000 ;% +1+ +#70000 +0+ +#75000 +0" +b0 8 +08% +0"$ +0j" +0T +b100000000000000 1 +1+ diff --git a/sim/parametric_32x4 b/sim/parametric_32x4 new file mode 100755 index 0000000..0b966e7 --- /dev/null +++ b/sim/parametric_32x4 @@ -0,0 +1,2118 @@ +#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp +:ivl_version "13.0 (stable)" "(v13_0)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi"; +:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi"; +S_0x105029620 .scope package, "$unit" "$unit" 2 1; + .timescale 0 0; +S_0x10502b920 .scope module, "tb" "tb" 3 3; + .timescale -9 -12; +P_0x10502b5e0 .param/l "ACC_WIDTH" 0 3 10, +C4<00000000000000000000000000101000>; +P_0x10502b620 .param/l "DATA_WIDTH" 0 3 5, +C4<00000000000000000000000000010000>; +P_0x10502b660 .param/l "FRAC_BITS" 0 3 6, +C4<00000000000000000000000000001000>; +P_0x10502b6a0 .param/l "N_INPUTS" 0 3 7, +C4<00000000000000000000000000100000>; +P_0x10502b6e0 .param/l "N_NEURONS" 0 3 8, +C4<00000000000000000000000000000100>; +P_0x10502b720 .param/l "PARALLEL" 0 3 9, +C4<00000000000000000000000000001000>; +v0x8cb0d9860_0 .var/s "bias_bus", 63 0; +v0x8cb0d9900_0 .net "busy", 0 0, L_0x8cb0acc80; 1 drivers +v0x8cb0d99a0_0 .var "clk", 0 0; +v0x8cb0d9a40_0 .net "done", 0 0, L_0x8cb0acbe0; 1 drivers +v0x8cb0d9ae0_0 .var/i "errors", 31 0; +v0x8cb0d9b80_0 .var/i "expected", 31 0; +v0x8cb0d9c20_0 .var/i "i", 31 0; +v0x8cb0d9cc0_0 .var "rst", 0 0; +v0x8cb0d9d60_0 .var "start", 0 0; +v0x8cb0d9e00_0 .var/s "weights_bus", 2047 0; +v0x8cb0d9ea0_0 .var/s "x_bus", 511 0; +v0x8cb0d9f40_0 .net/s "y_bus", 63 0, L_0x8cb0e06e0; 1 drivers +S_0x10502b2a0 .scope module, "dut" "layer" 3 42, 4 1 0, S_0x10502b920; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 512 "x_bus"; + .port_info 4 /INPUT 2048 "weights_bus"; + .port_info 5 /INPUT 64 "bias_bus"; + .port_info 6 /OUTPUT 64 "y_bus"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x10502af60 .param/l "ACC_WIDTH" 0 4 7, +C4<00000000000000000000000000101000>; +P_0x10502afa0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>; +P_0x10502afe0 .param/l "FRAC_BITS" 0 4 3, +C4<00000000000000000000000000001000>; +P_0x10502b020 .param/l "N_INPUTS" 0 4 4, +C4<00000000000000000000000000100000>; +P_0x10502b060 .param/l "N_NEURONS" 0 4 5, +C4<00000000000000000000000000000100>; +P_0x10502b0a0 .param/l "PARALLEL" 0 4 6, +C4<00000000000000000000000000001000>; +v0x8cb0d9040_0 .net/s "bias_bus", 63 0, v0x8cb0d9860_0; 1 drivers +v0x8cb0d90e0_0 .net "busy", 0 0, L_0x8cb0acc80; alias, 1 drivers +v0x8cb0d9180_0 .net "clk", 0 0, v0x8cb0d99a0_0; 1 drivers +v0x8cb0d9220_0 .net "done", 0 0, L_0x8cb0acbe0; alias, 1 drivers +v0x8cb0d92c0_0 .net "neuron_busy", 3 0, L_0x8cb0e0780; 1 drivers +v0x8cb0d9360_0 .net "neuron_done", 3 0, L_0x8cb0e0820; 1 drivers +v0x8cb0d9400_0 .net "rst", 0 0, v0x8cb0d9cc0_0; 1 drivers +v0x8cb0d94a0_0 .net "start", 0 0, v0x8cb0d9d60_0; 1 drivers +v0x8cb0d9540_0 .net/s "weights_bus", 2047 0, v0x8cb0d9e00_0; 1 drivers +v0x8cb0d95e0_0 .net/s "x_bus", 511 0, v0x8cb0d9ea0_0; 1 drivers +v0x8cb0d9680_0 .net/s "y_bus", 63 0, L_0x8cb0e06e0; alias, 1 drivers +L_0x8cad057c0 .part v0x8cb0d9e00_0, 0, 512; +L_0x8cad05860 .part v0x8cb0d9860_0, 0, 16; +L_0x8cad070c0 .part v0x8cb0d9e00_0, 512, 512; +L_0x8cad07160 .part v0x8cb0d9860_0, 16, 16; +L_0x8cad28a00 .part v0x8cb0d9e00_0, 1024, 512; +L_0x8cad28aa0 .part v0x8cb0d9860_0, 32, 16; +L_0x8cad2a300 .part v0x8cb0d9e00_0, 1536, 512; +L_0x8cad2a3a0 .part v0x8cb0d9860_0, 48, 16; +L_0x8cb0e06e0 .concat8 [ 16 16 16 16], v0x8cb0c9180_0, v0x8cb0ce620_0, v0x8cb0d3ac0_0, v0x8cb0d8fa0_0; +L_0x8cb0e0780 .concat8 [ 1 1 1 1], v0x8cb0c8a00_0, v0x8cb0cdea0_0, v0x8cb0d3340_0, v0x8cb0d8820_0; +L_0x8cb0e0820 .concat8 [ 1 1 1 1], v0x8cb0c8b40_0, v0x8cb0cdfe0_0, v0x8cb0d3480_0, v0x8cb0d8960_0; +L_0x8cb0acc80 .reduce/or L_0x8cb0e0780; +L_0x8cb0acbe0 .reduce/and L_0x8cb0e0820; +S_0x10502ac20 .scope generate, "GEN_NEURON[0]" "GEN_NEURON[0]" 4 35, 4 35 0, S_0x10502b2a0; + .timescale 0 0; +P_0x8cb04e980 .param/l "n" 1 4 35, +C4<00>; +S_0x10502a8e0 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x10502ac20; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 512 "x_bus"; + .port_info 4 /INPUT 512 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x10502a5a0 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x10502a5e0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x10502a620 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x10502a660 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000000100>; +P_0x10502a6a0 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000010>; +P_0x10502a6e0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000000100000>; +P_0x10502a720 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x10501fcf0 .functor BUFZ 16, L_0x8cad05860, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8cb0c7b60_0 .net *"_ivl_0", 31 0, L_0x8cb0d9fe0; 1 drivers +v0x8cb0c7c00_0 .net *"_ivl_11", 31 0, L_0x8cb0da120; 1 drivers +v0x8cb0c7ca0_0 .net *"_ivl_14", 31 0, L_0x8cb0da1c0; 1 drivers +L_0x8ca8780e8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c7d40_0 .net *"_ivl_17", 29 0, L_0x8ca8780e8; 1 drivers +L_0x8ca878130 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c7de0_0 .net/2u *"_ivl_18", 31 0, L_0x8ca878130; 1 drivers +v0x8cb0c7e80_0 .net *"_ivl_21", 31 0, L_0x8cb0da260; 1 drivers +L_0x8ca878178 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c7f20_0 .net/2u *"_ivl_22", 31 0, L_0x8ca878178; 1 drivers +v0x8cb0c8000_0 .net *"_ivl_25", 31 0, L_0x8cb0da300; 1 drivers +L_0x8ca878010 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c80a0_0 .net *"_ivl_3", 29 0, L_0x8ca878010; 1 drivers +v0x8cb0c8140_0 .net *"_ivl_31", 0 0, L_0x8cad05540; 1 drivers +v0x8cb0c81e0_0 .net *"_ivl_33", 23 0, L_0x8cad055e0; 1 drivers +v0x8cb0c8280_0 .net *"_ivl_36", 39 0, L_0x8cb0db840; 1 drivers +v0x8cb0c8320_0 .net *"_ivl_38", 31 0, L_0x8cad05680; 1 drivers +L_0x8ca878058 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c83c0_0 .net/2u *"_ivl_4", 31 0, L_0x8ca878058; 1 drivers +L_0x8ca878400 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c8460_0 .net *"_ivl_40", 7 0, L_0x8ca878400; 1 drivers +v0x8cb0c8500_0 .net *"_ivl_46", 31 0, L_0x8cad05720; 1 drivers +v0x8cb0c85a0_0 .net *"_ivl_7", 31 0, L_0x8cb0da080; 1 drivers +L_0x8ca8780a0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c8640_0 .net/2u *"_ivl_8", 31 0, L_0x8ca8780a0; 1 drivers +v0x8cb0c86e0_0 .var/s "acc", 39 0; +v0x8cb0c8780_0 .net/s "acc_next", 39 0, L_0x8cac66bc0; 1 drivers +v0x8cb0c8820_0 .net/s "bias", 15 0, L_0x8cad05860; 1 drivers +v0x8cb0c88c0_0 .net/s "bias_ext", 39 0, L_0x8cb0db7a0; 1 drivers +v0x8cb0c8960_0 .net/s "bias_ext_small", 15 0, L_0x10501fcf0; 1 drivers +v0x8cb0c8a00_0 .var "busy", 0 0; +v0x8cb0c8aa0_0 .net "clk", 0 0, v0x8cb0d99a0_0; alias, 1 drivers +v0x8cb0c8b40_0 .var "done", 0 0; +v0x8cb0c8be0_0 .net/s "final_acc", 39 0, L_0x8cac66c60; 1 drivers +v0x8cb0c8c80_0 .net/s "final_value", 39 0, L_0x8cb0db8e0; 1 drivers +v0x8cb0c8d20_0 .var "group_index", 1 0; +v0x8cb0c8dc0_0 .net "rst", 0 0, v0x8cb0d9cc0_0; alias, 1 drivers +v0x8cb0c8e60_0 .net "start", 0 0, v0x8cb0d9d60_0; alias, 1 drivers +v0x8cb0c8f00_0 .net/s "w_bus", 511 0, L_0x8cad057c0; 1 drivers +v0x8cb0c8fa0_0 .net/s "w_group", 127 0, L_0x8cad040a0; 1 drivers +v0x8cb0c9040_0 .net/s "x_bus", 511 0, v0x8cb0d9ea0_0; alias, 1 drivers +v0x8cb0c90e0_0 .net/s "x_group", 127 0, L_0x8cad04000; 1 drivers +v0x8cb0c9180_0 .var/s "y", 15 0; +E_0x8cacab2c0 .event posedge, v0x8cb0c8aa0_0; +L_0x8cb0d9fe0 .concat [ 2 30 0 0], v0x8cb0c8d20_0, L_0x8ca878010; +L_0x8cb0da080 .arith/mult 32, L_0x8cb0d9fe0, L_0x8ca878058; +L_0x8cb0da120 .arith/mult 32, L_0x8cb0da080, L_0x8ca8780a0; +L_0x8cad04000 .part/v v0x8cb0d9ea0_0, L_0x8cb0da120, 128; +L_0x8cb0da1c0 .concat [ 2 30 0 0], v0x8cb0c8d20_0, L_0x8ca8780e8; +L_0x8cb0da260 .arith/mult 32, L_0x8cb0da1c0, L_0x8ca878130; +L_0x8cb0da300 .arith/mult 32, L_0x8cb0da260, L_0x8ca878178; +L_0x8cad040a0 .part/v L_0x8cad057c0, L_0x8cb0da300, 128; +L_0x8cad05540 .part L_0x10501fcf0, 15, 1; +L_0x8cad055e0 .repeat 24, 24, L_0x8cad05540; +L_0x8cb0db7a0 .concat [ 16 24 0 0], L_0x10501fcf0, L_0x8cad055e0; +L_0x8cad05680 .part L_0x8cb0db7a0, 0, 32; +L_0x8cb0db840 .concat [ 8 32 0 0], L_0x8ca878400, L_0x8cad05680; +L_0x8cac66c60 .arith/sum 40, L_0x8cac66bc0, L_0x8cb0db840; +L_0x8cad05720 .part L_0x8cac66c60, 8, 32; +L_0x8cb0db8e0 .extend/s 40, L_0x8cad05720; +S_0x105024960 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x10502a8e0; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb064200 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8cb064240 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8cb0c6f80_0 .net/s "acc_in", 39 0, v0x8cb0c86e0_0; 1 drivers +v0x8cb0c7020_0 .net/s "acc_out", 39 0, L_0x8cac66bc0; alias, 1 drivers +v0x8cb0c70c0_0 .net/s "m0", 39 0, L_0x8cac66120; 1 drivers +v0x8cb0c7160_0 .net/s "m1", 39 0, L_0x8cac661c0; 1 drivers +v0x8cb0c7200_0 .net/s "m2", 39 0, L_0x8cac663a0; 1 drivers +v0x8cb0c72a0_0 .net/s "m3", 39 0, L_0x8cac66440; 1 drivers +v0x8cb0c7340_0 .net/s "m4", 39 0, L_0x8cac664e0; 1 drivers +v0x8cb0c73e0_0 .net/s "m5", 39 0, L_0x8cac66580; 1 drivers +v0x8cb0c7480_0 .net/s "m6", 39 0, L_0x8cac66620; 1 drivers +v0x8cb0c7520_0 .net/s "m7", 39 0, L_0x8cac666c0; 1 drivers +v0x8cb0c75c0_0 .net/s "s0", 39 0, L_0x8cac66760; 1 drivers +v0x8cb0c7660_0 .net/s "s1", 39 0, L_0x8cac66800; 1 drivers +v0x8cb0c7700_0 .net/s "s2", 39 0, L_0x8cac668a0; 1 drivers +v0x8cb0c77a0_0 .net/s "s3", 39 0, L_0x8cac66940; 1 drivers +v0x8cb0c7840_0 .net/s "s4", 39 0, L_0x8cac669e0; 1 drivers +v0x8cb0c78e0_0 .net/s "s5", 39 0, L_0x8cac66a80; 1 drivers +v0x8cb0c7980_0 .net/s "sum", 39 0, L_0x8cac66b20; 1 drivers +v0x8cb0c7a20_0 .net/s "w_bus", 127 0, L_0x8cad040a0; alias, 1 drivers +v0x8cb0c7ac0_0 .net/s "x_bus", 127 0, L_0x8cad04000; alias, 1 drivers +L_0x8cad04280 .part L_0x8cad04000, 0, 16; +L_0x8cad04320 .part L_0x8cad040a0, 0, 16; +L_0x8cad04500 .part L_0x8cad04000, 16, 16; +L_0x8cad045a0 .part L_0x8cad040a0, 16, 16; +L_0x8cad04780 .part L_0x8cad04000, 32, 16; +L_0x8cad04820 .part L_0x8cad040a0, 32, 16; +L_0x8cad04a00 .part L_0x8cad04000, 48, 16; +L_0x8cad04aa0 .part L_0x8cad040a0, 48, 16; +L_0x8cad04c80 .part L_0x8cad04000, 64, 16; +L_0x8cad04d20 .part L_0x8cad040a0, 64, 16; +L_0x8cad04f00 .part L_0x8cad04000, 80, 16; +L_0x8cad04fa0 .part L_0x8cad040a0, 80, 16; +L_0x8cad05180 .part L_0x8cad04000, 96, 16; +L_0x8cad05220 .part L_0x8cad040a0, 96, 16; +L_0x8cad05400 .part L_0x8cad04000, 112, 16; +L_0x8cad054a0 .part L_0x8cad040a0, 112, 16; +L_0x8cac66760 .arith/sum 40, L_0x8cac66120, L_0x8cac661c0; +L_0x8cac66800 .arith/sum 40, L_0x8cac663a0, L_0x8cac66440; +L_0x8cac668a0 .arith/sum 40, L_0x8cac664e0, L_0x8cac66580; +L_0x8cac66940 .arith/sum 40, L_0x8cac66620, L_0x8cac666c0; +L_0x8cac669e0 .arith/sum 40, L_0x8cac66760, L_0x8cac66800; +L_0x8cac66a80 .arith/sum 40, L_0x8cac668a0, L_0x8cac66940; +L_0x8cac66b20 .arith/sum 40, L_0x8cac669e0, L_0x8cac66a80; +L_0x8cac66bc0 .arith/sum 40, v0x8cb0c86e0_0, L_0x8cac66b20; +S_0x105024ae0 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x105024960; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb0380c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038100 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038140 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x10502a760_0 .net/s *"_ivl_0", 31 0, L_0x8cb0da3a0; 1 drivers +v0x10502aa60_0 .net/s *"_ivl_2", 31 0, L_0x8cb0da440; 1 drivers +v0x10502ada0_0 .net *"_ivl_7", 0 0, L_0x8cad04140; 1 drivers +v0x10502b0e0_0 .net *"_ivl_9", 7 0, L_0x8cad041e0; 1 drivers +L_0x8ca8781c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c4000_0 .net/s "acc_in", 39 0, L_0x8ca8781c0; 1 drivers +v0x8cb0c40a0_0 .net/s "acc_out", 39 0, L_0x8cac66120; alias, 1 drivers +v0x8cb0c4140_0 .net/s "product", 31 0, L_0x8cb0da4e0; 1 drivers +v0x8cb0c41e0_0 .net/s "product_ext", 39 0, L_0x8cb0da580; 1 drivers +v0x8cb0c4280_0 .net/s "w", 15 0, L_0x8cad04320; 1 drivers +v0x8cb0c4320_0 .net/s "x", 15 0, L_0x8cad04280; 1 drivers +L_0x8cb0da3a0 .extend/s 32, L_0x8cad04280; +L_0x8cb0da440 .extend/s 32, L_0x8cad04320; +L_0x8cb0da4e0 .arith/mult 32, L_0x8cb0da3a0, L_0x8cb0da440; +L_0x8cad04140 .part L_0x8cb0da4e0, 31, 1; +L_0x8cad041e0 .repeat 8, 8, L_0x8cad04140; +L_0x8cb0da580 .concat [ 32 8 0 0], L_0x8cb0da4e0, L_0x8cad041e0; +L_0x8cac66120 .arith/sum 40, L_0x8ca8781c0, L_0x8cb0da580; +S_0x10501f9f0 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x105024960; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038180 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb0381c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038200 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c43c0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0da620; 1 drivers +v0x8cb0c4460_0 .net/s *"_ivl_2", 31 0, L_0x8cb0da6c0; 1 drivers +v0x8cb0c4500_0 .net *"_ivl_7", 0 0, L_0x8cad043c0; 1 drivers +v0x8cb0c45a0_0 .net *"_ivl_9", 7 0, L_0x8cad04460; 1 drivers +L_0x8ca878208 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c4640_0 .net/s "acc_in", 39 0, L_0x8ca878208; 1 drivers +v0x8cb0c46e0_0 .net/s "acc_out", 39 0, L_0x8cac661c0; alias, 1 drivers +v0x8cb0c4780_0 .net/s "product", 31 0, L_0x8cb0da760; 1 drivers +v0x8cb0c4820_0 .net/s "product_ext", 39 0, L_0x8cb0da800; 1 drivers +v0x8cb0c48c0_0 .net/s "w", 15 0, L_0x8cad045a0; 1 drivers +v0x8cb0c4960_0 .net/s "x", 15 0, L_0x8cad04500; 1 drivers +L_0x8cb0da620 .extend/s 32, L_0x8cad04500; +L_0x8cb0da6c0 .extend/s 32, L_0x8cad045a0; +L_0x8cb0da760 .arith/mult 32, L_0x8cb0da620, L_0x8cb0da6c0; +L_0x8cad043c0 .part L_0x8cb0da760, 31, 1; +L_0x8cad04460 .repeat 8, 8, L_0x8cad043c0; +L_0x8cb0da800 .concat [ 32 8 0 0], L_0x8cb0da760, L_0x8cad04460; +L_0x8cac661c0 .arith/sum 40, L_0x8ca878208, L_0x8cb0da800; +S_0x10501fb70 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x105024960; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038240 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038280 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb0382c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c4a00_0 .net/s *"_ivl_0", 31 0, L_0x8cb0da8a0; 1 drivers +v0x8cb0c4aa0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0da940; 1 drivers +v0x8cb0c4b40_0 .net *"_ivl_7", 0 0, L_0x8cad04640; 1 drivers +v0x8cb0c4be0_0 .net *"_ivl_9", 7 0, L_0x8cad046e0; 1 drivers +L_0x8ca878250 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c4c80_0 .net/s "acc_in", 39 0, L_0x8ca878250; 1 drivers +v0x8cb0c4d20_0 .net/s "acc_out", 39 0, L_0x8cac663a0; alias, 1 drivers +v0x8cb0c4dc0_0 .net/s "product", 31 0, L_0x8cb0da9e0; 1 drivers +v0x8cb0c4e60_0 .net/s "product_ext", 39 0, L_0x8cb0daa80; 1 drivers +v0x8cb0c4f00_0 .net/s "w", 15 0, L_0x8cad04820; 1 drivers +v0x8cb0c4fa0_0 .net/s "x", 15 0, L_0x8cad04780; 1 drivers +L_0x8cb0da8a0 .extend/s 32, L_0x8cad04780; +L_0x8cb0da940 .extend/s 32, L_0x8cad04820; +L_0x8cb0da9e0 .arith/mult 32, L_0x8cb0da8a0, L_0x8cb0da940; +L_0x8cad04640 .part L_0x8cb0da9e0, 31, 1; +L_0x8cad046e0 .repeat 8, 8, L_0x8cad04640; +L_0x8cb0daa80 .concat [ 32 8 0 0], L_0x8cb0da9e0, L_0x8cad046e0; +L_0x8cac663a0 .arith/sum 40, L_0x8ca878250, L_0x8cb0daa80; +S_0x105018b90 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x105024960; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038300 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038340 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038380 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c5040_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dab20; 1 drivers +v0x8cb0c50e0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dabc0; 1 drivers +v0x8cb0c5180_0 .net *"_ivl_7", 0 0, L_0x8cad048c0; 1 drivers +v0x8cb0c5220_0 .net *"_ivl_9", 7 0, L_0x8cad04960; 1 drivers +L_0x8ca878298 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c52c0_0 .net/s "acc_in", 39 0, L_0x8ca878298; 1 drivers +v0x8cb0c5360_0 .net/s "acc_out", 39 0, L_0x8cac66440; alias, 1 drivers +v0x8cb0c5400_0 .net/s "product", 31 0, L_0x8cb0dac60; 1 drivers +v0x8cb0c54a0_0 .net/s "product_ext", 39 0, L_0x8cb0dad00; 1 drivers +v0x8cb0c5540_0 .net/s "w", 15 0, L_0x8cad04aa0; 1 drivers +v0x8cb0c55e0_0 .net/s "x", 15 0, L_0x8cad04a00; 1 drivers +L_0x8cb0dab20 .extend/s 32, L_0x8cad04a00; +L_0x8cb0dabc0 .extend/s 32, L_0x8cad04aa0; +L_0x8cb0dac60 .arith/mult 32, L_0x8cb0dab20, L_0x8cb0dabc0; +L_0x8cad048c0 .part L_0x8cb0dac60, 31, 1; +L_0x8cad04960 .repeat 8, 8, L_0x8cad048c0; +L_0x8cb0dad00 .concat [ 32 8 0 0], L_0x8cb0dac60, L_0x8cad04960; +L_0x8cac66440 .arith/sum 40, L_0x8ca878298, L_0x8cb0dad00; +S_0x8cad1c000 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x105024960; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb0383c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038400 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038440 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c5680_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dada0; 1 drivers +v0x8cb0c5720_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dae40; 1 drivers +v0x8cb0c57c0_0 .net *"_ivl_7", 0 0, L_0x8cad04b40; 1 drivers +v0x8cb0c5860_0 .net *"_ivl_9", 7 0, L_0x8cad04be0; 1 drivers +L_0x8ca8782e0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c5900_0 .net/s "acc_in", 39 0, L_0x8ca8782e0; 1 drivers +v0x8cb0c59a0_0 .net/s "acc_out", 39 0, L_0x8cac664e0; alias, 1 drivers +v0x8cb0c5a40_0 .net/s "product", 31 0, L_0x8cb0daee0; 1 drivers +v0x8cb0c5ae0_0 .net/s "product_ext", 39 0, L_0x8cb0daf80; 1 drivers +v0x8cb0c5b80_0 .net/s "w", 15 0, L_0x8cad04d20; 1 drivers +v0x8cb0c5c20_0 .net/s "x", 15 0, L_0x8cad04c80; 1 drivers +L_0x8cb0dada0 .extend/s 32, L_0x8cad04c80; +L_0x8cb0dae40 .extend/s 32, L_0x8cad04d20; +L_0x8cb0daee0 .arith/mult 32, L_0x8cb0dada0, L_0x8cb0dae40; +L_0x8cad04b40 .part L_0x8cb0daee0, 31, 1; +L_0x8cad04be0 .repeat 8, 8, L_0x8cad04b40; +L_0x8cb0daf80 .concat [ 32 8 0 0], L_0x8cb0daee0, L_0x8cad04be0; +L_0x8cac664e0 .arith/sum 40, L_0x8ca8782e0, L_0x8cb0daf80; +S_0x8cad1c180 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x105024960; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038480 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb0384c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038500 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c5cc0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0db020; 1 drivers +v0x8cb0c5d60_0 .net/s *"_ivl_2", 31 0, L_0x8cb0db0c0; 1 drivers +v0x8cb0c5e00_0 .net *"_ivl_7", 0 0, L_0x8cad04dc0; 1 drivers +v0x8cb0c5ea0_0 .net *"_ivl_9", 7 0, L_0x8cad04e60; 1 drivers +L_0x8ca878328 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c5f40_0 .net/s "acc_in", 39 0, L_0x8ca878328; 1 drivers +v0x8cb0c5fe0_0 .net/s "acc_out", 39 0, L_0x8cac66580; alias, 1 drivers +v0x8cb0c6080_0 .net/s "product", 31 0, L_0x8cb0db160; 1 drivers +v0x8cb0c6120_0 .net/s "product_ext", 39 0, L_0x8cb0db200; 1 drivers +v0x8cb0c61c0_0 .net/s "w", 15 0, L_0x8cad04fa0; 1 drivers +v0x8cb0c6260_0 .net/s "x", 15 0, L_0x8cad04f00; 1 drivers +L_0x8cb0db020 .extend/s 32, L_0x8cad04f00; +L_0x8cb0db0c0 .extend/s 32, L_0x8cad04fa0; +L_0x8cb0db160 .arith/mult 32, L_0x8cb0db020, L_0x8cb0db0c0; +L_0x8cad04dc0 .part L_0x8cb0db160, 31, 1; +L_0x8cad04e60 .repeat 8, 8, L_0x8cad04dc0; +L_0x8cb0db200 .concat [ 32 8 0 0], L_0x8cb0db160, L_0x8cad04e60; +L_0x8cac66580 .arith/sum 40, L_0x8ca878328, L_0x8cb0db200; +S_0x8cad1c300 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x105024960; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038540 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038580 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb0385c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c6300_0 .net/s *"_ivl_0", 31 0, L_0x8cb0db2a0; 1 drivers +v0x8cb0c63a0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0db340; 1 drivers +v0x8cb0c6440_0 .net *"_ivl_7", 0 0, L_0x8cad05040; 1 drivers +v0x8cb0c64e0_0 .net *"_ivl_9", 7 0, L_0x8cad050e0; 1 drivers +L_0x8ca878370 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c6580_0 .net/s "acc_in", 39 0, L_0x8ca878370; 1 drivers +v0x8cb0c6620_0 .net/s "acc_out", 39 0, L_0x8cac66620; alias, 1 drivers +v0x8cb0c66c0_0 .net/s "product", 31 0, L_0x8cb0db3e0; 1 drivers +v0x8cb0c6760_0 .net/s "product_ext", 39 0, L_0x8cb0db480; 1 drivers +v0x8cb0c6800_0 .net/s "w", 15 0, L_0x8cad05220; 1 drivers +v0x8cb0c68a0_0 .net/s "x", 15 0, L_0x8cad05180; 1 drivers +L_0x8cb0db2a0 .extend/s 32, L_0x8cad05180; +L_0x8cb0db340 .extend/s 32, L_0x8cad05220; +L_0x8cb0db3e0 .arith/mult 32, L_0x8cb0db2a0, L_0x8cb0db340; +L_0x8cad05040 .part L_0x8cb0db3e0, 31, 1; +L_0x8cad050e0 .repeat 8, 8, L_0x8cad05040; +L_0x8cb0db480 .concat [ 32 8 0 0], L_0x8cb0db3e0, L_0x8cad050e0; +L_0x8cac66620 .arith/sum 40, L_0x8ca878370, L_0x8cb0db480; +S_0x8cad1c480 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x105024960; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038600 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038640 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038680 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c6940_0 .net/s *"_ivl_0", 31 0, L_0x8cb0db520; 1 drivers +v0x8cb0c69e0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0db5c0; 1 drivers +v0x8cb0c6a80_0 .net *"_ivl_7", 0 0, L_0x8cad052c0; 1 drivers +v0x8cb0c6b20_0 .net *"_ivl_9", 7 0, L_0x8cad05360; 1 drivers +L_0x8ca8783b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c6bc0_0 .net/s "acc_in", 39 0, L_0x8ca8783b8; 1 drivers +v0x8cb0c6c60_0 .net/s "acc_out", 39 0, L_0x8cac666c0; alias, 1 drivers +v0x8cb0c6d00_0 .net/s "product", 31 0, L_0x8cb0db660; 1 drivers +v0x8cb0c6da0_0 .net/s "product_ext", 39 0, L_0x8cb0db700; 1 drivers +v0x8cb0c6e40_0 .net/s "w", 15 0, L_0x8cad054a0; 1 drivers +v0x8cb0c6ee0_0 .net/s "x", 15 0, L_0x8cad05400; 1 drivers +L_0x8cb0db520 .extend/s 32, L_0x8cad05400; +L_0x8cb0db5c0 .extend/s 32, L_0x8cad054a0; +L_0x8cb0db660 .arith/mult 32, L_0x8cb0db520, L_0x8cb0db5c0; +L_0x8cad052c0 .part L_0x8cb0db660, 31, 1; +L_0x8cad05360 .repeat 8, 8, L_0x8cad052c0; +L_0x8cb0db700 .concat [ 32 8 0 0], L_0x8cb0db660, L_0x8cad05360; +L_0x8cac666c0 .arith/sum 40, L_0x8ca8783b8, L_0x8cb0db700; +S_0x8cad1c600 .scope generate, "GEN_NEURON[1]" "GEN_NEURON[1]" 4 35, 4 35 0, S_0x10502b2a0; + .timescale 0 0; +P_0x8cb04e9c0 .param/l "n" 1 4 35, +C4<01>; +S_0x8cad1c780 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8cad1c600; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 512 "x_bus"; + .port_info 4 /INPUT 512 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x105018d10 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x105018d50 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x105018d90 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x105018dd0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000000100>; +P_0x105018e10 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000010>; +P_0x105018e50 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000000100000>; +P_0x105018e90 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x10502b180 .functor BUFZ 16, L_0x8cad07160, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8cb0cd040_0 .net *"_ivl_0", 31 0, L_0x8cb0db980; 1 drivers +v0x8cb0cd0e0_0 .net *"_ivl_11", 31 0, L_0x8cb0dbac0; 1 drivers +v0x8cb0cd180_0 .net *"_ivl_14", 31 0, L_0x8cb0dbb60; 1 drivers +L_0x8ca878520 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cd220_0 .net *"_ivl_17", 29 0, L_0x8ca878520; 1 drivers +L_0x8ca878568 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cd2c0_0 .net/2u *"_ivl_18", 31 0, L_0x8ca878568; 1 drivers +v0x8cb0cd360_0 .net *"_ivl_21", 31 0, L_0x8cb0dbc00; 1 drivers +L_0x8ca8785b0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cd400_0 .net/2u *"_ivl_22", 31 0, L_0x8ca8785b0; 1 drivers +v0x8cb0cd4a0_0 .net *"_ivl_25", 31 0, L_0x8cb0dbca0; 1 drivers +L_0x8ca878448 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cd540_0 .net *"_ivl_3", 29 0, L_0x8ca878448; 1 drivers +v0x8cb0cd5e0_0 .net *"_ivl_31", 0 0, L_0x8cad06e40; 1 drivers +v0x8cb0cd680_0 .net *"_ivl_33", 23 0, L_0x8cad06ee0; 1 drivers +v0x8cb0cd720_0 .net *"_ivl_36", 39 0, L_0x8cb0dd220; 1 drivers +v0x8cb0cd7c0_0 .net *"_ivl_38", 31 0, L_0x8cad06f80; 1 drivers +L_0x8ca878490 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cd860_0 .net/2u *"_ivl_4", 31 0, L_0x8ca878490; 1 drivers +L_0x8ca878838 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cd900_0 .net *"_ivl_40", 7 0, L_0x8ca878838; 1 drivers +v0x8cb0cd9a0_0 .net *"_ivl_46", 31 0, L_0x8cad07020; 1 drivers +v0x8cb0cda40_0 .net *"_ivl_7", 31 0, L_0x8cb0dba20; 1 drivers +L_0x8ca8784d8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cdae0_0 .net/2u *"_ivl_8", 31 0, L_0x8ca8784d8; 1 drivers +v0x8cb0cdb80_0 .var/s "acc", 39 0; +v0x8cb0cdc20_0 .net/s "acc_next", 39 0, L_0x8cac67660; 1 drivers +v0x8cb0cdcc0_0 .net/s "bias", 15 0, L_0x8cad07160; 1 drivers +v0x8cb0cdd60_0 .net/s "bias_ext", 39 0, L_0x8cb0dd180; 1 drivers +v0x8cb0cde00_0 .net/s "bias_ext_small", 15 0, L_0x10502b180; 1 drivers +v0x8cb0cdea0_0 .var "busy", 0 0; +v0x8cb0cdf40_0 .net "clk", 0 0, v0x8cb0d99a0_0; alias, 1 drivers +v0x8cb0cdfe0_0 .var "done", 0 0; +v0x8cb0ce080_0 .net/s "final_acc", 39 0, L_0x8cac67700; 1 drivers +v0x8cb0ce120_0 .net/s "final_value", 39 0, L_0x8cb0dd2c0; 1 drivers +v0x8cb0ce1c0_0 .var "group_index", 1 0; +v0x8cb0ce260_0 .net "rst", 0 0, v0x8cb0d9cc0_0; alias, 1 drivers +v0x8cb0ce300_0 .net "start", 0 0, v0x8cb0d9d60_0; alias, 1 drivers +v0x8cb0ce3a0_0 .net/s "w_bus", 511 0, L_0x8cad070c0; 1 drivers +v0x8cb0ce440_0 .net/s "w_group", 127 0, L_0x8cad059a0; 1 drivers +v0x8cb0ce4e0_0 .net/s "x_bus", 511 0, v0x8cb0d9ea0_0; alias, 1 drivers +v0x8cb0ce580_0 .net/s "x_group", 127 0, L_0x8cad05900; 1 drivers +v0x8cb0ce620_0 .var/s "y", 15 0; +L_0x8cb0db980 .concat [ 2 30 0 0], v0x8cb0ce1c0_0, L_0x8ca878448; +L_0x8cb0dba20 .arith/mult 32, L_0x8cb0db980, L_0x8ca878490; +L_0x8cb0dbac0 .arith/mult 32, L_0x8cb0dba20, L_0x8ca8784d8; +L_0x8cad05900 .part/v v0x8cb0d9ea0_0, L_0x8cb0dbac0, 128; +L_0x8cb0dbb60 .concat [ 2 30 0 0], v0x8cb0ce1c0_0, L_0x8ca878520; +L_0x8cb0dbc00 .arith/mult 32, L_0x8cb0dbb60, L_0x8ca878568; +L_0x8cb0dbca0 .arith/mult 32, L_0x8cb0dbc00, L_0x8ca8785b0; +L_0x8cad059a0 .part/v L_0x8cad070c0, L_0x8cb0dbca0, 128; +L_0x8cad06e40 .part L_0x10502b180, 15, 1; +L_0x8cad06ee0 .repeat 24, 24, L_0x8cad06e40; +L_0x8cb0dd180 .concat [ 16 24 0 0], L_0x10502b180, L_0x8cad06ee0; +L_0x8cad06f80 .part L_0x8cb0dd180, 0, 32; +L_0x8cb0dd220 .concat [ 8 32 0 0], L_0x8ca878838, L_0x8cad06f80; +L_0x8cac67700 .arith/sum 40, L_0x8cac67660, L_0x8cb0dd220; +L_0x8cad07020 .part L_0x8cac67700, 8, 32; +L_0x8cb0dd2c0 .extend/s 40, L_0x8cad07020; +S_0x8cad1c900 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8cad1c780; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb064280 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8cb0642c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8cb0cc460_0 .net/s "acc_in", 39 0, v0x8cb0cdb80_0; 1 drivers +v0x8cb0cc500_0 .net/s "acc_out", 39 0, L_0x8cac67660; alias, 1 drivers +v0x8cb0cc5a0_0 .net/s "m0", 39 0, L_0x8cac66d00; 1 drivers +v0x8cb0cc640_0 .net/s "m1", 39 0, L_0x8cac66da0; 1 drivers +v0x8cb0cc6e0_0 .net/s "m2", 39 0, L_0x8cac66e40; 1 drivers +v0x8cb0cc780_0 .net/s "m3", 39 0, L_0x8cac66ee0; 1 drivers +v0x8cb0cc820_0 .net/s "m4", 39 0, L_0x8cac66f80; 1 drivers +v0x8cb0cc8c0_0 .net/s "m5", 39 0, L_0x8cac67020; 1 drivers +v0x8cb0cc960_0 .net/s "m6", 39 0, L_0x8cac670c0; 1 drivers +v0x8cb0cca00_0 .net/s "m7", 39 0, L_0x8cac67160; 1 drivers +v0x8cb0ccaa0_0 .net/s "s0", 39 0, L_0x8cac67200; 1 drivers +v0x8cb0ccb40_0 .net/s "s1", 39 0, L_0x8cac672a0; 1 drivers +v0x8cb0ccbe0_0 .net/s "s2", 39 0, L_0x8cac67340; 1 drivers +v0x8cb0ccc80_0 .net/s "s3", 39 0, L_0x8cac673e0; 1 drivers +v0x8cb0ccd20_0 .net/s "s4", 39 0, L_0x8cac67480; 1 drivers +v0x8cb0ccdc0_0 .net/s "s5", 39 0, L_0x8cac67520; 1 drivers +v0x8cb0cce60_0 .net/s "sum", 39 0, L_0x8cac675c0; 1 drivers +v0x8cb0ccf00_0 .net/s "w_bus", 127 0, L_0x8cad059a0; alias, 1 drivers +v0x8cb0ccfa0_0 .net/s "x_bus", 127 0, L_0x8cad05900; alias, 1 drivers +L_0x8cad05b80 .part L_0x8cad05900, 0, 16; +L_0x8cad05c20 .part L_0x8cad059a0, 0, 16; +L_0x8cad05e00 .part L_0x8cad05900, 16, 16; +L_0x8cad05ea0 .part L_0x8cad059a0, 16, 16; +L_0x8cad06080 .part L_0x8cad05900, 32, 16; +L_0x8cad06120 .part L_0x8cad059a0, 32, 16; +L_0x8cad06300 .part L_0x8cad05900, 48, 16; +L_0x8cad063a0 .part L_0x8cad059a0, 48, 16; +L_0x8cad06580 .part L_0x8cad05900, 64, 16; +L_0x8cad06620 .part L_0x8cad059a0, 64, 16; +L_0x8cad06800 .part L_0x8cad05900, 80, 16; +L_0x8cad068a0 .part L_0x8cad059a0, 80, 16; +L_0x8cad06a80 .part L_0x8cad05900, 96, 16; +L_0x8cad06b20 .part L_0x8cad059a0, 96, 16; +L_0x8cad06d00 .part L_0x8cad05900, 112, 16; +L_0x8cad06da0 .part L_0x8cad059a0, 112, 16; +L_0x8cac67200 .arith/sum 40, L_0x8cac66d00, L_0x8cac66da0; +L_0x8cac672a0 .arith/sum 40, L_0x8cac66e40, L_0x8cac66ee0; +L_0x8cac67340 .arith/sum 40, L_0x8cac66f80, L_0x8cac67020; +L_0x8cac673e0 .arith/sum 40, L_0x8cac670c0, L_0x8cac67160; +L_0x8cac67480 .arith/sum 40, L_0x8cac67200, L_0x8cac672a0; +L_0x8cac67520 .arith/sum 40, L_0x8cac67340, L_0x8cac673e0; +L_0x8cac675c0 .arith/sum 40, L_0x8cac67480, L_0x8cac67520; +L_0x8cac67660 .arith/sum 40, v0x8cb0cdb80_0, L_0x8cac675c0; +S_0x8cad1ca80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8cad1c900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb0386c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038700 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038740 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c9220_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dbd40; 1 drivers +v0x8cb0c92c0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dbde0; 1 drivers +v0x8cb0c9360_0 .net *"_ivl_7", 0 0, L_0x8cad05a40; 1 drivers +v0x8cb0c9400_0 .net *"_ivl_9", 7 0, L_0x8cad05ae0; 1 drivers +L_0x8ca8785f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c94a0_0 .net/s "acc_in", 39 0, L_0x8ca8785f8; 1 drivers +v0x8cb0c9540_0 .net/s "acc_out", 39 0, L_0x8cac66d00; alias, 1 drivers +v0x8cb0c95e0_0 .net/s "product", 31 0, L_0x8cb0dbe80; 1 drivers +v0x8cb0c9680_0 .net/s "product_ext", 39 0, L_0x8cb0dbf20; 1 drivers +v0x8cb0c9720_0 .net/s "w", 15 0, L_0x8cad05c20; 1 drivers +v0x8cb0c97c0_0 .net/s "x", 15 0, L_0x8cad05b80; 1 drivers +L_0x8cb0dbd40 .extend/s 32, L_0x8cad05b80; +L_0x8cb0dbde0 .extend/s 32, L_0x8cad05c20; +L_0x8cb0dbe80 .arith/mult 32, L_0x8cb0dbd40, L_0x8cb0dbde0; +L_0x8cad05a40 .part L_0x8cb0dbe80, 31, 1; +L_0x8cad05ae0 .repeat 8, 8, L_0x8cad05a40; +L_0x8cb0dbf20 .concat [ 32 8 0 0], L_0x8cb0dbe80, L_0x8cad05ae0; +L_0x8cac66d00 .arith/sum 40, L_0x8ca8785f8, L_0x8cb0dbf20; +S_0x8cad1cc00 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8cad1c900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038780 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb0387c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038800 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c9860_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dc000; 1 drivers +v0x8cb0c9900_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dc0a0; 1 drivers +v0x8cb0c99a0_0 .net *"_ivl_7", 0 0, L_0x8cad05cc0; 1 drivers +v0x8cb0c9a40_0 .net *"_ivl_9", 7 0, L_0x8cad05d60; 1 drivers +L_0x8ca878640 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0c9ae0_0 .net/s "acc_in", 39 0, L_0x8ca878640; 1 drivers +v0x8cb0c9b80_0 .net/s "acc_out", 39 0, L_0x8cac66da0; alias, 1 drivers +v0x8cb0c9c20_0 .net/s "product", 31 0, L_0x8cb0dc140; 1 drivers +v0x8cb0c9cc0_0 .net/s "product_ext", 39 0, L_0x8cb0dc1e0; 1 drivers +v0x8cb0c9d60_0 .net/s "w", 15 0, L_0x8cad05ea0; 1 drivers +v0x8cb0c9e00_0 .net/s "x", 15 0, L_0x8cad05e00; 1 drivers +L_0x8cb0dc000 .extend/s 32, L_0x8cad05e00; +L_0x8cb0dc0a0 .extend/s 32, L_0x8cad05ea0; +L_0x8cb0dc140 .arith/mult 32, L_0x8cb0dc000, L_0x8cb0dc0a0; +L_0x8cad05cc0 .part L_0x8cb0dc140, 31, 1; +L_0x8cad05d60 .repeat 8, 8, L_0x8cad05cc0; +L_0x8cb0dc1e0 .concat [ 32 8 0 0], L_0x8cb0dc140, L_0x8cad05d60; +L_0x8cac66da0 .arith/sum 40, L_0x8ca878640, L_0x8cb0dc1e0; +S_0x8cad1cd80 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8cad1c900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038840 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038880 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb0388c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0c9ea0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dc280; 1 drivers +v0x8cb0c9f40_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dc320; 1 drivers +v0x8cb0c9fe0_0 .net *"_ivl_7", 0 0, L_0x8cad05f40; 1 drivers +v0x8cb0ca080_0 .net *"_ivl_9", 7 0, L_0x8cad05fe0; 1 drivers +L_0x8ca878688 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0ca120_0 .net/s "acc_in", 39 0, L_0x8ca878688; 1 drivers +v0x8cb0ca1c0_0 .net/s "acc_out", 39 0, L_0x8cac66e40; alias, 1 drivers +v0x8cb0ca260_0 .net/s "product", 31 0, L_0x8cb0dc3c0; 1 drivers +v0x8cb0ca300_0 .net/s "product_ext", 39 0, L_0x8cb0dc460; 1 drivers +v0x8cb0ca3a0_0 .net/s "w", 15 0, L_0x8cad06120; 1 drivers +v0x8cb0ca440_0 .net/s "x", 15 0, L_0x8cad06080; 1 drivers +L_0x8cb0dc280 .extend/s 32, L_0x8cad06080; +L_0x8cb0dc320 .extend/s 32, L_0x8cad06120; +L_0x8cb0dc3c0 .arith/mult 32, L_0x8cb0dc280, L_0x8cb0dc320; +L_0x8cad05f40 .part L_0x8cb0dc3c0, 31, 1; +L_0x8cad05fe0 .repeat 8, 8, L_0x8cad05f40; +L_0x8cb0dc460 .concat [ 32 8 0 0], L_0x8cb0dc3c0, L_0x8cad05fe0; +L_0x8cac66e40 .arith/sum 40, L_0x8ca878688, L_0x8cb0dc460; +S_0x8cad1cf00 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8cad1c900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038900 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038940 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038980 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0ca4e0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dc500; 1 drivers +v0x8cb0ca580_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dc5a0; 1 drivers +v0x8cb0ca620_0 .net *"_ivl_7", 0 0, L_0x8cad061c0; 1 drivers +v0x8cb0ca6c0_0 .net *"_ivl_9", 7 0, L_0x8cad06260; 1 drivers +L_0x8ca8786d0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0ca760_0 .net/s "acc_in", 39 0, L_0x8ca8786d0; 1 drivers +v0x8cb0ca800_0 .net/s "acc_out", 39 0, L_0x8cac66ee0; alias, 1 drivers +v0x8cb0ca8a0_0 .net/s "product", 31 0, L_0x8cb0dc640; 1 drivers +v0x8cb0ca940_0 .net/s "product_ext", 39 0, L_0x8cb0dc6e0; 1 drivers +v0x8cb0ca9e0_0 .net/s "w", 15 0, L_0x8cad063a0; 1 drivers +v0x8cb0caa80_0 .net/s "x", 15 0, L_0x8cad06300; 1 drivers +L_0x8cb0dc500 .extend/s 32, L_0x8cad06300; +L_0x8cb0dc5a0 .extend/s 32, L_0x8cad063a0; +L_0x8cb0dc640 .arith/mult 32, L_0x8cb0dc500, L_0x8cb0dc5a0; +L_0x8cad061c0 .part L_0x8cb0dc640, 31, 1; +L_0x8cad06260 .repeat 8, 8, L_0x8cad061c0; +L_0x8cb0dc6e0 .concat [ 32 8 0 0], L_0x8cb0dc640, L_0x8cad06260; +L_0x8cac66ee0 .arith/sum 40, L_0x8ca8786d0, L_0x8cb0dc6e0; +S_0x8cad1d080 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8cad1c900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb0389c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038a00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038a40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0cab20_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dc780; 1 drivers +v0x8cb0cabc0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dc820; 1 drivers +v0x8cb0cac60_0 .net *"_ivl_7", 0 0, L_0x8cad06440; 1 drivers +v0x8cb0cad00_0 .net *"_ivl_9", 7 0, L_0x8cad064e0; 1 drivers +L_0x8ca878718 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cada0_0 .net/s "acc_in", 39 0, L_0x8ca878718; 1 drivers +v0x8cb0cae40_0 .net/s "acc_out", 39 0, L_0x8cac66f80; alias, 1 drivers +v0x8cb0caee0_0 .net/s "product", 31 0, L_0x8cb0dc8c0; 1 drivers +v0x8cb0caf80_0 .net/s "product_ext", 39 0, L_0x8cb0dc960; 1 drivers +v0x8cb0cb020_0 .net/s "w", 15 0, L_0x8cad06620; 1 drivers +v0x8cb0cb0c0_0 .net/s "x", 15 0, L_0x8cad06580; 1 drivers +L_0x8cb0dc780 .extend/s 32, L_0x8cad06580; +L_0x8cb0dc820 .extend/s 32, L_0x8cad06620; +L_0x8cb0dc8c0 .arith/mult 32, L_0x8cb0dc780, L_0x8cb0dc820; +L_0x8cad06440 .part L_0x8cb0dc8c0, 31, 1; +L_0x8cad064e0 .repeat 8, 8, L_0x8cad06440; +L_0x8cb0dc960 .concat [ 32 8 0 0], L_0x8cb0dc8c0, L_0x8cad064e0; +L_0x8cac66f80 .arith/sum 40, L_0x8ca878718, L_0x8cb0dc960; +S_0x8cad1d200 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8cad1c900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038a80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038ac0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038b00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0cb160_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dca00; 1 drivers +v0x8cb0cb200_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dcaa0; 1 drivers +v0x8cb0cb2a0_0 .net *"_ivl_7", 0 0, L_0x8cad066c0; 1 drivers +v0x8cb0cb340_0 .net *"_ivl_9", 7 0, L_0x8cad06760; 1 drivers +L_0x8ca878760 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cb3e0_0 .net/s "acc_in", 39 0, L_0x8ca878760; 1 drivers +v0x8cb0cb480_0 .net/s "acc_out", 39 0, L_0x8cac67020; alias, 1 drivers +v0x8cb0cb520_0 .net/s "product", 31 0, L_0x8cb0dcb40; 1 drivers +v0x8cb0cb5c0_0 .net/s "product_ext", 39 0, L_0x8cb0dcbe0; 1 drivers +v0x8cb0cb660_0 .net/s "w", 15 0, L_0x8cad068a0; 1 drivers +v0x8cb0cb700_0 .net/s "x", 15 0, L_0x8cad06800; 1 drivers +L_0x8cb0dca00 .extend/s 32, L_0x8cad06800; +L_0x8cb0dcaa0 .extend/s 32, L_0x8cad068a0; +L_0x8cb0dcb40 .arith/mult 32, L_0x8cb0dca00, L_0x8cb0dcaa0; +L_0x8cad066c0 .part L_0x8cb0dcb40, 31, 1; +L_0x8cad06760 .repeat 8, 8, L_0x8cad066c0; +L_0x8cb0dcbe0 .concat [ 32 8 0 0], L_0x8cb0dcb40, L_0x8cad06760; +L_0x8cac67020 .arith/sum 40, L_0x8ca878760, L_0x8cb0dcbe0; +S_0x8cad1d380 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8cad1c900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038b40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038b80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038bc0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0cb7a0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dcc80; 1 drivers +v0x8cb0cb840_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dcd20; 1 drivers +v0x8cb0cb8e0_0 .net *"_ivl_7", 0 0, L_0x8cad06940; 1 drivers +v0x8cb0cb980_0 .net *"_ivl_9", 7 0, L_0x8cad069e0; 1 drivers +L_0x8ca8787a8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cba20_0 .net/s "acc_in", 39 0, L_0x8ca8787a8; 1 drivers +v0x8cb0cbac0_0 .net/s "acc_out", 39 0, L_0x8cac670c0; alias, 1 drivers +v0x8cb0cbb60_0 .net/s "product", 31 0, L_0x8cb0dcdc0; 1 drivers +v0x8cb0cbc00_0 .net/s "product_ext", 39 0, L_0x8cb0dce60; 1 drivers +v0x8cb0cbca0_0 .net/s "w", 15 0, L_0x8cad06b20; 1 drivers +v0x8cb0cbd40_0 .net/s "x", 15 0, L_0x8cad06a80; 1 drivers +L_0x8cb0dcc80 .extend/s 32, L_0x8cad06a80; +L_0x8cb0dcd20 .extend/s 32, L_0x8cad06b20; +L_0x8cb0dcdc0 .arith/mult 32, L_0x8cb0dcc80, L_0x8cb0dcd20; +L_0x8cad06940 .part L_0x8cb0dcdc0, 31, 1; +L_0x8cad069e0 .repeat 8, 8, L_0x8cad06940; +L_0x8cb0dce60 .concat [ 32 8 0 0], L_0x8cb0dcdc0, L_0x8cad069e0; +L_0x8cac670c0 .arith/sum 40, L_0x8ca8787a8, L_0x8cb0dce60; +S_0x8cad1d500 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8cad1c900; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038c00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038c40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038c80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0cbde0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dcf00; 1 drivers +v0x8cb0cbe80_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dcfa0; 1 drivers +v0x8cb0cbf20_0 .net *"_ivl_7", 0 0, L_0x8cad06bc0; 1 drivers +v0x8cb0cc000_0 .net *"_ivl_9", 7 0, L_0x8cad06c60; 1 drivers +L_0x8ca8787f0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cc0a0_0 .net/s "acc_in", 39 0, L_0x8ca8787f0; 1 drivers +v0x8cb0cc140_0 .net/s "acc_out", 39 0, L_0x8cac67160; alias, 1 drivers +v0x8cb0cc1e0_0 .net/s "product", 31 0, L_0x8cb0dd040; 1 drivers +v0x8cb0cc280_0 .net/s "product_ext", 39 0, L_0x8cb0dd0e0; 1 drivers +v0x8cb0cc320_0 .net/s "w", 15 0, L_0x8cad06da0; 1 drivers +v0x8cb0cc3c0_0 .net/s "x", 15 0, L_0x8cad06d00; 1 drivers +L_0x8cb0dcf00 .extend/s 32, L_0x8cad06d00; +L_0x8cb0dcfa0 .extend/s 32, L_0x8cad06da0; +L_0x8cb0dd040 .arith/mult 32, L_0x8cb0dcf00, L_0x8cb0dcfa0; +L_0x8cad06bc0 .part L_0x8cb0dd040, 31, 1; +L_0x8cad06c60 .repeat 8, 8, L_0x8cad06bc0; +L_0x8cb0dd0e0 .concat [ 32 8 0 0], L_0x8cb0dd040, L_0x8cad06c60; +L_0x8cac67160 .arith/sum 40, L_0x8ca8787f0, L_0x8cb0dd0e0; +S_0x8cad1d680 .scope generate, "GEN_NEURON[2]" "GEN_NEURON[2]" 4 35, 4 35 0, S_0x10502b2a0; + .timescale 0 0; +P_0x8cb04ea00 .param/l "n" 1 4 35, +C4<010>; +S_0x8cad1d800 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8cad1d680; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 512 "x_bus"; + .port_info 4 /INPUT 512 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x10501b270 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x10501b2b0 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x10501b2f0 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x10501b330 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000000100>; +P_0x10501b370 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000010>; +P_0x10501b3b0 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000000100000>; +P_0x10501b3f0 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x10502ae40 .functor BUFZ 16, L_0x8cad28aa0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8cb0d24e0_0 .net *"_ivl_0", 31 0, L_0x8cb0dd360; 1 drivers +v0x8cb0d2580_0 .net *"_ivl_11", 31 0, L_0x8cb0dd4a0; 1 drivers +v0x8cb0d2620_0 .net *"_ivl_14", 31 0, L_0x8cb0dd540; 1 drivers +L_0x8ca878958 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d26c0_0 .net *"_ivl_17", 29 0, L_0x8ca878958; 1 drivers +L_0x8ca8789a0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d2760_0 .net/2u *"_ivl_18", 31 0, L_0x8ca8789a0; 1 drivers +v0x8cb0d2800_0 .net *"_ivl_21", 31 0, L_0x8cb0dd5e0; 1 drivers +L_0x8ca8789e8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d28a0_0 .net/2u *"_ivl_22", 31 0, L_0x8ca8789e8; 1 drivers +v0x8cb0d2940_0 .net *"_ivl_25", 31 0, L_0x8cb0dd680; 1 drivers +L_0x8ca878880 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d29e0_0 .net *"_ivl_3", 29 0, L_0x8ca878880; 1 drivers +v0x8cb0d2a80_0 .net *"_ivl_31", 0 0, L_0x8cad28780; 1 drivers +v0x8cb0d2b20_0 .net *"_ivl_33", 23 0, L_0x8cad28820; 1 drivers +v0x8cb0d2bc0_0 .net *"_ivl_36", 39 0, L_0x8cb0debc0; 1 drivers +v0x8cb0d2c60_0 .net *"_ivl_38", 31 0, L_0x8cad288c0; 1 drivers +L_0x8ca8788c8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d2d00_0 .net/2u *"_ivl_4", 31 0, L_0x8ca8788c8; 1 drivers +L_0x8ca878c70 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d2da0_0 .net *"_ivl_40", 7 0, L_0x8ca878c70; 1 drivers +v0x8cb0d2e40_0 .net *"_ivl_46", 31 0, L_0x8cad28960; 1 drivers +v0x8cb0d2ee0_0 .net *"_ivl_7", 31 0, L_0x8cb0dd400; 1 drivers +L_0x8ca878910 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d2f80_0 .net/2u *"_ivl_8", 31 0, L_0x8ca878910; 1 drivers +v0x8cb0d3020_0 .var/s "acc", 39 0; +v0x8cb0d30c0_0 .net/s "acc_next", 39 0, L_0x8cad2c140; 1 drivers +v0x8cb0d3160_0 .net/s "bias", 15 0, L_0x8cad28aa0; 1 drivers +v0x8cb0d3200_0 .net/s "bias_ext", 39 0, L_0x8cb0deb20; 1 drivers +v0x8cb0d32a0_0 .net/s "bias_ext_small", 15 0, L_0x10502ae40; 1 drivers +v0x8cb0d3340_0 .var "busy", 0 0; +v0x8cb0d33e0_0 .net "clk", 0 0, v0x8cb0d99a0_0; alias, 1 drivers +v0x8cb0d3480_0 .var "done", 0 0; +v0x8cb0d3520_0 .net/s "final_acc", 39 0, L_0x8cad2c1e0; 1 drivers +v0x8cb0d35c0_0 .net/s "final_value", 39 0, L_0x8cb0dec60; 1 drivers +v0x8cb0d3660_0 .var "group_index", 1 0; +v0x8cb0d3700_0 .net "rst", 0 0, v0x8cb0d9cc0_0; alias, 1 drivers +v0x8cb0d37a0_0 .net "start", 0 0, v0x8cb0d9d60_0; alias, 1 drivers +v0x8cb0d3840_0 .net/s "w_bus", 511 0, L_0x8cad28a00; 1 drivers +v0x8cb0d38e0_0 .net/s "w_group", 127 0, L_0x8cad072a0; 1 drivers +v0x8cb0d3980_0 .net/s "x_bus", 511 0, v0x8cb0d9ea0_0; alias, 1 drivers +v0x8cb0d3a20_0 .net/s "x_group", 127 0, L_0x8cad07200; 1 drivers +v0x8cb0d3ac0_0 .var/s "y", 15 0; +L_0x8cb0dd360 .concat [ 2 30 0 0], v0x8cb0d3660_0, L_0x8ca878880; +L_0x8cb0dd400 .arith/mult 32, L_0x8cb0dd360, L_0x8ca8788c8; +L_0x8cb0dd4a0 .arith/mult 32, L_0x8cb0dd400, L_0x8ca878910; +L_0x8cad07200 .part/v v0x8cb0d9ea0_0, L_0x8cb0dd4a0, 128; +L_0x8cb0dd540 .concat [ 2 30 0 0], v0x8cb0d3660_0, L_0x8ca878958; +L_0x8cb0dd5e0 .arith/mult 32, L_0x8cb0dd540, L_0x8ca8789a0; +L_0x8cb0dd680 .arith/mult 32, L_0x8cb0dd5e0, L_0x8ca8789e8; +L_0x8cad072a0 .part/v L_0x8cad28a00, L_0x8cb0dd680, 128; +L_0x8cad28780 .part L_0x10502ae40, 15, 1; +L_0x8cad28820 .repeat 24, 24, L_0x8cad28780; +L_0x8cb0deb20 .concat [ 16 24 0 0], L_0x10502ae40, L_0x8cad28820; +L_0x8cad288c0 .part L_0x8cb0deb20, 0, 32; +L_0x8cb0debc0 .concat [ 8 32 0 0], L_0x8ca878c70, L_0x8cad288c0; +L_0x8cad2c1e0 .arith/sum 40, L_0x8cad2c140, L_0x8cb0debc0; +L_0x8cad28960 .part L_0x8cad2c1e0, 8, 32; +L_0x8cb0dec60 .extend/s 40, L_0x8cad28960; +S_0x8cad1d980 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8cad1d800; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb064300 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8cb064340 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8cb0d1900_0 .net/s "acc_in", 39 0, v0x8cb0d3020_0; 1 drivers +v0x8cb0d19a0_0 .net/s "acc_out", 39 0, L_0x8cad2c140; alias, 1 drivers +v0x8cb0d1a40_0 .net/s "m0", 39 0, L_0x8cac677a0; 1 drivers +v0x8cb0d1ae0_0 .net/s "m1", 39 0, L_0x8cac67840; 1 drivers +v0x8cb0d1b80_0 .net/s "m2", 39 0, L_0x8cac678e0; 1 drivers +v0x8cb0d1c20_0 .net/s "m3", 39 0, L_0x8cac67980; 1 drivers +v0x8cb0d1cc0_0 .net/s "m4", 39 0, L_0x8cac67a20; 1 drivers +v0x8cb0d1d60_0 .net/s "m5", 39 0, L_0x8cac67ac0; 1 drivers +v0x8cb0d1e00_0 .net/s "m6", 39 0, L_0x8cac67b60; 1 drivers +v0x8cb0d1ea0_0 .net/s "m7", 39 0, L_0x8cac67c00; 1 drivers +v0x8cb0d1f40_0 .net/s "s0", 39 0, L_0x8cac67ca0; 1 drivers +v0x8cb0d1fe0_0 .net/s "s1", 39 0, L_0x8cac67d40; 1 drivers +v0x8cb0d2080_0 .net/s "s2", 39 0, L_0x8cac67de0; 1 drivers +v0x8cb0d2120_0 .net/s "s3", 39 0, L_0x8cac67e80; 1 drivers +v0x8cb0d21c0_0 .net/s "s4", 39 0, L_0x8cac67f20; 1 drivers +v0x8cb0d2260_0 .net/s "s5", 39 0, L_0x8cad2c000; 1 drivers +v0x8cb0d2300_0 .net/s "sum", 39 0, L_0x8cad2c0a0; 1 drivers +v0x8cb0d23a0_0 .net/s "w_bus", 127 0, L_0x8cad072a0; alias, 1 drivers +v0x8cb0d2440_0 .net/s "x_bus", 127 0, L_0x8cad07200; alias, 1 drivers +L_0x8cad07480 .part L_0x8cad07200, 0, 16; +L_0x8cad07520 .part L_0x8cad072a0, 0, 16; +L_0x8cad07700 .part L_0x8cad07200, 16, 16; +L_0x8cad077a0 .part L_0x8cad072a0, 16, 16; +L_0x8cad07980 .part L_0x8cad07200, 32, 16; +L_0x8cad07a20 .part L_0x8cad072a0, 32, 16; +L_0x8cad07c00 .part L_0x8cad07200, 48, 16; +L_0x8cad07ca0 .part L_0x8cad072a0, 48, 16; +L_0x8cad07e80 .part L_0x8cad07200, 64, 16; +L_0x8cad07f20 .part L_0x8cad072a0, 64, 16; +L_0x8cad28140 .part L_0x8cad07200, 80, 16; +L_0x8cad281e0 .part L_0x8cad072a0, 80, 16; +L_0x8cad283c0 .part L_0x8cad07200, 96, 16; +L_0x8cad28460 .part L_0x8cad072a0, 96, 16; +L_0x8cad28640 .part L_0x8cad07200, 112, 16; +L_0x8cad286e0 .part L_0x8cad072a0, 112, 16; +L_0x8cac67ca0 .arith/sum 40, L_0x8cac677a0, L_0x8cac67840; +L_0x8cac67d40 .arith/sum 40, L_0x8cac678e0, L_0x8cac67980; +L_0x8cac67de0 .arith/sum 40, L_0x8cac67a20, L_0x8cac67ac0; +L_0x8cac67e80 .arith/sum 40, L_0x8cac67b60, L_0x8cac67c00; +L_0x8cac67f20 .arith/sum 40, L_0x8cac67ca0, L_0x8cac67d40; +L_0x8cad2c000 .arith/sum 40, L_0x8cac67de0, L_0x8cac67e80; +L_0x8cad2c0a0 .arith/sum 40, L_0x8cac67f20, L_0x8cad2c000; +L_0x8cad2c140 .arith/sum 40, v0x8cb0d3020_0, L_0x8cad2c0a0; +S_0x8cad1db00 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8cad1d980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038cc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038d00 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038d40 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0ce6c0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dd720; 1 drivers +v0x8cb0ce760_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dd7c0; 1 drivers +v0x8cb0ce800_0 .net *"_ivl_7", 0 0, L_0x8cad07340; 1 drivers +v0x8cb0ce8a0_0 .net *"_ivl_9", 7 0, L_0x8cad073e0; 1 drivers +L_0x8ca878a30 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0ce940_0 .net/s "acc_in", 39 0, L_0x8ca878a30; 1 drivers +v0x8cb0ce9e0_0 .net/s "acc_out", 39 0, L_0x8cac677a0; alias, 1 drivers +v0x8cb0cea80_0 .net/s "product", 31 0, L_0x8cb0dd860; 1 drivers +v0x8cb0ceb20_0 .net/s "product_ext", 39 0, L_0x8cb0dd900; 1 drivers +v0x8cb0cebc0_0 .net/s "w", 15 0, L_0x8cad07520; 1 drivers +v0x8cb0cec60_0 .net/s "x", 15 0, L_0x8cad07480; 1 drivers +L_0x8cb0dd720 .extend/s 32, L_0x8cad07480; +L_0x8cb0dd7c0 .extend/s 32, L_0x8cad07520; +L_0x8cb0dd860 .arith/mult 32, L_0x8cb0dd720, L_0x8cb0dd7c0; +L_0x8cad07340 .part L_0x8cb0dd860, 31, 1; +L_0x8cad073e0 .repeat 8, 8, L_0x8cad07340; +L_0x8cb0dd900 .concat [ 32 8 0 0], L_0x8cb0dd860, L_0x8cad073e0; +L_0x8cac677a0 .arith/sum 40, L_0x8ca878a30, L_0x8cb0dd900; +S_0x8cad1dc80 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8cad1d980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038d80 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038dc0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038e00 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0ced00_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dd9a0; 1 drivers +v0x8cb0ceda0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dda40; 1 drivers +v0x8cb0cee40_0 .net *"_ivl_7", 0 0, L_0x8cad075c0; 1 drivers +v0x8cb0ceee0_0 .net *"_ivl_9", 7 0, L_0x8cad07660; 1 drivers +L_0x8ca878a78 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cef80_0 .net/s "acc_in", 39 0, L_0x8ca878a78; 1 drivers +v0x8cb0cf020_0 .net/s "acc_out", 39 0, L_0x8cac67840; alias, 1 drivers +v0x8cb0cf0c0_0 .net/s "product", 31 0, L_0x8cb0ddae0; 1 drivers +v0x8cb0cf160_0 .net/s "product_ext", 39 0, L_0x8cb0ddb80; 1 drivers +v0x8cb0cf200_0 .net/s "w", 15 0, L_0x8cad077a0; 1 drivers +v0x8cb0cf2a0_0 .net/s "x", 15 0, L_0x8cad07700; 1 drivers +L_0x8cb0dd9a0 .extend/s 32, L_0x8cad07700; +L_0x8cb0dda40 .extend/s 32, L_0x8cad077a0; +L_0x8cb0ddae0 .arith/mult 32, L_0x8cb0dd9a0, L_0x8cb0dda40; +L_0x8cad075c0 .part L_0x8cb0ddae0, 31, 1; +L_0x8cad07660 .repeat 8, 8, L_0x8cad075c0; +L_0x8cb0ddb80 .concat [ 32 8 0 0], L_0x8cb0ddae0, L_0x8cad07660; +L_0x8cac67840 .arith/sum 40, L_0x8ca878a78, L_0x8cb0ddb80; +S_0x8cad1de00 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8cad1d980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038e40 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038e80 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038ec0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0cf340_0 .net/s *"_ivl_0", 31 0, L_0x8cb0ddc20; 1 drivers +v0x8cb0cf3e0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0ddcc0; 1 drivers +v0x8cb0cf480_0 .net *"_ivl_7", 0 0, L_0x8cad07840; 1 drivers +v0x8cb0cf520_0 .net *"_ivl_9", 7 0, L_0x8cad078e0; 1 drivers +L_0x8ca878ac0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cf5c0_0 .net/s "acc_in", 39 0, L_0x8ca878ac0; 1 drivers +v0x8cb0cf660_0 .net/s "acc_out", 39 0, L_0x8cac678e0; alias, 1 drivers +v0x8cb0cf700_0 .net/s "product", 31 0, L_0x8cb0ddd60; 1 drivers +v0x8cb0cf7a0_0 .net/s "product_ext", 39 0, L_0x8cb0dde00; 1 drivers +v0x8cb0cf840_0 .net/s "w", 15 0, L_0x8cad07a20; 1 drivers +v0x8cb0cf8e0_0 .net/s "x", 15 0, L_0x8cad07980; 1 drivers +L_0x8cb0ddc20 .extend/s 32, L_0x8cad07980; +L_0x8cb0ddcc0 .extend/s 32, L_0x8cad07a20; +L_0x8cb0ddd60 .arith/mult 32, L_0x8cb0ddc20, L_0x8cb0ddcc0; +L_0x8cad07840 .part L_0x8cb0ddd60, 31, 1; +L_0x8cad078e0 .repeat 8, 8, L_0x8cad07840; +L_0x8cb0dde00 .concat [ 32 8 0 0], L_0x8cb0ddd60, L_0x8cad078e0; +L_0x8cac678e0 .arith/sum 40, L_0x8ca878ac0, L_0x8cb0dde00; +S_0x8cad1df80 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8cad1d980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038f00 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb038f40 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb038f80 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0cf980_0 .net/s *"_ivl_0", 31 0, L_0x8cb0ddea0; 1 drivers +v0x8cb0cfa20_0 .net/s *"_ivl_2", 31 0, L_0x8cb0ddf40; 1 drivers +v0x8cb0cfac0_0 .net *"_ivl_7", 0 0, L_0x8cad07ac0; 1 drivers +v0x8cb0cfb60_0 .net *"_ivl_9", 7 0, L_0x8cad07b60; 1 drivers +L_0x8ca878b08 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0cfc00_0 .net/s "acc_in", 39 0, L_0x8ca878b08; 1 drivers +v0x8cb0cfca0_0 .net/s "acc_out", 39 0, L_0x8cac67980; alias, 1 drivers +v0x8cb0cfd40_0 .net/s "product", 31 0, L_0x8cb0ddfe0; 1 drivers +v0x8cb0cfde0_0 .net/s "product_ext", 39 0, L_0x8cb0de080; 1 drivers +v0x8cb0cfe80_0 .net/s "w", 15 0, L_0x8cad07ca0; 1 drivers +v0x8cb0cff20_0 .net/s "x", 15 0, L_0x8cad07c00; 1 drivers +L_0x8cb0ddea0 .extend/s 32, L_0x8cad07c00; +L_0x8cb0ddf40 .extend/s 32, L_0x8cad07ca0; +L_0x8cb0ddfe0 .arith/mult 32, L_0x8cb0ddea0, L_0x8cb0ddf40; +L_0x8cad07ac0 .part L_0x8cb0ddfe0, 31, 1; +L_0x8cad07b60 .repeat 8, 8, L_0x8cad07ac0; +L_0x8cb0de080 .concat [ 32 8 0 0], L_0x8cb0ddfe0, L_0x8cad07b60; +L_0x8cac67980 .arith/sum 40, L_0x8ca878b08, L_0x8cb0de080; +S_0x8cad1e100 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8cad1d980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb038fc0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039000 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039040 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d0000_0 .net/s *"_ivl_0", 31 0, L_0x8cb0de120; 1 drivers +v0x8cb0d00a0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0de1c0; 1 drivers +v0x8cb0d0140_0 .net *"_ivl_7", 0 0, L_0x8cad07d40; 1 drivers +v0x8cb0d01e0_0 .net *"_ivl_9", 7 0, L_0x8cad07de0; 1 drivers +L_0x8ca878b50 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d0280_0 .net/s "acc_in", 39 0, L_0x8ca878b50; 1 drivers +v0x8cb0d0320_0 .net/s "acc_out", 39 0, L_0x8cac67a20; alias, 1 drivers +v0x8cb0d03c0_0 .net/s "product", 31 0, L_0x8cb0de260; 1 drivers +v0x8cb0d0460_0 .net/s "product_ext", 39 0, L_0x8cb0de300; 1 drivers +v0x8cb0d0500_0 .net/s "w", 15 0, L_0x8cad07f20; 1 drivers +v0x8cb0d05a0_0 .net/s "x", 15 0, L_0x8cad07e80; 1 drivers +L_0x8cb0de120 .extend/s 32, L_0x8cad07e80; +L_0x8cb0de1c0 .extend/s 32, L_0x8cad07f20; +L_0x8cb0de260 .arith/mult 32, L_0x8cb0de120, L_0x8cb0de1c0; +L_0x8cad07d40 .part L_0x8cb0de260, 31, 1; +L_0x8cad07de0 .repeat 8, 8, L_0x8cad07d40; +L_0x8cb0de300 .concat [ 32 8 0 0], L_0x8cb0de260, L_0x8cad07de0; +L_0x8cac67a20 .arith/sum 40, L_0x8ca878b50, L_0x8cb0de300; +S_0x8cad1e280 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8cad1d980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039080 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb0390c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039100 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d0640_0 .net/s *"_ivl_0", 31 0, L_0x8cb0de3a0; 1 drivers +v0x8cb0d06e0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0de440; 1 drivers +v0x8cb0d0780_0 .net *"_ivl_7", 0 0, L_0x8cad28000; 1 drivers +v0x8cb0d0820_0 .net *"_ivl_9", 7 0, L_0x8cad280a0; 1 drivers +L_0x8ca878b98 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d08c0_0 .net/s "acc_in", 39 0, L_0x8ca878b98; 1 drivers +v0x8cb0d0960_0 .net/s "acc_out", 39 0, L_0x8cac67ac0; alias, 1 drivers +v0x8cb0d0a00_0 .net/s "product", 31 0, L_0x8cb0de4e0; 1 drivers +v0x8cb0d0aa0_0 .net/s "product_ext", 39 0, L_0x8cb0de580; 1 drivers +v0x8cb0d0b40_0 .net/s "w", 15 0, L_0x8cad281e0; 1 drivers +v0x8cb0d0be0_0 .net/s "x", 15 0, L_0x8cad28140; 1 drivers +L_0x8cb0de3a0 .extend/s 32, L_0x8cad28140; +L_0x8cb0de440 .extend/s 32, L_0x8cad281e0; +L_0x8cb0de4e0 .arith/mult 32, L_0x8cb0de3a0, L_0x8cb0de440; +L_0x8cad28000 .part L_0x8cb0de4e0, 31, 1; +L_0x8cad280a0 .repeat 8, 8, L_0x8cad28000; +L_0x8cb0de580 .concat [ 32 8 0 0], L_0x8cb0de4e0, L_0x8cad280a0; +L_0x8cac67ac0 .arith/sum 40, L_0x8ca878b98, L_0x8cb0de580; +S_0x8cad1e400 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8cad1d980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039140 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039180 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb0391c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d0c80_0 .net/s *"_ivl_0", 31 0, L_0x8cb0de620; 1 drivers +v0x8cb0d0d20_0 .net/s *"_ivl_2", 31 0, L_0x8cb0de6c0; 1 drivers +v0x8cb0d0dc0_0 .net *"_ivl_7", 0 0, L_0x8cad28280; 1 drivers +v0x8cb0d0e60_0 .net *"_ivl_9", 7 0, L_0x8cad28320; 1 drivers +L_0x8ca878be0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d0f00_0 .net/s "acc_in", 39 0, L_0x8ca878be0; 1 drivers +v0x8cb0d0fa0_0 .net/s "acc_out", 39 0, L_0x8cac67b60; alias, 1 drivers +v0x8cb0d1040_0 .net/s "product", 31 0, L_0x8cb0de760; 1 drivers +v0x8cb0d10e0_0 .net/s "product_ext", 39 0, L_0x8cb0de800; 1 drivers +v0x8cb0d1180_0 .net/s "w", 15 0, L_0x8cad28460; 1 drivers +v0x8cb0d1220_0 .net/s "x", 15 0, L_0x8cad283c0; 1 drivers +L_0x8cb0de620 .extend/s 32, L_0x8cad283c0; +L_0x8cb0de6c0 .extend/s 32, L_0x8cad28460; +L_0x8cb0de760 .arith/mult 32, L_0x8cb0de620, L_0x8cb0de6c0; +L_0x8cad28280 .part L_0x8cb0de760, 31, 1; +L_0x8cad28320 .repeat 8, 8, L_0x8cad28280; +L_0x8cb0de800 .concat [ 32 8 0 0], L_0x8cb0de760, L_0x8cad28320; +L_0x8cac67b60 .arith/sum 40, L_0x8ca878be0, L_0x8cb0de800; +S_0x8cad1e580 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8cad1d980; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039200 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039240 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039280 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d12c0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0de8a0; 1 drivers +v0x8cb0d1360_0 .net/s *"_ivl_2", 31 0, L_0x8cb0de940; 1 drivers +v0x8cb0d1400_0 .net *"_ivl_7", 0 0, L_0x8cad28500; 1 drivers +v0x8cb0d14a0_0 .net *"_ivl_9", 7 0, L_0x8cad285a0; 1 drivers +L_0x8ca878c28 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d1540_0 .net/s "acc_in", 39 0, L_0x8ca878c28; 1 drivers +v0x8cb0d15e0_0 .net/s "acc_out", 39 0, L_0x8cac67c00; alias, 1 drivers +v0x8cb0d1680_0 .net/s "product", 31 0, L_0x8cb0de9e0; 1 drivers +v0x8cb0d1720_0 .net/s "product_ext", 39 0, L_0x8cb0dea80; 1 drivers +v0x8cb0d17c0_0 .net/s "w", 15 0, L_0x8cad286e0; 1 drivers +v0x8cb0d1860_0 .net/s "x", 15 0, L_0x8cad28640; 1 drivers +L_0x8cb0de8a0 .extend/s 32, L_0x8cad28640; +L_0x8cb0de940 .extend/s 32, L_0x8cad286e0; +L_0x8cb0de9e0 .arith/mult 32, L_0x8cb0de8a0, L_0x8cb0de940; +L_0x8cad28500 .part L_0x8cb0de9e0, 31, 1; +L_0x8cad285a0 .repeat 8, 8, L_0x8cad28500; +L_0x8cb0dea80 .concat [ 32 8 0 0], L_0x8cb0de9e0, L_0x8cad285a0; +L_0x8cac67c00 .arith/sum 40, L_0x8ca878c28, L_0x8cb0dea80; +S_0x8cad1e700 .scope generate, "GEN_NEURON[3]" "GEN_NEURON[3]" 4 35, 4 35 0, S_0x10502b2a0; + .timescale 0 0; +P_0x8cb04ea40 .param/l "n" 1 4 35, +C4<011>; +S_0x8cad1e880 .scope module, "u_neuron" "neuron_parallel" 4 43, 5 1 0, S_0x8cad1e700; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "start"; + .port_info 3 /INPUT 512 "x_bus"; + .port_info 4 /INPUT 512 "w_bus"; + .port_info 5 /INPUT 16 "bias"; + .port_info 6 /OUTPUT 16 "y"; + .port_info 7 /OUTPUT 1 "busy"; + .port_info 8 /OUTPUT 1 "done"; +P_0x105023d20 .param/l "ACC_WIDTH" 0 5 6, +C4<00000000000000000000000000101000>; +P_0x105023d60 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>; +P_0x105023da0 .param/l "FRAC_BITS" 0 5 3, +C4<00000000000000000000000000001000>; +P_0x105023de0 .param/l "GROUPS" 1 5 21, +C4<00000000000000000000000000000100>; +P_0x105023e20 .param/l "GROUP_INDEX_WIDTH" 1 5 22, +C4<00000000000000000000000000000010>; +P_0x105023e60 .param/l "N_INPUTS" 0 5 4, +C4<00000000000000000000000000100000>; +P_0x105023ea0 .param/l "PARALLEL" 0 5 5, +C4<00000000000000000000000000001000>; +L_0x10502ab00 .functor BUFZ 16, L_0x8cad2a3a0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x8cb0d7980_0 .net *"_ivl_0", 31 0, L_0x8cb0ded00; 1 drivers +v0x8cb0d7a20_0 .net *"_ivl_11", 31 0, L_0x8cb0dee40; 1 drivers +v0x8cb0d7ac0_0 .net *"_ivl_14", 31 0, L_0x8cb0deee0; 1 drivers +L_0x8ca878d90 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d7b60_0 .net *"_ivl_17", 29 0, L_0x8ca878d90; 1 drivers +L_0x8ca878dd8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d7c00_0 .net/2u *"_ivl_18", 31 0, L_0x8ca878dd8; 1 drivers +v0x8cb0d7ca0_0 .net *"_ivl_21", 31 0, L_0x8cb0def80; 1 drivers +L_0x8ca878e20 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d7d40_0 .net/2u *"_ivl_22", 31 0, L_0x8ca878e20; 1 drivers +v0x8cb0d7de0_0 .net *"_ivl_25", 31 0, L_0x8cb0df020; 1 drivers +L_0x8ca878cb8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d7e80_0 .net *"_ivl_3", 29 0, L_0x8ca878cb8; 1 drivers +v0x8cb0d7f20_0 .net *"_ivl_31", 0 0, L_0x8cad2a080; 1 drivers +v0x8cb0d8000_0 .net *"_ivl_33", 23 0, L_0x8cad2a120; 1 drivers +v0x8cb0d80a0_0 .net *"_ivl_36", 39 0, L_0x8cb0e05a0; 1 drivers +v0x8cb0d8140_0 .net *"_ivl_38", 31 0, L_0x8cad2a1c0; 1 drivers +L_0x8ca878d00 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d81e0_0 .net/2u *"_ivl_4", 31 0, L_0x8ca878d00; 1 drivers +L_0x8ca8790a8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d8280_0 .net *"_ivl_40", 7 0, L_0x8ca8790a8; 1 drivers +v0x8cb0d8320_0 .net *"_ivl_46", 31 0, L_0x8cad2a260; 1 drivers +v0x8cb0d83c0_0 .net *"_ivl_7", 31 0, L_0x8cb0deda0; 1 drivers +L_0x8ca878d48 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d8460_0 .net/2u *"_ivl_8", 31 0, L_0x8ca878d48; 1 drivers +v0x8cb0d8500_0 .var/s "acc", 39 0; +v0x8cb0d85a0_0 .net/s "acc_next", 39 0, L_0x8cad2cbe0; 1 drivers +v0x8cb0d8640_0 .net/s "bias", 15 0, L_0x8cad2a3a0; 1 drivers +v0x8cb0d86e0_0 .net/s "bias_ext", 39 0, L_0x8cb0e0500; 1 drivers +v0x8cb0d8780_0 .net/s "bias_ext_small", 15 0, L_0x10502ab00; 1 drivers +v0x8cb0d8820_0 .var "busy", 0 0; +v0x8cb0d88c0_0 .net "clk", 0 0, v0x8cb0d99a0_0; alias, 1 drivers +v0x8cb0d8960_0 .var "done", 0 0; +v0x8cb0d8a00_0 .net/s "final_acc", 39 0, L_0x8cad2cc80; 1 drivers +v0x8cb0d8aa0_0 .net/s "final_value", 39 0, L_0x8cb0e0640; 1 drivers +v0x8cb0d8b40_0 .var "group_index", 1 0; +v0x8cb0d8be0_0 .net "rst", 0 0, v0x8cb0d9cc0_0; alias, 1 drivers +v0x8cb0d8c80_0 .net "start", 0 0, v0x8cb0d9d60_0; alias, 1 drivers +v0x8cb0d8d20_0 .net/s "w_bus", 511 0, L_0x8cad2a300; 1 drivers +v0x8cb0d8dc0_0 .net/s "w_group", 127 0, L_0x8cad28be0; 1 drivers +v0x8cb0d8e60_0 .net/s "x_bus", 511 0, v0x8cb0d9ea0_0; alias, 1 drivers +v0x8cb0d8f00_0 .net/s "x_group", 127 0, L_0x8cad28b40; 1 drivers +v0x8cb0d8fa0_0 .var/s "y", 15 0; +L_0x8cb0ded00 .concat [ 2 30 0 0], v0x8cb0d8b40_0, L_0x8ca878cb8; +L_0x8cb0deda0 .arith/mult 32, L_0x8cb0ded00, L_0x8ca878d00; +L_0x8cb0dee40 .arith/mult 32, L_0x8cb0deda0, L_0x8ca878d48; +L_0x8cad28b40 .part/v v0x8cb0d9ea0_0, L_0x8cb0dee40, 128; +L_0x8cb0deee0 .concat [ 2 30 0 0], v0x8cb0d8b40_0, L_0x8ca878d90; +L_0x8cb0def80 .arith/mult 32, L_0x8cb0deee0, L_0x8ca878dd8; +L_0x8cb0df020 .arith/mult 32, L_0x8cb0def80, L_0x8ca878e20; +L_0x8cad28be0 .part/v L_0x8cad2a300, L_0x8cb0df020, 128; +L_0x8cad2a080 .part L_0x10502ab00, 15, 1; +L_0x8cad2a120 .repeat 24, 24, L_0x8cad2a080; +L_0x8cb0e0500 .concat [ 16 24 0 0], L_0x10502ab00, L_0x8cad2a120; +L_0x8cad2a1c0 .part L_0x8cb0e0500, 0, 32; +L_0x8cb0e05a0 .concat [ 8 32 0 0], L_0x8ca8790a8, L_0x8cad2a1c0; +L_0x8cad2cc80 .arith/sum 40, L_0x8cad2cbe0, L_0x8cb0e05a0; +L_0x8cad2a260 .part L_0x8cad2cc80, 8, 32; +L_0x8cb0e0640 .extend/s 40, L_0x8cad2a260; +S_0x8cad1ea00 .scope module, "u_mac8" "mac8" 5 51, 6 1 0, S_0x8cad1e880; + .timescale 0 0; + .port_info 0 /INPUT 128 "x_bus"; + .port_info 1 /INPUT 128 "w_bus"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb064380 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>; +P_0x8cb0643c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>; +v0x8cb0d6da0_0 .net/s "acc_in", 39 0, v0x8cb0d8500_0; 1 drivers +v0x8cb0d6e40_0 .net/s "acc_out", 39 0, L_0x8cad2cbe0; alias, 1 drivers +v0x8cb0d6ee0_0 .net/s "m0", 39 0, L_0x8cad2c280; 1 drivers +v0x8cb0d6f80_0 .net/s "m1", 39 0, L_0x8cad2c320; 1 drivers +v0x8cb0d7020_0 .net/s "m2", 39 0, L_0x8cad2c3c0; 1 drivers +v0x8cb0d70c0_0 .net/s "m3", 39 0, L_0x8cad2c460; 1 drivers +v0x8cb0d7160_0 .net/s "m4", 39 0, L_0x8cad2c500; 1 drivers +v0x8cb0d7200_0 .net/s "m5", 39 0, L_0x8cad2c5a0; 1 drivers +v0x8cb0d72a0_0 .net/s "m6", 39 0, L_0x8cad2c640; 1 drivers +v0x8cb0d7340_0 .net/s "m7", 39 0, L_0x8cad2c6e0; 1 drivers +v0x8cb0d73e0_0 .net/s "s0", 39 0, L_0x8cad2c780; 1 drivers +v0x8cb0d7480_0 .net/s "s1", 39 0, L_0x8cad2c820; 1 drivers +v0x8cb0d7520_0 .net/s "s2", 39 0, L_0x8cad2c8c0; 1 drivers +v0x8cb0d75c0_0 .net/s "s3", 39 0, L_0x8cad2c960; 1 drivers +v0x8cb0d7660_0 .net/s "s4", 39 0, L_0x8cad2ca00; 1 drivers +v0x8cb0d7700_0 .net/s "s5", 39 0, L_0x8cad2caa0; 1 drivers +v0x8cb0d77a0_0 .net/s "sum", 39 0, L_0x8cad2cb40; 1 drivers +v0x8cb0d7840_0 .net/s "w_bus", 127 0, L_0x8cad28be0; alias, 1 drivers +v0x8cb0d78e0_0 .net/s "x_bus", 127 0, L_0x8cad28b40; alias, 1 drivers +L_0x8cad28dc0 .part L_0x8cad28b40, 0, 16; +L_0x8cad28e60 .part L_0x8cad28be0, 0, 16; +L_0x8cad29040 .part L_0x8cad28b40, 16, 16; +L_0x8cad290e0 .part L_0x8cad28be0, 16, 16; +L_0x8cad292c0 .part L_0x8cad28b40, 32, 16; +L_0x8cad29360 .part L_0x8cad28be0, 32, 16; +L_0x8cad29540 .part L_0x8cad28b40, 48, 16; +L_0x8cad295e0 .part L_0x8cad28be0, 48, 16; +L_0x8cad297c0 .part L_0x8cad28b40, 64, 16; +L_0x8cad29860 .part L_0x8cad28be0, 64, 16; +L_0x8cad29a40 .part L_0x8cad28b40, 80, 16; +L_0x8cad29ae0 .part L_0x8cad28be0, 80, 16; +L_0x8cad29cc0 .part L_0x8cad28b40, 96, 16; +L_0x8cad29d60 .part L_0x8cad28be0, 96, 16; +L_0x8cad29f40 .part L_0x8cad28b40, 112, 16; +L_0x8cad29fe0 .part L_0x8cad28be0, 112, 16; +L_0x8cad2c780 .arith/sum 40, L_0x8cad2c280, L_0x8cad2c320; +L_0x8cad2c820 .arith/sum 40, L_0x8cad2c3c0, L_0x8cad2c460; +L_0x8cad2c8c0 .arith/sum 40, L_0x8cad2c500, L_0x8cad2c5a0; +L_0x8cad2c960 .arith/sum 40, L_0x8cad2c640, L_0x8cad2c6e0; +L_0x8cad2ca00 .arith/sum 40, L_0x8cad2c780, L_0x8cad2c820; +L_0x8cad2caa0 .arith/sum 40, L_0x8cad2c8c0, L_0x8cad2c960; +L_0x8cad2cb40 .arith/sum 40, L_0x8cad2ca00, L_0x8cad2caa0; +L_0x8cad2cbe0 .arith/sum 40, v0x8cb0d8500_0, L_0x8cad2cb40; +S_0x8cad1eb80 .scope module, "mac0" "mac_unit" 6 33, 7 1 0, S_0x8cad1ea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb0392c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039300 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039340 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d3b60_0 .net/s *"_ivl_0", 31 0, L_0x8cb0df0c0; 1 drivers +v0x8cb0d3c00_0 .net/s *"_ivl_2", 31 0, L_0x8cb0df160; 1 drivers +v0x8cb0d3ca0_0 .net *"_ivl_7", 0 0, L_0x8cad28c80; 1 drivers +v0x8cb0d3d40_0 .net *"_ivl_9", 7 0, L_0x8cad28d20; 1 drivers +L_0x8ca878e68 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d3de0_0 .net/s "acc_in", 39 0, L_0x8ca878e68; 1 drivers +v0x8cb0d3e80_0 .net/s "acc_out", 39 0, L_0x8cad2c280; alias, 1 drivers +v0x8cb0d3f20_0 .net/s "product", 31 0, L_0x8cb0df200; 1 drivers +v0x8cb0d4000_0 .net/s "product_ext", 39 0, L_0x8cb0df2a0; 1 drivers +v0x8cb0d40a0_0 .net/s "w", 15 0, L_0x8cad28e60; 1 drivers +v0x8cb0d4140_0 .net/s "x", 15 0, L_0x8cad28dc0; 1 drivers +L_0x8cb0df0c0 .extend/s 32, L_0x8cad28dc0; +L_0x8cb0df160 .extend/s 32, L_0x8cad28e60; +L_0x8cb0df200 .arith/mult 32, L_0x8cb0df0c0, L_0x8cb0df160; +L_0x8cad28c80 .part L_0x8cb0df200, 31, 1; +L_0x8cad28d20 .repeat 8, 8, L_0x8cad28c80; +L_0x8cb0df2a0 .concat [ 32 8 0 0], L_0x8cb0df200, L_0x8cad28d20; +L_0x8cad2c280 .arith/sum 40, L_0x8ca878e68, L_0x8cb0df2a0; +S_0x8cad1ed00 .scope module, "mac1" "mac_unit" 6 43, 7 1 0, S_0x8cad1ea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039380 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb0393c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039400 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d41e0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0df340; 1 drivers +v0x8cb0d4280_0 .net/s *"_ivl_2", 31 0, L_0x8cb0df3e0; 1 drivers +v0x8cb0d4320_0 .net *"_ivl_7", 0 0, L_0x8cad28f00; 1 drivers +v0x8cb0d43c0_0 .net *"_ivl_9", 7 0, L_0x8cad28fa0; 1 drivers +L_0x8ca878eb0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d4460_0 .net/s "acc_in", 39 0, L_0x8ca878eb0; 1 drivers +v0x8cb0d4500_0 .net/s "acc_out", 39 0, L_0x8cad2c320; alias, 1 drivers +v0x8cb0d45a0_0 .net/s "product", 31 0, L_0x8cb0df480; 1 drivers +v0x8cb0d4640_0 .net/s "product_ext", 39 0, L_0x8cb0df520; 1 drivers +v0x8cb0d46e0_0 .net/s "w", 15 0, L_0x8cad290e0; 1 drivers +v0x8cb0d4780_0 .net/s "x", 15 0, L_0x8cad29040; 1 drivers +L_0x8cb0df340 .extend/s 32, L_0x8cad29040; +L_0x8cb0df3e0 .extend/s 32, L_0x8cad290e0; +L_0x8cb0df480 .arith/mult 32, L_0x8cb0df340, L_0x8cb0df3e0; +L_0x8cad28f00 .part L_0x8cb0df480, 31, 1; +L_0x8cad28fa0 .repeat 8, 8, L_0x8cad28f00; +L_0x8cb0df520 .concat [ 32 8 0 0], L_0x8cb0df480, L_0x8cad28fa0; +L_0x8cad2c320 .arith/sum 40, L_0x8ca878eb0, L_0x8cb0df520; +S_0x8cad1ee80 .scope module, "mac2" "mac_unit" 6 53, 7 1 0, S_0x8cad1ea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039440 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039480 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb0394c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d4820_0 .net/s *"_ivl_0", 31 0, L_0x8cb0df5c0; 1 drivers +v0x8cb0d48c0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0df660; 1 drivers +v0x8cb0d4960_0 .net *"_ivl_7", 0 0, L_0x8cad29180; 1 drivers +v0x8cb0d4a00_0 .net *"_ivl_9", 7 0, L_0x8cad29220; 1 drivers +L_0x8ca878ef8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d4aa0_0 .net/s "acc_in", 39 0, L_0x8ca878ef8; 1 drivers +v0x8cb0d4b40_0 .net/s "acc_out", 39 0, L_0x8cad2c3c0; alias, 1 drivers +v0x8cb0d4be0_0 .net/s "product", 31 0, L_0x8cb0df700; 1 drivers +v0x8cb0d4c80_0 .net/s "product_ext", 39 0, L_0x8cb0df7a0; 1 drivers +v0x8cb0d4d20_0 .net/s "w", 15 0, L_0x8cad29360; 1 drivers +v0x8cb0d4dc0_0 .net/s "x", 15 0, L_0x8cad292c0; 1 drivers +L_0x8cb0df5c0 .extend/s 32, L_0x8cad292c0; +L_0x8cb0df660 .extend/s 32, L_0x8cad29360; +L_0x8cb0df700 .arith/mult 32, L_0x8cb0df5c0, L_0x8cb0df660; +L_0x8cad29180 .part L_0x8cb0df700, 31, 1; +L_0x8cad29220 .repeat 8, 8, L_0x8cad29180; +L_0x8cb0df7a0 .concat [ 32 8 0 0], L_0x8cb0df700, L_0x8cad29220; +L_0x8cad2c3c0 .arith/sum 40, L_0x8ca878ef8, L_0x8cb0df7a0; +S_0x8cad1f000 .scope module, "mac3" "mac_unit" 6 63, 7 1 0, S_0x8cad1ea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039500 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039540 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039580 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d4e60_0 .net/s *"_ivl_0", 31 0, L_0x8cb0df840; 1 drivers +v0x8cb0d4f00_0 .net/s *"_ivl_2", 31 0, L_0x8cb0df8e0; 1 drivers +v0x8cb0d4fa0_0 .net *"_ivl_7", 0 0, L_0x8cad29400; 1 drivers +v0x8cb0d5040_0 .net *"_ivl_9", 7 0, L_0x8cad294a0; 1 drivers +L_0x8ca878f40 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d50e0_0 .net/s "acc_in", 39 0, L_0x8ca878f40; 1 drivers +v0x8cb0d5180_0 .net/s "acc_out", 39 0, L_0x8cad2c460; alias, 1 drivers +v0x8cb0d5220_0 .net/s "product", 31 0, L_0x8cb0df980; 1 drivers +v0x8cb0d52c0_0 .net/s "product_ext", 39 0, L_0x8cb0dfa20; 1 drivers +v0x8cb0d5360_0 .net/s "w", 15 0, L_0x8cad295e0; 1 drivers +v0x8cb0d5400_0 .net/s "x", 15 0, L_0x8cad29540; 1 drivers +L_0x8cb0df840 .extend/s 32, L_0x8cad29540; +L_0x8cb0df8e0 .extend/s 32, L_0x8cad295e0; +L_0x8cb0df980 .arith/mult 32, L_0x8cb0df840, L_0x8cb0df8e0; +L_0x8cad29400 .part L_0x8cb0df980, 31, 1; +L_0x8cad294a0 .repeat 8, 8, L_0x8cad29400; +L_0x8cb0dfa20 .concat [ 32 8 0 0], L_0x8cb0df980, L_0x8cad294a0; +L_0x8cad2c460 .arith/sum 40, L_0x8ca878f40, L_0x8cb0dfa20; +S_0x8cad1f180 .scope module, "mac4" "mac_unit" 6 73, 7 1 0, S_0x8cad1ea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb0395c0 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039600 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039640 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d54a0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dfac0; 1 drivers +v0x8cb0d5540_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dfb60; 1 drivers +v0x8cb0d55e0_0 .net *"_ivl_7", 0 0, L_0x8cad29680; 1 drivers +v0x8cb0d5680_0 .net *"_ivl_9", 7 0, L_0x8cad29720; 1 drivers +L_0x8ca878f88 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d5720_0 .net/s "acc_in", 39 0, L_0x8ca878f88; 1 drivers +v0x8cb0d57c0_0 .net/s "acc_out", 39 0, L_0x8cad2c500; alias, 1 drivers +v0x8cb0d5860_0 .net/s "product", 31 0, L_0x8cb0dfc00; 1 drivers +v0x8cb0d5900_0 .net/s "product_ext", 39 0, L_0x8cb0dfca0; 1 drivers +v0x8cb0d59a0_0 .net/s "w", 15 0, L_0x8cad29860; 1 drivers +v0x8cb0d5a40_0 .net/s "x", 15 0, L_0x8cad297c0; 1 drivers +L_0x8cb0dfac0 .extend/s 32, L_0x8cad297c0; +L_0x8cb0dfb60 .extend/s 32, L_0x8cad29860; +L_0x8cb0dfc00 .arith/mult 32, L_0x8cb0dfac0, L_0x8cb0dfb60; +L_0x8cad29680 .part L_0x8cb0dfc00, 31, 1; +L_0x8cad29720 .repeat 8, 8, L_0x8cad29680; +L_0x8cb0dfca0 .concat [ 32 8 0 0], L_0x8cb0dfc00, L_0x8cad29720; +L_0x8cad2c500 .arith/sum 40, L_0x8ca878f88, L_0x8cb0dfca0; +S_0x8cad1f300 .scope module, "mac5" "mac_unit" 6 83, 7 1 0, S_0x8cad1ea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039680 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb0396c0 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039700 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d5ae0_0 .net/s *"_ivl_0", 31 0, L_0x8cb0dfd40; 1 drivers +v0x8cb0d5b80_0 .net/s *"_ivl_2", 31 0, L_0x8cb0dfde0; 1 drivers +v0x8cb0d5c20_0 .net *"_ivl_7", 0 0, L_0x8cad29900; 1 drivers +v0x8cb0d5cc0_0 .net *"_ivl_9", 7 0, L_0x8cad299a0; 1 drivers +L_0x8ca878fd0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d5d60_0 .net/s "acc_in", 39 0, L_0x8ca878fd0; 1 drivers +v0x8cb0d5e00_0 .net/s "acc_out", 39 0, L_0x8cad2c5a0; alias, 1 drivers +v0x8cb0d5ea0_0 .net/s "product", 31 0, L_0x8cb0dfe80; 1 drivers +v0x8cb0d5f40_0 .net/s "product_ext", 39 0, L_0x8cb0dff20; 1 drivers +v0x8cb0d5fe0_0 .net/s "w", 15 0, L_0x8cad29ae0; 1 drivers +v0x8cb0d6080_0 .net/s "x", 15 0, L_0x8cad29a40; 1 drivers +L_0x8cb0dfd40 .extend/s 32, L_0x8cad29a40; +L_0x8cb0dfde0 .extend/s 32, L_0x8cad29ae0; +L_0x8cb0dfe80 .arith/mult 32, L_0x8cb0dfd40, L_0x8cb0dfde0; +L_0x8cad29900 .part L_0x8cb0dfe80, 31, 1; +L_0x8cad299a0 .repeat 8, 8, L_0x8cad29900; +L_0x8cb0dff20 .concat [ 32 8 0 0], L_0x8cb0dfe80, L_0x8cad299a0; +L_0x8cad2c5a0 .arith/sum 40, L_0x8ca878fd0, L_0x8cb0dff20; +S_0x8cad1f480 .scope module, "mac6" "mac_unit" 6 93, 7 1 0, S_0x8cad1ea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039740 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039780 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb0397c0 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d6120_0 .net/s *"_ivl_0", 31 0, L_0x8cb0e0000; 1 drivers +v0x8cb0d61c0_0 .net/s *"_ivl_2", 31 0, L_0x8cb0e00a0; 1 drivers +v0x8cb0d6260_0 .net *"_ivl_7", 0 0, L_0x8cad29b80; 1 drivers +v0x8cb0d6300_0 .net *"_ivl_9", 7 0, L_0x8cad29c20; 1 drivers +L_0x8ca879018 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d63a0_0 .net/s "acc_in", 39 0, L_0x8ca879018; 1 drivers +v0x8cb0d6440_0 .net/s "acc_out", 39 0, L_0x8cad2c640; alias, 1 drivers +v0x8cb0d64e0_0 .net/s "product", 31 0, L_0x8cb0e0140; 1 drivers +v0x8cb0d6580_0 .net/s "product_ext", 39 0, L_0x8cb0e01e0; 1 drivers +v0x8cb0d6620_0 .net/s "w", 15 0, L_0x8cad29d60; 1 drivers +v0x8cb0d66c0_0 .net/s "x", 15 0, L_0x8cad29cc0; 1 drivers +L_0x8cb0e0000 .extend/s 32, L_0x8cad29cc0; +L_0x8cb0e00a0 .extend/s 32, L_0x8cad29d60; +L_0x8cb0e0140 .arith/mult 32, L_0x8cb0e0000, L_0x8cb0e00a0; +L_0x8cad29b80 .part L_0x8cb0e0140, 31, 1; +L_0x8cad29c20 .repeat 8, 8, L_0x8cad29b80; +L_0x8cb0e01e0 .concat [ 32 8 0 0], L_0x8cb0e0140, L_0x8cad29c20; +L_0x8cad2c640 .arith/sum 40, L_0x8ca879018, L_0x8cb0e01e0; +S_0x8cad1f600 .scope module, "mac7" "mac_unit" 6 103, 7 1 0, S_0x8cad1ea00; + .timescale 0 0; + .port_info 0 /INPUT 16 "x"; + .port_info 1 /INPUT 16 "w"; + .port_info 2 /INPUT 40 "acc_in"; + .port_info 3 /OUTPUT 40 "acc_out"; +P_0x8cb039800 .param/l "ACC_WIDTH" 0 7 3, +C4<00000000000000000000000000101000>; +P_0x8cb039840 .param/l "DATA_WIDTH" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x8cb039880 .param/l "PROD_WIDTH" 1 7 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>; +v0x8cb0d6760_0 .net/s *"_ivl_0", 31 0, L_0x8cb0e0280; 1 drivers +v0x8cb0d6800_0 .net/s *"_ivl_2", 31 0, L_0x8cb0e0320; 1 drivers +v0x8cb0d68a0_0 .net *"_ivl_7", 0 0, L_0x8cad29e00; 1 drivers +v0x8cb0d6940_0 .net *"_ivl_9", 7 0, L_0x8cad29ea0; 1 drivers +L_0x8ca879060 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x8cb0d69e0_0 .net/s "acc_in", 39 0, L_0x8ca879060; 1 drivers +v0x8cb0d6a80_0 .net/s "acc_out", 39 0, L_0x8cad2c6e0; alias, 1 drivers +v0x8cb0d6b20_0 .net/s "product", 31 0, L_0x8cb0e03c0; 1 drivers +v0x8cb0d6bc0_0 .net/s "product_ext", 39 0, L_0x8cb0e0460; 1 drivers +v0x8cb0d6c60_0 .net/s "w", 15 0, L_0x8cad29fe0; 1 drivers +v0x8cb0d6d00_0 .net/s "x", 15 0, L_0x8cad29f40; 1 drivers +L_0x8cb0e0280 .extend/s 32, L_0x8cad29f40; +L_0x8cb0e0320 .extend/s 32, L_0x8cad29fe0; +L_0x8cb0e03c0 .arith/mult 32, L_0x8cb0e0280, L_0x8cb0e0320; +L_0x8cad29e00 .part L_0x8cb0e03c0, 31, 1; +L_0x8cad29ea0 .repeat 8, 8, L_0x8cad29e00; +L_0x8cb0e0460 .concat [ 32 8 0 0], L_0x8cb0e03c0, L_0x8cad29ea0; +L_0x8cad2c6e0 .arith/sum 40, L_0x8ca879060, L_0x8cb0e0460; +S_0x8cad1f780 .scope function.vec4.u16, "q8_8" "q8_8" 3 59, 3 59 0, S_0x10502b920; + .timescale -9 -12; +; Variable q8_8 is vec4 return value of scope S_0x8cad1f780 +v0x8cb0d97c0_0 .var/real "value", 0 0; +TD_tb.q8_8 ; + %load/real v0x8cb0d97c0_0; + %pushi/real 1073741824, 4074; load=256.000 + %mul/wr; + %vpi_func 3 62 "$rtoi" 32, W<0,r> {0 1 0}; + %pad/s 16; + %ret/vec4 0, 0, 16; Assign to q8_8 (store_vec4_to_lval) + %end; +S_0x8cad1f900 .scope task, "run_layer" "run_layer" 3 66, 3 66 0, S_0x10502b920; + .timescale -9 -12; +E_0x8cacabc00 .event anyedge, v0x8cb0d9220_0; +TD_tb.run_layer ; + %wait E_0x8cacab2c0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x8cb0d9d60_0, 0, 1; + %wait E_0x8cacab2c0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x8cb0d9d60_0, 0, 1; +T_1.0 ; + %load/vec4 v0x8cb0d9a40_0; + %pad/u 32; + %pushi/vec4 1, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %cmpi/ne 1, 0, 1; + %jmp/0xz T_1.1, 6; + %wait E_0x8cacabc00; + %jmp T_1.0; +T_1.1 ; + %wait E_0x8cacab2c0; + %end; + .scope S_0x10502a8e0; +T_2 ; + %wait E_0x8cacab2c0; + %load/vec4 v0x8cb0c8dc0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x8cb0c8d20_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8cb0c86e0_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8cb0c9180_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0c8a00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0c8b40_0, 0; + %jmp T_2.1; +T_2.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0c8b40_0, 0; + %load/vec4 v0x8cb0c8e60_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_2.4, 9; + %load/vec4 v0x8cb0c8a00_0; + %nor/r; + %and; +T_2.4; + %flag_set/vec4 8; + %jmp/0xz T_2.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x8cb0c8d20_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8cb0c86e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8cb0c8a00_0, 0; + %jmp T_2.3; +T_2.2 ; + %load/vec4 v0x8cb0c8a00_0; + %flag_set/vec4 8; + %jmp/0xz T_2.5, 8; + %load/vec4 v0x8cb0c8d20_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_2.7, 4; + %load/vec4 v0x8cb0c8be0_0; + %assign/vec4 v0x8cb0c86e0_0, 0; + %load/vec4 v0x8cb0c8c80_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_2.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8cb0c9180_0, 0; + %jmp T_2.10; +T_2.9 ; + %load/vec4 v0x8cb0c8c80_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_2.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8cb0c9180_0, 0; + %jmp T_2.12; +T_2.11 ; + %load/vec4 v0x8cb0c8c80_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8cb0c9180_0, 0; +T_2.12 ; +T_2.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0c8a00_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8cb0c8b40_0, 0; + %jmp T_2.8; +T_2.7 ; + %load/vec4 v0x8cb0c8780_0; + %assign/vec4 v0x8cb0c86e0_0, 0; + %load/vec4 v0x8cb0c8d20_0; + %addi 1, 0, 2; + %assign/vec4 v0x8cb0c8d20_0, 0; +T_2.8 ; +T_2.5 ; +T_2.3 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x8cad1c780; +T_3 ; + %wait E_0x8cacab2c0; + %load/vec4 v0x8cb0ce260_0; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x8cb0ce1c0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8cb0cdb80_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8cb0ce620_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0cdea0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0cdfe0_0, 0; + %jmp T_3.1; +T_3.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0cdfe0_0, 0; + %load/vec4 v0x8cb0ce300_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_3.4, 9; + %load/vec4 v0x8cb0cdea0_0; + %nor/r; + %and; +T_3.4; + %flag_set/vec4 8; + %jmp/0xz T_3.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x8cb0ce1c0_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8cb0cdb80_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8cb0cdea0_0, 0; + %jmp T_3.3; +T_3.2 ; + %load/vec4 v0x8cb0cdea0_0; + %flag_set/vec4 8; + %jmp/0xz T_3.5, 8; + %load/vec4 v0x8cb0ce1c0_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_3.7, 4; + %load/vec4 v0x8cb0ce080_0; + %assign/vec4 v0x8cb0cdb80_0, 0; + %load/vec4 v0x8cb0ce120_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_3.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8cb0ce620_0, 0; + %jmp T_3.10; +T_3.9 ; + %load/vec4 v0x8cb0ce120_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_3.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8cb0ce620_0, 0; + %jmp T_3.12; +T_3.11 ; + %load/vec4 v0x8cb0ce120_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8cb0ce620_0, 0; +T_3.12 ; +T_3.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0cdea0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8cb0cdfe0_0, 0; + %jmp T_3.8; +T_3.7 ; + %load/vec4 v0x8cb0cdc20_0; + %assign/vec4 v0x8cb0cdb80_0, 0; + %load/vec4 v0x8cb0ce1c0_0; + %addi 1, 0, 2; + %assign/vec4 v0x8cb0ce1c0_0, 0; +T_3.8 ; +T_3.5 ; +T_3.3 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x8cad1d800; +T_4 ; + %wait E_0x8cacab2c0; + %load/vec4 v0x8cb0d3700_0; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x8cb0d3660_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8cb0d3020_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8cb0d3ac0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0d3340_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0d3480_0, 0; + %jmp T_4.1; +T_4.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0d3480_0, 0; + %load/vec4 v0x8cb0d37a0_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_4.4, 9; + %load/vec4 v0x8cb0d3340_0; + %nor/r; + %and; +T_4.4; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x8cb0d3660_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8cb0d3020_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8cb0d3340_0, 0; + %jmp T_4.3; +T_4.2 ; + %load/vec4 v0x8cb0d3340_0; + %flag_set/vec4 8; + %jmp/0xz T_4.5, 8; + %load/vec4 v0x8cb0d3660_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_4.7, 4; + %load/vec4 v0x8cb0d3520_0; + %assign/vec4 v0x8cb0d3020_0, 0; + %load/vec4 v0x8cb0d35c0_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_4.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8cb0d3ac0_0, 0; + %jmp T_4.10; +T_4.9 ; + %load/vec4 v0x8cb0d35c0_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_4.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8cb0d3ac0_0, 0; + %jmp T_4.12; +T_4.11 ; + %load/vec4 v0x8cb0d35c0_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8cb0d3ac0_0, 0; +T_4.12 ; +T_4.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0d3340_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8cb0d3480_0, 0; + %jmp T_4.8; +T_4.7 ; + %load/vec4 v0x8cb0d30c0_0; + %assign/vec4 v0x8cb0d3020_0, 0; + %load/vec4 v0x8cb0d3660_0; + %addi 1, 0, 2; + %assign/vec4 v0x8cb0d3660_0, 0; +T_4.8 ; +T_4.5 ; +T_4.3 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x8cad1e880; +T_5 ; + %wait E_0x8cacab2c0; + %load/vec4 v0x8cb0d8be0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x8cb0d8b40_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8cb0d8500_0, 0; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8cb0d8fa0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0d8820_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0d8960_0, 0; + %jmp T_5.1; +T_5.0 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0d8960_0, 0; + %load/vec4 v0x8cb0d8c80_0; + %flag_set/vec4 9; + %flag_get/vec4 9; + %jmp/0 T_5.4, 9; + %load/vec4 v0x8cb0d8820_0; + %nor/r; + %and; +T_5.4; + %flag_set/vec4 8; + %jmp/0xz T_5.2, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x8cb0d8b40_0, 0; + %pushi/vec4 0, 0, 40; + %assign/vec4 v0x8cb0d8500_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8cb0d8820_0, 0; + %jmp T_5.3; +T_5.2 ; + %load/vec4 v0x8cb0d8820_0; + %flag_set/vec4 8; + %jmp/0xz T_5.5, 8; + %load/vec4 v0x8cb0d8b40_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_5.7, 4; + %load/vec4 v0x8cb0d8a00_0; + %assign/vec4 v0x8cb0d8500_0, 0; + %load/vec4 v0x8cb0d8aa0_0; + %cmpi/s 0, 0, 40; + %flag_or 5, 4; + %jmp/0xz T_5.9, 5; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x8cb0d8fa0_0, 0; + %jmp T_5.10; +T_5.9 ; + %load/vec4 v0x8cb0d8aa0_0; + %cmpi/s 32767, 0, 40; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_5.11, 5; + %pushi/vec4 32767, 0, 16; + %assign/vec4 v0x8cb0d8fa0_0, 0; + %jmp T_5.12; +T_5.11 ; + %load/vec4 v0x8cb0d8aa0_0; + %parti/s 16, 0, 2; + %assign/vec4 v0x8cb0d8fa0_0, 0; +T_5.12 ; +T_5.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x8cb0d8820_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x8cb0d8960_0, 0; + %jmp T_5.8; +T_5.7 ; + %load/vec4 v0x8cb0d85a0_0; + %assign/vec4 v0x8cb0d8500_0, 0; + %load/vec4 v0x8cb0d8b40_0; + %addi 1, 0, 2; + %assign/vec4 v0x8cb0d8b40_0, 0; +T_5.8 ; +T_5.5 ; +T_5.3 ; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0x10502b920; +T_6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x8cb0d99a0_0, 0, 1; +T_6.0 ; + %delay 5000, 0; + %load/vec4 v0x8cb0d99a0_0; + %inv; + %store/vec4 v0x8cb0d99a0_0, 0, 1; + %jmp T_6.0; +T_6.1 ; + %end; + .thread T_6; + .scope S_0x10502b920; +T_7 ; + %vpi_call/w 3 82 "$dumpfile", "sim/parametric.vcd" {0 0 0}; + %vpi_call/w 3 83 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x10502b920 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x8cb0d9cc0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x8cb0d9d60_0, 0, 1; + %pushi/vec4 0, 0, 512; + %store/vec4 v0x8cb0d9ea0_0, 0, 512; + %pushi/vec4 0, 0, 2048; + %store/vec4 v0x8cb0d9e00_0, 0, 2048; + %pushi/vec4 0, 0, 64; + %store/vec4 v0x8cb0d9860_0, 0, 64; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8cb0d9ae0_0, 0, 32; + %pushi/vec4 2, 0, 32; +T_7.0 %dup/vec4; + %cmpi/s 0, 0, 32; + %jmp/1xz T_7.1, 5; + %jmp/1 T_7.1, 4; + %subi 1, 0, 32; + %wait E_0x8cacab2c0; + %jmp T_7.0; +T_7.1 ; + %pop/vec4 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x8cb0d9cc0_0, 0, 1; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; +T_7.2 ; Top of for-loop + %load/vec4 v0x8cb0d9c20_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_7.3, 5; + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x8cb0d97c0_0; + %callf/vec4 TD_tb.q8_8, S_0x8cad1f780; + %load/vec4 v0x8cb0d9c20_0; + %muli 16, 0, 32; + %ix/vec4/s 4; + %store/vec4 v0x8cb0d9ea0_0, 4, 16; +T_7.4 ; for-loop step statement + %load/vec4 v0x8cb0d9c20_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; + %jmp T_7.2; +T_7.3 ; for-loop exit label + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; +T_7.5 ; Top of for-loop + %load/vec4 v0x8cb0d9c20_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_7.6, 5; + %pushi/real 1073741824, 4066; load=1.00000 + %store/real v0x8cb0d97c0_0; + %callf/vec4 TD_tb.q8_8, S_0x8cad1f780; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x8cb0d9c20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8cb0d9e00_0, 4, 16; +T_7.7 ; for-loop step statement + %load/vec4 v0x8cb0d9c20_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; + %jmp T_7.5; +T_7.6 ; for-loop exit label + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; +T_7.8 ; Top of for-loop + %load/vec4 v0x8cb0d9c20_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_7.9, 5; + %pushi/real 1073741824, 4065; load=0.500000 + %store/real v0x8cb0d97c0_0; + %callf/vec4 TD_tb.q8_8, S_0x8cad1f780; + %pushi/vec4 512, 0, 32; + %load/vec4 v0x8cb0d9c20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8cb0d9e00_0, 4, 16; +T_7.10 ; for-loop step statement + %load/vec4 v0x8cb0d9c20_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; + %jmp T_7.8; +T_7.9 ; for-loop exit label + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; +T_7.11 ; Top of for-loop + %load/vec4 v0x8cb0d9c20_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_7.12, 5; + %pushi/real 1073741824, 20449; load=-0.500000 + %store/real v0x8cb0d97c0_0; + %callf/vec4 TD_tb.q8_8, S_0x8cad1f780; + %pushi/vec4 1024, 0, 32; + %load/vec4 v0x8cb0d9c20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8cb0d9e00_0, 4, 16; +T_7.13 ; for-loop step statement + %load/vec4 v0x8cb0d9c20_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; + %jmp T_7.11; +T_7.12 ; for-loop exit label + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; +T_7.14 ; Top of for-loop + %load/vec4 v0x8cb0d9c20_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_7.15, 5; + %pushi/real 1073741824, 4067; load=2.00000 + %store/real v0x8cb0d97c0_0; + %callf/vec4 TD_tb.q8_8, S_0x8cad1f780; + %pushi/vec4 1536, 0, 32; + %load/vec4 v0x8cb0d9c20_0; + %muli 16, 0, 32; + %add; + %ix/vec4/s 4; + %store/vec4 v0x8cb0d9e00_0, 4, 16; +T_7.16 ; for-loop step statement + %load/vec4 v0x8cb0d9c20_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9c20_0, 0, 32; + %jmp T_7.14; +T_7.15 ; for-loop exit label + %vpi_call/w 3 192 "$display", "\000" {0 0 0}; + %vpi_call/w 3 193 "$display", "========================================" {0 0 0}; + %vpi_call/w 3 194 "$display", "PARAMETRIC LAYER TEST" {0 0 0}; + %vpi_call/w 3 195 "$display", "N_INPUTS = %0d", P_0x10502b6a0 {0 0 0}; + %vpi_call/w 3 196 "$display", "N_NEURONS = %0d", P_0x10502b6e0 {0 0 0}; + %vpi_call/w 3 197 "$display", "PARALLEL = %0d", P_0x10502b720 {0 0 0}; + %vpi_call/w 3 198 "$display", "========================================" {0 0 0}; + %fork TD_tb.run_layer, S_0x8cad1f900; + %join; + %pushi/vec4 8192, 0, 32; + %store/vec4 v0x8cb0d9b80_0, 0, 32; + %load/vec4 v0x8cb0d9f40_0; + %parti/s 16, 0, 2; + %load/vec4 v0x8cb0d9b80_0; + %parti/s 16, 0, 2; + %cmp/ne; + %jmp/0xz T_7.17, 6; + %vpi_call/w 3 208 "$display", "FAIL N0: got %0d expected %0d", &PV, v0x8cb0d9b80_0 {0 0 0}; + %load/vec4 v0x8cb0d9ae0_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9ae0_0, 0, 32; + %jmp T_7.18; +T_7.17 ; + %vpi_call/w 3 213 "$display", "PASS N0: %0d", &PV {0 0 0}; +T_7.18 ; + %pushi/vec4 4096, 0, 32; + %store/vec4 v0x8cb0d9b80_0, 0, 32; + %load/vec4 v0x8cb0d9f40_0; + %parti/s 16, 16, 6; + %load/vec4 v0x8cb0d9b80_0; + %parti/s 16, 0, 2; + %cmp/ne; + %jmp/0xz T_7.19, 6; + %vpi_call/w 3 222 "$display", "FAIL N1: got %0d expected %0d", &PV, v0x8cb0d9b80_0 {0 0 0}; + %load/vec4 v0x8cb0d9ae0_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9ae0_0, 0, 32; + %jmp T_7.20; +T_7.19 ; + %vpi_call/w 3 227 "$display", "PASS N1: %0d", &PV {0 0 0}; +T_7.20 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x8cb0d9b80_0, 0, 32; + %load/vec4 v0x8cb0d9f40_0; + %parti/s 16, 32, 7; + %cmpi/ne 0, 0, 16; + %jmp/0xz T_7.21, 6; + %vpi_call/w 3 237 "$display", "FAIL N2: got %0d expected 0", &PV {0 0 0}; + %load/vec4 v0x8cb0d9ae0_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9ae0_0, 0, 32; + %jmp T_7.22; +T_7.21 ; + %vpi_call/w 3 242 "$display", "PASS N2: 0 (ReLU)" {0 0 0}; +T_7.22 ; + %pushi/vec4 16384, 0, 32; + %store/vec4 v0x8cb0d9b80_0, 0, 32; + %load/vec4 v0x8cb0d9b80_0; + %cmpi/s 32767, 0, 32; + %flag_or 5, 4; GT is !LE + %flag_inv 5; + %jmp/0xz T_7.23, 5; + %pushi/vec4 32767, 0, 32; + %store/vec4 v0x8cb0d9b80_0, 0, 32; +T_7.23 ; + %load/vec4 v0x8cb0d9f40_0; + %parti/s 16, 48, 7; + %load/vec4 v0x8cb0d9b80_0; + %parti/s 16, 0, 2; + %cmp/ne; + %jmp/0xz T_7.25, 6; + %vpi_call/w 3 260 "$display", "FAIL N3: got %0d expected %0d", &PV, v0x8cb0d9b80_0 {0 0 0}; + %load/vec4 v0x8cb0d9ae0_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9ae0_0, 0, 32; + %jmp T_7.26; +T_7.25 ; + %load/vec4 v0x8cb0d9b80_0; + %cmpi/e 32767, 0, 32; + %jmp/0xz T_7.27, 4; + %vpi_call/w 3 266 "$display", "PASS N3: %0d (saturation)", &PV {0 0 0}; + %jmp T_7.28; +T_7.27 ; + %vpi_call/w 3 268 "$display", "PASS N3: %0d", &PV {0 0 0}; +T_7.28 ; +T_7.26 ; + %load/vec4 v0x8cb0d9900_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_7.29, 6; + %vpi_call/w 3 329 "$display", "FAIL: busy still active" {0 0 0}; + %load/vec4 v0x8cb0d9ae0_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9ae0_0, 0, 32; +T_7.29 ; + %load/vec4 v0x8cb0d9a40_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_7.31, 6; + %vpi_call/w 3 334 "$display", "FAIL: done not asserted" {0 0 0}; + %load/vec4 v0x8cb0d9ae0_0; + %addi 1, 0, 32; + %store/vec4 v0x8cb0d9ae0_0, 0, 32; +T_7.31 ; + %vpi_call/w 3 338 "$display", "\000" {0 0 0}; + %vpi_call/w 3 339 "$display", "========================================" {0 0 0}; + %load/vec4 v0x8cb0d9ae0_0; + %cmpi/e 0, 0, 32; + %jmp/0xz T_7.33, 4; + %vpi_call/w 3 342 "$display", "PARAMETRIC TEST PASSED" {0 0 0}; + %jmp T_7.34; +T_7.33 ; + %vpi_call/w 3 344 "$display", "PARAMETRIC TEST FAILED: %0d errors", v0x8cb0d9ae0_0 {0 0 0}; +T_7.34 ; + %vpi_call/w 3 346 "$display", "========================================" {0 0 0}; + %vpi_call/w 3 347 "$display", "\000" {0 0 0}; + %vpi_call/w 3 349 "$finish" {0 0 0}; + %end; + .thread T_7; +# The file index is used to find the file name in the following table. +:file_names 8; + "N/A"; + ""; + "-"; + "sim/parametric_tb.v"; + "rtl/layer.v"; + "rtl/neuron_parallel.v"; + "rtl/mac8.v"; + "rtl/mac_unit.v"; diff --git a/sim/parametric_tb.v b/sim/parametric_tb.v new file mode 100644 index 0000000..34e6130 --- /dev/null +++ b/sim/parametric_tb.v @@ -0,0 +1,352 @@ +`timescale 1ns/1ps + +module tb; + + parameter DATA_WIDTH = 16; + parameter FRAC_BITS = 8; + parameter N_INPUTS = 32; + parameter N_NEURONS = 4; + parameter PARALLEL = 8; + parameter ACC_WIDTH = 40; + + reg clk; + reg rst; + reg start; + + reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus; + + reg signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] + weights_bus; + + reg signed [DATA_WIDTH*N_NEURONS-1:0] + bias_bus; + + wire signed [DATA_WIDTH*N_NEURONS-1:0] + y_bus; + + wire busy; + wire done; + + integer i; + integer n; + integer errors; + integer expected; + + layer #( + .DATA_WIDTH(DATA_WIDTH), + .FRAC_BITS(FRAC_BITS), + .N_INPUTS(N_INPUTS), + .N_NEURONS(N_NEURONS), + .PARALLEL(PARALLEL), + .ACC_WIDTH(ACC_WIDTH) + ) dut ( + .clk(clk), + .rst(rst), + .start(start), + .x_bus(x_bus), + .weights_bus(weights_bus), + .bias_bus(bias_bus), + .y_bus(y_bus), + .busy(busy), + .done(done) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + function signed [15:0] q8_8; + input real value; + begin + q8_8 = $rtoi(value * 256.0); + end + endfunction + + task run_layer; + begin + @(posedge clk); + start = 1; + + @(posedge clk); + start = 0; + + wait(done == 1); + + @(posedge clk); + end + endtask + + initial begin + + $dumpfile("sim/parametric.vcd"); + $dumpvars(0, tb); + + rst = 1; + start = 0; + x_bus = 0; + weights_bus = 0; + bias_bus = 0; + errors = 0; + + repeat (2) @(posedge clk); + + rst = 0; + + /* + * All inputs = 1.0 + */ + for (i = 0; i < N_INPUTS; i = i + 1) + x_bus[i*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + + /* + * Neuron 0: weight = 1.0 + * result = N_INPUTS + */ + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 0*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(1.0); + + /* + * Neuron 1: weight = 0.5 + * result = N_INPUTS / 2 + */ + if (N_NEURONS > 1) + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 1*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(0.5); + + /* + * Neuron 2: weight = -0.5 + * ReLU -> 0 + */ + if (N_NEURONS > 2) + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 2*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(-0.5); + + /* + * Neuron 3: weight = 2.0 + * Large positive result -> saturation + */ + if (N_NEURONS > 3) + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 3*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(2.0); + + /* + * Neuron 4: zero weights + bias +1 + */ + if (N_NEURONS > 4) + bias_bus[4*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + + /* + * Neuron 5: zero weights + bias -1 + * ReLU -> 0 + */ + if (N_NEURONS > 5) + bias_bus[5*DATA_WIDTH +: DATA_WIDTH] = q8_8(-1.0); + + /* + * Neuron 6: weight 1.0 + bias -1.0 + * result = N_INPUTS - 1 + */ + if (N_NEURONS > 6) begin + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 6*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(1.0); + + bias_bus[6*DATA_WIDTH +: DATA_WIDTH] = q8_8(-1.0); + end + + /* + * Neuron 7: weight 0.25 + bias 1 + * result = N_INPUTS/4 + 1 + */ + if (N_NEURONS > 7) begin + for (i = 0; i < N_INPUTS; i = i + 1) + weights_bus[ + 7*N_INPUTS*DATA_WIDTH + + i*DATA_WIDTH +: + DATA_WIDTH + ] = q8_8(0.25); + + bias_bus[7*DATA_WIDTH +: DATA_WIDTH] = q8_8(1.0); + end + + $display(""); + $display("========================================"); + $display("PARAMETRIC LAYER TEST"); + $display("N_INPUTS = %0d", N_INPUTS); + $display("N_NEURONS = %0d", N_NEURONS); + $display("PARALLEL = %0d", PARALLEL); + $display("========================================"); + + run_layer; + + /* + * Neuron 0 + */ + expected = N_INPUTS * 256; + + if (y_bus[0*16 +: 16] !== expected[15:0]) begin + $display("FAIL N0: got %0d expected %0d", + y_bus[0*16 +: 16], expected); + errors = errors + 1; + end + else + $display("PASS N0: %0d", y_bus[0*16 +: 16]); + + /* + * Neuron 1 + */ + if (N_NEURONS > 1) begin + expected = (N_INPUTS * 128); + + if (y_bus[1*16 +: 16] !== expected[15:0]) begin + $display("FAIL N1: got %0d expected %0d", + y_bus[1*16 +: 16], expected); + errors = errors + 1; + end + else + $display("PASS N1: %0d", y_bus[1*16 +: 16]); + end + + /* + * Neuron 2 + */ + if (N_NEURONS > 2) begin + expected = 0; + + if (y_bus[2*16 +: 16] !== 16'sd0) begin + $display("FAIL N2: got %0d expected 0", + y_bus[2*16 +: 16]); + errors = errors + 1; + end + else + $display("PASS N2: 0 (ReLU)"); + end + + /* + * Neuron 3: + * weight = 2.0 + * result = N_INPUTS * 2.0 + * + * Saturation only occurs when result > 127.996... + */ + if (N_NEURONS > 3) begin + + expected = N_INPUTS * 2 * 256; + + if (expected > 32767) + expected = 32767; + + if (y_bus[3*16 +: 16] !== expected[15:0]) begin + $display("FAIL N3: got %0d expected %0d", + y_bus[3*16 +: 16], expected); + errors = errors + 1; + end + else begin + if (expected == 32767) + $display("PASS N3: %0d (saturation)", y_bus[3*16 +: 16]); + else + $display("PASS N3: %0d", y_bus[3*16 +: 16]); + end + end + + /* + * Neuron 4 + */ + if (N_NEURONS > 4) begin + if (y_bus[4*16 +: 16] !== 16'sd256) begin + $display("FAIL N4: got %0d expected 256", + y_bus[4*16 +: 16]); + errors = errors + 1; + end + else + $display("PASS N4: 256 (bias)"); + end + + /* + * Neuron 5 + */ + if (N_NEURONS > 5) begin + if (y_bus[5*16 +: 16] !== 16'sd0) begin + $display("FAIL N5: got %0d expected 0", + y_bus[5*16 +: 16]); + errors = errors + 1; + end + else + $display("PASS N5: 0 (negative bias + ReLU)"); + end + + /* + * Neuron 6 + */ + if (N_NEURONS > 6) begin + expected = (N_INPUTS - 1) * 256; + + if (y_bus[6*16 +: 16] !== expected[15:0]) begin + $display("FAIL N6: got %0d expected %0d", + y_bus[6*16 +: 16], expected); + errors = errors + 1; + end + else + $display("PASS N6: %0d", y_bus[6*16 +: 16]); + end + + /* + * Neuron 7 + */ + if (N_NEURONS > 7) begin + expected = (N_INPUTS / 4 + 1) * 256; + + if (y_bus[7*16 +: 16] !== expected[15:0]) begin + $display("FAIL N7: got %0d expected %0d", + y_bus[7*16 +: 16], expected); + errors = errors + 1; + end + else + $display("PASS N7: %0d", y_bus[7*16 +: 16]); + end + + if (busy !== 0) begin + $display("FAIL: busy still active"); + errors = errors + 1; + end + + if (done !== 1) begin + $display("FAIL: done not asserted"); + errors = errors + 1; + end + + $display(""); + $display("========================================"); + + if (errors == 0) + $display("PARAMETRIC TEST PASSED"); + else + $display("PARAMETRIC TEST FAILED: %0d errors", errors); + + $display("========================================"); + $display(""); + + $finish; + end + +endmodule diff --git a/sim/top.v b/sim/top.v new file mode 100644 index 0000000..2efa871 --- /dev/null +++ b/sim/top.v @@ -0,0 +1,33 @@ +module top; + + reg clk; + reg rst; + reg start; + + reg signed [1023:0] x_bus; + reg signed [1023:0] w_bus; + reg signed [15:0] bias; + + wire signed [15:0] y; + wire busy; + wire done; + + neuron_parallel #( + .DATA_WIDTH(16), + .FRAC_BITS(8), + .N_INPUTS(64), + .PARALLEL(8), + .ACC_WIDTH(40) + ) dut ( + .clk(clk), + .rst(rst), + .start(start), + .x_bus(x_bus), + .w_bus(w_bus), + .bias(bias), + .y(y), + .busy(busy), + .done(done) + ); + +endmodule \ No newline at end of file